R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 15 | #define MAX_SOURCES 400 |
| 16 | #define DIRECT_IRQ(irq) (MAX_SOURCES + irq) |
| 17 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 18 | / { |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | |
| 22 | compatible = "ti,dra7xx"; |
| 23 | interrupt-parent = <&gic>; |
| 24 | |
| 25 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 26 | i2c0 = &i2c1; |
| 27 | i2c1 = &i2c2; |
| 28 | i2c2 = &i2c3; |
| 29 | i2c3 = &i2c4; |
| 30 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 31 | serial0 = &uart1; |
| 32 | serial1 = &uart2; |
| 33 | serial2 = &uart3; |
| 34 | serial3 = &uart4; |
| 35 | serial4 = &uart5; |
| 36 | serial5 = &uart6; |
Nishanth Menon | 065bd7f | 2014-10-21 11:18:15 -0500 | [diff] [blame^] | 37 | serial6 = &uart7; |
| 38 | serial7 = &uart8; |
| 39 | serial8 = &uart9; |
| 40 | serial9 = &uart10; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 41 | ethernet0 = &cpsw_emac0; |
| 42 | ethernet1 = &cpsw_emac1; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 43 | }; |
| 44 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 45 | timer { |
| 46 | compatible = "arm,armv7-timer"; |
| 47 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 48 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 49 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 51 | }; |
| 52 | |
| 53 | gic: interrupt-controller@48211000 { |
| 54 | compatible = "arm,cortex-a15-gic"; |
| 55 | interrupt-controller; |
| 56 | #interrupt-cells = <3>; |
R Sricharan | 5130063 | 2014-06-26 12:55:30 +0530 | [diff] [blame] | 57 | arm,routable-irqs = <192>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 58 | reg = <0x48211000 0x1000>, |
| 59 | <0x48212000 0x1000>, |
| 60 | <0x48214000 0x2000>, |
| 61 | <0x48216000 0x2000>; |
| 62 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 63 | }; |
| 64 | |
| 65 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 66 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 67 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 68 | */ |
| 69 | soc { |
| 70 | compatible = "ti,omap-infra"; |
| 71 | mpu { |
| 72 | compatible = "ti,omap5-mpu"; |
| 73 | ti,hwmods = "mpu"; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | /* |
| 78 | * XXX: Use a flat representation of the SOC interconnect. |
| 79 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 80 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 81 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 82 | * hierarchy. |
| 83 | */ |
| 84 | ocp { |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 85 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 86 | #address-cells = <1>; |
| 87 | #size-cells = <1>; |
| 88 | ranges; |
| 89 | ti,hwmods = "l3_main_1", "l3_main_2"; |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 90 | reg = <0x44000000 0x1000000>, |
| 91 | <0x45000000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 92 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 94 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 95 | prm: prm@4ae06000 { |
| 96 | compatible = "ti,dra7-prm"; |
| 97 | reg = <0x4ae06000 0x3000>; |
Nishanth Menon | 5081ce6 | 2014-08-22 09:03:50 -0500 | [diff] [blame] | 98 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 99 | |
| 100 | prm_clocks: clocks { |
| 101 | #address-cells = <1>; |
| 102 | #size-cells = <0>; |
| 103 | }; |
| 104 | |
| 105 | prm_clockdomains: clockdomains { |
| 106 | }; |
| 107 | }; |
| 108 | |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 109 | axi@0 { |
| 110 | compatible = "simple-bus"; |
| 111 | #size-cells = <1>; |
| 112 | #address-cells = <1>; |
| 113 | ranges = <0x51000000 0x51000000 0x3000 |
| 114 | 0x0 0x20000000 0x10000000>; |
| 115 | pcie@51000000 { |
| 116 | compatible = "ti,dra7-pcie"; |
| 117 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| 118 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 119 | interrupts = <0 232 0x4>, <0 233 0x4>; |
| 120 | #address-cells = <3>; |
| 121 | #size-cells = <2>; |
| 122 | device_type = "pci"; |
| 123 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 124 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| 125 | #interrupt-cells = <1>; |
| 126 | num-lanes = <1>; |
| 127 | ti,hwmods = "pcie1"; |
| 128 | phys = <&pcie1_phy>; |
| 129 | phy-names = "pcie-phy0"; |
| 130 | interrupt-map-mask = <0 0 0 7>; |
| 131 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| 132 | <0 0 0 2 &pcie1_intc 2>, |
| 133 | <0 0 0 3 &pcie1_intc 3>, |
| 134 | <0 0 0 4 &pcie1_intc 4>; |
| 135 | pcie1_intc: interrupt-controller { |
| 136 | interrupt-controller; |
| 137 | #address-cells = <0>; |
| 138 | #interrupt-cells = <1>; |
| 139 | }; |
| 140 | }; |
| 141 | }; |
| 142 | |
| 143 | axi@1 { |
| 144 | compatible = "simple-bus"; |
| 145 | #size-cells = <1>; |
| 146 | #address-cells = <1>; |
| 147 | ranges = <0x51800000 0x51800000 0x3000 |
| 148 | 0x0 0x30000000 0x10000000>; |
| 149 | status = "disabled"; |
| 150 | pcie@51000000 { |
| 151 | compatible = "ti,dra7-pcie"; |
| 152 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| 153 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 154 | interrupts = <0 355 0x4>, <0 356 0x4>; |
| 155 | #address-cells = <3>; |
| 156 | #size-cells = <2>; |
| 157 | device_type = "pci"; |
| 158 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 159 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| 160 | #interrupt-cells = <1>; |
| 161 | num-lanes = <1>; |
| 162 | ti,hwmods = "pcie2"; |
| 163 | phys = <&pcie2_phy>; |
| 164 | phy-names = "pcie-phy0"; |
| 165 | interrupt-map-mask = <0 0 0 7>; |
| 166 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| 167 | <0 0 0 2 &pcie2_intc 2>, |
| 168 | <0 0 0 3 &pcie2_intc 3>, |
| 169 | <0 0 0 4 &pcie2_intc 4>; |
| 170 | pcie2_intc: interrupt-controller { |
| 171 | interrupt-controller; |
| 172 | #address-cells = <0>; |
| 173 | #interrupt-cells = <1>; |
| 174 | }; |
| 175 | }; |
| 176 | }; |
| 177 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 178 | cm_core_aon: cm_core_aon@4a005000 { |
| 179 | compatible = "ti,dra7-cm-core-aon"; |
| 180 | reg = <0x4a005000 0x2000>; |
| 181 | |
| 182 | cm_core_aon_clocks: clocks { |
| 183 | #address-cells = <1>; |
| 184 | #size-cells = <0>; |
| 185 | }; |
| 186 | |
| 187 | cm_core_aon_clockdomains: clockdomains { |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | cm_core: cm_core@4a008000 { |
| 192 | compatible = "ti,dra7-cm-core"; |
| 193 | reg = <0x4a008000 0x3000>; |
| 194 | |
| 195 | cm_core_clocks: clocks { |
| 196 | #address-cells = <1>; |
| 197 | #size-cells = <0>; |
| 198 | }; |
| 199 | |
| 200 | cm_core_clockdomains: clockdomains { |
| 201 | }; |
| 202 | }; |
| 203 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 204 | counter32k: counter@4ae04000 { |
| 205 | compatible = "ti,omap-counter32k"; |
| 206 | reg = <0x4ae04000 0x40>; |
| 207 | ti,hwmods = "counter_32k"; |
| 208 | }; |
| 209 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 210 | dra7_ctrl_general: tisyscon@4a002e00 { |
| 211 | compatible = "syscon"; |
| 212 | reg = <0x4a002e00 0x7c>; |
| 213 | }; |
| 214 | |
| 215 | pbias_regulator: pbias_regulator { |
| 216 | compatible = "ti,pbias-omap"; |
| 217 | reg = <0 0x4>; |
| 218 | syscon = <&dra7_ctrl_general>; |
| 219 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 220 | regulator-name = "pbias_mmc_omap5"; |
| 221 | regulator-min-microvolt = <1800000>; |
| 222 | regulator-max-microvolt = <3000000>; |
| 223 | }; |
| 224 | }; |
| 225 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 226 | dra7_pmx_core: pinmux@4a003400 { |
Nishanth Menon | 817c037 | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 227 | compatible = "ti,dra7-padconf", "pinctrl-single"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 228 | reg = <0x4a003400 0x0464>; |
| 229 | #address-cells = <1>; |
| 230 | #size-cells = <0>; |
Nishanth Menon | 817c037 | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 231 | #interrupt-cells = <1>; |
| 232 | interrupt-controller; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 233 | pinctrl-single,register-width = <32>; |
| 234 | pinctrl-single,function-mask = <0x3fffffff>; |
| 235 | }; |
| 236 | |
| 237 | sdma: dma-controller@4a056000 { |
| 238 | compatible = "ti,omap4430-sdma"; |
| 239 | reg = <0x4a056000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 240 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 241 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 242 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 243 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 244 | #dma-cells = <1>; |
| 245 | #dma-channels = <32>; |
| 246 | #dma-requests = <127>; |
| 247 | }; |
| 248 | |
| 249 | gpio1: gpio@4ae10000 { |
| 250 | compatible = "ti,omap4-gpio"; |
| 251 | reg = <0x4ae10000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 252 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 253 | ti,hwmods = "gpio1"; |
| 254 | gpio-controller; |
| 255 | #gpio-cells = <2>; |
| 256 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 257 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 258 | }; |
| 259 | |
| 260 | gpio2: gpio@48055000 { |
| 261 | compatible = "ti,omap4-gpio"; |
| 262 | reg = <0x48055000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 263 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 264 | ti,hwmods = "gpio2"; |
| 265 | gpio-controller; |
| 266 | #gpio-cells = <2>; |
| 267 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 268 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 269 | }; |
| 270 | |
| 271 | gpio3: gpio@48057000 { |
| 272 | compatible = "ti,omap4-gpio"; |
| 273 | reg = <0x48057000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 274 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 275 | ti,hwmods = "gpio3"; |
| 276 | gpio-controller; |
| 277 | #gpio-cells = <2>; |
| 278 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 279 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | gpio4: gpio@48059000 { |
| 283 | compatible = "ti,omap4-gpio"; |
| 284 | reg = <0x48059000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 285 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 286 | ti,hwmods = "gpio4"; |
| 287 | gpio-controller; |
| 288 | #gpio-cells = <2>; |
| 289 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 290 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 291 | }; |
| 292 | |
| 293 | gpio5: gpio@4805b000 { |
| 294 | compatible = "ti,omap4-gpio"; |
| 295 | reg = <0x4805b000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 296 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 297 | ti,hwmods = "gpio5"; |
| 298 | gpio-controller; |
| 299 | #gpio-cells = <2>; |
| 300 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 301 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 302 | }; |
| 303 | |
| 304 | gpio6: gpio@4805d000 { |
| 305 | compatible = "ti,omap4-gpio"; |
| 306 | reg = <0x4805d000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 307 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 308 | ti,hwmods = "gpio6"; |
| 309 | gpio-controller; |
| 310 | #gpio-cells = <2>; |
| 311 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 312 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 313 | }; |
| 314 | |
| 315 | gpio7: gpio@48051000 { |
| 316 | compatible = "ti,omap4-gpio"; |
| 317 | reg = <0x48051000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 318 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 319 | ti,hwmods = "gpio7"; |
| 320 | gpio-controller; |
| 321 | #gpio-cells = <2>; |
| 322 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 323 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 324 | }; |
| 325 | |
| 326 | gpio8: gpio@48053000 { |
| 327 | compatible = "ti,omap4-gpio"; |
| 328 | reg = <0x48053000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 329 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 330 | ti,hwmods = "gpio8"; |
| 331 | gpio-controller; |
| 332 | #gpio-cells = <2>; |
| 333 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 334 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 335 | }; |
| 336 | |
| 337 | uart1: serial@4806a000 { |
| 338 | compatible = "ti,omap4-uart"; |
| 339 | reg = <0x4806a000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 340 | interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 341 | ti,hwmods = "uart1"; |
| 342 | clock-frequency = <48000000>; |
| 343 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 344 | dmas = <&sdma 49>, <&sdma 50>; |
| 345 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 346 | }; |
| 347 | |
| 348 | uart2: serial@4806c000 { |
| 349 | compatible = "ti,omap4-uart"; |
| 350 | reg = <0x4806c000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 351 | interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 352 | ti,hwmods = "uart2"; |
| 353 | clock-frequency = <48000000>; |
| 354 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 355 | dmas = <&sdma 51>, <&sdma 52>; |
| 356 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | uart3: serial@48020000 { |
| 360 | compatible = "ti,omap4-uart"; |
| 361 | reg = <0x48020000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 362 | interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 363 | ti,hwmods = "uart3"; |
| 364 | clock-frequency = <48000000>; |
| 365 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 366 | dmas = <&sdma 53>, <&sdma 54>; |
| 367 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 368 | }; |
| 369 | |
| 370 | uart4: serial@4806e000 { |
| 371 | compatible = "ti,omap4-uart"; |
| 372 | reg = <0x4806e000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 373 | interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 374 | ti,hwmods = "uart4"; |
| 375 | clock-frequency = <48000000>; |
| 376 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 377 | dmas = <&sdma 55>, <&sdma 56>; |
| 378 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 379 | }; |
| 380 | |
| 381 | uart5: serial@48066000 { |
| 382 | compatible = "ti,omap4-uart"; |
| 383 | reg = <0x48066000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 384 | interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 385 | ti,hwmods = "uart5"; |
| 386 | clock-frequency = <48000000>; |
| 387 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 388 | dmas = <&sdma 63>, <&sdma 64>; |
| 389 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 390 | }; |
| 391 | |
| 392 | uart6: serial@48068000 { |
| 393 | compatible = "ti,omap4-uart"; |
| 394 | reg = <0x48068000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 395 | interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 396 | ti,hwmods = "uart6"; |
| 397 | clock-frequency = <48000000>; |
| 398 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 399 | dmas = <&sdma 79>, <&sdma 80>; |
| 400 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 401 | }; |
| 402 | |
| 403 | uart7: serial@48420000 { |
| 404 | compatible = "ti,omap4-uart"; |
| 405 | reg = <0x48420000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 406 | interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 407 | ti,hwmods = "uart7"; |
| 408 | clock-frequency = <48000000>; |
| 409 | status = "disabled"; |
| 410 | }; |
| 411 | |
| 412 | uart8: serial@48422000 { |
| 413 | compatible = "ti,omap4-uart"; |
| 414 | reg = <0x48422000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 415 | interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 416 | ti,hwmods = "uart8"; |
| 417 | clock-frequency = <48000000>; |
| 418 | status = "disabled"; |
| 419 | }; |
| 420 | |
| 421 | uart9: serial@48424000 { |
| 422 | compatible = "ti,omap4-uart"; |
| 423 | reg = <0x48424000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 424 | interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 425 | ti,hwmods = "uart9"; |
| 426 | clock-frequency = <48000000>; |
| 427 | status = "disabled"; |
| 428 | }; |
| 429 | |
| 430 | uart10: serial@4ae2b000 { |
| 431 | compatible = "ti,omap4-uart"; |
| 432 | reg = <0x4ae2b000 0x100>; |
Nishanth Menon | e2265ab | 2014-05-23 00:04:02 -0500 | [diff] [blame] | 433 | interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 434 | ti,hwmods = "uart10"; |
| 435 | clock-frequency = <48000000>; |
| 436 | status = "disabled"; |
| 437 | }; |
| 438 | |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 439 | mailbox1: mailbox@4a0f4000 { |
| 440 | compatible = "ti,omap4-mailbox"; |
| 441 | reg = <0x4a0f4000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 442 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 443 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 444 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 445 | ti,hwmods = "mailbox1"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 446 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 447 | ti,mbox-num-users = <3>; |
| 448 | ti,mbox-num-fifos = <8>; |
| 449 | status = "disabled"; |
| 450 | }; |
| 451 | |
| 452 | mailbox2: mailbox@4883a000 { |
| 453 | compatible = "ti,omap4-mailbox"; |
| 454 | reg = <0x4883a000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 455 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 456 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| 457 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| 458 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 459 | ti,hwmods = "mailbox2"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 460 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 461 | ti,mbox-num-users = <4>; |
| 462 | ti,mbox-num-fifos = <12>; |
| 463 | status = "disabled"; |
| 464 | }; |
| 465 | |
| 466 | mailbox3: mailbox@4883c000 { |
| 467 | compatible = "ti,omap4-mailbox"; |
| 468 | reg = <0x4883c000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 469 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 470 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 471 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| 472 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 473 | ti,hwmods = "mailbox3"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 474 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 475 | ti,mbox-num-users = <4>; |
| 476 | ti,mbox-num-fifos = <12>; |
| 477 | status = "disabled"; |
| 478 | }; |
| 479 | |
| 480 | mailbox4: mailbox@4883e000 { |
| 481 | compatible = "ti,omap4-mailbox"; |
| 482 | reg = <0x4883e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 483 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 484 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 485 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 486 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 487 | ti,hwmods = "mailbox4"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 488 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 489 | ti,mbox-num-users = <4>; |
| 490 | ti,mbox-num-fifos = <12>; |
| 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
| 494 | mailbox5: mailbox@48840000 { |
| 495 | compatible = "ti,omap4-mailbox"; |
| 496 | reg = <0x48840000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 497 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 498 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 499 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 500 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 501 | ti,hwmods = "mailbox5"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 502 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 503 | ti,mbox-num-users = <4>; |
| 504 | ti,mbox-num-fifos = <12>; |
| 505 | status = "disabled"; |
| 506 | }; |
| 507 | |
| 508 | mailbox6: mailbox@48842000 { |
| 509 | compatible = "ti,omap4-mailbox"; |
| 510 | reg = <0x48842000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 511 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 512 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 513 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 514 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 515 | ti,hwmods = "mailbox6"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 516 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 517 | ti,mbox-num-users = <4>; |
| 518 | ti,mbox-num-fifos = <12>; |
| 519 | status = "disabled"; |
| 520 | }; |
| 521 | |
| 522 | mailbox7: mailbox@48844000 { |
| 523 | compatible = "ti,omap4-mailbox"; |
| 524 | reg = <0x48844000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 525 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 526 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| 527 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| 528 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 529 | ti,hwmods = "mailbox7"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 530 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 531 | ti,mbox-num-users = <4>; |
| 532 | ti,mbox-num-fifos = <12>; |
| 533 | status = "disabled"; |
| 534 | }; |
| 535 | |
| 536 | mailbox8: mailbox@48846000 { |
| 537 | compatible = "ti,omap4-mailbox"; |
| 538 | reg = <0x48846000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 539 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 540 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| 541 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| 542 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 543 | ti,hwmods = "mailbox8"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 544 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 545 | ti,mbox-num-users = <4>; |
| 546 | ti,mbox-num-fifos = <12>; |
| 547 | status = "disabled"; |
| 548 | }; |
| 549 | |
| 550 | mailbox9: mailbox@4885e000 { |
| 551 | compatible = "ti,omap4-mailbox"; |
| 552 | reg = <0x4885e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 553 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 554 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| 555 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| 556 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 557 | ti,hwmods = "mailbox9"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 558 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 559 | ti,mbox-num-users = <4>; |
| 560 | ti,mbox-num-fifos = <12>; |
| 561 | status = "disabled"; |
| 562 | }; |
| 563 | |
| 564 | mailbox10: mailbox@48860000 { |
| 565 | compatible = "ti,omap4-mailbox"; |
| 566 | reg = <0x48860000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 567 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 568 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| 569 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| 570 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 571 | ti,hwmods = "mailbox10"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 572 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 573 | ti,mbox-num-users = <4>; |
| 574 | ti,mbox-num-fifos = <12>; |
| 575 | status = "disabled"; |
| 576 | }; |
| 577 | |
| 578 | mailbox11: mailbox@48862000 { |
| 579 | compatible = "ti,omap4-mailbox"; |
| 580 | reg = <0x48862000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 581 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 582 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| 583 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| 584 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 585 | ti,hwmods = "mailbox11"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 586 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 587 | ti,mbox-num-users = <4>; |
| 588 | ti,mbox-num-fifos = <12>; |
| 589 | status = "disabled"; |
| 590 | }; |
| 591 | |
| 592 | mailbox12: mailbox@48864000 { |
| 593 | compatible = "ti,omap4-mailbox"; |
| 594 | reg = <0x48864000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 595 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 596 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| 597 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 598 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 599 | ti,hwmods = "mailbox12"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 600 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 601 | ti,mbox-num-users = <4>; |
| 602 | ti,mbox-num-fifos = <12>; |
| 603 | status = "disabled"; |
| 604 | }; |
| 605 | |
| 606 | mailbox13: mailbox@48802000 { |
| 607 | compatible = "ti,omap4-mailbox"; |
| 608 | reg = <0x48802000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 609 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 610 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| 611 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| 612 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 613 | ti,hwmods = "mailbox13"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 614 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 615 | ti,mbox-num-users = <4>; |
| 616 | ti,mbox-num-fifos = <12>; |
| 617 | status = "disabled"; |
| 618 | }; |
| 619 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 620 | timer1: timer@4ae18000 { |
| 621 | compatible = "ti,omap5430-timer"; |
| 622 | reg = <0x4ae18000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 623 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 624 | ti,hwmods = "timer1"; |
| 625 | ti,timer-alwon; |
| 626 | }; |
| 627 | |
| 628 | timer2: timer@48032000 { |
| 629 | compatible = "ti,omap5430-timer"; |
| 630 | reg = <0x48032000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 631 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 632 | ti,hwmods = "timer2"; |
| 633 | }; |
| 634 | |
| 635 | timer3: timer@48034000 { |
| 636 | compatible = "ti,omap5430-timer"; |
| 637 | reg = <0x48034000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 638 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 639 | ti,hwmods = "timer3"; |
| 640 | }; |
| 641 | |
| 642 | timer4: timer@48036000 { |
| 643 | compatible = "ti,omap5430-timer"; |
| 644 | reg = <0x48036000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 645 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 646 | ti,hwmods = "timer4"; |
| 647 | }; |
| 648 | |
| 649 | timer5: timer@48820000 { |
| 650 | compatible = "ti,omap5430-timer"; |
| 651 | reg = <0x48820000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 652 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 653 | ti,hwmods = "timer5"; |
| 654 | ti,timer-dsp; |
| 655 | }; |
| 656 | |
| 657 | timer6: timer@48822000 { |
| 658 | compatible = "ti,omap5430-timer"; |
| 659 | reg = <0x48822000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 660 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 661 | ti,hwmods = "timer6"; |
| 662 | ti,timer-dsp; |
| 663 | ti,timer-pwm; |
| 664 | }; |
| 665 | |
| 666 | timer7: timer@48824000 { |
| 667 | compatible = "ti,omap5430-timer"; |
| 668 | reg = <0x48824000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 669 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 670 | ti,hwmods = "timer7"; |
| 671 | ti,timer-dsp; |
| 672 | }; |
| 673 | |
| 674 | timer8: timer@48826000 { |
| 675 | compatible = "ti,omap5430-timer"; |
| 676 | reg = <0x48826000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 677 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 678 | ti,hwmods = "timer8"; |
| 679 | ti,timer-dsp; |
| 680 | ti,timer-pwm; |
| 681 | }; |
| 682 | |
| 683 | timer9: timer@4803e000 { |
| 684 | compatible = "ti,omap5430-timer"; |
| 685 | reg = <0x4803e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 686 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 687 | ti,hwmods = "timer9"; |
| 688 | }; |
| 689 | |
| 690 | timer10: timer@48086000 { |
| 691 | compatible = "ti,omap5430-timer"; |
| 692 | reg = <0x48086000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 693 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 694 | ti,hwmods = "timer10"; |
| 695 | }; |
| 696 | |
| 697 | timer11: timer@48088000 { |
| 698 | compatible = "ti,omap5430-timer"; |
| 699 | reg = <0x48088000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 700 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 701 | ti,hwmods = "timer11"; |
| 702 | ti,timer-pwm; |
| 703 | }; |
| 704 | |
| 705 | timer13: timer@48828000 { |
| 706 | compatible = "ti,omap5430-timer"; |
| 707 | reg = <0x48828000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 708 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 709 | ti,hwmods = "timer13"; |
| 710 | status = "disabled"; |
| 711 | }; |
| 712 | |
| 713 | timer14: timer@4882a000 { |
| 714 | compatible = "ti,omap5430-timer"; |
| 715 | reg = <0x4882a000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 716 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 717 | ti,hwmods = "timer14"; |
| 718 | status = "disabled"; |
| 719 | }; |
| 720 | |
| 721 | timer15: timer@4882c000 { |
| 722 | compatible = "ti,omap5430-timer"; |
| 723 | reg = <0x4882c000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 724 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 725 | ti,hwmods = "timer15"; |
| 726 | status = "disabled"; |
| 727 | }; |
| 728 | |
| 729 | timer16: timer@4882e000 { |
| 730 | compatible = "ti,omap5430-timer"; |
| 731 | reg = <0x4882e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 732 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 733 | ti,hwmods = "timer16"; |
| 734 | status = "disabled"; |
| 735 | }; |
| 736 | |
| 737 | wdt2: wdt@4ae14000 { |
| 738 | compatible = "ti,omap4-wdt"; |
| 739 | reg = <0x4ae14000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 740 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 741 | ti,hwmods = "wd_timer2"; |
| 742 | }; |
| 743 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 744 | hwspinlock: spinlock@4a0f6000 { |
| 745 | compatible = "ti,omap4-hwspinlock"; |
| 746 | reg = <0x4a0f6000 0x1000>; |
| 747 | ti,hwmods = "spinlock"; |
| 748 | #hwlock-cells = <1>; |
| 749 | }; |
| 750 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 751 | dmm@4e000000 { |
| 752 | compatible = "ti,omap5-dmm"; |
| 753 | reg = <0x4e000000 0x800>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 754 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 755 | ti,hwmods = "dmm"; |
| 756 | }; |
| 757 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 758 | i2c1: i2c@48070000 { |
| 759 | compatible = "ti,omap4-i2c"; |
| 760 | reg = <0x48070000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 761 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 762 | #address-cells = <1>; |
| 763 | #size-cells = <0>; |
| 764 | ti,hwmods = "i2c1"; |
| 765 | status = "disabled"; |
| 766 | }; |
| 767 | |
| 768 | i2c2: i2c@48072000 { |
| 769 | compatible = "ti,omap4-i2c"; |
| 770 | reg = <0x48072000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 771 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 772 | #address-cells = <1>; |
| 773 | #size-cells = <0>; |
| 774 | ti,hwmods = "i2c2"; |
| 775 | status = "disabled"; |
| 776 | }; |
| 777 | |
| 778 | i2c3: i2c@48060000 { |
| 779 | compatible = "ti,omap4-i2c"; |
| 780 | reg = <0x48060000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 781 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 782 | #address-cells = <1>; |
| 783 | #size-cells = <0>; |
| 784 | ti,hwmods = "i2c3"; |
| 785 | status = "disabled"; |
| 786 | }; |
| 787 | |
| 788 | i2c4: i2c@4807a000 { |
| 789 | compatible = "ti,omap4-i2c"; |
| 790 | reg = <0x4807a000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 791 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 792 | #address-cells = <1>; |
| 793 | #size-cells = <0>; |
| 794 | ti,hwmods = "i2c4"; |
| 795 | status = "disabled"; |
| 796 | }; |
| 797 | |
| 798 | i2c5: i2c@4807c000 { |
| 799 | compatible = "ti,omap4-i2c"; |
| 800 | reg = <0x4807c000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 801 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 802 | #address-cells = <1>; |
| 803 | #size-cells = <0>; |
| 804 | ti,hwmods = "i2c5"; |
| 805 | status = "disabled"; |
| 806 | }; |
| 807 | |
| 808 | mmc1: mmc@4809c000 { |
| 809 | compatible = "ti,omap4-hsmmc"; |
| 810 | reg = <0x4809c000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 811 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 812 | ti,hwmods = "mmc1"; |
| 813 | ti,dual-volt; |
| 814 | ti,needs-special-reset; |
| 815 | dmas = <&sdma 61>, <&sdma 62>; |
| 816 | dma-names = "tx", "rx"; |
| 817 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 818 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 819 | }; |
| 820 | |
| 821 | mmc2: mmc@480b4000 { |
| 822 | compatible = "ti,omap4-hsmmc"; |
| 823 | reg = <0x480b4000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 824 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 825 | ti,hwmods = "mmc2"; |
| 826 | ti,needs-special-reset; |
| 827 | dmas = <&sdma 47>, <&sdma 48>; |
| 828 | dma-names = "tx", "rx"; |
| 829 | status = "disabled"; |
| 830 | }; |
| 831 | |
| 832 | mmc3: mmc@480ad000 { |
| 833 | compatible = "ti,omap4-hsmmc"; |
| 834 | reg = <0x480ad000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 835 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 836 | ti,hwmods = "mmc3"; |
| 837 | ti,needs-special-reset; |
| 838 | dmas = <&sdma 77>, <&sdma 78>; |
| 839 | dma-names = "tx", "rx"; |
| 840 | status = "disabled"; |
| 841 | }; |
| 842 | |
| 843 | mmc4: mmc@480d1000 { |
| 844 | compatible = "ti,omap4-hsmmc"; |
| 845 | reg = <0x480d1000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 846 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 847 | ti,hwmods = "mmc4"; |
| 848 | ti,needs-special-reset; |
| 849 | dmas = <&sdma 57>, <&sdma 58>; |
| 850 | dma-names = "tx", "rx"; |
| 851 | status = "disabled"; |
| 852 | }; |
| 853 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 854 | abb_mpu: regulator-abb-mpu { |
| 855 | compatible = "ti,abb-v3"; |
| 856 | regulator-name = "abb_mpu"; |
| 857 | #address-cells = <0>; |
| 858 | #size-cells = <0>; |
| 859 | clocks = <&sys_clkin1>; |
| 860 | ti,settling-time = <50>; |
| 861 | ti,clock-cycles = <16>; |
| 862 | |
| 863 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| 864 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, |
| 865 | <0x4ae0c158 0x4>; |
| 866 | reg-names = "setup-address", "control-address", |
| 867 | "int-address", "efuse-address", |
| 868 | "ldo-address"; |
| 869 | ti,tranxdone-status-mask = <0x80>; |
| 870 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 871 | ti,ldovbb-override-mask = <0x400>; |
| 872 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 873 | ti,ldovbb-vset-mask = <0x1F>; |
| 874 | |
| 875 | /* |
| 876 | * NOTE: only FBB mode used but actual vset will |
| 877 | * determine final biasing |
| 878 | */ |
| 879 | ti,abb_info = < |
| 880 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 881 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 882 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 883 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 884 | >; |
| 885 | }; |
| 886 | |
| 887 | abb_ivahd: regulator-abb-ivahd { |
| 888 | compatible = "ti,abb-v3"; |
| 889 | regulator-name = "abb_ivahd"; |
| 890 | #address-cells = <0>; |
| 891 | #size-cells = <0>; |
| 892 | clocks = <&sys_clkin1>; |
| 893 | ti,settling-time = <50>; |
| 894 | ti,clock-cycles = <16>; |
| 895 | |
| 896 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| 897 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, |
| 898 | <0x4a002470 0x4>; |
| 899 | reg-names = "setup-address", "control-address", |
| 900 | "int-address", "efuse-address", |
| 901 | "ldo-address"; |
| 902 | ti,tranxdone-status-mask = <0x40000000>; |
| 903 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 904 | ti,ldovbb-override-mask = <0x400>; |
| 905 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 906 | ti,ldovbb-vset-mask = <0x1F>; |
| 907 | |
| 908 | /* |
| 909 | * NOTE: only FBB mode used but actual vset will |
| 910 | * determine final biasing |
| 911 | */ |
| 912 | ti,abb_info = < |
| 913 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 914 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 915 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 916 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 917 | >; |
| 918 | }; |
| 919 | |
| 920 | abb_dspeve: regulator-abb-dspeve { |
| 921 | compatible = "ti,abb-v3"; |
| 922 | regulator-name = "abb_dspeve"; |
| 923 | #address-cells = <0>; |
| 924 | #size-cells = <0>; |
| 925 | clocks = <&sys_clkin1>; |
| 926 | ti,settling-time = <50>; |
| 927 | ti,clock-cycles = <16>; |
| 928 | |
| 929 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| 930 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, |
| 931 | <0x4a00246c 0x4>; |
| 932 | reg-names = "setup-address", "control-address", |
| 933 | "int-address", "efuse-address", |
| 934 | "ldo-address"; |
| 935 | ti,tranxdone-status-mask = <0x20000000>; |
| 936 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 937 | ti,ldovbb-override-mask = <0x400>; |
| 938 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 939 | ti,ldovbb-vset-mask = <0x1F>; |
| 940 | |
| 941 | /* |
| 942 | * NOTE: only FBB mode used but actual vset will |
| 943 | * determine final biasing |
| 944 | */ |
| 945 | ti,abb_info = < |
| 946 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 947 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 948 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 949 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 950 | >; |
| 951 | }; |
| 952 | |
| 953 | abb_gpu: regulator-abb-gpu { |
| 954 | compatible = "ti,abb-v3"; |
| 955 | regulator-name = "abb_gpu"; |
| 956 | #address-cells = <0>; |
| 957 | #size-cells = <0>; |
| 958 | clocks = <&sys_clkin1>; |
| 959 | ti,settling-time = <50>; |
| 960 | ti,clock-cycles = <16>; |
| 961 | |
| 962 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| 963 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, |
| 964 | <0x4ae0c154 0x4>; |
| 965 | reg-names = "setup-address", "control-address", |
| 966 | "int-address", "efuse-address", |
| 967 | "ldo-address"; |
| 968 | ti,tranxdone-status-mask = <0x10000000>; |
| 969 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 970 | ti,ldovbb-override-mask = <0x400>; |
| 971 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 972 | ti,ldovbb-vset-mask = <0x1F>; |
| 973 | |
| 974 | /* |
| 975 | * NOTE: only FBB mode used but actual vset will |
| 976 | * determine final biasing |
| 977 | */ |
| 978 | ti,abb_info = < |
| 979 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 980 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 981 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 982 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 983 | >; |
| 984 | }; |
| 985 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 986 | mcspi1: spi@48098000 { |
| 987 | compatible = "ti,omap4-mcspi"; |
| 988 | reg = <0x48098000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 989 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 990 | #address-cells = <1>; |
| 991 | #size-cells = <0>; |
| 992 | ti,hwmods = "mcspi1"; |
| 993 | ti,spi-num-cs = <4>; |
| 994 | dmas = <&sdma 35>, |
| 995 | <&sdma 36>, |
| 996 | <&sdma 37>, |
| 997 | <&sdma 38>, |
| 998 | <&sdma 39>, |
| 999 | <&sdma 40>, |
| 1000 | <&sdma 41>, |
| 1001 | <&sdma 42>; |
| 1002 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1003 | "tx2", "rx2", "tx3", "rx3"; |
| 1004 | status = "disabled"; |
| 1005 | }; |
| 1006 | |
| 1007 | mcspi2: spi@4809a000 { |
| 1008 | compatible = "ti,omap4-mcspi"; |
| 1009 | reg = <0x4809a000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1010 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1011 | #address-cells = <1>; |
| 1012 | #size-cells = <0>; |
| 1013 | ti,hwmods = "mcspi2"; |
| 1014 | ti,spi-num-cs = <2>; |
| 1015 | dmas = <&sdma 43>, |
| 1016 | <&sdma 44>, |
| 1017 | <&sdma 45>, |
| 1018 | <&sdma 46>; |
| 1019 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1020 | status = "disabled"; |
| 1021 | }; |
| 1022 | |
| 1023 | mcspi3: spi@480b8000 { |
| 1024 | compatible = "ti,omap4-mcspi"; |
| 1025 | reg = <0x480b8000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1026 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1027 | #address-cells = <1>; |
| 1028 | #size-cells = <0>; |
| 1029 | ti,hwmods = "mcspi3"; |
| 1030 | ti,spi-num-cs = <2>; |
| 1031 | dmas = <&sdma 15>, <&sdma 16>; |
| 1032 | dma-names = "tx0", "rx0"; |
| 1033 | status = "disabled"; |
| 1034 | }; |
| 1035 | |
| 1036 | mcspi4: spi@480ba000 { |
| 1037 | compatible = "ti,omap4-mcspi"; |
| 1038 | reg = <0x480ba000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1039 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1040 | #address-cells = <1>; |
| 1041 | #size-cells = <0>; |
| 1042 | ti,hwmods = "mcspi4"; |
| 1043 | ti,spi-num-cs = <1>; |
| 1044 | dmas = <&sdma 70>, <&sdma 71>; |
| 1045 | dma-names = "tx0", "rx0"; |
| 1046 | status = "disabled"; |
| 1047 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1048 | |
| 1049 | qspi: qspi@4b300000 { |
| 1050 | compatible = "ti,dra7xxx-qspi"; |
| 1051 | reg = <0x4b300000 0x100>; |
| 1052 | reg-names = "qspi_base"; |
| 1053 | #address-cells = <1>; |
| 1054 | #size-cells = <0>; |
| 1055 | ti,hwmods = "qspi"; |
| 1056 | clocks = <&qspi_gfclk_div>; |
| 1057 | clock-names = "fck"; |
| 1058 | num-cs = <4>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1059 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1060 | status = "disabled"; |
| 1061 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1062 | |
| 1063 | omap_control_sata: control-phy@4a002374 { |
| 1064 | compatible = "ti,control-phy-pipe3"; |
| 1065 | reg = <0x4a002374 0x4>; |
| 1066 | reg-names = "power"; |
| 1067 | clocks = <&sys_clkin1>; |
| 1068 | clock-names = "sysclk"; |
| 1069 | }; |
| 1070 | |
| 1071 | /* OCP2SCP3 */ |
| 1072 | ocp2scp@4a090000 { |
| 1073 | compatible = "ti,omap-ocp2scp"; |
| 1074 | #address-cells = <1>; |
| 1075 | #size-cells = <1>; |
| 1076 | ranges; |
| 1077 | reg = <0x4a090000 0x20>; |
| 1078 | ti,hwmods = "ocp2scp3"; |
| 1079 | sata_phy: phy@4A096000 { |
| 1080 | compatible = "ti,phy-pipe3-sata"; |
| 1081 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 1082 | <0x4A096400 0x64>, /* phy_tx */ |
| 1083 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 1084 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1085 | ctrl-module = <&omap_control_sata>; |
| 1086 | clocks = <&sys_clkin1>; |
| 1087 | clock-names = "sysclk"; |
| 1088 | #phy-cells = <0>; |
| 1089 | }; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1090 | |
| 1091 | pcie1_phy: pciephy@4a094000 { |
| 1092 | compatible = "ti,phy-pipe3-pcie"; |
| 1093 | reg = <0x4a094000 0x80>, /* phy_rx */ |
| 1094 | <0x4a094400 0x64>; /* phy_tx */ |
| 1095 | reg-names = "phy_rx", "phy_tx"; |
| 1096 | ctrl-module = <&omap_control_pcie1phy>; |
| 1097 | clocks = <&dpll_pcie_ref_ck>, |
| 1098 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1099 | <&optfclk_pciephy1_32khz>, |
| 1100 | <&optfclk_pciephy1_clk>, |
| 1101 | <&optfclk_pciephy1_div_clk>, |
| 1102 | <&optfclk_pciephy_div>; |
| 1103 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1104 | "wkupclk", "refclk", |
| 1105 | "div-clk", "phy-div"; |
| 1106 | #phy-cells = <0>; |
| 1107 | id = <1>; |
| 1108 | ti,hwmods = "pcie1-phy"; |
| 1109 | }; |
| 1110 | |
| 1111 | pcie2_phy: pciephy@4a095000 { |
| 1112 | compatible = "ti,phy-pipe3-pcie"; |
| 1113 | reg = <0x4a095000 0x80>, /* phy_rx */ |
| 1114 | <0x4a095400 0x64>; /* phy_tx */ |
| 1115 | reg-names = "phy_rx", "phy_tx"; |
| 1116 | ctrl-module = <&omap_control_pcie2phy>; |
| 1117 | clocks = <&dpll_pcie_ref_ck>, |
| 1118 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1119 | <&optfclk_pciephy2_32khz>, |
| 1120 | <&optfclk_pciephy2_clk>, |
| 1121 | <&optfclk_pciephy2_div_clk>, |
| 1122 | <&optfclk_pciephy_div>; |
| 1123 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1124 | "wkupclk", "refclk", |
| 1125 | "div-clk", "phy-div"; |
| 1126 | #phy-cells = <0>; |
| 1127 | ti,hwmods = "pcie2-phy"; |
| 1128 | id = <2>; |
| 1129 | status = "disabled"; |
| 1130 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1131 | }; |
| 1132 | |
| 1133 | sata: sata@4a141100 { |
| 1134 | compatible = "snps,dwc-ahci"; |
| 1135 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1136 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1137 | phys = <&sata_phy>; |
| 1138 | phy-names = "sata-phy"; |
| 1139 | clocks = <&sata_ref_clk>; |
| 1140 | ti,hwmods = "sata"; |
| 1141 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1142 | |
Kishon Vijay Abraham I | d1ff66b | 2014-07-14 16:12:21 +0530 | [diff] [blame] | 1143 | omap_control_pcie1phy: control-phy@0x4a003c40 { |
| 1144 | compatible = "ti,control-phy-pcie"; |
| 1145 | reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1146 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1147 | clocks = <&sys_clkin1>; |
| 1148 | clock-names = "sysclk"; |
| 1149 | }; |
| 1150 | |
| 1151 | omap_control_pcie2phy: control-pcie@0x4a003c44 { |
| 1152 | compatible = "ti,control-phy-pcie"; |
| 1153 | reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1154 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1155 | clocks = <&sys_clkin1>; |
| 1156 | clock-names = "sysclk"; |
| 1157 | status = "disabled"; |
| 1158 | }; |
| 1159 | |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1160 | omap_control_usb2phy1: control-phy@4a002300 { |
| 1161 | compatible = "ti,control-phy-usb2"; |
| 1162 | reg = <0x4a002300 0x4>; |
| 1163 | reg-names = "power"; |
| 1164 | }; |
| 1165 | |
| 1166 | omap_control_usb3phy1: control-phy@4a002370 { |
| 1167 | compatible = "ti,control-phy-pipe3"; |
| 1168 | reg = <0x4a002370 0x4>; |
| 1169 | reg-names = "power"; |
| 1170 | }; |
| 1171 | |
| 1172 | omap_control_usb2phy2: control-phy@0x4a002e74 { |
| 1173 | compatible = "ti,control-phy-usb2-dra7"; |
| 1174 | reg = <0x4a002e74 0x4>; |
| 1175 | reg-names = "power"; |
| 1176 | }; |
| 1177 | |
| 1178 | /* OCP2SCP1 */ |
| 1179 | ocp2scp@4a080000 { |
| 1180 | compatible = "ti,omap-ocp2scp"; |
| 1181 | #address-cells = <1>; |
| 1182 | #size-cells = <1>; |
| 1183 | ranges; |
| 1184 | reg = <0x4a080000 0x20>; |
| 1185 | ti,hwmods = "ocp2scp1"; |
| 1186 | |
| 1187 | usb2_phy1: phy@4a084000 { |
| 1188 | compatible = "ti,omap-usb2"; |
| 1189 | reg = <0x4a084000 0x400>; |
| 1190 | ctrl-module = <&omap_control_usb2phy1>; |
| 1191 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1192 | <&usb_otg_ss1_refclk960m>; |
| 1193 | clock-names = "wkupclk", |
| 1194 | "refclk"; |
| 1195 | #phy-cells = <0>; |
| 1196 | }; |
| 1197 | |
| 1198 | usb2_phy2: phy@4a085000 { |
| 1199 | compatible = "ti,omap-usb2"; |
| 1200 | reg = <0x4a085000 0x400>; |
| 1201 | ctrl-module = <&omap_control_usb2phy2>; |
| 1202 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1203 | <&usb_otg_ss2_refclk960m>; |
| 1204 | clock-names = "wkupclk", |
| 1205 | "refclk"; |
| 1206 | #phy-cells = <0>; |
| 1207 | }; |
| 1208 | |
| 1209 | usb3_phy1: phy@4a084400 { |
| 1210 | compatible = "ti,omap-usb3"; |
| 1211 | reg = <0x4a084400 0x80>, |
| 1212 | <0x4a084800 0x64>, |
| 1213 | <0x4a084c00 0x40>; |
| 1214 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1215 | ctrl-module = <&omap_control_usb3phy1>; |
| 1216 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1217 | <&sys_clkin1>, |
| 1218 | <&usb_otg_ss1_refclk960m>; |
| 1219 | clock-names = "wkupclk", |
| 1220 | "sysclk", |
| 1221 | "refclk"; |
| 1222 | #phy-cells = <0>; |
| 1223 | }; |
| 1224 | }; |
| 1225 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1226 | omap_dwc3_1: omap_dwc3_1@48880000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1227 | compatible = "ti,dwc3"; |
| 1228 | ti,hwmods = "usb_otg_ss1"; |
| 1229 | reg = <0x48880000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1230 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1231 | #address-cells = <1>; |
| 1232 | #size-cells = <1>; |
| 1233 | utmi-mode = <2>; |
| 1234 | ranges; |
| 1235 | usb1: usb@48890000 { |
| 1236 | compatible = "snps,dwc3"; |
| 1237 | reg = <0x48890000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1238 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1239 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1240 | phy-names = "usb2-phy", "usb3-phy"; |
| 1241 | tx-fifo-resize; |
| 1242 | maximum-speed = "super-speed"; |
| 1243 | dr_mode = "otg"; |
| 1244 | }; |
| 1245 | }; |
| 1246 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1247 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1248 | compatible = "ti,dwc3"; |
| 1249 | ti,hwmods = "usb_otg_ss2"; |
| 1250 | reg = <0x488c0000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1251 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1252 | #address-cells = <1>; |
| 1253 | #size-cells = <1>; |
| 1254 | utmi-mode = <2>; |
| 1255 | ranges; |
| 1256 | usb2: usb@488d0000 { |
| 1257 | compatible = "snps,dwc3"; |
| 1258 | reg = <0x488d0000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1259 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1260 | phys = <&usb2_phy2>; |
| 1261 | phy-names = "usb2-phy"; |
| 1262 | tx-fifo-resize; |
| 1263 | maximum-speed = "high-speed"; |
| 1264 | dr_mode = "otg"; |
| 1265 | }; |
| 1266 | }; |
| 1267 | |
| 1268 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1269 | omap_dwc3_3: omap_dwc3_3@48900000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1270 | compatible = "ti,dwc3"; |
| 1271 | ti,hwmods = "usb_otg_ss3"; |
| 1272 | reg = <0x48900000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1273 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1274 | #address-cells = <1>; |
| 1275 | #size-cells = <1>; |
| 1276 | utmi-mode = <2>; |
| 1277 | ranges; |
| 1278 | status = "disabled"; |
| 1279 | usb3: usb@48910000 { |
| 1280 | compatible = "snps,dwc3"; |
| 1281 | reg = <0x48910000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1282 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1283 | tx-fifo-resize; |
| 1284 | maximum-speed = "high-speed"; |
| 1285 | dr_mode = "otg"; |
| 1286 | }; |
| 1287 | }; |
| 1288 | |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1289 | elm: elm@48078000 { |
| 1290 | compatible = "ti,am3352-elm"; |
| 1291 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1292 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1293 | ti,hwmods = "elm"; |
| 1294 | status = "disabled"; |
| 1295 | }; |
| 1296 | |
| 1297 | gpmc: gpmc@50000000 { |
| 1298 | compatible = "ti,am3352-gpmc"; |
| 1299 | ti,hwmods = "gpmc"; |
| 1300 | reg = <0x50000000 0x37c>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1301 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1302 | gpmc,num-cs = <8>; |
| 1303 | gpmc,num-waitpins = <2>; |
| 1304 | #address-cells = <2>; |
| 1305 | #size-cells = <1>; |
| 1306 | status = "disabled"; |
| 1307 | }; |
Peter Ujfalusi | 2ca0945 | 2014-05-07 13:20:48 +0300 | [diff] [blame] | 1308 | |
| 1309 | atl: atl@4843c000 { |
| 1310 | compatible = "ti,dra7-atl"; |
| 1311 | reg = <0x4843c000 0x3ff>; |
| 1312 | ti,hwmods = "atl"; |
| 1313 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| 1314 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| 1315 | clocks = <&atl_gfclk_mux>; |
| 1316 | clock-names = "fck"; |
| 1317 | status = "disabled"; |
| 1318 | }; |
Olof Johansson | 412a9bb | 2014-07-18 22:16:15 -0700 | [diff] [blame] | 1319 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1320 | crossbar_mpu: crossbar@4a020000 { |
| 1321 | compatible = "ti,irq-crossbar"; |
| 1322 | reg = <0x4a002a48 0x130>; |
| 1323 | ti,max-irqs = <160>; |
| 1324 | ti,max-crossbar-sources = <MAX_SOURCES>; |
| 1325 | ti,reg-size = <2>; |
| 1326 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| 1327 | ti,irqs-skip = <10 133 139 140>; |
| 1328 | ti,irqs-safe-map = <0>; |
| 1329 | }; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1330 | |
| 1331 | mac: ethernet@4a100000 { |
| 1332 | compatible = "ti,cpsw"; |
| 1333 | ti,hwmods = "gmac"; |
| 1334 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| 1335 | clock-names = "fck", "cpts"; |
| 1336 | cpdma_channels = <8>; |
| 1337 | ale_entries = <1024>; |
| 1338 | bd_ram_size = <0x2000>; |
| 1339 | no_bd_ram = <0>; |
| 1340 | rx_descs = <64>; |
| 1341 | mac_control = <0x20>; |
| 1342 | slaves = <2>; |
| 1343 | active_slave = <0>; |
| 1344 | cpts_clock_mult = <0x80000000>; |
| 1345 | cpts_clock_shift = <29>; |
| 1346 | reg = <0x48484000 0x1000 |
| 1347 | 0x48485200 0x2E00>; |
| 1348 | #address-cells = <1>; |
| 1349 | #size-cells = <1>; |
| 1350 | /* |
| 1351 | * rx_thresh_pend |
| 1352 | * rx_pend |
| 1353 | * tx_pend |
| 1354 | * misc_pend |
| 1355 | */ |
| 1356 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 1357 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 1358 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 1359 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| 1360 | ranges; |
| 1361 | status = "disabled"; |
| 1362 | |
| 1363 | davinci_mdio: mdio@48485000 { |
| 1364 | compatible = "ti,davinci_mdio"; |
| 1365 | #address-cells = <1>; |
| 1366 | #size-cells = <0>; |
| 1367 | ti,hwmods = "davinci_mdio"; |
| 1368 | bus_freq = <1000000>; |
| 1369 | reg = <0x48485000 0x100>; |
| 1370 | }; |
| 1371 | |
| 1372 | cpsw_emac0: slave@48480200 { |
| 1373 | /* Filled in by U-Boot */ |
| 1374 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1375 | }; |
| 1376 | |
| 1377 | cpsw_emac1: slave@48480300 { |
| 1378 | /* Filled in by U-Boot */ |
| 1379 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1380 | }; |
| 1381 | |
| 1382 | phy_sel: cpsw-phy-sel@4a002554 { |
| 1383 | compatible = "ti,dra7xx-cpsw-phy-sel"; |
| 1384 | reg= <0x4a002554 0x4>; |
| 1385 | reg-names = "gmii-sel"; |
| 1386 | }; |
| 1387 | }; |
| 1388 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1389 | }; |
| 1390 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 1391 | |
| 1392 | /include/ "dra7xx-clocks.dtsi" |