blob: c79bbff00cb72e81801e977511627dc095a630f0 [file] [log] [blame]
Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
Jeeja KPb663a8c2015-10-07 11:31:57 +010027#include "skl-topology.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053028
29#define HDA_MONO 1
30#define HDA_STEREO 2
31
32static struct snd_pcm_hardware azx_pcm_hw = {
33 .info = (SNDRV_PCM_INFO_MMAP |
34 SNDRV_PCM_INFO_INTERLEAVED |
35 SNDRV_PCM_INFO_BLOCK_TRANSFER |
36 SNDRV_PCM_INFO_MMAP_VALID |
37 SNDRV_PCM_INFO_PAUSE |
38 SNDRV_PCM_INFO_SYNC_START |
39 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
40 SNDRV_PCM_INFO_HAS_LINK_ATIME |
41 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
Jeeja KP06b23d92015-11-23 22:26:26 +053042 .formats = SNDRV_PCM_FMTBIT_S16_LE |
43 SNDRV_PCM_FMTBIT_S32_LE |
44 SNDRV_PCM_FMTBIT_S24_LE,
45 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
46 SNDRV_PCM_RATE_8000,
47 .rate_min = 8000,
Jeeja KPa40e6932015-07-09 15:20:08 +053048 .rate_max = 48000,
49 .channels_min = 2,
50 .channels_max = 2,
51 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
52 .period_bytes_min = 128,
53 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
54 .periods_min = 2,
55 .periods_max = AZX_MAX_FRAG,
56 .fifo_size = 0,
57};
58
59static inline
60struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
61{
62 return substream->runtime->private_data;
63}
64
65static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
66{
67 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
68 struct hdac_stream *hstream = hdac_stream(stream);
69 struct hdac_bus *bus = hstream->bus;
70
71 return hbus_to_ebus(bus);
72}
73
74static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
75 struct snd_pcm_substream *substream,
76 size_t size)
77{
78 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
79
80 hdac_stream(stream)->bufsize = 0;
81 hdac_stream(stream)->period_bytes = 0;
82 hdac_stream(stream)->format_val = 0;
83
84 return snd_pcm_lib_malloc_pages(substream, size);
85}
86
87static int skl_substream_free_pages(struct hdac_bus *bus,
88 struct snd_pcm_substream *substream)
89{
90 return snd_pcm_lib_free_pages(substream);
91}
92
93static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
94 struct snd_pcm_runtime *runtime)
95{
96 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
97
98 /* avoid wrap-around with wall-clock */
99 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
100 20, 178000000);
101}
102
Jeeja KP05057002015-07-09 15:20:11 +0530103static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
104{
105 if (ebus->ppcap)
106 return HDAC_EXT_STREAM_TYPE_HOST;
107 else
108 return HDAC_EXT_STREAM_TYPE_COUPLED;
109}
110
Jeeja KPa40e6932015-07-09 15:20:08 +0530111static int skl_pcm_open(struct snd_pcm_substream *substream,
112 struct snd_soc_dai *dai)
113{
114 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
115 struct hdac_ext_stream *stream;
116 struct snd_pcm_runtime *runtime = substream->runtime;
117 struct skl_dma_params *dma_params;
Jeeja KPa40e6932015-07-09 15:20:08 +0530118
119 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530120
121 stream = snd_hdac_ext_stream_assign(ebus, substream,
Jeeja KP05057002015-07-09 15:20:11 +0530122 skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530123 if (stream == NULL)
124 return -EBUSY;
125
126 skl_set_pcm_constrains(ebus, runtime);
127
128 /*
129 * disable WALLCLOCK timestamps for capture streams
130 * until we figure out how to handle digital inputs
131 */
132 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
133 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
134 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
135 }
136
137 runtime->private_data = stream;
138
139 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
140 if (!dma_params)
141 return -ENOMEM;
142
143 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
144 snd_soc_dai_set_dma_data(dai, substream, dma_params);
145
146 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
147 dma_params->stream_tag);
148 snd_pcm_set_sync(substream);
149
150 return 0;
151}
152
153static int skl_get_format(struct snd_pcm_substream *substream,
154 struct snd_soc_dai *dai)
155{
156 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
157 struct skl_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530158 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530159 int format_val = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530160
Jeeja KP05057002015-07-09 15:20:11 +0530161 if (ebus->ppcap) {
162 struct snd_pcm_runtime *runtime = substream->runtime;
163
164 format_val = snd_hdac_calc_stream_format(runtime->rate,
165 runtime->channels,
166 runtime->format,
167 32, 0);
168 } else {
169 struct snd_soc_dai *codec_dai = rtd->codec_dai;
170
171 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
172 if (dma_params)
173 format_val = dma_params->format;
174 }
Jeeja KPa40e6932015-07-09 15:20:08 +0530175
176 return format_val;
177}
178
179static int skl_pcm_prepare(struct snd_pcm_substream *substream,
180 struct snd_soc_dai *dai)
181{
182 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
183 unsigned int format_val;
184 int err;
185
186 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530187
188 format_val = skl_get_format(substream, dai);
189 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
190 hdac_stream(stream)->stream_tag, format_val);
191 snd_hdac_stream_reset(hdac_stream(stream));
192
193 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
194 if (err < 0)
195 return err;
196
197 err = snd_hdac_stream_setup(hdac_stream(stream));
198 if (err < 0)
199 return err;
200
201 hdac_stream(stream)->prepared = 1;
202
203 return err;
204}
205
206static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
207 struct snd_pcm_hw_params *params,
208 struct snd_soc_dai *dai)
209{
210 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KP05057002015-07-09 15:20:11 +0530211 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530212 struct snd_pcm_runtime *runtime = substream->runtime;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100213 struct skl_pipe_params p_params = {0};
214 struct skl_module_cfg *m_cfg;
Jeeja KP05057002015-07-09 15:20:11 +0530215 int ret, dma_id;
Jeeja KPa40e6932015-07-09 15:20:08 +0530216
217 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
218 ret = skl_substream_alloc_pages(ebus, substream,
219 params_buffer_bytes(params));
220 if (ret < 0)
221 return ret;
222
223 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
224 runtime->rate, runtime->channels, runtime->format);
225
Jeeja KP05057002015-07-09 15:20:11 +0530226 dma_id = hdac_stream(stream)->stream_tag - 1;
227 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
228
Jeeja KPb663a8c2015-10-07 11:31:57 +0100229 p_params.s_fmt = snd_pcm_format_width(params_format(params));
230 p_params.ch = params_channels(params);
231 p_params.s_freq = params_rate(params);
232 p_params.host_dma_id = dma_id;
233 p_params.stream = substream->stream;
234
235 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
236 if (m_cfg)
237 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
238
Jeeja KPa40e6932015-07-09 15:20:08 +0530239 return 0;
240}
241
242static void skl_pcm_close(struct snd_pcm_substream *substream,
243 struct snd_soc_dai *dai)
244{
245 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530246 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530247 struct skl_dma_params *dma_params = NULL;
248
249 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KP05057002015-07-09 15:20:11 +0530250
251 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530252
253 dma_params = snd_soc_dai_get_dma_data(dai, substream);
254 /*
255 * now we should set this to NULL as we are freeing by the
256 * dma_params
257 */
258 snd_soc_dai_set_dma_data(dai, substream, NULL);
259
Jeeja KPa40e6932015-07-09 15:20:08 +0530260 kfree(dma_params);
261}
262
263static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
264 struct snd_soc_dai *dai)
265{
266 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
267 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
268
269 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
270
271 snd_hdac_stream_cleanup(hdac_stream(stream));
272 hdac_stream(stream)->prepared = 0;
273
274 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
275}
276
Jeeja KPb663a8c2015-10-07 11:31:57 +0100277static int skl_be_hw_params(struct snd_pcm_substream *substream,
278 struct snd_pcm_hw_params *params,
279 struct snd_soc_dai *dai)
280{
281 struct skl_pipe_params p_params = {0};
282
283 p_params.s_fmt = snd_pcm_format_width(params_format(params));
284 p_params.ch = params_channels(params);
285 p_params.s_freq = params_rate(params);
286 p_params.stream = substream->stream;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100287
Jeeja KP4bd073f2015-10-27 09:22:45 +0900288 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100289}
290
Jeeja KPd1730c32015-10-27 09:22:53 +0900291static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
292 int cmd)
293{
294 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
295 struct hdac_bus *bus = ebus_to_hbus(ebus);
296 struct hdac_ext_stream *stream;
297 int start;
298 unsigned long cookie;
299 struct hdac_stream *hstr;
300
301 stream = get_hdac_ext_stream(substream);
302 hstr = hdac_stream(stream);
303
304 if (!hstr->prepared)
305 return -EPIPE;
306
307 switch (cmd) {
308 case SNDRV_PCM_TRIGGER_START:
309 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
310 case SNDRV_PCM_TRIGGER_RESUME:
311 start = 1;
312 break;
313
314 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
315 case SNDRV_PCM_TRIGGER_SUSPEND:
316 case SNDRV_PCM_TRIGGER_STOP:
317 start = 0;
318 break;
319
320 default:
321 return -EINVAL;
322 }
323
324 spin_lock_irqsave(&bus->reg_lock, cookie);
325
326 if (start) {
327 snd_hdac_stream_start(hdac_stream(stream), true);
328 snd_hdac_stream_timecounter_init(hstr, 0);
329 } else {
330 snd_hdac_stream_stop(hdac_stream(stream));
331 }
332
333 spin_unlock_irqrestore(&bus->reg_lock, cookie);
334
335 return 0;
336}
337
Jeeja KPb663a8c2015-10-07 11:31:57 +0100338static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
339 struct snd_soc_dai *dai)
340{
341 struct skl *skl = get_skl_ctx(dai->dev);
342 struct skl_sst *ctx = skl->skl_sst;
343 struct skl_module_cfg *mconfig;
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530344 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
345 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPd1730c32015-10-27 09:22:53 +0900346 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100347
348 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
349 if (!mconfig)
350 return -EIO;
351
352 switch (cmd) {
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530353 case SNDRV_PCM_TRIGGER_RESUME:
354 skl_pcm_prepare(substream, dai);
Jeeja KPd1730c32015-10-27 09:22:53 +0900355 case SNDRV_PCM_TRIGGER_START:
Jeeja KPb663a8c2015-10-07 11:31:57 +0100356 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KPd1730c32015-10-27 09:22:53 +0900357 /*
358 * Start HOST DMA and Start FE Pipe.This is to make sure that
359 * there are no underrun/overrun in the case when the FE
360 * pipeline is started but there is a delay in starting the
361 * DMA channel on the host.
362 */
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530363 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KPd1730c32015-10-27 09:22:53 +0900364 ret = skl_decoupled_trigger(substream, cmd);
365 if (ret < 0)
366 return ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100367 return skl_run_pipe(ctx, mconfig->pipe);
Jeeja KPd1730c32015-10-27 09:22:53 +0900368 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100369
370 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
371 case SNDRV_PCM_TRIGGER_SUSPEND:
Jeeja KPd1730c32015-10-27 09:22:53 +0900372 case SNDRV_PCM_TRIGGER_STOP:
373 /*
374 * Stop FE Pipe first and stop DMA. This is to make sure that
375 * there are no underrun/overrun in the case if there is a delay
376 * between the two operations.
377 */
378 ret = skl_stop_pipe(ctx, mconfig->pipe);
379 if (ret < 0)
380 return ret;
381
382 ret = skl_decoupled_trigger(substream, cmd);
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530383 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
384 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KPd1730c32015-10-27 09:22:53 +0900385 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100386
387 default:
Jeeja KPd1730c32015-10-27 09:22:53 +0900388 return -EINVAL;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100389 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900390
391 return 0;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100392}
393
Jeeja KP05057002015-07-09 15:20:11 +0530394static int skl_link_hw_params(struct snd_pcm_substream *substream,
395 struct snd_pcm_hw_params *params,
396 struct snd_soc_dai *dai)
397{
398 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
399 struct hdac_ext_stream *link_dev;
400 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
401 struct skl_dma_params *dma_params;
402 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100403 struct skl_pipe_params p_params = {0};
Jeeja KP05057002015-07-09 15:20:11 +0530404
Jeeja KP05057002015-07-09 15:20:11 +0530405 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
406 HDAC_EXT_STREAM_TYPE_LINK);
407 if (!link_dev)
408 return -EBUSY;
409
410 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
411
412 /* set the stream tag in the codec dai dma params */
413 dma_params = (struct skl_dma_params *)
414 snd_soc_dai_get_dma_data(codec_dai, substream);
415 if (dma_params)
416 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
417 snd_soc_dai_set_dma_data(codec_dai, substream, (void *)dma_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100418
419 p_params.s_fmt = snd_pcm_format_width(params_format(params));
420 p_params.ch = params_channels(params);
421 p_params.s_freq = params_rate(params);
422 p_params.stream = substream->stream;
423 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
424
Jeeja KP4bd073f2015-10-27 09:22:45 +0900425 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KP05057002015-07-09 15:20:11 +0530426}
427
428static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
429 struct snd_soc_dai *dai)
430{
431 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
432 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
433 struct hdac_ext_stream *link_dev =
434 snd_soc_dai_get_dma_data(dai, substream);
435 unsigned int format_val = 0;
436 struct skl_dma_params *dma_params;
437 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KP05057002015-07-09 15:20:11 +0530438 struct hdac_ext_link *link;
439
Jeeja KP05057002015-07-09 15:20:11 +0530440 if (link_dev->link_prepared) {
441 dev_dbg(dai->dev, "already stream is prepared - returning\n");
442 return 0;
443 }
Jeeja KP05057002015-07-09 15:20:11 +0530444
445 dma_params = (struct skl_dma_params *)
446 snd_soc_dai_get_dma_data(codec_dai, substream);
447 if (dma_params)
448 format_val = dma_params->format;
449 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
450 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
451
452 snd_hdac_ext_link_stream_reset(link_dev);
453
454 snd_hdac_ext_link_stream_setup(link_dev, format_val);
455
456 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
457 if (!link)
458 return -EINVAL;
459
460 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
461 link_dev->link_prepared = 1;
462
463 return 0;
464}
465
466static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
467 int cmd, struct snd_soc_dai *dai)
468{
469 struct hdac_ext_stream *link_dev =
470 snd_soc_dai_get_dma_data(dai, substream);
471
472 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
473 switch (cmd) {
474 case SNDRV_PCM_TRIGGER_START:
475 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
476 case SNDRV_PCM_TRIGGER_RESUME:
477 snd_hdac_ext_link_stream_start(link_dev);
478 break;
479
480 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
481 case SNDRV_PCM_TRIGGER_SUSPEND:
482 case SNDRV_PCM_TRIGGER_STOP:
483 snd_hdac_ext_link_stream_clear(link_dev);
484 break;
485
486 default:
487 return -EINVAL;
488 }
489 return 0;
490}
491
492static int skl_link_hw_free(struct snd_pcm_substream *substream,
493 struct snd_soc_dai *dai)
494{
495 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
496 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
497 struct hdac_ext_stream *link_dev =
498 snd_soc_dai_get_dma_data(dai, substream);
499 struct hdac_ext_link *link;
500
501 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
502
503 link_dev->link_prepared = 0;
504
505 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
506 if (!link)
507 return -EINVAL;
508
509 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
510 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
511 return 0;
512}
513
Jeeja KPa40e6932015-07-09 15:20:08 +0530514static struct snd_soc_dai_ops skl_pcm_dai_ops = {
515 .startup = skl_pcm_open,
516 .shutdown = skl_pcm_close,
517 .prepare = skl_pcm_prepare,
518 .hw_params = skl_pcm_hw_params,
519 .hw_free = skl_pcm_hw_free,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100520 .trigger = skl_pcm_trigger,
Jeeja KPa40e6932015-07-09 15:20:08 +0530521};
522
Jeeja KP05057002015-07-09 15:20:11 +0530523static struct snd_soc_dai_ops skl_dmic_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100524 .hw_params = skl_be_hw_params,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100525};
526
527static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100528 .hw_params = skl_be_hw_params,
Jeeja KP05057002015-07-09 15:20:11 +0530529};
530
531static struct snd_soc_dai_ops skl_link_dai_ops = {
Jeeja KP05057002015-07-09 15:20:11 +0530532 .prepare = skl_link_pcm_prepare,
533 .hw_params = skl_link_hw_params,
534 .hw_free = skl_link_hw_free,
535 .trigger = skl_link_pcm_trigger,
Jeeja KP05057002015-07-09 15:20:11 +0530536};
537
Jeeja KPa40e6932015-07-09 15:20:08 +0530538static struct snd_soc_dai_driver skl_platform_dai[] = {
539{
540 .name = "System Pin",
541 .ops = &skl_pcm_dai_ops,
542 .playback = {
543 .stream_name = "System Playback",
544 .channels_min = HDA_MONO,
545 .channels_max = HDA_STEREO,
546 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
547 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
548 },
549 .capture = {
550 .stream_name = "System Capture",
551 .channels_min = HDA_MONO,
552 .channels_max = HDA_STEREO,
553 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
554 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
555 },
556},
557{
Jeeja KP05057002015-07-09 15:20:11 +0530558 .name = "Reference Pin",
559 .ops = &skl_pcm_dai_ops,
560 .capture = {
561 .stream_name = "Reference Capture",
562 .channels_min = HDA_MONO,
563 .channels_max = HDA_STEREO,
564 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
565 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
566 },
567},
568{
Jeeja KPa40e6932015-07-09 15:20:08 +0530569 .name = "Deepbuffer Pin",
570 .ops = &skl_pcm_dai_ops,
571 .playback = {
572 .stream_name = "Deepbuffer Playback",
573 .channels_min = HDA_STEREO,
574 .channels_max = HDA_STEREO,
575 .rates = SNDRV_PCM_RATE_48000,
576 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
577 },
578},
579{
580 .name = "LowLatency Pin",
581 .ops = &skl_pcm_dai_ops,
582 .playback = {
583 .stream_name = "Low Latency Playback",
584 .channels_min = HDA_STEREO,
585 .channels_max = HDA_STEREO,
586 .rates = SNDRV_PCM_RATE_48000,
587 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
588 },
589},
Jeeja KP05057002015-07-09 15:20:11 +0530590/* BE CPU Dais */
591{
Jeeja KPb663a8c2015-10-07 11:31:57 +0100592 .name = "SSP0 Pin",
593 .ops = &skl_be_ssp_dai_ops,
594 .playback = {
595 .stream_name = "ssp0 Tx",
596 .channels_min = HDA_STEREO,
597 .channels_max = HDA_STEREO,
598 .rates = SNDRV_PCM_RATE_48000,
599 .formats = SNDRV_PCM_FMTBIT_S16_LE,
600 },
601 .capture = {
602 .stream_name = "ssp0 Rx",
603 .channels_min = HDA_STEREO,
604 .channels_max = HDA_STEREO,
605 .rates = SNDRV_PCM_RATE_48000,
606 .formats = SNDRV_PCM_FMTBIT_S16_LE,
607 },
608},
609{
Jeeja KPc80fd4d2015-11-05 22:53:06 +0530610 .name = "SSP1 Pin",
611 .ops = &skl_be_ssp_dai_ops,
612 .playback = {
613 .stream_name = "ssp1 Tx",
614 .channels_min = HDA_STEREO,
615 .channels_max = HDA_STEREO,
616 .rates = SNDRV_PCM_RATE_48000,
617 .formats = SNDRV_PCM_FMTBIT_S16_LE,
618 },
619 .capture = {
620 .stream_name = "ssp1 Rx",
621 .channels_min = HDA_STEREO,
622 .channels_max = HDA_STEREO,
623 .rates = SNDRV_PCM_RATE_48000,
624 .formats = SNDRV_PCM_FMTBIT_S16_LE,
625 },
626},
627{
Jeeja KP05057002015-07-09 15:20:11 +0530628 .name = "iDisp Pin",
629 .ops = &skl_link_dai_ops,
630 .playback = {
631 .stream_name = "iDisp Tx",
632 .channels_min = HDA_STEREO,
633 .channels_max = HDA_STEREO,
634 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
635 .formats = SNDRV_PCM_FMTBIT_S16_LE,
636 },
637},
638{
639 .name = "DMIC01 Pin",
640 .ops = &skl_dmic_dai_ops,
641 .capture = {
642 .stream_name = "DMIC01 Rx",
643 .channels_min = HDA_STEREO,
644 .channels_max = HDA_STEREO,
645 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
646 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
647 },
648},
649{
Jeeja KP05057002015-07-09 15:20:11 +0530650 .name = "HD-Codec Pin",
651 .ops = &skl_link_dai_ops,
652 .playback = {
653 .stream_name = "HD-Codec Tx",
654 .channels_min = HDA_STEREO,
655 .channels_max = HDA_STEREO,
656 .rates = SNDRV_PCM_RATE_48000,
657 .formats = SNDRV_PCM_FMTBIT_S16_LE,
658 },
659 .capture = {
660 .stream_name = "HD-Codec Rx",
661 .channels_min = HDA_STEREO,
662 .channels_max = HDA_STEREO,
663 .rates = SNDRV_PCM_RATE_48000,
664 .formats = SNDRV_PCM_FMTBIT_S16_LE,
665 },
666},
Jeeja KPa40e6932015-07-09 15:20:08 +0530667};
668
669static int skl_platform_open(struct snd_pcm_substream *substream)
670{
671 struct snd_pcm_runtime *runtime;
672 struct snd_soc_pcm_runtime *rtd = substream->private_data;
673 struct snd_soc_dai_link *dai_link = rtd->dai_link;
674
675 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
676 dai_link->cpu_dai_name);
677
678 runtime = substream->runtime;
679 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
680
681 return 0;
682}
683
Jeeja KPb663a8c2015-10-07 11:31:57 +0100684static int skl_coupled_trigger(struct snd_pcm_substream *substream,
Jeeja KPa40e6932015-07-09 15:20:08 +0530685 int cmd)
686{
687 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
688 struct hdac_bus *bus = ebus_to_hbus(ebus);
689 struct hdac_ext_stream *stream;
690 struct snd_pcm_substream *s;
691 bool start;
692 int sbits = 0;
693 unsigned long cookie;
694 struct hdac_stream *hstr;
695
696 stream = get_hdac_ext_stream(substream);
697 hstr = hdac_stream(stream);
698
699 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
700
701 if (!hstr->prepared)
702 return -EPIPE;
703
704 switch (cmd) {
705 case SNDRV_PCM_TRIGGER_START:
706 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
707 case SNDRV_PCM_TRIGGER_RESUME:
708 start = true;
709 break;
710
711 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
712 case SNDRV_PCM_TRIGGER_SUSPEND:
713 case SNDRV_PCM_TRIGGER_STOP:
714 start = false;
715 break;
716
717 default:
718 return -EINVAL;
719 }
720
721 snd_pcm_group_for_each_entry(s, substream) {
722 if (s->pcm->card != substream->pcm->card)
723 continue;
724 stream = get_hdac_ext_stream(s);
725 sbits |= 1 << hdac_stream(stream)->index;
726 snd_pcm_trigger_done(s, substream);
727 }
728
729 spin_lock_irqsave(&bus->reg_lock, cookie);
730
731 /* first, set SYNC bits of corresponding streams */
732 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
733
734 snd_pcm_group_for_each_entry(s, substream) {
735 if (s->pcm->card != substream->pcm->card)
736 continue;
737 stream = get_hdac_ext_stream(s);
738 if (start)
739 snd_hdac_stream_start(hdac_stream(stream), true);
740 else
741 snd_hdac_stream_stop(hdac_stream(stream));
742 }
743 spin_unlock_irqrestore(&bus->reg_lock, cookie);
744
745 snd_hdac_stream_sync(hstr, start, sbits);
746
747 spin_lock_irqsave(&bus->reg_lock, cookie);
748
749 /* reset SYNC bits */
750 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
751 if (start)
752 snd_hdac_stream_timecounter_init(hstr, sbits);
753 spin_unlock_irqrestore(&bus->reg_lock, cookie);
754
755 return 0;
756}
757
Jeeja KP05057002015-07-09 15:20:11 +0530758static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
759 int cmd)
760{
761 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
762
Jeeja KPd1730c32015-10-27 09:22:53 +0900763 if (!ebus->ppcap)
Jeeja KPb663a8c2015-10-07 11:31:57 +0100764 return skl_coupled_trigger(substream, cmd);
Jeeja KPd1730c32015-10-27 09:22:53 +0900765
766 return 0;
Jeeja KP05057002015-07-09 15:20:11 +0530767}
768
Jeeja KPa40e6932015-07-09 15:20:08 +0530769/* calculate runtime delay from LPIB */
770static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
771 struct hdac_ext_stream *sstream,
772 unsigned int pos)
773{
774 struct hdac_bus *bus = ebus_to_hbus(ebus);
775 struct hdac_stream *hstream = hdac_stream(sstream);
776 struct snd_pcm_substream *substream = hstream->substream;
777 int stream = substream->stream;
778 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
779 int delay;
780
781 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
782 delay = pos - lpib_pos;
783 else
784 delay = lpib_pos - pos;
785
786 if (delay < 0) {
787 if (delay >= hstream->delay_negative_threshold)
788 delay = 0;
789 else
790 delay += hstream->bufsize;
791 }
792
793 if (delay >= hstream->period_bytes) {
794 dev_info(bus->dev,
795 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
796 delay, hstream->period_bytes);
797 delay = 0;
798 }
799
800 return bytes_to_frames(substream->runtime, delay);
801}
802
803static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
804 int codec_delay)
805{
806 struct hdac_stream *hstr = hdac_stream(hstream);
807 struct snd_pcm_substream *substream = hstr->substream;
Vinod Koulc7b2a442015-10-30 20:34:20 +0530808 struct hdac_ext_bus *ebus;
Jeeja KPa40e6932015-07-09 15:20:08 +0530809 unsigned int pos;
810 int delay;
811
812 /* use the position buffer as default */
813 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
814
815 if (pos >= hdac_stream(hstream)->bufsize)
816 pos = 0;
817
818 if (substream->runtime) {
Vinod Koulc7b2a442015-10-30 20:34:20 +0530819 ebus = get_bus_ctx(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530820 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
821 + codec_delay;
822 substream->runtime->delay += delay;
823 }
824
825 return pos;
826}
827
828static snd_pcm_uframes_t skl_platform_pcm_pointer
829 (struct snd_pcm_substream *substream)
830{
831 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
832
833 return bytes_to_frames(substream->runtime,
834 skl_get_position(hstream, 0));
835}
836
837static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
838 u64 nsec)
839{
840 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
841 struct snd_soc_dai *codec_dai = rtd->codec_dai;
842 u64 codec_frames, codec_nsecs;
843
844 if (!codec_dai->driver->ops->delay)
845 return nsec;
846
847 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
848 codec_nsecs = div_u64(codec_frames * 1000000000LL,
849 substream->runtime->rate);
850
851 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
852 return nsec + codec_nsecs;
853
854 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
855}
856
857static int skl_get_time_info(struct snd_pcm_substream *substream,
858 struct timespec *system_ts, struct timespec *audio_ts,
859 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
860 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
861{
862 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
863 struct hdac_stream *hstr = hdac_stream(sstream);
864 u64 nsec;
865
866 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
867 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
868
869 snd_pcm_gettime(substream->runtime, system_ts);
870
871 nsec = timecounter_read(&hstr->tc);
872 nsec = div_u64(nsec, 3); /* can be optimized */
873 if (audio_tstamp_config->report_delay)
874 nsec = skl_adjust_codec_delay(substream, nsec);
875
876 *audio_ts = ns_to_timespec(nsec);
877
878 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
879 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
880 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
881
882 } else {
883 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
884 }
885
886 return 0;
887}
888
889static struct snd_pcm_ops skl_platform_ops = {
890 .open = skl_platform_open,
891 .ioctl = snd_pcm_lib_ioctl,
892 .trigger = skl_platform_pcm_trigger,
893 .pointer = skl_platform_pcm_pointer,
894 .get_time_info = skl_get_time_info,
895 .mmap = snd_pcm_lib_default_mmap,
896 .page = snd_pcm_sgbuf_ops_page,
897};
898
899static void skl_pcm_free(struct snd_pcm *pcm)
900{
901 snd_pcm_lib_preallocate_free_for_all(pcm);
902}
903
904#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
905
906static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
907{
908 struct snd_soc_dai *dai = rtd->cpu_dai;
909 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
910 struct snd_pcm *pcm = rtd->pcm;
911 unsigned int size;
912 int retval = 0;
913 struct skl *skl = ebus_to_skl(ebus);
914
915 if (dai->driver->playback.channels_min ||
916 dai->driver->capture.channels_min) {
917 /* buffer pre-allocation */
918 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
919 if (size > MAX_PREALLOC_SIZE)
920 size = MAX_PREALLOC_SIZE;
921 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
922 SNDRV_DMA_TYPE_DEV_SG,
923 snd_dma_pci_data(skl->pci),
924 size, MAX_PREALLOC_SIZE);
925 if (retval) {
926 dev_err(dai->dev, "dma buffer allocationf fail\n");
927 return retval;
928 }
929 }
930
931 return retval;
932}
933
Jeeja KPb663a8c2015-10-07 11:31:57 +0100934static int skl_platform_soc_probe(struct snd_soc_platform *platform)
935{
936 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
937
938 if (ebus->ppcap)
939 return skl_tplg_init(platform, ebus);
940
941 return 0;
942}
Jeeja KPa40e6932015-07-09 15:20:08 +0530943static struct snd_soc_platform_driver skl_platform_drv = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100944 .probe = skl_platform_soc_probe,
Jeeja KPa40e6932015-07-09 15:20:08 +0530945 .ops = &skl_platform_ops,
946 .pcm_new = skl_pcm_new,
947 .pcm_free = skl_pcm_free,
948};
949
950static const struct snd_soc_component_driver skl_component = {
951 .name = "pcm",
952};
953
954int skl_platform_register(struct device *dev)
955{
956 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100957 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
958 struct skl *skl = ebus_to_skl(ebus);
959
960 INIT_LIST_HEAD(&skl->ppl_list);
Jeeja KPa40e6932015-07-09 15:20:08 +0530961
962 ret = snd_soc_register_platform(dev, &skl_platform_drv);
963 if (ret) {
964 dev_err(dev, "soc platform registration failed %d\n", ret);
965 return ret;
966 }
967 ret = snd_soc_register_component(dev, &skl_component,
968 skl_platform_dai,
969 ARRAY_SIZE(skl_platform_dai));
970 if (ret) {
971 dev_err(dev, "soc component registration failed %d\n", ret);
972 snd_soc_unregister_platform(dev);
973 }
974
975 return ret;
976
977}
978
979int skl_platform_unregister(struct device *dev)
980{
981 snd_soc_unregister_component(dev);
982 snd_soc_unregister_platform(dev);
983 return 0;
984}