Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
| 8 | * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of version 2 of the GNU General Public License as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 22 | * USA |
| 23 | * |
| 24 | * The full GNU General Public License is included in this distribution |
| 25 | * in the file called LICENSE.GPL. |
| 26 | * |
| 27 | * Contact Information: |
| 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
| 29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 30 | * |
| 31 | * BSD LICENSE |
| 32 | * |
| 33 | * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved. |
| 34 | * All rights reserved. |
| 35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without |
| 37 | * modification, are permitted provided that the following conditions |
| 38 | * are met: |
| 39 | * |
| 40 | * * Redistributions of source code must retain the above copyright |
| 41 | * notice, this list of conditions and the following disclaimer. |
| 42 | * * Redistributions in binary form must reproduce the above copyright |
| 43 | * notice, this list of conditions and the following disclaimer in |
| 44 | * the documentation and/or other materials provided with the |
| 45 | * distribution. |
| 46 | * * Neither the name Intel Corporation nor the names of its |
| 47 | * contributors may be used to endorse or promote products derived |
| 48 | * from this software without specific prior written permission. |
| 49 | * |
| 50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 61 | * |
| 62 | *****************************************************************************/ |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 63 | #include <linux/interrupt.h> |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 64 | #include <linux/debugfs.h> |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 65 | #include <linux/bitops.h> |
| 66 | #include <linux/gfp.h> |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 67 | |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 68 | #include "iwl-trans.h" |
Johannes Berg | c17d068 | 2011-09-15 11:46:42 -0700 | [diff] [blame] | 69 | #include "iwl-trans-pcie-int.h" |
Emmanuel Grumbach | 522376d | 2011-09-06 09:31:19 -0700 | [diff] [blame] | 70 | #include "iwl-csr.h" |
| 71 | #include "iwl-prph.h" |
Emmanuel Grumbach | 48f20d3 | 2011-08-25 23:10:36 -0700 | [diff] [blame] | 72 | #include "iwl-shared.h" |
Emmanuel Grumbach | 522376d | 2011-09-06 09:31:19 -0700 | [diff] [blame] | 73 | #include "iwl-eeprom.h" |
Emmanuel Grumbach | 7a10e3e4 | 2011-09-06 09:31:21 -0700 | [diff] [blame] | 74 | #include "iwl-agn-hw.h" |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 75 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 76 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 77 | { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 78 | struct iwl_trans_pcie *trans_pcie = |
| 79 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 80 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
| 81 | struct device *dev = bus(trans)->dev; |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 82 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 83 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 84 | |
| 85 | spin_lock_init(&rxq->lock); |
| 86 | INIT_LIST_HEAD(&rxq->rx_free); |
| 87 | INIT_LIST_HEAD(&rxq->rx_used); |
| 88 | |
| 89 | if (WARN_ON(rxq->bd || rxq->rb_stts)) |
| 90 | return -EINVAL; |
| 91 | |
| 92 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 93 | rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
| 94 | &rxq->bd_dma, GFP_KERNEL); |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 95 | if (!rxq->bd) |
| 96 | goto err_bd; |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 97 | memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE); |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 98 | |
| 99 | /*Allocate the driver's pointer to receive buffer status */ |
| 100 | rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts), |
| 101 | &rxq->rb_stts_dma, GFP_KERNEL); |
| 102 | if (!rxq->rb_stts) |
| 103 | goto err_rb_stts; |
| 104 | memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts)); |
| 105 | |
| 106 | return 0; |
| 107 | |
| 108 | err_rb_stts: |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 109 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
| 110 | rxq->bd, rxq->bd_dma); |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 111 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
| 112 | rxq->bd = NULL; |
| 113 | err_bd: |
| 114 | return -ENOMEM; |
| 115 | } |
| 116 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 117 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 118 | { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 119 | struct iwl_trans_pcie *trans_pcie = |
| 120 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 121 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 122 | int i; |
| 123 | |
| 124 | /* Fill the rx_used queue with _all_ of the Rx buffers */ |
| 125 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { |
| 126 | /* In the reset function, these buffers may have been allocated |
| 127 | * to an SKB, so we need to unmap and free potential storage */ |
| 128 | if (rxq->pool[i].page != NULL) { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 129 | dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma, |
| 130 | PAGE_SIZE << hw_params(trans).rx_page_order, |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 131 | DMA_FROM_DEVICE); |
Emmanuel Grumbach | 790428b | 2011-08-25 23:11:05 -0700 | [diff] [blame] | 132 | __free_pages(rxq->pool[i].page, |
| 133 | hw_params(trans).rx_page_order); |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 134 | rxq->pool[i].page = NULL; |
| 135 | } |
| 136 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); |
| 137 | } |
| 138 | } |
| 139 | |
Emmanuel Grumbach | fd65693 | 2011-08-25 23:11:19 -0700 | [diff] [blame] | 140 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 141 | struct iwl_rx_queue *rxq) |
| 142 | { |
| 143 | u32 rb_size; |
| 144 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ |
Johannes Berg | c17d068 | 2011-09-15 11:46:42 -0700 | [diff] [blame] | 145 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 146 | |
| 147 | if (iwlagn_mod_params.amsdu_size_8K) |
| 148 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; |
| 149 | else |
| 150 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; |
| 151 | |
| 152 | /* Stop Rx DMA */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 153 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 154 | |
| 155 | /* Reset driver's Rx queue write index */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 156 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 157 | |
| 158 | /* Tell device where to find RBD circular buffer in DRAM */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 159 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 160 | (u32)(rxq->bd_dma >> 8)); |
| 161 | |
| 162 | /* Tell device where in DRAM to update its Rx status */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 163 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG, |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 164 | rxq->rb_stts_dma >> 4); |
| 165 | |
| 166 | /* Enable Rx DMA |
| 167 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in |
| 168 | * the credit mechanism in 5000 HW RX FIFO |
| 169 | * Direct rx interrupts to hosts |
| 170 | * Rx buffer size 4 or 8k |
| 171 | * RB timeout 0x10 |
| 172 | * 256 RBDs |
| 173 | */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 174 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 175 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
| 176 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | |
| 177 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
| 178 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | |
| 179 | rb_size| |
| 180 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| |
| 181 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); |
| 182 | |
| 183 | /* Set interrupt coalescing timer to default (2048 usecs) */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 184 | iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 185 | } |
| 186 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 187 | static int iwl_rx_init(struct iwl_trans *trans) |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 188 | { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 189 | struct iwl_trans_pcie *trans_pcie = |
| 190 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 191 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
| 192 | |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 193 | int i, err; |
| 194 | unsigned long flags; |
| 195 | |
| 196 | if (!rxq->bd) { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 197 | err = iwl_trans_rx_alloc(trans); |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 198 | if (err) |
| 199 | return err; |
| 200 | } |
| 201 | |
| 202 | spin_lock_irqsave(&rxq->lock, flags); |
| 203 | INIT_LIST_HEAD(&rxq->rx_free); |
| 204 | INIT_LIST_HEAD(&rxq->rx_used); |
| 205 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 206 | iwl_trans_rxq_free_rx_bufs(trans); |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 207 | |
| 208 | for (i = 0; i < RX_QUEUE_SIZE; i++) |
| 209 | rxq->queue[i] = NULL; |
| 210 | |
| 211 | /* Set us so that we have processed and used all buffers, but have |
| 212 | * not restocked the Rx queue with fresh buffers */ |
| 213 | rxq->read = rxq->write = 0; |
| 214 | rxq->write_actual = 0; |
| 215 | rxq->free_count = 0; |
| 216 | spin_unlock_irqrestore(&rxq->lock, flags); |
| 217 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 218 | iwlagn_rx_replenish(trans); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 219 | |
Emmanuel Grumbach | fd65693 | 2011-08-25 23:11:19 -0700 | [diff] [blame] | 220 | iwl_trans_rx_hw_init(trans, rxq); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 221 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 222 | spin_lock_irqsave(&trans->shrd->lock, flags); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 223 | rxq->need_update = 1; |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 224 | iwl_rx_queue_update_write_ptr(trans, rxq); |
| 225 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
Emmanuel Grumbach | ab697a9 | 2011-07-11 07:35:34 -0700 | [diff] [blame] | 226 | |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 227 | return 0; |
| 228 | } |
| 229 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 230 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 231 | { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 232 | struct iwl_trans_pcie *trans_pcie = |
| 233 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 234 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
| 235 | |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 236 | unsigned long flags; |
| 237 | |
| 238 | /*if rxq->bd is NULL, it means that nothing has been allocated, |
| 239 | * exit now */ |
| 240 | if (!rxq->bd) { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 241 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 242 | return; |
| 243 | } |
| 244 | |
| 245 | spin_lock_irqsave(&rxq->lock, flags); |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 246 | iwl_trans_rxq_free_rx_bufs(trans); |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 247 | spin_unlock_irqrestore(&rxq->lock, flags); |
| 248 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 249 | dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 250 | rxq->bd, rxq->bd_dma); |
| 251 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
| 252 | rxq->bd = NULL; |
| 253 | |
| 254 | if (rxq->rb_stts) |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 255 | dma_free_coherent(bus(trans)->dev, |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 256 | sizeof(struct iwl_rb_status), |
| 257 | rxq->rb_stts, rxq->rb_stts_dma); |
| 258 | else |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 259 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
Emmanuel Grumbach | a0f6b0a | 2011-06-21 14:25:45 +0300 | [diff] [blame] | 260 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
| 261 | rxq->rb_stts = NULL; |
| 262 | } |
| 263 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 264 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
Emmanuel Grumbach | c2c52e8 | 2011-07-08 08:46:11 -0700 | [diff] [blame] | 265 | { |
| 266 | |
| 267 | /* stop Rx DMA */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 268 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
| 269 | return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG, |
Emmanuel Grumbach | c2c52e8 | 2011-07-08 08:46:11 -0700 | [diff] [blame] | 270 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
| 271 | } |
| 272 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 273 | static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 274 | struct iwl_dma_ptr *ptr, size_t size) |
| 275 | { |
| 276 | if (WARN_ON(ptr->addr)) |
| 277 | return -EINVAL; |
| 278 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 279 | ptr->addr = dma_alloc_coherent(bus(trans)->dev, size, |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 280 | &ptr->dma, GFP_KERNEL); |
| 281 | if (!ptr->addr) |
| 282 | return -ENOMEM; |
| 283 | ptr->size = size; |
| 284 | return 0; |
| 285 | } |
| 286 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 287 | static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 288 | struct iwl_dma_ptr *ptr) |
| 289 | { |
| 290 | if (unlikely(!ptr->addr)) |
| 291 | return; |
| 292 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 293 | dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 294 | memset(ptr, 0, sizeof(*ptr)); |
| 295 | } |
| 296 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 297 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
| 298 | struct iwl_tx_queue *txq, int slots_num, |
| 299 | u32 txq_id) |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 300 | { |
Emmanuel Grumbach | ab9e212 | 2011-08-25 23:11:10 -0700 | [diff] [blame] | 301 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 302 | int i; |
| 303 | |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 304 | if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds)) |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 305 | return -EINVAL; |
| 306 | |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 307 | txq->q.n_window = slots_num; |
| 308 | |
Johannes Berg | c17d068 | 2011-09-15 11:46:42 -0700 | [diff] [blame] | 309 | txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num, GFP_KERNEL); |
| 310 | txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num, GFP_KERNEL); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 311 | |
| 312 | if (!txq->meta || !txq->cmd) |
| 313 | goto error; |
| 314 | |
Emmanuel Grumbach | dfa2bdb | 2011-08-25 23:11:23 -0700 | [diff] [blame] | 315 | if (txq_id == trans->shrd->cmd_queue) |
| 316 | for (i = 0; i < slots_num; i++) { |
| 317 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), |
| 318 | GFP_KERNEL); |
| 319 | if (!txq->cmd[i]) |
| 320 | goto error; |
| 321 | } |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 322 | |
| 323 | /* Alloc driver data array and TFD circular buffer */ |
| 324 | /* Driver private data, only for Tx (not command) queues, |
| 325 | * not shared with device. */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 326 | if (txq_id != trans->shrd->cmd_queue) { |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 327 | txq->skbs = kzalloc(sizeof(txq->skbs[0]) * |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 328 | TFD_QUEUE_SIZE_MAX, GFP_KERNEL); |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 329 | if (!txq->skbs) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 330 | IWL_ERR(trans, "kmalloc for auxiliary BD " |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 331 | "structures failed\n"); |
| 332 | goto error; |
| 333 | } |
| 334 | } else { |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 335 | txq->skbs = NULL; |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | /* Circular buffer of transmit frame descriptors (TFDs), |
| 339 | * shared with device */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 340 | txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz, |
| 341 | &txq->q.dma_addr, GFP_KERNEL); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 342 | if (!txq->tfds) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 343 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 344 | goto error; |
| 345 | } |
| 346 | txq->q.id = txq_id; |
| 347 | |
| 348 | return 0; |
| 349 | error: |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 350 | kfree(txq->skbs); |
| 351 | txq->skbs = NULL; |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 352 | /* since txq->cmd has been zeroed, |
| 353 | * all non allocated cmd[i] will be NULL */ |
Emmanuel Grumbach | dfa2bdb | 2011-08-25 23:11:23 -0700 | [diff] [blame] | 354 | if (txq->cmd && txq_id == trans->shrd->cmd_queue) |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 355 | for (i = 0; i < slots_num; i++) |
| 356 | kfree(txq->cmd[i]); |
| 357 | kfree(txq->meta); |
| 358 | kfree(txq->cmd); |
| 359 | txq->meta = NULL; |
| 360 | txq->cmd = NULL; |
| 361 | |
| 362 | return -ENOMEM; |
| 363 | |
| 364 | } |
| 365 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 366 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 367 | int slots_num, u32 txq_id) |
| 368 | { |
| 369 | int ret; |
| 370 | |
| 371 | txq->need_update = 0; |
| 372 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); |
| 373 | |
| 374 | /* |
| 375 | * For the default queues 0-3, set up the swq_id |
| 376 | * already -- all others need to get one later |
| 377 | * (if they need one at all). |
| 378 | */ |
| 379 | if (txq_id < 4) |
| 380 | iwl_set_swq_id(txq, txq_id, txq_id); |
| 381 | |
| 382 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise |
| 383 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ |
| 384 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); |
| 385 | |
| 386 | /* Initialize queue's high/low-water marks, and head/tail indexes */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 387 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 388 | txq_id); |
| 389 | if (ret) |
| 390 | return ret; |
| 391 | |
| 392 | /* |
| 393 | * Tell nic where to find circular buffer of Tx Frame Descriptors for |
| 394 | * given Tx queue, and enable the DMA channel used for that queue. |
| 395 | * Circular buffer (TFD queue in DRAM) physical base address */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 396 | iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id), |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 397 | txq->q.dma_addr >> 8); |
| 398 | |
| 399 | return 0; |
| 400 | } |
| 401 | |
| 402 | /** |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 403 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's |
| 404 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 405 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 406 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 407 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 408 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 409 | struct iwl_queue *q = &txq->q; |
Emmanuel Grumbach | 39644e9 | 2011-09-15 11:46:29 -0700 | [diff] [blame] | 410 | enum dma_data_direction dma_dir; |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 411 | |
| 412 | if (!q->n_bd) |
| 413 | return; |
| 414 | |
Emmanuel Grumbach | 39644e9 | 2011-09-15 11:46:29 -0700 | [diff] [blame] | 415 | /* In the command queue, all the TBs are mapped as BIDI |
| 416 | * so unmap them as such. |
| 417 | */ |
| 418 | if (txq_id == trans->shrd->cmd_queue) |
| 419 | dma_dir = DMA_BIDIRECTIONAL; |
| 420 | else |
| 421 | dma_dir = DMA_TO_DEVICE; |
| 422 | |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 423 | while (q->write_ptr != q->read_ptr) { |
| 424 | /* The read_ptr needs to bound by q->n_window */ |
Emmanuel Grumbach | 39644e9 | 2011-09-15 11:46:29 -0700 | [diff] [blame] | 425 | iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr), |
| 426 | dma_dir); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 427 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | /** |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 432 | * iwl_tx_queue_free - Deallocate DMA queue. |
| 433 | * @txq: Transmit queue to deallocate. |
| 434 | * |
| 435 | * Empty queue by removing and destroying all BD's. |
| 436 | * Free all buffers. |
| 437 | * 0-fill, but do not free "txq" descriptor structure. |
| 438 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 439 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 440 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 441 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 442 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 443 | struct device *dev = bus(trans)->dev; |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 444 | int i; |
| 445 | if (WARN_ON(!txq)) |
| 446 | return; |
| 447 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 448 | iwl_tx_queue_unmap(trans, txq_id); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 449 | |
| 450 | /* De-alloc array of command/tx buffers */ |
Emmanuel Grumbach | dfa2bdb | 2011-08-25 23:11:23 -0700 | [diff] [blame] | 451 | |
| 452 | if (txq_id == trans->shrd->cmd_queue) |
| 453 | for (i = 0; i < txq->q.n_window; i++) |
| 454 | kfree(txq->cmd[i]); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 455 | |
| 456 | /* De-alloc circular buffer of TFDs */ |
| 457 | if (txq->q.n_bd) { |
Emmanuel Grumbach | ab9e212 | 2011-08-25 23:11:10 -0700 | [diff] [blame] | 458 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 459 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
| 460 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); |
| 461 | } |
| 462 | |
| 463 | /* De-alloc array of per-TFD driver data */ |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 464 | kfree(txq->skbs); |
| 465 | txq->skbs = NULL; |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 466 | |
| 467 | /* deallocate arrays */ |
| 468 | kfree(txq->cmd); |
| 469 | kfree(txq->meta); |
| 470 | txq->cmd = NULL; |
| 471 | txq->meta = NULL; |
| 472 | |
| 473 | /* 0-fill queue descriptor structure */ |
| 474 | memset(txq, 0, sizeof(*txq)); |
| 475 | } |
| 476 | |
| 477 | /** |
| 478 | * iwl_trans_tx_free - Free TXQ Context |
| 479 | * |
| 480 | * Destroy all TX DMA queues and structures |
| 481 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 482 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 483 | { |
| 484 | int txq_id; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 485 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 486 | |
| 487 | /* Tx queues */ |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 488 | if (trans_pcie->txq) { |
Emmanuel Grumbach | d618912 | 2011-08-25 23:10:39 -0700 | [diff] [blame] | 489 | for (txq_id = 0; |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 490 | txq_id < hw_params(trans).max_txq_num; txq_id++) |
| 491 | iwl_tx_queue_free(trans, txq_id); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 492 | } |
| 493 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 494 | kfree(trans_pcie->txq); |
| 495 | trans_pcie->txq = NULL; |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 496 | |
Emmanuel Grumbach | 9d6b2cb | 2011-08-25 23:11:12 -0700 | [diff] [blame] | 497 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 498 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 499 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
Emmanuel Grumbach | 1359ca4 | 2011-07-08 08:46:10 -0700 | [diff] [blame] | 500 | } |
| 501 | |
| 502 | /** |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 503 | * iwl_trans_tx_alloc - allocate TX context |
| 504 | * Allocate all Tx DMA structures and initialize them |
| 505 | * |
| 506 | * @param priv |
| 507 | * @return error code |
| 508 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 509 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 510 | { |
| 511 | int ret; |
| 512 | int txq_id, slots_num; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 513 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 514 | |
Emmanuel Grumbach | fd65693 | 2011-08-25 23:11:19 -0700 | [diff] [blame] | 515 | u16 scd_bc_tbls_size = hw_params(trans).max_txq_num * |
Emmanuel Grumbach | ab9e212 | 2011-08-25 23:11:10 -0700 | [diff] [blame] | 516 | sizeof(struct iwlagn_scd_bc_tbl); |
| 517 | |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 518 | /*It is not allowed to alloc twice, so warn when this happens. |
| 519 | * We cannot rely on the previous allocation, so free and fail */ |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 520 | if (WARN_ON(trans_pcie->txq)) { |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 521 | ret = -EINVAL; |
| 522 | goto error; |
| 523 | } |
| 524 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 525 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
Emmanuel Grumbach | ab9e212 | 2011-08-25 23:11:10 -0700 | [diff] [blame] | 526 | scd_bc_tbls_size); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 527 | if (ret) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 528 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 529 | goto error; |
| 530 | } |
| 531 | |
| 532 | /* Alloc keep-warm buffer */ |
Emmanuel Grumbach | 9d6b2cb | 2011-08-25 23:11:12 -0700 | [diff] [blame] | 533 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 534 | if (ret) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 535 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 536 | goto error; |
| 537 | } |
| 538 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 539 | trans_pcie->txq = kzalloc(sizeof(struct iwl_tx_queue) * |
Emmanuel Grumbach | fd65693 | 2011-08-25 23:11:19 -0700 | [diff] [blame] | 540 | hw_params(trans).max_txq_num, GFP_KERNEL); |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 541 | if (!trans_pcie->txq) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 542 | IWL_ERR(trans, "Not enough memory for txq\n"); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 543 | ret = ENOMEM; |
| 544 | goto error; |
| 545 | } |
| 546 | |
| 547 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 548 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
| 549 | slots_num = (txq_id == trans->shrd->cmd_queue) ? |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 550 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 551 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
| 552 | slots_num, txq_id); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 553 | if (ret) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 554 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 555 | goto error; |
| 556 | } |
| 557 | } |
| 558 | |
| 559 | return 0; |
| 560 | |
| 561 | error: |
Emmanuel Grumbach | ae2c30b | 2011-08-25 23:11:20 -0700 | [diff] [blame] | 562 | iwl_trans_pcie_tx_free(trans); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 563 | |
| 564 | return ret; |
| 565 | } |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 566 | static int iwl_tx_init(struct iwl_trans *trans) |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 567 | { |
| 568 | int ret; |
| 569 | int txq_id, slots_num; |
| 570 | unsigned long flags; |
| 571 | bool alloc = false; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 572 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 573 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 574 | if (!trans_pcie->txq) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 575 | ret = iwl_trans_tx_alloc(trans); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 576 | if (ret) |
| 577 | goto error; |
| 578 | alloc = true; |
| 579 | } |
| 580 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 581 | spin_lock_irqsave(&trans->shrd->lock, flags); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 582 | |
| 583 | /* Turn off all Tx DMA fifos */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 584 | iwl_write_prph(bus(trans), SCD_TXFACT, 0); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 585 | |
| 586 | /* Tell NIC where to find the "keep warm" buffer */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 587 | iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG, |
| 588 | trans_pcie->kw.dma >> 4); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 589 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 590 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 591 | |
| 592 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 593 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
| 594 | slots_num = (txq_id == trans->shrd->cmd_queue) ? |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 595 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 596 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
| 597 | slots_num, txq_id); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 598 | if (ret) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 599 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 600 | goto error; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | return 0; |
| 605 | error: |
| 606 | /*Upon error, free only if we allocated something */ |
| 607 | if (alloc) |
Emmanuel Grumbach | ae2c30b | 2011-08-25 23:11:20 -0700 | [diff] [blame] | 608 | iwl_trans_pcie_tx_free(trans); |
Emmanuel Grumbach | 02aca58 | 2011-06-28 08:58:41 -0700 | [diff] [blame] | 609 | return ret; |
| 610 | } |
| 611 | |
Emmanuel Grumbach | 3e10cae | 2011-09-06 09:31:18 -0700 | [diff] [blame] | 612 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 613 | { |
| 614 | /* |
| 615 | * (for documentation purposes) |
| 616 | * to set power to V_AUX, do: |
| 617 | |
| 618 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 619 | iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 620 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
| 621 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
| 622 | */ |
| 623 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 624 | iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 625 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
| 626 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
| 627 | } |
| 628 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 629 | static int iwl_nic_init(struct iwl_trans *trans) |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 630 | { |
| 631 | unsigned long flags; |
| 632 | |
| 633 | /* nic_init */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 634 | spin_lock_irqsave(&trans->shrd->lock, flags); |
Emmanuel Grumbach | 3e10cae | 2011-09-06 09:31:18 -0700 | [diff] [blame] | 635 | iwl_apm_init(priv(trans)); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 636 | |
| 637 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 638 | iwl_write8(bus(trans), CSR_INT_COALESCING, |
| 639 | IWL_HOST_INT_CALIB_TIMEOUT_DEF); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 640 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 641 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 642 | |
Emmanuel Grumbach | 3e10cae | 2011-09-06 09:31:18 -0700 | [diff] [blame] | 643 | iwl_set_pwr_vmain(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 644 | |
Emmanuel Grumbach | 7a10e3e4 | 2011-09-06 09:31:21 -0700 | [diff] [blame] | 645 | iwl_nic_config(priv(trans)); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 646 | |
| 647 | /* Allocate the RX queue, or reset if it is already allocated */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 648 | iwl_rx_init(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 649 | |
| 650 | /* Allocate or reset and init all Tx and Command queues */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 651 | if (iwl_tx_init(trans)) |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 652 | return -ENOMEM; |
| 653 | |
Emmanuel Grumbach | fd65693 | 2011-08-25 23:11:19 -0700 | [diff] [blame] | 654 | if (hw_params(trans).shadow_reg_enable) { |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 655 | /* enable shadow regs in HW */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 656 | iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 657 | 0x800FFFFF); |
| 658 | } |
| 659 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 660 | set_bit(STATUS_INIT, &trans->shrd->status); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 661 | |
| 662 | return 0; |
| 663 | } |
| 664 | |
| 665 | #define HW_READY_TIMEOUT (50) |
| 666 | |
| 667 | /* Note: returns poll_bit return value, which is >= 0 if success */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 668 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 669 | { |
| 670 | int ret; |
| 671 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 672 | iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 673 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
| 674 | |
| 675 | /* See if we got it */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 676 | ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 677 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
| 678 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
| 679 | HW_READY_TIMEOUT); |
| 680 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 681 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 682 | return ret; |
| 683 | } |
| 684 | |
| 685 | /* Note: returns standard 0/-ERROR code */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 686 | static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans) |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 687 | { |
| 688 | int ret; |
| 689 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 690 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 691 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 692 | ret = iwl_set_hw_ready(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 693 | if (ret >= 0) |
| 694 | return 0; |
| 695 | |
| 696 | /* If HW is not ready, prepare the conditions to check again */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 697 | iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 698 | CSR_HW_IF_CONFIG_REG_PREPARE); |
| 699 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 700 | ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 701 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
| 702 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); |
| 703 | |
| 704 | if (ret < 0) |
| 705 | return ret; |
| 706 | |
| 707 | /* HW should be ready by now, check again. */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 708 | ret = iwl_set_hw_ready(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 709 | if (ret >= 0) |
| 710 | return 0; |
| 711 | return ret; |
| 712 | } |
| 713 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 714 | #define IWL_AC_UNSET -1 |
| 715 | |
| 716 | struct queue_to_fifo_ac { |
| 717 | s8 fifo, ac; |
| 718 | }; |
| 719 | |
| 720 | static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = { |
| 721 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, |
| 722 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, |
| 723 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, |
| 724 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, |
| 725 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, |
| 726 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
| 727 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
| 728 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
| 729 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
| 730 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
| 731 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, |
| 732 | }; |
| 733 | |
| 734 | static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = { |
| 735 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, |
| 736 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, |
| 737 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, |
| 738 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, |
| 739 | { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, }, |
| 740 | { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, }, |
| 741 | { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, }, |
| 742 | { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, }, |
| 743 | { IWL_TX_FIFO_BE_IPAN, 2, }, |
| 744 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, |
| 745 | { IWL_TX_FIFO_AUX, IWL_AC_UNSET, }, |
| 746 | }; |
| 747 | |
| 748 | static const u8 iwlagn_bss_ac_to_fifo[] = { |
| 749 | IWL_TX_FIFO_VO, |
| 750 | IWL_TX_FIFO_VI, |
| 751 | IWL_TX_FIFO_BE, |
| 752 | IWL_TX_FIFO_BK, |
| 753 | }; |
| 754 | static const u8 iwlagn_bss_ac_to_queue[] = { |
| 755 | 0, 1, 2, 3, |
| 756 | }; |
| 757 | static const u8 iwlagn_pan_ac_to_fifo[] = { |
| 758 | IWL_TX_FIFO_VO_IPAN, |
| 759 | IWL_TX_FIFO_VI_IPAN, |
| 760 | IWL_TX_FIFO_BE_IPAN, |
| 761 | IWL_TX_FIFO_BK_IPAN, |
| 762 | }; |
| 763 | static const u8 iwlagn_pan_ac_to_queue[] = { |
| 764 | 7, 6, 5, 4, |
| 765 | }; |
| 766 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 767 | static int iwl_trans_pcie_start_device(struct iwl_trans *trans) |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 768 | { |
| 769 | int ret; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 770 | struct iwl_trans_pcie *trans_pcie = |
| 771 | IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 772 | |
Emmanuel Grumbach | c91bd12 | 2011-08-25 23:11:28 -0700 | [diff] [blame] | 773 | trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 774 | trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue; |
| 775 | trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue; |
| 776 | |
| 777 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo; |
| 778 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo; |
| 779 | |
| 780 | trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0; |
| 781 | trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE; |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 782 | |
Emmanuel Grumbach | c91bd12 | 2011-08-25 23:11:28 -0700 | [diff] [blame] | 783 | if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) && |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 784 | iwl_trans_pcie_prepare_card_hw(trans)) { |
| 785 | IWL_WARN(trans, "Exit HW not ready\n"); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 786 | return -EIO; |
| 787 | } |
| 788 | |
| 789 | /* If platform's RF_KILL switch is NOT set to KILL */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 790 | if (iwl_read32(bus(trans), CSR_GP_CNTRL) & |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 791 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 792 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 793 | else |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 794 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 795 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 796 | if (iwl_is_rfkill(trans->shrd)) { |
Emmanuel Grumbach | 3e10cae | 2011-09-06 09:31:18 -0700 | [diff] [blame] | 797 | iwl_set_hw_rfkill_state(priv(trans), true); |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 798 | iwl_enable_interrupts(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 799 | return -ERFKILL; |
| 800 | } |
| 801 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 802 | iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 803 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 804 | ret = iwl_nic_init(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 805 | if (ret) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 806 | IWL_ERR(trans, "Unable to init nic\n"); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 807 | return ret; |
| 808 | } |
| 809 | |
| 810 | /* make sure rfkill handshake bits are cleared */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 811 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
| 812 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 813 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
| 814 | |
| 815 | /* clear (again), then enable host interrupts */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 816 | iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 817 | iwl_enable_interrupts(trans); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 818 | |
| 819 | /* really make sure rfkill handshake bits are cleared */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 820 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
| 821 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
Emmanuel Grumbach | 392f8b7 | 2011-07-10 15:30:15 +0300 | [diff] [blame] | 822 | |
| 823 | return 0; |
| 824 | } |
| 825 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 826 | /* |
| 827 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
Emmanuel Grumbach | 10b15e6 | 2011-08-25 23:10:43 -0700 | [diff] [blame] | 828 | * must be called under priv->shrd->lock and mac access |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 829 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 830 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 831 | { |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 832 | iwl_write_prph(bus(trans), SCD_TXFACT, mask); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 833 | } |
| 834 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 835 | static void iwl_trans_pcie_tx_start(struct iwl_trans *trans) |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 836 | { |
| 837 | const struct queue_to_fifo_ac *queue_to_fifo; |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 838 | struct iwl_trans_pcie *trans_pcie = |
| 839 | IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 840 | u32 a; |
| 841 | unsigned long flags; |
| 842 | int i, chan; |
| 843 | u32 reg_val; |
| 844 | |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 845 | spin_lock_irqsave(&trans->shrd->lock, flags); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 846 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 847 | trans_pcie->scd_base_addr = |
| 848 | iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR); |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 849 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 850 | /* reset conext data memory */ |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 851 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 852 | a += 4) |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 853 | iwl_write_targ_mem(bus(trans), a, 0); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 854 | /* reset tx status memory */ |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 855 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 856 | a += 4) |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 857 | iwl_write_targ_mem(bus(trans), a, 0); |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 858 | for (; a < trans_pcie->scd_base_addr + |
Emmanuel Grumbach | c91bd12 | 2011-08-25 23:11:28 -0700 | [diff] [blame] | 859 | SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num); |
Emmanuel Grumbach | d618912 | 2011-08-25 23:10:39 -0700 | [diff] [blame] | 860 | a += 4) |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 861 | iwl_write_targ_mem(bus(trans), a, 0); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 862 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 863 | iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR, |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 864 | trans_pcie->scd_bc_tbls.dma >> 10); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 865 | |
| 866 | /* Enable DMA channel */ |
| 867 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 868 | iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 869 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
| 870 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); |
| 871 | |
| 872 | /* Update FH chicken bits */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 873 | reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG); |
| 874 | iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG, |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 875 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
| 876 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 877 | iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL, |
Emmanuel Grumbach | c91bd12 | 2011-08-25 23:11:28 -0700 | [diff] [blame] | 878 | SCD_QUEUECHAIN_SEL_ALL(trans)); |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 879 | iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 880 | |
| 881 | /* initiate the queues */ |
Emmanuel Grumbach | c91bd12 | 2011-08-25 23:11:28 -0700 | [diff] [blame] | 882 | for (i = 0; i < hw_params(trans).max_txq_num; i++) { |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 883 | iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0); |
| 884 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8)); |
| 885 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 886 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 887 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 888 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
| 889 | sizeof(u32), |
| 890 | ((SCD_WIN_SIZE << |
| 891 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & |
| 892 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | |
| 893 | ((SCD_FRAME_LIMIT << |
| 894 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
| 895 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); |
| 896 | } |
| 897 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 898 | iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK, |
Emmanuel Grumbach | 105183b | 2011-08-25 23:11:02 -0700 | [diff] [blame] | 899 | IWL_MASK(0, hw_params(trans).max_txq_num)); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 900 | |
| 901 | /* Activate all Tx DMA/FIFO channels */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 902 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 903 | |
| 904 | /* map queues to FIFOs */ |
Emmanuel Grumbach | 7a10e3e4 | 2011-09-06 09:31:21 -0700 | [diff] [blame] | 905 | if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 906 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; |
| 907 | else |
| 908 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; |
| 909 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 910 | iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 911 | |
| 912 | /* make sure all queue are not stopped */ |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 913 | memset(&trans_pcie->queue_stopped[0], 0, |
| 914 | sizeof(trans_pcie->queue_stopped)); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 915 | for (i = 0; i < 4; i++) |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 916 | atomic_set(&trans_pcie->queue_stop_count[i], 0); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 917 | |
| 918 | /* reset to 0 to enable all the queue first */ |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 919 | trans_pcie->txq_ctx_active_msk = 0; |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 920 | |
Emmanuel Grumbach | effcea1 | 2011-08-25 23:11:03 -0700 | [diff] [blame] | 921 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) < |
Johannes Berg | 72c04ce | 2011-07-23 10:24:40 -0700 | [diff] [blame] | 922 | IWLAGN_FIRST_AMPDU_QUEUE); |
Emmanuel Grumbach | effcea1 | 2011-08-25 23:11:03 -0700 | [diff] [blame] | 923 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) < |
Johannes Berg | 72c04ce | 2011-07-23 10:24:40 -0700 | [diff] [blame] | 924 | IWLAGN_FIRST_AMPDU_QUEUE); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 925 | |
Johannes Berg | 72c04ce | 2011-07-23 10:24:40 -0700 | [diff] [blame] | 926 | for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) { |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 927 | int fifo = queue_to_fifo[i].fifo; |
| 928 | int ac = queue_to_fifo[i].ac; |
| 929 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 930 | iwl_txq_ctx_activate(trans_pcie, i); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 931 | |
| 932 | if (fifo == IWL_TX_FIFO_UNUSED) |
| 933 | continue; |
| 934 | |
| 935 | if (ac != IWL_AC_UNSET) |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 936 | iwl_set_swq_id(&trans_pcie->txq[i], ac, i); |
| 937 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], |
| 938 | fifo, 0); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 939 | } |
| 940 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 941 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 942 | |
| 943 | /* Enable L1-Active */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 944 | iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG, |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 945 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
| 946 | } |
| 947 | |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 948 | /** |
| 949 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels |
| 950 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 951 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 952 | { |
| 953 | int ch, txq_id; |
| 954 | unsigned long flags; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 955 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 956 | |
| 957 | /* Turn off all Tx DMA fifos */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 958 | spin_lock_irqsave(&trans->shrd->lock, flags); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 959 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 960 | iwl_trans_txq_set_sched(trans, 0); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 961 | |
| 962 | /* Stop each Tx DMA channel, and wait for it to be idle */ |
Wey-Yi Guy | 02f6f65 | 2011-07-08 08:46:15 -0700 | [diff] [blame] | 963 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 964 | iwl_write_direct32(bus(trans), |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 965 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 966 | if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG, |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 967 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
| 968 | 1000)) |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 969 | IWL_ERR(trans, "Failing on timeout while stopping" |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 970 | " DMA channel %d [0x%08x]", ch, |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 971 | iwl_read_direct32(bus(trans), |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 972 | FH_TSSR_TX_STATUS_REG)); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 973 | } |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 974 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 975 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 976 | if (!trans_pcie->txq) { |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 977 | IWL_WARN(trans, "Stopping tx queues that aren't allocated..."); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 978 | return 0; |
| 979 | } |
| 980 | |
| 981 | /* Unmap DMA from host system and free skb's */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 982 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) |
| 983 | iwl_tx_queue_unmap(trans, txq_id); |
Emmanuel Grumbach | c170b86 | 2011-07-08 08:46:12 -0700 | [diff] [blame] | 984 | |
| 985 | return 0; |
| 986 | } |
| 987 | |
Emmanuel Grumbach | ae2c30b | 2011-08-25 23:11:20 -0700 | [diff] [blame] | 988 | static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans) |
| 989 | { |
| 990 | unsigned long flags; |
| 991 | struct iwl_trans_pcie *trans_pcie = |
| 992 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 993 | |
| 994 | spin_lock_irqsave(&trans->shrd->lock, flags); |
| 995 | iwl_disable_interrupts(trans); |
| 996 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
| 997 | |
| 998 | /* wait to make sure we flush pending tasklet*/ |
| 999 | synchronize_irq(bus(trans)->irq); |
| 1000 | tasklet_kill(&trans_pcie->irq_tasklet); |
| 1001 | } |
| 1002 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1003 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1004 | { |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1005 | /* stop and reset the on-board processor */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 1006 | iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1007 | |
| 1008 | /* tell the device to stop sending interrupts */ |
Emmanuel Grumbach | ae2c30b | 2011-08-25 23:11:20 -0700 | [diff] [blame] | 1009 | iwl_trans_pcie_disable_sync_irq(trans); |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1010 | |
| 1011 | /* device going down, Stop using ICT table */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1012 | iwl_disable_ict(trans); |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1013 | |
| 1014 | /* |
| 1015 | * If a HW restart happens during firmware loading, |
| 1016 | * then the firmware loading might call this function |
| 1017 | * and later it might be called again due to the |
| 1018 | * restart. So don't process again if the device is |
| 1019 | * already dead. |
| 1020 | */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1021 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) { |
| 1022 | iwl_trans_tx_stop(trans); |
| 1023 | iwl_trans_rx_stop(trans); |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1024 | |
| 1025 | /* Power-down device's busmaster DMA clocks */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 1026 | iwl_write_prph(bus(trans), APMG_CLK_DIS_REG, |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1027 | APMG_CLK_VAL_DMA_CLK_RQT); |
| 1028 | udelay(5); |
| 1029 | } |
| 1030 | |
| 1031 | /* Make sure (redundant) we've released our request to stay awake */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 1032 | iwl_clear_bit(bus(trans), CSR_GP_CNTRL, |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1033 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1034 | |
| 1035 | /* Stop the device, and put it in low power state */ |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1036 | iwl_apm_stop(priv(trans)); |
Emmanuel Grumbach | ab6cf8e | 2011-07-07 14:37:26 +0300 | [diff] [blame] | 1037 | } |
| 1038 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1039 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
Emmanuel Grumbach | 14991a9 | 2011-09-15 11:46:32 -0700 | [diff] [blame] | 1040 | struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx, |
| 1041 | u8 sta_id) |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1042 | { |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1043 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1044 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 1045 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
Emmanuel Grumbach | 132f98c | 2011-09-20 15:37:24 -0700 | [diff] [blame] | 1046 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1047 | struct iwl_cmd_meta *out_meta; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1048 | struct iwl_tx_queue *txq; |
| 1049 | struct iwl_queue *q; |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1050 | |
| 1051 | dma_addr_t phys_addr = 0; |
| 1052 | dma_addr_t txcmd_phys; |
| 1053 | dma_addr_t scratch_phys; |
| 1054 | u16 len, firstlen, secondlen; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1055 | u16 seq_number = 0; |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1056 | u8 wait_write_ptr = 0; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1057 | u8 txq_id; |
| 1058 | u8 tid = 0; |
| 1059 | bool is_agg = false; |
| 1060 | __le16 fc = hdr->frame_control; |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1061 | u8 hdr_len = ieee80211_hdrlen(fc); |
| 1062 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1063 | /* |
| 1064 | * Send this frame after DTIM -- there's a special queue |
| 1065 | * reserved for this for contexts that support AP mode. |
| 1066 | */ |
| 1067 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { |
| 1068 | txq_id = trans_pcie->mcast_queue[ctx]; |
| 1069 | |
| 1070 | /* |
| 1071 | * The microcode will clear the more data |
| 1072 | * bit in the last frame it transmits. |
| 1073 | */ |
| 1074 | hdr->frame_control |= |
| 1075 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); |
| 1076 | } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) |
| 1077 | txq_id = IWL_AUX_QUEUE; |
| 1078 | else |
| 1079 | txq_id = |
| 1080 | trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)]; |
| 1081 | |
| 1082 | if (ieee80211_is_data_qos(fc)) { |
| 1083 | u8 *qc = NULL; |
| 1084 | struct iwl_tid_data *tid_data; |
| 1085 | qc = ieee80211_get_qos_ctl(hdr); |
| 1086 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
| 1087 | tid_data = &trans->shrd->tid_data[sta_id][tid]; |
| 1088 | |
| 1089 | if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT)) |
| 1090 | return -1; |
| 1091 | |
| 1092 | seq_number = tid_data->seq_number; |
| 1093 | seq_number &= IEEE80211_SCTL_SEQ; |
| 1094 | hdr->seq_ctrl = hdr->seq_ctrl & |
| 1095 | cpu_to_le16(IEEE80211_SCTL_FRAG); |
| 1096 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
| 1097 | seq_number += 0x10; |
| 1098 | /* aggregation is on for this <sta,tid> */ |
Emmanuel Grumbach | 08ecf10 | 2011-09-20 15:37:26 -0700 | [diff] [blame^] | 1099 | if (info->flags & IEEE80211_TX_CTL_AMPDU) { |
| 1100 | WARN_ON(tid_data->agg.state != IWL_AGG_ON); |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1101 | txq_id = tid_data->agg.txq_id; |
| 1102 | is_agg = true; |
| 1103 | } |
| 1104 | } |
| 1105 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1106 | txq = &trans_pcie->txq[txq_id]; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1107 | q = &txq->q; |
| 1108 | |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1109 | /* Set up driver data for this TFD */ |
Emmanuel Grumbach | 2c45229 | 2011-08-25 23:11:21 -0700 | [diff] [blame] | 1110 | txq->skbs[q->write_ptr] = skb; |
Emmanuel Grumbach | dfa2bdb | 2011-08-25 23:11:23 -0700 | [diff] [blame] | 1111 | txq->cmd[q->write_ptr] = dev_cmd; |
| 1112 | |
| 1113 | dev_cmd->hdr.cmd = REPLY_TX; |
| 1114 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | |
| 1115 | INDEX_TO_SEQ(q->write_ptr))); |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1116 | |
| 1117 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
| 1118 | out_meta = &txq->meta[q->write_ptr]; |
| 1119 | |
| 1120 | /* |
| 1121 | * Use the first empty entry in this queue's command buffer array |
| 1122 | * to contain the Tx command and MAC header concatenated together |
| 1123 | * (payload data will be in another buffer). |
| 1124 | * Size of this varies, due to varying MAC header length. |
| 1125 | * If end is not dword aligned, we'll have 2 extra bytes at the end |
| 1126 | * of the MAC header (device reads on dword boundaries). |
| 1127 | * We'll tell device about this padding later. |
| 1128 | */ |
| 1129 | len = sizeof(struct iwl_tx_cmd) + |
| 1130 | sizeof(struct iwl_cmd_header) + hdr_len; |
| 1131 | firstlen = (len + 3) & ~3; |
| 1132 | |
| 1133 | /* Tell NIC about any 2-byte padding after MAC header */ |
| 1134 | if (firstlen != len) |
| 1135 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
| 1136 | |
| 1137 | /* Physical address of this Tx command's header (not MAC header!), |
| 1138 | * within command buffer array. */ |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1139 | txcmd_phys = dma_map_single(bus(trans)->dev, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1140 | &dev_cmd->hdr, firstlen, |
| 1141 | DMA_BIDIRECTIONAL); |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1142 | if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys))) |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1143 | return -1; |
| 1144 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
| 1145 | dma_unmap_len_set(out_meta, len, firstlen); |
| 1146 | |
| 1147 | if (!ieee80211_has_morefrags(fc)) { |
| 1148 | txq->need_update = 1; |
| 1149 | } else { |
| 1150 | wait_write_ptr = 1; |
| 1151 | txq->need_update = 0; |
| 1152 | } |
| 1153 | |
| 1154 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
| 1155 | * if any (802.11 null frames have no payload). */ |
| 1156 | secondlen = skb->len - hdr_len; |
| 1157 | if (secondlen > 0) { |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1158 | phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1159 | secondlen, DMA_TO_DEVICE); |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1160 | if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { |
| 1161 | dma_unmap_single(bus(trans)->dev, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1162 | dma_unmap_addr(out_meta, mapping), |
| 1163 | dma_unmap_len(out_meta, len), |
| 1164 | DMA_BIDIRECTIONAL); |
| 1165 | return -1; |
| 1166 | } |
| 1167 | } |
| 1168 | |
| 1169 | /* Attach buffers to TFD */ |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1170 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1171 | if (secondlen > 0) |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1172 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1173 | secondlen, 0); |
| 1174 | |
| 1175 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + |
| 1176 | offsetof(struct iwl_tx_cmd, scratch); |
| 1177 | |
| 1178 | /* take back ownership of DMA buffer to enable update */ |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1179 | dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1180 | DMA_BIDIRECTIONAL); |
| 1181 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
| 1182 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); |
| 1183 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1184 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1185 | le16_to_cpu(dev_cmd->hdr.sequence)); |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1186 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
| 1187 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); |
| 1188 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1189 | |
| 1190 | /* Set up entry for this TFD in Tx byte-count array */ |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1191 | if (is_agg) |
| 1192 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1193 | le16_to_cpu(tx_cmd->len)); |
| 1194 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1195 | dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen, |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1196 | DMA_BIDIRECTIONAL); |
| 1197 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1198 | trace_iwlwifi_dev_tx(priv(trans), |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1199 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], |
| 1200 | sizeof(struct iwl_tfd), |
| 1201 | &dev_cmd->hdr, firstlen, |
| 1202 | skb->data + hdr_len, secondlen); |
| 1203 | |
| 1204 | /* Tell device the write index *just past* this latest filled TFD */ |
| 1205 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1206 | iwl_txq_update_write_ptr(trans, txq); |
| 1207 | |
| 1208 | if (ieee80211_is_data_qos(fc)) { |
| 1209 | trans->shrd->tid_data[sta_id][tid].tfds_in_queue++; |
| 1210 | if (!ieee80211_has_morefrags(fc)) |
| 1211 | trans->shrd->tid_data[sta_id][tid].seq_number = |
| 1212 | seq_number; |
| 1213 | } |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1214 | |
| 1215 | /* |
| 1216 | * At this point the frame is "transmitted" successfully |
| 1217 | * and we will get a TX status notification eventually, |
| 1218 | * regardless of the value of ret. "ret" only indicates |
| 1219 | * whether or not we should update the write pointer. |
| 1220 | */ |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1221 | if (iwl_queue_space(q) < q->high_mark) { |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1222 | if (wait_write_ptr) { |
| 1223 | txq->need_update = 1; |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1224 | iwl_txq_update_write_ptr(trans, txq); |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1225 | } else { |
Emmanuel Grumbach | e20d4341 | 2011-08-25 23:11:31 -0700 | [diff] [blame] | 1226 | iwl_stop_queue(trans, txq); |
Emmanuel Grumbach | 47c1b49 | 2011-07-03 11:22:15 +0300 | [diff] [blame] | 1227 | } |
| 1228 | } |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1232 | static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans) |
Emmanuel Grumbach | 56d90f4 | 2011-07-07 18:20:01 +0300 | [diff] [blame] | 1233 | { |
| 1234 | /* Remove all resets to allow NIC to operate */ |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 1235 | iwl_write32(bus(trans), CSR_RESET, 0); |
Emmanuel Grumbach | 56d90f4 | 2011-07-07 18:20:01 +0300 | [diff] [blame] | 1236 | } |
| 1237 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1238 | static int iwl_trans_pcie_request_irq(struct iwl_trans *trans) |
Emmanuel Grumbach | a27367d | 2011-07-04 09:06:44 +0300 | [diff] [blame] | 1239 | { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1240 | struct iwl_trans_pcie *trans_pcie = |
| 1241 | IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 34c1b7b | 2011-07-04 08:58:19 +0300 | [diff] [blame] | 1242 | int err; |
| 1243 | |
Emmanuel Grumbach | 0c32576 | 2011-08-25 23:10:53 -0700 | [diff] [blame] | 1244 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
Emmanuel Grumbach | 1e89cbac | 2011-07-20 17:51:22 -0700 | [diff] [blame] | 1245 | |
Emmanuel Grumbach | 0c32576 | 2011-08-25 23:10:53 -0700 | [diff] [blame] | 1246 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) |
| 1247 | iwl_irq_tasklet, (unsigned long)trans); |
| 1248 | |
| 1249 | iwl_alloc_isr_ict(trans); |
Emmanuel Grumbach | 34c1b7b | 2011-07-04 08:58:19 +0300 | [diff] [blame] | 1250 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1251 | err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED, |
Emmanuel Grumbach | 0c32576 | 2011-08-25 23:10:53 -0700 | [diff] [blame] | 1252 | DRV_NAME, trans); |
Emmanuel Grumbach | 34c1b7b | 2011-07-04 08:58:19 +0300 | [diff] [blame] | 1253 | if (err) { |
Emmanuel Grumbach | 0c32576 | 2011-08-25 23:10:53 -0700 | [diff] [blame] | 1254 | IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq); |
| 1255 | iwl_free_isr_ict(trans); |
Emmanuel Grumbach | 34c1b7b | 2011-07-04 08:58:19 +0300 | [diff] [blame] | 1256 | return err; |
| 1257 | } |
| 1258 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1259 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); |
Emmanuel Grumbach | 34c1b7b | 2011-07-04 08:58:19 +0300 | [diff] [blame] | 1260 | return 0; |
Emmanuel Grumbach | c85eb61 | 2011-06-14 10:13:24 +0300 | [diff] [blame] | 1261 | } |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1262 | |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1263 | static int iwlagn_txq_check_empty(struct iwl_trans *trans, |
| 1264 | int sta_id, u8 tid, int txq_id) |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1265 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1266 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1267 | struct iwl_queue *q = &trans_pcie->txq[txq_id].q; |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1268 | struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid]; |
| 1269 | |
| 1270 | lockdep_assert_held(&trans->shrd->sta_lock); |
| 1271 | |
| 1272 | switch (trans->shrd->tid_data[sta_id][tid].agg.state) { |
| 1273 | case IWL_EMPTYING_HW_QUEUE_DELBA: |
| 1274 | /* We are reclaiming the last packet of the */ |
| 1275 | /* aggregated HW queue */ |
| 1276 | if ((txq_id == tid_data->agg.txq_id) && |
| 1277 | (q->read_ptr == q->write_ptr)) { |
| 1278 | IWL_DEBUG_HT(trans, |
| 1279 | "HW queue empty: continue DELBA flow\n"); |
Emmanuel Grumbach | 7f01d56 | 2011-08-25 23:11:27 -0700 | [diff] [blame] | 1280 | iwl_trans_pcie_txq_agg_disable(trans, txq_id); |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1281 | tid_data->agg.state = IWL_AGG_OFF; |
| 1282 | iwl_stop_tx_ba_trans_ready(priv(trans), |
| 1283 | NUM_IWL_RXON_CTX, |
| 1284 | sta_id, tid); |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1285 | iwl_wake_queue(trans, &trans_pcie->txq[txq_id]); |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1286 | } |
| 1287 | break; |
| 1288 | case IWL_EMPTYING_HW_QUEUE_ADDBA: |
| 1289 | /* We are reclaiming the last packet of the queue */ |
| 1290 | if (tid_data->tfds_in_queue == 0) { |
| 1291 | IWL_DEBUG_HT(trans, |
| 1292 | "HW queue empty: continue ADDBA flow\n"); |
| 1293 | tid_data->agg.state = IWL_AGG_ON; |
| 1294 | iwl_start_tx_ba_trans_ready(priv(trans), |
| 1295 | NUM_IWL_RXON_CTX, |
| 1296 | sta_id, tid); |
| 1297 | } |
| 1298 | break; |
Emmanuel Grumbach | 21023e2 | 2011-09-15 11:46:34 -0700 | [diff] [blame] | 1299 | default: |
| 1300 | break; |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1301 | } |
| 1302 | |
| 1303 | return 0; |
| 1304 | } |
| 1305 | |
| 1306 | static void iwl_free_tfds_in_queue(struct iwl_trans *trans, |
| 1307 | int sta_id, int tid, int freed) |
| 1308 | { |
| 1309 | lockdep_assert_held(&trans->shrd->sta_lock); |
| 1310 | |
| 1311 | if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed) |
| 1312 | trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed; |
| 1313 | else { |
| 1314 | IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n", |
| 1315 | trans->shrd->tid_data[sta_id][tid].tfds_in_queue, |
| 1316 | freed); |
| 1317 | trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0; |
| 1318 | } |
| 1319 | } |
| 1320 | |
| 1321 | static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid, |
| 1322 | int txq_id, int ssn, u32 status, |
| 1323 | struct sk_buff_head *skbs) |
| 1324 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1325 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1326 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; |
Emmanuel Grumbach | 21023e2 | 2011-09-15 11:46:34 -0700 | [diff] [blame] | 1327 | enum iwl_agg_state agg_state; |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1328 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
| 1329 | int tfd_num = ssn & (txq->q.n_bd - 1); |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1330 | int freed = 0; |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1331 | bool cond; |
| 1332 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1333 | txq->time_stamp = jiffies; |
| 1334 | |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1335 | if (txq->sched_retry) { |
| 1336 | agg_state = |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1337 | trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state; |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1338 | cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA); |
| 1339 | } else { |
| 1340 | cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX); |
| 1341 | } |
| 1342 | |
| 1343 | if (txq->q.read_ptr != tfd_num) { |
| 1344 | IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim " |
| 1345 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", |
| 1346 | ssn , tfd_num, txq_id, txq->swq_id); |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1347 | freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1348 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond) |
Emmanuel Grumbach | e20d4341 | 2011-08-25 23:11:31 -0700 | [diff] [blame] | 1349 | iwl_wake_queue(trans, txq); |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1350 | } |
Emmanuel Grumbach | 464021f | 2011-08-25 23:11:26 -0700 | [diff] [blame] | 1351 | |
| 1352 | iwl_free_tfds_in_queue(trans, sta_id, tid, freed); |
| 1353 | iwlagn_txq_check_empty(trans, sta_id, tid, txq_id); |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1354 | } |
| 1355 | |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1356 | static void iwl_trans_pcie_free(struct iwl_trans *trans) |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1357 | { |
Emmanuel Grumbach | ae2c30b | 2011-08-25 23:11:20 -0700 | [diff] [blame] | 1358 | iwl_trans_pcie_tx_free(trans); |
| 1359 | iwl_trans_pcie_rx_free(trans); |
Emmanuel Grumbach | 6d8f6ee | 2011-08-25 23:11:06 -0700 | [diff] [blame] | 1360 | free_irq(bus(trans)->irq, trans); |
| 1361 | iwl_free_isr_ict(trans); |
| 1362 | trans->shrd->trans = NULL; |
| 1363 | kfree(trans); |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1364 | } |
| 1365 | |
Johannes Berg | c01a404 | 2011-09-15 11:46:45 -0700 | [diff] [blame] | 1366 | #ifdef CONFIG_PM_SLEEP |
Emmanuel Grumbach | 57210f7 | 2011-08-25 23:10:52 -0700 | [diff] [blame] | 1367 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
| 1368 | { |
| 1369 | /* |
| 1370 | * This function is called when system goes into suspend state |
| 1371 | * mac80211 will call iwl_mac_stop() from the mac80211 suspend function |
| 1372 | * first but since iwl_mac_stop() has no knowledge of who the caller is, |
| 1373 | * it will not call apm_ops.stop() to stop the DMA operation. |
| 1374 | * Calling apm_ops.stop here to make sure we stop the DMA. |
| 1375 | * |
| 1376 | * But of course ... if we have configured WoWLAN then we did other |
| 1377 | * things already :-) |
| 1378 | */ |
| 1379 | if (!trans->shrd->wowlan) |
| 1380 | iwl_apm_stop(priv(trans)); |
| 1381 | |
| 1382 | return 0; |
| 1383 | } |
| 1384 | |
| 1385 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) |
| 1386 | { |
| 1387 | bool hw_rfkill = false; |
| 1388 | |
Emmanuel Grumbach | 0c32576 | 2011-08-25 23:10:53 -0700 | [diff] [blame] | 1389 | iwl_enable_interrupts(trans); |
Emmanuel Grumbach | 57210f7 | 2011-08-25 23:10:52 -0700 | [diff] [blame] | 1390 | |
Emmanuel Grumbach | 83ed901 | 2011-08-25 23:11:14 -0700 | [diff] [blame] | 1391 | if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) & |
Emmanuel Grumbach | 57210f7 | 2011-08-25 23:10:52 -0700 | [diff] [blame] | 1392 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
| 1393 | hw_rfkill = true; |
| 1394 | |
| 1395 | if (hw_rfkill) |
| 1396 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
| 1397 | else |
| 1398 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
| 1399 | |
Emmanuel Grumbach | 3e10cae | 2011-09-06 09:31:18 -0700 | [diff] [blame] | 1400 | iwl_set_hw_rfkill_state(priv(trans), hw_rfkill); |
Emmanuel Grumbach | 57210f7 | 2011-08-25 23:10:52 -0700 | [diff] [blame] | 1401 | |
| 1402 | return 0; |
| 1403 | } |
Johannes Berg | c01a404 | 2011-09-15 11:46:45 -0700 | [diff] [blame] | 1404 | #endif /* CONFIG_PM_SLEEP */ |
Emmanuel Grumbach | 57210f7 | 2011-08-25 23:10:52 -0700 | [diff] [blame] | 1405 | |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1406 | static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans, |
Emmanuel Grumbach | 14991a9 | 2011-09-15 11:46:32 -0700 | [diff] [blame] | 1407 | enum iwl_rxon_context_id ctx) |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1408 | { |
| 1409 | u8 ac, txq_id; |
| 1410 | struct iwl_trans_pcie *trans_pcie = |
| 1411 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1412 | |
| 1413 | for (ac = 0; ac < AC_NUM; ac++) { |
| 1414 | txq_id = trans_pcie->ac_to_queue[ctx][ac]; |
| 1415 | IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n", |
| 1416 | ac, |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1417 | (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0) |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1418 | ? "stopped" : "awake"); |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1419 | iwl_wake_queue(trans, &trans_pcie->txq[txq_id]); |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1420 | } |
| 1421 | } |
| 1422 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1423 | const struct iwl_trans_ops trans_ops_pcie; |
| 1424 | |
| 1425 | static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd) |
| 1426 | { |
| 1427 | struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) + |
| 1428 | sizeof(struct iwl_trans_pcie), |
| 1429 | GFP_KERNEL); |
| 1430 | if (iwl_trans) { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1431 | struct iwl_trans_pcie *trans_pcie = |
| 1432 | IWL_TRANS_GET_PCIE_TRANS(iwl_trans); |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1433 | iwl_trans->ops = &trans_ops_pcie; |
| 1434 | iwl_trans->shrd = shrd; |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1435 | trans_pcie->trans = iwl_trans; |
Emmanuel Grumbach | 7201247 | 2011-08-25 23:11:07 -0700 | [diff] [blame] | 1436 | spin_lock_init(&iwl_trans->hcmd_lock); |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1437 | } |
| 1438 | |
| 1439 | return iwl_trans; |
| 1440 | } |
| 1441 | |
Emmanuel Grumbach | e20d4341 | 2011-08-25 23:11:31 -0700 | [diff] [blame] | 1442 | static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id) |
| 1443 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1444 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1445 | |
| 1446 | iwl_stop_queue(trans, &trans_pcie->txq[txq_id]); |
Emmanuel Grumbach | e20d4341 | 2011-08-25 23:11:31 -0700 | [diff] [blame] | 1447 | } |
| 1448 | |
Emmanuel Grumbach | 5f178cd | 2011-08-25 23:11:29 -0700 | [diff] [blame] | 1449 | #define IWL_FLUSH_WAIT_MS 2000 |
| 1450 | |
| 1451 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) |
| 1452 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1453 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 5f178cd | 2011-08-25 23:11:29 -0700 | [diff] [blame] | 1454 | struct iwl_tx_queue *txq; |
| 1455 | struct iwl_queue *q; |
| 1456 | int cnt; |
| 1457 | unsigned long now = jiffies; |
| 1458 | int ret = 0; |
| 1459 | |
| 1460 | /* waiting for all the tx frames complete might take a while */ |
| 1461 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
| 1462 | if (cnt == trans->shrd->cmd_queue) |
| 1463 | continue; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1464 | txq = &trans_pcie->txq[cnt]; |
Emmanuel Grumbach | 5f178cd | 2011-08-25 23:11:29 -0700 | [diff] [blame] | 1465 | q = &txq->q; |
| 1466 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, |
| 1467 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) |
| 1468 | msleep(1); |
| 1469 | |
| 1470 | if (q->read_ptr != q->write_ptr) { |
| 1471 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); |
| 1472 | ret = -ETIMEDOUT; |
| 1473 | break; |
| 1474 | } |
| 1475 | } |
| 1476 | return ret; |
| 1477 | } |
| 1478 | |
Emmanuel Grumbach | f22be62 | 2011-08-25 23:11:30 -0700 | [diff] [blame] | 1479 | /* |
| 1480 | * On every watchdog tick we check (latest) time stamp. If it does not |
| 1481 | * change during timeout period and queue is not empty we reset firmware. |
| 1482 | */ |
| 1483 | static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt) |
| 1484 | { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1485 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1486 | struct iwl_tx_queue *txq = &trans_pcie->txq[cnt]; |
Emmanuel Grumbach | f22be62 | 2011-08-25 23:11:30 -0700 | [diff] [blame] | 1487 | struct iwl_queue *q = &txq->q; |
| 1488 | unsigned long timeout; |
| 1489 | |
| 1490 | if (q->read_ptr == q->write_ptr) { |
| 1491 | txq->time_stamp = jiffies; |
| 1492 | return 0; |
| 1493 | } |
| 1494 | |
| 1495 | timeout = txq->time_stamp + |
| 1496 | msecs_to_jiffies(hw_params(trans).wd_timeout); |
| 1497 | |
| 1498 | if (time_after(jiffies, timeout)) { |
| 1499 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, |
| 1500 | hw_params(trans).wd_timeout); |
Wey-Yi Guy | 05f8a09 | 2011-09-06 09:31:22 -0700 | [diff] [blame] | 1501 | IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n", |
| 1502 | q->read_ptr, q->write_ptr); |
Emmanuel Grumbach | f22be62 | 2011-08-25 23:11:30 -0700 | [diff] [blame] | 1503 | return 1; |
| 1504 | } |
| 1505 | |
| 1506 | return 0; |
| 1507 | } |
| 1508 | |
Emmanuel Grumbach | ff62084 | 2011-09-06 09:31:25 -0700 | [diff] [blame] | 1509 | static const char *get_fh_string(int cmd) |
| 1510 | { |
| 1511 | switch (cmd) { |
| 1512 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); |
| 1513 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); |
| 1514 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); |
| 1515 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); |
| 1516 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); |
| 1517 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); |
| 1518 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); |
| 1519 | IWL_CMD(FH_TSSR_TX_STATUS_REG); |
| 1520 | IWL_CMD(FH_TSSR_TX_ERROR_REG); |
| 1521 | default: |
| 1522 | return "UNKNOWN"; |
| 1523 | } |
| 1524 | } |
| 1525 | |
| 1526 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) |
| 1527 | { |
| 1528 | int i; |
| 1529 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1530 | int pos = 0; |
| 1531 | size_t bufsz = 0; |
| 1532 | #endif |
| 1533 | static const u32 fh_tbl[] = { |
| 1534 | FH_RSCSR_CHNL0_STTS_WPTR_REG, |
| 1535 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
| 1536 | FH_RSCSR_CHNL0_WPTR, |
| 1537 | FH_MEM_RCSR_CHNL0_CONFIG_REG, |
| 1538 | FH_MEM_RSSR_SHARED_CTRL_REG, |
| 1539 | FH_MEM_RSSR_RX_STATUS_REG, |
| 1540 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, |
| 1541 | FH_TSSR_TX_STATUS_REG, |
| 1542 | FH_TSSR_TX_ERROR_REG |
| 1543 | }; |
| 1544 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1545 | if (display) { |
| 1546 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; |
| 1547 | *buf = kmalloc(bufsz, GFP_KERNEL); |
| 1548 | if (!*buf) |
| 1549 | return -ENOMEM; |
| 1550 | pos += scnprintf(*buf + pos, bufsz - pos, |
| 1551 | "FH register values:\n"); |
| 1552 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { |
| 1553 | pos += scnprintf(*buf + pos, bufsz - pos, |
| 1554 | " %34s: 0X%08x\n", |
| 1555 | get_fh_string(fh_tbl[i]), |
| 1556 | iwl_read_direct32(bus(trans), fh_tbl[i])); |
| 1557 | } |
| 1558 | return pos; |
| 1559 | } |
| 1560 | #endif |
| 1561 | IWL_ERR(trans, "FH register values:\n"); |
| 1562 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { |
| 1563 | IWL_ERR(trans, " %34s: 0X%08x\n", |
| 1564 | get_fh_string(fh_tbl[i]), |
| 1565 | iwl_read_direct32(bus(trans), fh_tbl[i])); |
| 1566 | } |
| 1567 | return 0; |
| 1568 | } |
| 1569 | |
| 1570 | static const char *get_csr_string(int cmd) |
| 1571 | { |
| 1572 | switch (cmd) { |
| 1573 | IWL_CMD(CSR_HW_IF_CONFIG_REG); |
| 1574 | IWL_CMD(CSR_INT_COALESCING); |
| 1575 | IWL_CMD(CSR_INT); |
| 1576 | IWL_CMD(CSR_INT_MASK); |
| 1577 | IWL_CMD(CSR_FH_INT_STATUS); |
| 1578 | IWL_CMD(CSR_GPIO_IN); |
| 1579 | IWL_CMD(CSR_RESET); |
| 1580 | IWL_CMD(CSR_GP_CNTRL); |
| 1581 | IWL_CMD(CSR_HW_REV); |
| 1582 | IWL_CMD(CSR_EEPROM_REG); |
| 1583 | IWL_CMD(CSR_EEPROM_GP); |
| 1584 | IWL_CMD(CSR_OTP_GP_REG); |
| 1585 | IWL_CMD(CSR_GIO_REG); |
| 1586 | IWL_CMD(CSR_GP_UCODE_REG); |
| 1587 | IWL_CMD(CSR_GP_DRIVER_REG); |
| 1588 | IWL_CMD(CSR_UCODE_DRV_GP1); |
| 1589 | IWL_CMD(CSR_UCODE_DRV_GP2); |
| 1590 | IWL_CMD(CSR_LED_REG); |
| 1591 | IWL_CMD(CSR_DRAM_INT_TBL_REG); |
| 1592 | IWL_CMD(CSR_GIO_CHICKEN_BITS); |
| 1593 | IWL_CMD(CSR_ANA_PLL_CFG); |
| 1594 | IWL_CMD(CSR_HW_REV_WA_REG); |
| 1595 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
| 1596 | default: |
| 1597 | return "UNKNOWN"; |
| 1598 | } |
| 1599 | } |
| 1600 | |
| 1601 | void iwl_dump_csr(struct iwl_trans *trans) |
| 1602 | { |
| 1603 | int i; |
| 1604 | static const u32 csr_tbl[] = { |
| 1605 | CSR_HW_IF_CONFIG_REG, |
| 1606 | CSR_INT_COALESCING, |
| 1607 | CSR_INT, |
| 1608 | CSR_INT_MASK, |
| 1609 | CSR_FH_INT_STATUS, |
| 1610 | CSR_GPIO_IN, |
| 1611 | CSR_RESET, |
| 1612 | CSR_GP_CNTRL, |
| 1613 | CSR_HW_REV, |
| 1614 | CSR_EEPROM_REG, |
| 1615 | CSR_EEPROM_GP, |
| 1616 | CSR_OTP_GP_REG, |
| 1617 | CSR_GIO_REG, |
| 1618 | CSR_GP_UCODE_REG, |
| 1619 | CSR_GP_DRIVER_REG, |
| 1620 | CSR_UCODE_DRV_GP1, |
| 1621 | CSR_UCODE_DRV_GP2, |
| 1622 | CSR_LED_REG, |
| 1623 | CSR_DRAM_INT_TBL_REG, |
| 1624 | CSR_GIO_CHICKEN_BITS, |
| 1625 | CSR_ANA_PLL_CFG, |
| 1626 | CSR_HW_REV_WA_REG, |
| 1627 | CSR_DBG_HPET_MEM_REG |
| 1628 | }; |
| 1629 | IWL_ERR(trans, "CSR values:\n"); |
| 1630 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " |
| 1631 | "CSR_INT_PERIODIC_REG)\n"); |
| 1632 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { |
| 1633 | IWL_ERR(trans, " %25s: 0X%08x\n", |
| 1634 | get_csr_string(csr_tbl[i]), |
| 1635 | iwl_read32(bus(trans), csr_tbl[i])); |
| 1636 | } |
| 1637 | } |
| 1638 | |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1639 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
| 1640 | /* create and remove of files */ |
| 1641 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1642 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1643 | &iwl_dbgfs_##name##_ops)) \ |
| 1644 | return -ENOMEM; \ |
| 1645 | } while (0) |
| 1646 | |
| 1647 | /* file operation */ |
| 1648 | #define DEBUGFS_READ_FUNC(name) \ |
| 1649 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ |
| 1650 | char __user *user_buf, \ |
| 1651 | size_t count, loff_t *ppos); |
| 1652 | |
| 1653 | #define DEBUGFS_WRITE_FUNC(name) \ |
| 1654 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ |
| 1655 | const char __user *user_buf, \ |
| 1656 | size_t count, loff_t *ppos); |
| 1657 | |
| 1658 | |
| 1659 | static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file) |
| 1660 | { |
| 1661 | file->private_data = inode->i_private; |
| 1662 | return 0; |
| 1663 | } |
| 1664 | |
| 1665 | #define DEBUGFS_READ_FILE_OPS(name) \ |
| 1666 | DEBUGFS_READ_FUNC(name); \ |
| 1667 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
| 1668 | .read = iwl_dbgfs_##name##_read, \ |
| 1669 | .open = iwl_dbgfs_open_file_generic, \ |
| 1670 | .llseek = generic_file_llseek, \ |
| 1671 | }; |
| 1672 | |
Emmanuel Grumbach | 16db88b | 2011-08-25 23:11:08 -0700 | [diff] [blame] | 1673 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
| 1674 | DEBUGFS_WRITE_FUNC(name); \ |
| 1675 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
| 1676 | .write = iwl_dbgfs_##name##_write, \ |
| 1677 | .open = iwl_dbgfs_open_file_generic, \ |
| 1678 | .llseek = generic_file_llseek, \ |
| 1679 | }; |
| 1680 | |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1681 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
| 1682 | DEBUGFS_READ_FUNC(name); \ |
| 1683 | DEBUGFS_WRITE_FUNC(name); \ |
| 1684 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
| 1685 | .write = iwl_dbgfs_##name##_write, \ |
| 1686 | .read = iwl_dbgfs_##name##_read, \ |
| 1687 | .open = iwl_dbgfs_open_file_generic, \ |
| 1688 | .llseek = generic_file_llseek, \ |
| 1689 | }; |
| 1690 | |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1691 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
| 1692 | char __user *user_buf, |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1693 | size_t count, loff_t *ppos) |
| 1694 | { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1695 | struct iwl_trans *trans = file->private_data; |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1696 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1697 | struct iwl_tx_queue *txq; |
| 1698 | struct iwl_queue *q; |
| 1699 | char *buf; |
| 1700 | int pos = 0; |
| 1701 | int cnt; |
| 1702 | int ret; |
Emmanuel Grumbach | fd65693 | 2011-08-25 23:11:19 -0700 | [diff] [blame] | 1703 | const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num; |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1704 | |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1705 | if (!trans_pcie->txq) { |
Emmanuel Grumbach | 3e10cae | 2011-09-06 09:31:18 -0700 | [diff] [blame] | 1706 | IWL_ERR(trans, "txq not ready\n"); |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1707 | return -EAGAIN; |
| 1708 | } |
| 1709 | buf = kzalloc(bufsz, GFP_KERNEL); |
| 1710 | if (!buf) |
| 1711 | return -ENOMEM; |
| 1712 | |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1713 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1714 | txq = &trans_pcie->txq[cnt]; |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1715 | q = &txq->q; |
| 1716 | pos += scnprintf(buf + pos, bufsz - pos, |
| 1717 | "hwq %.2d: read=%u write=%u stop=%d" |
| 1718 | " swq_id=%#.2x (ac %d/hwq %d)\n", |
| 1719 | cnt, q->read_ptr, q->write_ptr, |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1720 | !!test_bit(cnt, trans_pcie->queue_stopped), |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1721 | txq->swq_id, txq->swq_id & 3, |
| 1722 | (txq->swq_id >> 2) & 0x1f); |
| 1723 | if (cnt >= 4) |
| 1724 | continue; |
| 1725 | /* for the ACs, display the stop count too */ |
| 1726 | pos += scnprintf(buf + pos, bufsz - pos, |
Emmanuel Grumbach | 8ad71be | 2011-08-25 23:11:32 -0700 | [diff] [blame] | 1727 | " stop-count: %d\n", |
| 1728 | atomic_read(&trans_pcie->queue_stop_count[cnt])); |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1729 | } |
| 1730 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 1731 | kfree(buf); |
| 1732 | return ret; |
| 1733 | } |
| 1734 | |
| 1735 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, |
| 1736 | char __user *user_buf, |
| 1737 | size_t count, loff_t *ppos) { |
Emmanuel Grumbach | 5a878bf | 2011-08-25 23:10:51 -0700 | [diff] [blame] | 1738 | struct iwl_trans *trans = file->private_data; |
| 1739 | struct iwl_trans_pcie *trans_pcie = |
| 1740 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1741 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1742 | char buf[256]; |
| 1743 | int pos = 0; |
| 1744 | const size_t bufsz = sizeof(buf); |
| 1745 | |
| 1746 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", |
| 1747 | rxq->read); |
| 1748 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", |
| 1749 | rxq->write); |
| 1750 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", |
| 1751 | rxq->free_count); |
| 1752 | if (rxq->rb_stts) { |
| 1753 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", |
| 1754 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); |
| 1755 | } else { |
| 1756 | pos += scnprintf(buf + pos, bufsz - pos, |
| 1757 | "closed_rb_num: Not Allocated\n"); |
| 1758 | } |
| 1759 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 1760 | } |
| 1761 | |
Emmanuel Grumbach | 7ff9470 | 2011-08-25 23:10:54 -0700 | [diff] [blame] | 1762 | static ssize_t iwl_dbgfs_log_event_read(struct file *file, |
| 1763 | char __user *user_buf, |
| 1764 | size_t count, loff_t *ppos) |
| 1765 | { |
| 1766 | struct iwl_trans *trans = file->private_data; |
| 1767 | char *buf; |
| 1768 | int pos = 0; |
| 1769 | ssize_t ret = -ENOMEM; |
| 1770 | |
Emmanuel Grumbach | 6bb7884 | 2011-08-25 23:11:09 -0700 | [diff] [blame] | 1771 | ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true); |
Emmanuel Grumbach | 7ff9470 | 2011-08-25 23:10:54 -0700 | [diff] [blame] | 1772 | if (buf) { |
| 1773 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 1774 | kfree(buf); |
| 1775 | } |
| 1776 | return ret; |
| 1777 | } |
| 1778 | |
| 1779 | static ssize_t iwl_dbgfs_log_event_write(struct file *file, |
| 1780 | const char __user *user_buf, |
| 1781 | size_t count, loff_t *ppos) |
| 1782 | { |
| 1783 | struct iwl_trans *trans = file->private_data; |
| 1784 | u32 event_log_flag; |
| 1785 | char buf[8]; |
| 1786 | int buf_size; |
| 1787 | |
| 1788 | memset(buf, 0, sizeof(buf)); |
| 1789 | buf_size = min(count, sizeof(buf) - 1); |
| 1790 | if (copy_from_user(buf, user_buf, buf_size)) |
| 1791 | return -EFAULT; |
| 1792 | if (sscanf(buf, "%d", &event_log_flag) != 1) |
| 1793 | return -EFAULT; |
| 1794 | if (event_log_flag == 1) |
Emmanuel Grumbach | 6bb7884 | 2011-08-25 23:11:09 -0700 | [diff] [blame] | 1795 | iwl_dump_nic_event_log(trans, true, NULL, false); |
Emmanuel Grumbach | 7ff9470 | 2011-08-25 23:10:54 -0700 | [diff] [blame] | 1796 | |
| 1797 | return count; |
| 1798 | } |
| 1799 | |
Emmanuel Grumbach | 1f7b617 | 2011-08-25 23:10:59 -0700 | [diff] [blame] | 1800 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
| 1801 | char __user *user_buf, |
| 1802 | size_t count, loff_t *ppos) { |
| 1803 | |
| 1804 | struct iwl_trans *trans = file->private_data; |
| 1805 | struct iwl_trans_pcie *trans_pcie = |
| 1806 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1807 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
| 1808 | |
| 1809 | int pos = 0; |
| 1810 | char *buf; |
| 1811 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ |
| 1812 | ssize_t ret; |
| 1813 | |
| 1814 | buf = kzalloc(bufsz, GFP_KERNEL); |
| 1815 | if (!buf) { |
| 1816 | IWL_ERR(trans, "Can not allocate Buffer\n"); |
| 1817 | return -ENOMEM; |
| 1818 | } |
| 1819 | |
| 1820 | pos += scnprintf(buf + pos, bufsz - pos, |
| 1821 | "Interrupt Statistics Report:\n"); |
| 1822 | |
| 1823 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", |
| 1824 | isr_stats->hw); |
| 1825 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", |
| 1826 | isr_stats->sw); |
| 1827 | if (isr_stats->sw || isr_stats->hw) { |
| 1828 | pos += scnprintf(buf + pos, bufsz - pos, |
| 1829 | "\tLast Restarting Code: 0x%X\n", |
| 1830 | isr_stats->err_code); |
| 1831 | } |
| 1832 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 1833 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", |
| 1834 | isr_stats->sch); |
| 1835 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", |
| 1836 | isr_stats->alive); |
| 1837 | #endif |
| 1838 | pos += scnprintf(buf + pos, bufsz - pos, |
| 1839 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); |
| 1840 | |
| 1841 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", |
| 1842 | isr_stats->ctkill); |
| 1843 | |
| 1844 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", |
| 1845 | isr_stats->wakeup); |
| 1846 | |
| 1847 | pos += scnprintf(buf + pos, bufsz - pos, |
| 1848 | "Rx command responses:\t\t %u\n", isr_stats->rx); |
| 1849 | |
| 1850 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", |
| 1851 | isr_stats->tx); |
| 1852 | |
| 1853 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", |
| 1854 | isr_stats->unhandled); |
| 1855 | |
| 1856 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); |
| 1857 | kfree(buf); |
| 1858 | return ret; |
| 1859 | } |
| 1860 | |
| 1861 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, |
| 1862 | const char __user *user_buf, |
| 1863 | size_t count, loff_t *ppos) |
| 1864 | { |
| 1865 | struct iwl_trans *trans = file->private_data; |
| 1866 | struct iwl_trans_pcie *trans_pcie = |
| 1867 | IWL_TRANS_GET_PCIE_TRANS(trans); |
| 1868 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
| 1869 | |
| 1870 | char buf[8]; |
| 1871 | int buf_size; |
| 1872 | u32 reset_flag; |
| 1873 | |
| 1874 | memset(buf, 0, sizeof(buf)); |
| 1875 | buf_size = min(count, sizeof(buf) - 1); |
| 1876 | if (copy_from_user(buf, user_buf, buf_size)) |
| 1877 | return -EFAULT; |
| 1878 | if (sscanf(buf, "%x", &reset_flag) != 1) |
| 1879 | return -EFAULT; |
| 1880 | if (reset_flag == 0) |
| 1881 | memset(isr_stats, 0, sizeof(*isr_stats)); |
| 1882 | |
| 1883 | return count; |
| 1884 | } |
| 1885 | |
Emmanuel Grumbach | 16db88b | 2011-08-25 23:11:08 -0700 | [diff] [blame] | 1886 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
| 1887 | const char __user *user_buf, |
| 1888 | size_t count, loff_t *ppos) |
| 1889 | { |
| 1890 | struct iwl_trans *trans = file->private_data; |
| 1891 | char buf[8]; |
| 1892 | int buf_size; |
| 1893 | int csr; |
| 1894 | |
| 1895 | memset(buf, 0, sizeof(buf)); |
| 1896 | buf_size = min(count, sizeof(buf) - 1); |
| 1897 | if (copy_from_user(buf, user_buf, buf_size)) |
| 1898 | return -EFAULT; |
| 1899 | if (sscanf(buf, "%d", &csr) != 1) |
| 1900 | return -EFAULT; |
| 1901 | |
| 1902 | iwl_dump_csr(trans); |
| 1903 | |
| 1904 | return count; |
| 1905 | } |
| 1906 | |
Emmanuel Grumbach | 16db88b | 2011-08-25 23:11:08 -0700 | [diff] [blame] | 1907 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
| 1908 | char __user *user_buf, |
| 1909 | size_t count, loff_t *ppos) |
| 1910 | { |
| 1911 | struct iwl_trans *trans = file->private_data; |
| 1912 | char *buf; |
| 1913 | int pos = 0; |
| 1914 | ssize_t ret = -EFAULT; |
| 1915 | |
| 1916 | ret = pos = iwl_dump_fh(trans, &buf, true); |
| 1917 | if (buf) { |
| 1918 | ret = simple_read_from_buffer(user_buf, |
| 1919 | count, ppos, buf, pos); |
| 1920 | kfree(buf); |
| 1921 | } |
| 1922 | |
| 1923 | return ret; |
| 1924 | } |
| 1925 | |
Emmanuel Grumbach | 7ff9470 | 2011-08-25 23:10:54 -0700 | [diff] [blame] | 1926 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
Emmanuel Grumbach | 1f7b617 | 2011-08-25 23:10:59 -0700 | [diff] [blame] | 1927 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
Emmanuel Grumbach | 16db88b | 2011-08-25 23:11:08 -0700 | [diff] [blame] | 1928 | DEBUGFS_READ_FILE_OPS(fh_reg); |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1929 | DEBUGFS_READ_FILE_OPS(rx_queue); |
| 1930 | DEBUGFS_READ_FILE_OPS(tx_queue); |
Emmanuel Grumbach | 16db88b | 2011-08-25 23:11:08 -0700 | [diff] [blame] | 1931 | DEBUGFS_WRITE_FILE_OPS(csr); |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1932 | |
| 1933 | /* |
| 1934 | * Create the debugfs files and directories |
| 1935 | * |
| 1936 | */ |
| 1937 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, |
| 1938 | struct dentry *dir) |
| 1939 | { |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1940 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
| 1941 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); |
Emmanuel Grumbach | 7ff9470 | 2011-08-25 23:10:54 -0700 | [diff] [blame] | 1942 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
Emmanuel Grumbach | 1f7b617 | 2011-08-25 23:10:59 -0700 | [diff] [blame] | 1943 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
Emmanuel Grumbach | 16db88b | 2011-08-25 23:11:08 -0700 | [diff] [blame] | 1944 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
| 1945 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1946 | return 0; |
| 1947 | } |
| 1948 | #else |
| 1949 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, |
| 1950 | struct dentry *dir) |
| 1951 | { return 0; } |
| 1952 | |
| 1953 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ |
| 1954 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1955 | const struct iwl_trans_ops trans_ops_pcie = { |
| 1956 | .alloc = iwl_trans_pcie_alloc, |
| 1957 | .request_irq = iwl_trans_pcie_request_irq, |
| 1958 | .start_device = iwl_trans_pcie_start_device, |
| 1959 | .prepare_card_hw = iwl_trans_pcie_prepare_card_hw, |
| 1960 | .stop_device = iwl_trans_pcie_stop_device, |
| 1961 | |
| 1962 | .tx_start = iwl_trans_pcie_tx_start, |
Emmanuel Grumbach | e13c0c5 | 2011-08-25 23:11:24 -0700 | [diff] [blame] | 1963 | .wake_any_queue = iwl_trans_pcie_wake_any_queue, |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1964 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1965 | .send_cmd = iwl_trans_pcie_send_cmd, |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1966 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1967 | .tx = iwl_trans_pcie_tx, |
Emmanuel Grumbach | a0eaad7 | 2011-08-25 23:11:00 -0700 | [diff] [blame] | 1968 | .reclaim = iwl_trans_pcie_reclaim, |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1969 | |
Emmanuel Grumbach | 7f01d56 | 2011-08-25 23:11:27 -0700 | [diff] [blame] | 1970 | .tx_agg_disable = iwl_trans_pcie_tx_agg_disable, |
Emmanuel Grumbach | 288712a | 2011-08-25 23:11:25 -0700 | [diff] [blame] | 1971 | .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc, |
Emmanuel Grumbach | c91bd12 | 2011-08-25 23:11:28 -0700 | [diff] [blame] | 1972 | .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1973 | |
| 1974 | .kick_nic = iwl_trans_pcie_kick_nic, |
| 1975 | |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1976 | .free = iwl_trans_pcie_free, |
Emmanuel Grumbach | e20d4341 | 2011-08-25 23:11:31 -0700 | [diff] [blame] | 1977 | .stop_queue = iwl_trans_pcie_stop_queue, |
Emmanuel Grumbach | 87e5666 | 2011-08-25 23:10:50 -0700 | [diff] [blame] | 1978 | |
| 1979 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
Emmanuel Grumbach | 5f178cd | 2011-08-25 23:11:29 -0700 | [diff] [blame] | 1980 | |
| 1981 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, |
Emmanuel Grumbach | f22be62 | 2011-08-25 23:11:30 -0700 | [diff] [blame] | 1982 | .check_stuck_queue = iwl_trans_pcie_check_stuck_queue, |
Emmanuel Grumbach | 5f178cd | 2011-08-25 23:11:29 -0700 | [diff] [blame] | 1983 | |
Johannes Berg | c01a404 | 2011-09-15 11:46:45 -0700 | [diff] [blame] | 1984 | #ifdef CONFIG_PM_SLEEP |
Emmanuel Grumbach | 57210f7 | 2011-08-25 23:10:52 -0700 | [diff] [blame] | 1985 | .suspend = iwl_trans_pcie_suspend, |
| 1986 | .resume = iwl_trans_pcie_resume, |
Johannes Berg | c01a404 | 2011-09-15 11:46:45 -0700 | [diff] [blame] | 1987 | #endif |
Emmanuel Grumbach | e6bb4c9 | 2011-08-25 23:10:48 -0700 | [diff] [blame] | 1988 | }; |