blob: b5c4ada1cff5fa69c13d5ca2447f26e245cecce6 [file] [log] [blame]
Changhwan Younc8bef142010-07-27 17:52:39 +09001/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
Kukjin Kimc598c472010-08-18 21:45:49 +090018#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
Changhwan Younc8bef142010-07-27 17:52:39 +090019
20#define S5P_INFORM0 S5P_CLKREG(0x800)
21
Sunyoung Kang7af36b92010-09-18 10:59:31 +090022#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
23#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
27
Kukjin Kimc598c472010-08-18 21:45:49 +090028#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
31#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
Changhwan Younc8bef142010-07-27 17:52:39 +090032
Kukjin Kimc598c472010-08-18 21:45:49 +090033#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
Kukjin Kime33ed872010-08-18 21:59:01 +090035#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
36#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
37#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
38#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
39#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
Kukjin Kimc598c472010-08-18 21:45:49 +090040#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
Kukjin Kime33ed872010-08-18 21:59:01 +090041#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
Changhwan Younc8bef142010-07-27 17:52:39 +090042
Kukjin Kimc598c472010-08-18 21:45:49 +090043#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
Kukjin Kime33ed872010-08-18 21:59:01 +090044#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
45#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
46#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
47#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
48#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
49#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
50#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
51#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
Kukjin Kimc598c472010-08-18 21:45:49 +090052#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
53#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
54#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
55#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
56#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
57#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
Changhwan Younc8bef142010-07-27 17:52:39 +090058
Kukjin Kime33ed872010-08-18 21:59:01 +090059#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
60#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
61#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
62#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
63#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
Jongpill Lee3297c2e2010-08-27 17:53:26 +090064#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
Kukjin Kime33ed872010-08-18 21:59:01 +090065#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
Jongpill Lee3297c2e2010-08-27 17:53:26 +090066
Sunyoung Kang7af36b92010-09-18 10:59:31 +090067#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
68
Kukjin Kime33ed872010-08-18 21:59:01 +090069#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
70#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
71#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
72#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
73#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
Kukjin Kimc598c472010-08-18 21:45:49 +090074#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
Jongpill Lee82260bf2010-08-18 22:49:24 +090075#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
Changhwan Younc8bef142010-07-27 17:52:39 +090076
Sunyoung Kang7af36b92010-09-18 10:59:31 +090077#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
78#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
79#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
Changhwan Younc8bef142010-07-27 17:52:39 +090080
Kukjin Kimc598c472010-08-18 21:45:49 +090081#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
82#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
83#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
84#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
85#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
86#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
Changhwan Younc8bef142010-07-27 17:52:39 +090087
Kukjin Kimc598c472010-08-18 21:45:49 +090088#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
89#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
Changhwan Younc8bef142010-07-27 17:52:39 +090090
Kukjin Kimc598c472010-08-18 21:45:49 +090091#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
Sangwook Ju09dc7812010-12-22 07:26:40 +090092#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
Kukjin Kimc598c472010-08-18 21:45:49 +090093#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
Sangwook Ju09dc7812010-12-22 07:26:40 +090094#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
Changhwan Younc8bef142010-07-27 17:52:39 +090095
Kukjin Kimc598c472010-08-18 21:45:49 +090096#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
Changhwan Younc8bef142010-07-27 17:52:39 +090097
Sunyoung Kang7af36b92010-09-18 10:59:31 +090098/* APLL_LOCK */
99#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
100
101/* APLL_CON0 */
102#define S5P_APLLCON0_ENABLE_SHIFT (31)
103#define S5P_APLLCON0_LOCKED_SHIFT (29)
104#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
Sangwook Ju09dc7812010-12-22 07:26:40 +0900105#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
Sunyoung Kang7af36b92010-09-18 10:59:31 +0900106
107/* CLK_SRC_CPU */
108#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
109#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
110
111/* CLKDIV_CPU0 */
112#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
113#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
114#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
115#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
116#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
117#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
118#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
119#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
120#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
121#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
122#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
123#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
124#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
125#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
126
127/* CLKDIV_DMC0 */
128#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
129#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
130#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
131#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
132#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
133#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
134#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
135#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
136#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
137#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
138#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
139#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
140#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
141#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
142#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
143#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
144
145/* CLKDIV_TOP */
146#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
147#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
148#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
149#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
150#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
151#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
152#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
153#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
154#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
155#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
156
157/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
158#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
159#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
162
Seungwhan Yound4b34c62010-10-14 10:39:08 +0900163/* Compatibility defines */
164
165#define S5P_EPLL_CON S5P_EPLL_CON0
166
Changhwan Younc8bef142010-07-27 17:52:39 +0900167#endif /* __ASM_ARCH_REGS_CLOCK_H */