blob: aef64de77495b4be5867dc6ee0fcc9892bdcea7e [file] [log] [blame]
Stefan Wahren12091112015-01-29 18:10:50 +00001#include <dt-bindings/pinctrl/bcm2835.h>
Eric Anholt94cb7f72015-09-28 14:22:05 -07002#include <dt-bindings/clock/bcm2835.h>
Stefan Wahren12091112015-01-29 18:10:50 +00003#include "skeleton.dtsi"
Simon Arlottec9653b2012-05-26 01:04:43 -06004
5/ {
6 compatible = "brcm,bcm2835";
7 model = "BCM2835";
Simon Arlott89214f02012-09-12 19:57:26 -06008 interrupt-parent = <&intc>;
Simon Arlottec9653b2012-05-26 01:04:43 -06009
10 chosen {
Simon Arlott407f9be2012-09-10 23:29:17 -060011 bootargs = "earlyprintk console=ttyAMA0";
Simon Arlottec9653b2012-05-26 01:04:43 -060012 };
13
14 soc {
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0x7e000000 0x20000000 0x02000000>;
Eric Anholt1215baa2015-05-05 13:10:11 -070019 dma-ranges = <0x40000000 0x00000000 0x20000000>;
Simon Arlott89214f02012-09-12 19:57:26 -060020
Stephen Warren25b2f1b2014-02-11 21:48:47 -070021 timer@7e003000 {
Simon Arlottee4af562012-09-10 22:38:35 -060022 compatible = "brcm,bcm2835-system-timer";
23 reg = <0x7e003000 0x1000>;
24 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
Eric Anholt94cb7f72015-09-28 14:22:05 -070025 /* This could be a reference to BCM2835_CLOCK_TIMER,
26 * but we don't have the driver using the common clock
27 * support yet.
28 */
Simon Arlottee4af562012-09-10 22:38:35 -060029 clock-frequency = <1000000>;
30 };
31
Florian Meier89072332014-01-13 12:11:43 +010032 dma: dma@7e007000 {
33 compatible = "brcm,bcm2835-dma";
34 reg = <0x7e007000 0xf00>;
35 interrupts = <1 16>,
36 <1 17>,
37 <1 18>,
38 <1 19>,
39 <1 20>,
40 <1 21>,
41 <1 22>,
42 <1 23>,
43 <1 24>,
44 <1 25>,
45 <1 26>,
46 <1 27>,
47 <1 28>;
48
49 #dma-cells = <1>;
50 brcm,dma-channel-mask = <0x7f35>;
51 };
52
Stephen Warren25b2f1b2014-02-11 21:48:47 -070053 intc: interrupt-controller@7e00b200 {
Simon Arlott89214f02012-09-12 19:57:26 -060054 compatible = "brcm,bcm2835-armctrl-ic";
55 reg = <0x7e00b200 0x200>;
56 interrupt-controller;
57 #interrupt-cells = <2>;
58 };
Simon Arlott407f9be2012-09-10 23:29:17 -060059
Stephen Warren25b2f1b2014-02-11 21:48:47 -070060 watchdog@7e100000 {
Stephen Warrend0f1c7f2012-09-15 22:18:10 -060061 compatible = "brcm,bcm2835-pm-wdt";
62 reg = <0x7e100000 0x28>;
63 };
64
Eric Anholt94cb7f72015-09-28 14:22:05 -070065 clocks: cprman@7e101000 {
66 compatible = "brcm,bcm2835-cprman";
67 #clock-cells = <1>;
68 reg = <0x7e101000 0x2000>;
69
70 /* CPRMAN derives everything from the platform's
71 * oscillator.
72 */
73 clocks = <&clk_osc>;
74 };
75
Stephen Warren25b2f1b2014-02-11 21:48:47 -070076 rng@7e104000 {
Lubomir Rintela1bf7082013-03-28 07:12:04 +010077 compatible = "brcm,bcm2835-rng";
78 reg = <0x7e104000 0x10>;
79 };
80
Eric Anholt05b682b2015-05-05 13:27:46 -070081 mailbox: mailbox@7e00b800 {
82 compatible = "brcm,bcm2835-mbox";
83 reg = <0x7e00b880 0x40>;
84 interrupts = <0 1>;
85 #mbox-cells = <0>;
86 };
87
Stephen Warren25b2f1b2014-02-11 21:48:47 -070088 gpio: gpio@7e200000 {
Stephen Warren805504a2012-09-27 21:54:21 -060089 compatible = "brcm,bcm2835-gpio";
90 reg = <0x7e200000 0xb4>;
91 /*
92 * The GPIO IP block is designed for 3 banks of GPIOs.
93 * Each bank has a GPIO interrupt for itself.
94 * There is an overall "any bank" interrupt.
95 * In order, these are GIC interrupts 17, 18, 19, 20.
96 * Since the BCM2835 only has 2 banks, the 2nd bank
97 * interrupt output appears to be mirrored onto the
98 * 3rd bank's interrupt signal.
99 * So, a bank0 interrupt shows up on 17, 20, and
100 * a bank1 interrupt shows up on 18, 19, 20!
101 */
102 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
103
104 gpio-controller;
105 #gpio-cells = <2>;
106
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 };
Stephen Warren5186bf22012-12-24 21:58:56 -0700110
Stefan Wahren755f1212015-10-02 18:31:15 +0000111 uart0: uart@7e201000 {
Stephen Warrenef3c6902014-02-11 21:44:35 -0700112 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
113 reg = <0x7e201000 0x1000>;
114 interrupts = <2 25>;
Eric Anholt94cb7f72015-09-28 14:22:05 -0700115 clocks = <&clocks BCM2835_CLOCK_UART>,
116 <&clocks BCM2835_CLOCK_VPU>;
117 clock-names = "uartclk", "apb_pclk";
Stephen Warrenef3c6902014-02-11 21:44:35 -0700118 arm,primecell-periphid = <0x00241011>;
119 };
120
Florian Meier9511cc4d2014-01-13 12:16:40 +0100121 i2s: i2s@7e203000 {
122 compatible = "brcm,bcm2835-i2s";
123 reg = <0x7e203000 0x20>,
124 <0x7e101098 0x02>;
125
126 dmas = <&dma 2>,
127 <&dma 3>;
128 dma-names = "tx", "rx";
Mark Brown667bbd52014-09-16 19:51:36 -0600129 status = "disabled";
Florian Meier9511cc4d2014-01-13 12:16:40 +0100130 };
131
Stephen Warren25b2f1b2014-02-11 21:48:47 -0700132 spi: spi@7e204000 {
Stephen Warren6ce5f022013-02-19 21:39:58 -0700133 compatible = "brcm,bcm2835-spi";
134 reg = <0x7e204000 0x1000>;
135 interrupts = <2 22>;
Eric Anholt94cb7f72015-09-28 14:22:05 -0700136 clocks = <&clocks BCM2835_CLOCK_VPU>;
Stephen Warren6ce5f022013-02-19 21:39:58 -0700137 #address-cells = <1>;
138 #size-cells = <0>;
139 status = "disabled";
140 };
141
Baruch Siach64146f22015-03-18 11:00:22 +0200142 i2c0: i2c@7e205000 {
Stephen Warren232fed42012-12-31 23:26:45 -0700143 compatible = "brcm,bcm2835-i2c";
144 reg = <0x7e205000 0x1000>;
145 interrupts = <2 21>;
Eric Anholt94cb7f72015-09-28 14:22:05 -0700146 clocks = <&clocks BCM2835_CLOCK_VPU>;
Stephen Warrena31ab442013-11-25 20:35:42 -0700147 #address-cells = <1>;
148 #size-cells = <0>;
Stephen Warren232fed42012-12-31 23:26:45 -0700149 status = "disabled";
150 };
151
Stephen Warren25b2f1b2014-02-11 21:48:47 -0700152 sdhci: sdhci@7e300000 {
Stephen Warrenef3c6902014-02-11 21:44:35 -0700153 compatible = "brcm,bcm2835-sdhci";
154 reg = <0x7e300000 0x100>;
155 interrupts = <2 30>;
Eric Anholt94cb7f72015-09-28 14:22:05 -0700156 clocks = <&clocks BCM2835_CLOCK_EMMC>;
Stephen Warrenef3c6902014-02-11 21:44:35 -0700157 status = "disabled";
158 };
159
Stephen Warren25b2f1b2014-02-11 21:48:47 -0700160 i2c1: i2c@7e804000 {
Stephen Warren232fed42012-12-31 23:26:45 -0700161 compatible = "brcm,bcm2835-i2c";
162 reg = <0x7e804000 0x1000>;
163 interrupts = <2 21>;
Eric Anholt94cb7f72015-09-28 14:22:05 -0700164 clocks = <&clocks BCM2835_CLOCK_VPU>;
Stephen Warrena31ab442013-11-25 20:35:42 -0700165 #address-cells = <1>;
166 #size-cells = <0>;
Stephen Warren232fed42012-12-31 23:26:45 -0700167 status = "disabled";
168 };
169
Eric Anholt121432c2015-10-09 14:27:47 -0700170 i2c2: i2c@7e805000 {
171 compatible = "brcm,bcm2835-i2c";
172 reg = <0x7e805000 0x1000>;
173 interrupts = <2 21>;
174 clocks = <&clocks BCM2835_CLOCK_VPU>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 status = "disabled";
178 };
179
Stephen Warren25b2f1b2014-02-11 21:48:47 -0700180 usb@7e980000 {
Stephen Warren5631e7f2013-12-26 19:43:10 -0700181 compatible = "brcm,bcm2835-usb";
182 reg = <0x7e980000 0x10000>;
183 interrupts = <1 9>;
184 };
Vince Weaver14ac6522013-12-31 16:54:16 -0500185
186 arm-pmu {
187 compatible = "arm,arm1176-pmu";
188 };
Stephen Warren5186bf22012-12-24 21:58:56 -0700189 };
190
Stephen Warren9692c192013-01-14 21:07:20 -0700191 clocks {
192 compatible = "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <0>;
Stephen Warren232fed42012-12-31 23:26:45 -0700195
Eric Anholt94cb7f72015-09-28 14:22:05 -0700196 /* The oscillator is the root of the clock tree. */
197 clk_osc: clock@3 {
Stephen Warren9692c192013-01-14 21:07:20 -0700198 compatible = "fixed-clock";
Eric Anholt94cb7f72015-09-28 14:22:05 -0700199 reg = <3>;
Stephen Warren9692c192013-01-14 21:07:20 -0700200 #clock-cells = <0>;
Eric Anholt94cb7f72015-09-28 14:22:05 -0700201 clock-output-names = "osc";
202 clock-frequency = <19200000>;
Stephen Warren9692c192013-01-14 21:07:20 -0700203 };
204
Simon Arlottec9653b2012-05-26 01:04:43 -0600205 };
206};