blob: 6f9daaead5f90a7355d6e1fadc0baf6f2c5f6a4a [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +02001/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020011 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrene5cbeef2012-03-13 13:28:02 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
Stephen Warren8c6a3852012-03-27 12:41:37 -060054 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -060063 };
64 };
65
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020066 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -060067 status = "okay";
Stephen Warren95decf82012-05-11 16:11:38 -060068 clock-frequency = <408000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020069 };
70
71 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -060072 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020073 clock-frequency = <100000>;
74 };
75
76 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -060077 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020078 clock-frequency = <100000>;
79 };
80
81 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -060082 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020083 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +053084
85 /* ALS and Proximity sensor */
86 isl29028@44 {
87 compatible = "isil,isl29028";
88 reg = <0x44>;
89 interrupt-parent = <&gpio>;
90 interrupts = <88 0x04>; /*gpio PL0 */
91 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020092 };
93
94 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -060095 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020096 clock-frequency = <100000>;
97 };
98
99 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600100 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200101 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600102
103 wm8903: wm8903@1a {
104 compatible = "wlf,wm8903";
105 reg = <0x1a>;
106 interrupt-parent = <&gpio>;
107 interrupts = <179 0x04>; /* gpio PW3 */
108
109 gpio-controller;
110 #gpio-cells = <2>;
111
112 micdet-cfg = <0>;
113 micdet-delay = <100>;
114 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
115 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000116
117 tps62361 {
118 compatible = "ti,tps62361";
119 reg = <0x60>;
120
121 regulator-name = "tps62361-vout";
122 regulator-min-microvolt = <500000>;
123 regulator-max-microvolt = <1500000>;
124 regulator-boot-on;
125 regulator-always-on;
126 ti,vsel0-state-high;
127 ti,vsel1-state-high;
128 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530129
130 pmic: tps65911@2d {
131 compatible = "ti,tps65911";
132 reg = <0x2d>;
133
134 interrupts = <0 86 0x4>;
135 #interrupt-cells = <2>;
136 interrupt-controller;
137
138 #gpio-cells = <2>;
139 gpio-controller;
140
141 vcc1-supply = <&vdd_ac_bat_reg>;
142 vcc2-supply = <&vdd_ac_bat_reg>;
143 vcc3-supply = <&vio_reg>;
144 vcc5-supply = <&vdd_ac_bat_reg>;
145 vcc6-supply = <&vdd2_reg>;
146 vcc7-supply = <&vdd_ac_bat_reg>;
147 vccio-supply = <&vdd_ac_bat_reg>;
148
149 regulators {
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 vdd1_reg: regulator@0 {
154 reg = <0>;
155 regulator-compatible = "vdd1";
156 regulator-name = "vddio_ddr_1v2";
157 regulator-min-microvolt = <1200000>;
158 regulator-max-microvolt = <1200000>;
159 regulator-always-on;
160 };
161
162 vdd2_reg: regulator@1 {
163 reg = <1>;
164 regulator-compatible = "vdd2";
165 regulator-name = "vdd_1v5_gen";
166 regulator-min-microvolt = <1500000>;
167 regulator-max-microvolt = <1500000>;
168 regulator-always-on;
169 };
170
171 vddctrl_reg: regulator@2 {
172 reg = <2>;
173 regulator-compatible = "vddctrl";
174 regulator-name = "vdd_cpu,vdd_sys";
175 regulator-min-microvolt = <1000000>;
176 regulator-max-microvolt = <1000000>;
177 regulator-always-on;
178 };
179
180 vio_reg: regulator@3 {
181 reg = <3>;
182 regulator-compatible = "vio";
183 regulator-name = "vdd_1v8_gen";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <1800000>;
186 regulator-always-on;
187 };
188
189 ldo1_reg: regulator@4 {
190 reg = <4>;
191 regulator-compatible = "ldo1";
192 regulator-name = "vdd_pexa,vdd_pexb";
193 regulator-min-microvolt = <1050000>;
194 regulator-max-microvolt = <1050000>;
195 };
196
197 ldo2_reg: regulator@5 {
198 reg = <5>;
199 regulator-compatible = "ldo2";
200 regulator-name = "vdd_sata,avdd_plle";
201 regulator-min-microvolt = <1050000>;
202 regulator-max-microvolt = <1050000>;
203 };
204
205 /* LDO3 is not connected to anything */
206
207 ldo4_reg: regulator@7 {
208 reg = <7>;
209 regulator-compatible = "ldo4";
210 regulator-name = "vdd_rtc";
211 regulator-min-microvolt = <1200000>;
212 regulator-max-microvolt = <1200000>;
213 regulator-always-on;
214 };
215
216 ldo6_reg: regulator@9 {
217 reg = <9>;
218 regulator-compatible = "ldo6";
219 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
220 regulator-min-microvolt = <1200000>;
221 regulator-max-microvolt = <1200000>;
222 };
223
224 ldo7_reg: regulator@10 {
225 reg = <10>;
226 regulator-compatible = "ldo7";
227 regulator-name = "vdd_pllm,x,u,a_p_c_s";
228 regulator-min-microvolt = <1200000>;
229 regulator-max-microvolt = <1200000>;
230 regulator-always-on;
231 };
232
233 ldo8_reg: regulator@11 {
234 reg = <11>;
235 regulator-compatible = "ldo8";
236 regulator-name = "vdd_ddr_hs";
237 regulator-min-microvolt = <1000000>;
238 regulator-max-microvolt = <1000000>;
239 regulator-always-on;
240 };
241 };
242 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200243 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700244
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600245 ahub {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600246 i2s@70080400 {
247 status = "okay";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600248 };
249 };
250
Laxman Dewangan167e6272012-08-09 16:30:37 +0530251 pmc {
252 status = "okay";
253 nvidia,invert-interrupt;
254 };
255
Stephen Warrenc04abb32012-05-11 17:03:26 -0600256 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600257 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600258 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
259 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
260 power-gpios = <&gpio 31 0>; /* gpio PD7 */
Arnd Bergmann7f217792012-05-13 00:14:24 -0400261 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600262 };
263
Stephen Warrenc04abb32012-05-11 17:03:26 -0600264 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600265 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400266 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600267 };
268
Laxman Dewangan167e6272012-08-09 16:30:37 +0530269 regulators {
270 compatible = "simple-bus";
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 vdd_ac_bat_reg: regulator@0 {
275 compatible = "regulator-fixed";
276 reg = <0>;
277 regulator-name = "vdd_ac_bat";
278 regulator-min-microvolt = <5000000>;
279 regulator-max-microvolt = <5000000>;
280 regulator-always-on;
281 };
282 };
283
Stephen Warren8c6a3852012-03-27 12:41:37 -0600284 sound {
285 compatible = "nvidia,tegra-audio-wm8903-cardhu",
286 "nvidia,tegra-audio-wm8903";
287 nvidia,model = "NVIDIA Tegra Cardhu";
288
289 nvidia,audio-routing =
290 "Headphone Jack", "HPOUTR",
291 "Headphone Jack", "HPOUTL",
292 "Int Spk", "ROP",
293 "Int Spk", "RON",
294 "Int Spk", "LOP",
295 "Int Spk", "LON",
296 "Mic Jack", "MICBIAS",
297 "IN1L", "Mic Jack";
298
299 nvidia,i2s-controller = <&tegra_i2s1>;
300 nvidia,audio-codec = <&wm8903>;
301
302 nvidia,spkr-en-gpios = <&wm8903 2 0>;
303 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
304 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200305};