Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1 | /* |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 2 | * Copyright (C) Ericsson AB 2007-2008 |
| 3 | * Copyright (C) ST-Ericsson SA 2008-2010 |
Per Forlin | 661385f | 2010-10-06 09:05:28 +0000 | [diff] [blame] | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 6 | * License terms: GNU General Public License (GPL) version 2 |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
Alexey Dobriyan | b7f080c | 2011-06-16 11:01:34 +0000 | [diff] [blame] | 9 | #include <linux/dma-mapping.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 10 | #include <linux/kernel.h> |
| 11 | #include <linux/slab.h> |
Paul Gortmaker | f492b21 | 2011-07-31 16:17:36 -0400 | [diff] [blame] | 12 | #include <linux/export.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 13 | #include <linux/dmaengine.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/delay.h> |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 17 | #include <linux/pm.h> |
| 18 | #include <linux/pm_runtime.h> |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 19 | #include <linux/err.h> |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 20 | #include <linux/of.h> |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 21 | #include <linux/amba/bus.h> |
Linus Walleij | 15e4b78 | 2012-04-12 18:12:43 +0200 | [diff] [blame] | 22 | #include <linux/regulator/consumer.h> |
Linus Walleij | 865fab6 | 2012-10-18 14:20:16 +0200 | [diff] [blame] | 23 | #include <linux/platform_data/dma-ste-dma40.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 24 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 25 | #include "dmaengine.h" |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 26 | #include "ste_dma40_ll.h" |
| 27 | |
| 28 | #define D40_NAME "dma40" |
| 29 | |
| 30 | #define D40_PHY_CHAN -1 |
| 31 | |
| 32 | /* For masking out/in 2 bit channel positions */ |
| 33 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) |
| 34 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) |
| 35 | |
| 36 | /* Maximum iterations taken before giving up suspending a channel */ |
| 37 | #define D40_SUSPEND_MAX_IT 500 |
| 38 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 39 | /* Milliseconds */ |
| 40 | #define DMA40_AUTOSUSPEND_DELAY 100 |
| 41 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 42 | /* Hardware requirement on LCLA alignment */ |
| 43 | #define LCLA_ALIGNMENT 0x40000 |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 44 | |
| 45 | /* Max number of links per event group */ |
| 46 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 |
| 47 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP |
| 48 | |
Lee Jones | db72da9 | 2013-05-03 15:32:03 +0100 | [diff] [blame] | 49 | /* Max number of logical channels per physical channel */ |
| 50 | #define D40_MAX_LOG_CHAN_PER_PHY 32 |
| 51 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 52 | /* Attempts before giving up to trying to get pages that are aligned */ |
| 53 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 |
| 54 | |
| 55 | /* Bit markings for allocation map */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 56 | #define D40_ALLOC_FREE (1 << 31) |
| 57 | #define D40_ALLOC_PHY (1 << 30) |
| 58 | #define D40_ALLOC_LOG_FREE 0 |
| 59 | |
Lee Jones | 664a57e | 2013-05-03 15:31:53 +0100 | [diff] [blame] | 60 | /* Reserved event lines for memcpy only. */ |
Linus Walleij | a2acaa2 | 2013-05-03 21:46:09 +0200 | [diff] [blame] | 61 | #define DB8500_DMA_MEMCPY_EV_0 51 |
| 62 | #define DB8500_DMA_MEMCPY_EV_1 56 |
| 63 | #define DB8500_DMA_MEMCPY_EV_2 57 |
| 64 | #define DB8500_DMA_MEMCPY_EV_3 58 |
| 65 | #define DB8500_DMA_MEMCPY_EV_4 59 |
| 66 | #define DB8500_DMA_MEMCPY_EV_5 60 |
| 67 | |
| 68 | static int dma40_memcpy_channels[] = { |
| 69 | DB8500_DMA_MEMCPY_EV_0, |
| 70 | DB8500_DMA_MEMCPY_EV_1, |
| 71 | DB8500_DMA_MEMCPY_EV_2, |
| 72 | DB8500_DMA_MEMCPY_EV_3, |
| 73 | DB8500_DMA_MEMCPY_EV_4, |
| 74 | DB8500_DMA_MEMCPY_EV_5, |
| 75 | }; |
Lee Jones | 664a57e | 2013-05-03 15:31:53 +0100 | [diff] [blame] | 76 | |
Lee Jones | 29027a1 | 2013-05-03 15:31:54 +0100 | [diff] [blame] | 77 | /* Default configuration for physcial memcpy */ |
| 78 | struct stedma40_chan_cfg dma40_memcpy_conf_phy = { |
| 79 | .mode = STEDMA40_MODE_PHYSICAL, |
| 80 | .dir = STEDMA40_MEM_TO_MEM, |
| 81 | |
| 82 | .src_info.data_width = STEDMA40_BYTE_WIDTH, |
| 83 | .src_info.psize = STEDMA40_PSIZE_PHY_1, |
| 84 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 85 | |
| 86 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, |
| 87 | .dst_info.psize = STEDMA40_PSIZE_PHY_1, |
| 88 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 89 | }; |
| 90 | |
| 91 | /* Default configuration for logical memcpy */ |
| 92 | struct stedma40_chan_cfg dma40_memcpy_conf_log = { |
| 93 | .mode = STEDMA40_MODE_LOGICAL, |
| 94 | .dir = STEDMA40_MEM_TO_MEM, |
| 95 | |
| 96 | .src_info.data_width = STEDMA40_BYTE_WIDTH, |
| 97 | .src_info.psize = STEDMA40_PSIZE_LOG_1, |
| 98 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 99 | |
| 100 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, |
| 101 | .dst_info.psize = STEDMA40_PSIZE_LOG_1, |
| 102 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 103 | }; |
| 104 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 105 | /** |
| 106 | * enum 40_command - The different commands and/or statuses. |
| 107 | * |
| 108 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, |
| 109 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. |
| 110 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. |
| 111 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. |
| 112 | */ |
| 113 | enum d40_command { |
| 114 | D40_DMA_STOP = 0, |
| 115 | D40_DMA_RUN = 1, |
| 116 | D40_DMA_SUSPEND_REQ = 2, |
| 117 | D40_DMA_SUSPENDED = 3 |
| 118 | }; |
| 119 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 120 | /* |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 121 | * enum d40_events - The different Event Enables for the event lines. |
| 122 | * |
| 123 | * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan. |
| 124 | * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan. |
| 125 | * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line. |
| 126 | * @D40_ROUND_EVENTLINE: Status check for event line. |
| 127 | */ |
| 128 | |
| 129 | enum d40_events { |
| 130 | D40_DEACTIVATE_EVENTLINE = 0, |
| 131 | D40_ACTIVATE_EVENTLINE = 1, |
| 132 | D40_SUSPEND_REQ_EVENTLINE = 2, |
| 133 | D40_ROUND_EVENTLINE = 3 |
| 134 | }; |
| 135 | |
| 136 | /* |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 137 | * These are the registers that has to be saved and later restored |
| 138 | * when the DMA hw is powered off. |
| 139 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. |
| 140 | */ |
| 141 | static u32 d40_backup_regs[] = { |
| 142 | D40_DREG_LCPA, |
| 143 | D40_DREG_LCLA, |
| 144 | D40_DREG_PRMSE, |
| 145 | D40_DREG_PRMSO, |
| 146 | D40_DREG_PRMOE, |
| 147 | D40_DREG_PRMOO, |
| 148 | }; |
| 149 | |
| 150 | #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs) |
| 151 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 152 | /* |
| 153 | * since 9540 and 8540 has the same HW revision |
| 154 | * use v4a for 9540 or ealier |
| 155 | * use v4b for 8540 or later |
| 156 | * HW revision: |
| 157 | * DB8500ed has revision 0 |
| 158 | * DB8500v1 has revision 2 |
| 159 | * DB8500v2 has revision 3 |
| 160 | * AP9540v1 has revision 4 |
| 161 | * DB8540v1 has revision 4 |
| 162 | * TODO: Check if all these registers have to be saved/restored on dma40 v4a |
| 163 | */ |
| 164 | static u32 d40_backup_regs_v4a[] = { |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 165 | D40_DREG_PSEG1, |
| 166 | D40_DREG_PSEG2, |
| 167 | D40_DREG_PSEG3, |
| 168 | D40_DREG_PSEG4, |
| 169 | D40_DREG_PCEG1, |
| 170 | D40_DREG_PCEG2, |
| 171 | D40_DREG_PCEG3, |
| 172 | D40_DREG_PCEG4, |
| 173 | D40_DREG_RSEG1, |
| 174 | D40_DREG_RSEG2, |
| 175 | D40_DREG_RSEG3, |
| 176 | D40_DREG_RSEG4, |
| 177 | D40_DREG_RCEG1, |
| 178 | D40_DREG_RCEG2, |
| 179 | D40_DREG_RCEG3, |
| 180 | D40_DREG_RCEG4, |
| 181 | }; |
| 182 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 183 | #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a) |
| 184 | |
| 185 | static u32 d40_backup_regs_v4b[] = { |
| 186 | D40_DREG_CPSEG1, |
| 187 | D40_DREG_CPSEG2, |
| 188 | D40_DREG_CPSEG3, |
| 189 | D40_DREG_CPSEG4, |
| 190 | D40_DREG_CPSEG5, |
| 191 | D40_DREG_CPCEG1, |
| 192 | D40_DREG_CPCEG2, |
| 193 | D40_DREG_CPCEG3, |
| 194 | D40_DREG_CPCEG4, |
| 195 | D40_DREG_CPCEG5, |
| 196 | D40_DREG_CRSEG1, |
| 197 | D40_DREG_CRSEG2, |
| 198 | D40_DREG_CRSEG3, |
| 199 | D40_DREG_CRSEG4, |
| 200 | D40_DREG_CRSEG5, |
| 201 | D40_DREG_CRCEG1, |
| 202 | D40_DREG_CRCEG2, |
| 203 | D40_DREG_CRCEG3, |
| 204 | D40_DREG_CRCEG4, |
| 205 | D40_DREG_CRCEG5, |
| 206 | }; |
| 207 | |
| 208 | #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b) |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 209 | |
| 210 | static u32 d40_backup_regs_chan[] = { |
| 211 | D40_CHAN_REG_SSCFG, |
| 212 | D40_CHAN_REG_SSELT, |
| 213 | D40_CHAN_REG_SSPTR, |
| 214 | D40_CHAN_REG_SSLNK, |
| 215 | D40_CHAN_REG_SDCFG, |
| 216 | D40_CHAN_REG_SDELT, |
| 217 | D40_CHAN_REG_SDPTR, |
| 218 | D40_CHAN_REG_SDLNK, |
| 219 | }; |
| 220 | |
Lee Jones | 84b3da1 | 2013-05-03 15:31:58 +0100 | [diff] [blame] | 221 | #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \ |
| 222 | BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B) |
| 223 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 224 | /** |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 225 | * struct d40_interrupt_lookup - lookup table for interrupt handler |
| 226 | * |
| 227 | * @src: Interrupt mask register. |
| 228 | * @clr: Interrupt clear register. |
| 229 | * @is_error: true if this is an error interrupt. |
| 230 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to |
| 231 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. |
| 232 | */ |
| 233 | struct d40_interrupt_lookup { |
| 234 | u32 src; |
| 235 | u32 clr; |
| 236 | bool is_error; |
| 237 | int offset; |
| 238 | }; |
| 239 | |
| 240 | |
| 241 | static struct d40_interrupt_lookup il_v4a[] = { |
| 242 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, |
| 243 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, |
| 244 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, |
| 245 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, |
| 246 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, |
| 247 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, |
| 248 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, |
| 249 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, |
| 250 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, |
| 251 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, |
| 252 | }; |
| 253 | |
| 254 | static struct d40_interrupt_lookup il_v4b[] = { |
| 255 | {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0}, |
| 256 | {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32}, |
| 257 | {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64}, |
| 258 | {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96}, |
| 259 | {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128}, |
| 260 | {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0}, |
| 261 | {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32}, |
| 262 | {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64}, |
| 263 | {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96}, |
| 264 | {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128}, |
| 265 | {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN}, |
| 266 | {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN}, |
| 267 | }; |
| 268 | |
| 269 | /** |
| 270 | * struct d40_reg_val - simple lookup struct |
| 271 | * |
| 272 | * @reg: The register. |
| 273 | * @val: The value that belongs to the register in reg. |
| 274 | */ |
| 275 | struct d40_reg_val { |
| 276 | unsigned int reg; |
| 277 | unsigned int val; |
| 278 | }; |
| 279 | |
| 280 | static __initdata struct d40_reg_val dma_init_reg_v4a[] = { |
| 281 | /* Clock every part of the DMA block from start */ |
| 282 | { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, |
| 283 | |
| 284 | /* Interrupts on all logical channels */ |
| 285 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, |
| 286 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, |
| 287 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, |
| 288 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, |
| 289 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, |
| 290 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, |
| 291 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, |
| 292 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, |
| 293 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, |
| 294 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, |
| 295 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, |
| 296 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} |
| 297 | }; |
| 298 | static __initdata struct d40_reg_val dma_init_reg_v4b[] = { |
| 299 | /* Clock every part of the DMA block from start */ |
| 300 | { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, |
| 301 | |
| 302 | /* Interrupts on all logical channels */ |
| 303 | { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF}, |
| 304 | { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF}, |
| 305 | { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF}, |
| 306 | { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF}, |
| 307 | { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF}, |
| 308 | { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF}, |
| 309 | { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF}, |
| 310 | { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF}, |
| 311 | { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF}, |
| 312 | { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF}, |
| 313 | { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF}, |
| 314 | { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF}, |
| 315 | { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF}, |
| 316 | { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF}, |
| 317 | { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF} |
| 318 | }; |
| 319 | |
| 320 | /** |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 321 | * struct d40_lli_pool - Structure for keeping LLIs in memory |
| 322 | * |
| 323 | * @base: Pointer to memory area when the pre_alloc_lli's are not large |
| 324 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if |
| 325 | * pre_alloc_lli is used. |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 326 | * @dma_addr: DMA address, if mapped |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 327 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
| 328 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, |
| 329 | * one buffer to one buffer. |
| 330 | */ |
| 331 | struct d40_lli_pool { |
| 332 | void *base; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 333 | int size; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 334 | dma_addr_t dma_addr; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 335 | /* Space for dst and src, plus an extra for padding */ |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 336 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | /** |
| 340 | * struct d40_desc - A descriptor is one DMA job. |
| 341 | * |
| 342 | * @lli_phy: LLI settings for physical channel. Both src and dst= |
| 343 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if |
| 344 | * lli_len equals one. |
| 345 | * @lli_log: Same as above but for logical channels. |
| 346 | * @lli_pool: The pool with two entries pre-allocated. |
Per Friden | 941b77a | 2010-06-20 21:24:45 +0000 | [diff] [blame] | 347 | * @lli_len: Number of llis of current descriptor. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 348 | * @lli_current: Number of transferred llis. |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 349 | * @lcla_alloc: Number of LCLA entries allocated. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 350 | * @txd: DMA engine struct. Used for among other things for communication |
| 351 | * during a transfer. |
| 352 | * @node: List entry. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 353 | * @is_in_client_list: true if the client owns this descriptor. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 354 | * @cyclic: true if this is a cyclic job |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 355 | * |
| 356 | * This descriptor is used for both logical and physical transfers. |
| 357 | */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 358 | struct d40_desc { |
| 359 | /* LLI physical */ |
| 360 | struct d40_phy_lli_bidir lli_phy; |
| 361 | /* LLI logical */ |
| 362 | struct d40_log_lli_bidir lli_log; |
| 363 | |
| 364 | struct d40_lli_pool lli_pool; |
Per Friden | 941b77a | 2010-06-20 21:24:45 +0000 | [diff] [blame] | 365 | int lli_len; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 366 | int lli_current; |
| 367 | int lcla_alloc; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 368 | |
| 369 | struct dma_async_tx_descriptor txd; |
| 370 | struct list_head node; |
| 371 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 372 | bool is_in_client_list; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 373 | bool cyclic; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 374 | }; |
| 375 | |
| 376 | /** |
| 377 | * struct d40_lcla_pool - LCLA pool settings and data. |
| 378 | * |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 379 | * @base: The virtual address of LCLA. 18 bit aligned. |
| 380 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. |
| 381 | * This pointer is only there for clean-up on error. |
| 382 | * @pages: The number of pages needed for all physical channels. |
| 383 | * Only used later for clean-up on error |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 384 | * @lock: Lock to protect the content in this struct. |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 385 | * @alloc_map: big map over which LCLA entry is own by which job. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 386 | */ |
| 387 | struct d40_lcla_pool { |
| 388 | void *base; |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 389 | dma_addr_t dma_addr; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 390 | void *base_unaligned; |
| 391 | int pages; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 392 | spinlock_t lock; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 393 | struct d40_desc **alloc_map; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 394 | }; |
| 395 | |
| 396 | /** |
| 397 | * struct d40_phy_res - struct for handling eventlines mapped to physical |
| 398 | * channels. |
| 399 | * |
| 400 | * @lock: A lock protection this entity. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 401 | * @reserved: True if used by secure world or otherwise. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 402 | * @num: The physical channel number of this entity. |
| 403 | * @allocated_src: Bit mapped to show which src event line's are mapped to |
| 404 | * this physical channel. Can also be free or physically allocated. |
| 405 | * @allocated_dst: Same as for src but is dst. |
| 406 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 407 | * event line number. |
Fabio Baltieri | 7407048 | 2012-12-18 12:25:14 +0100 | [diff] [blame] | 408 | * @use_soft_lli: To mark if the linked lists of channel are managed by SW. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 409 | */ |
| 410 | struct d40_phy_res { |
| 411 | spinlock_t lock; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 412 | bool reserved; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 413 | int num; |
| 414 | u32 allocated_src; |
| 415 | u32 allocated_dst; |
Fabio Baltieri | 7407048 | 2012-12-18 12:25:14 +0100 | [diff] [blame] | 416 | bool use_soft_lli; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 417 | }; |
| 418 | |
| 419 | struct d40_base; |
| 420 | |
| 421 | /** |
| 422 | * struct d40_chan - Struct that describes a channel. |
| 423 | * |
| 424 | * @lock: A spinlock to protect this struct. |
| 425 | * @log_num: The logical number, if any of this channel. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 426 | * @pending_tx: The number of pending transfers. Used between interrupt handler |
| 427 | * and tasklet. |
| 428 | * @busy: Set to true when transfer is ongoing on this channel. |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 429 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
| 430 | * point is NULL, then the channel is not allocated. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 431 | * @chan: DMA engine handle. |
| 432 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a |
| 433 | * transfer and call client callback. |
| 434 | * @client: Cliented owned descriptor list. |
Per Forlin | da063d2 | 2011-08-29 13:33:32 +0200 | [diff] [blame] | 435 | * @pending_queue: Submitted jobs, to be issued by issue_pending() |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 436 | * @active: Active descriptor. |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 437 | * @done: Completed jobs |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 438 | * @queue: Queued jobs. |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 439 | * @prepare_queue: Prepared jobs. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 440 | * @dma_cfg: The client configuration of this dma channel. |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 441 | * @configured: whether the dma_cfg configuration is valid |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 442 | * @base: Pointer to the device instance struct. |
| 443 | * @src_def_cfg: Default cfg register setting for src. |
| 444 | * @dst_def_cfg: Default cfg register setting for dst. |
| 445 | * @log_def: Default logical channel settings. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 446 | * @lcpa: Pointer to dst and src lcpa settings. |
om prakash | ae752bf | 2011-06-27 11:33:31 +0200 | [diff] [blame] | 447 | * @runtime_addr: runtime configured address. |
| 448 | * @runtime_direction: runtime configured direction. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 449 | * |
| 450 | * This struct can either "be" a logical or a physical channel. |
| 451 | */ |
| 452 | struct d40_chan { |
| 453 | spinlock_t lock; |
| 454 | int log_num; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 455 | int pending_tx; |
| 456 | bool busy; |
| 457 | struct d40_phy_res *phy_chan; |
| 458 | struct dma_chan chan; |
| 459 | struct tasklet_struct tasklet; |
| 460 | struct list_head client; |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 461 | struct list_head pending_queue; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 462 | struct list_head active; |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 463 | struct list_head done; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 464 | struct list_head queue; |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 465 | struct list_head prepare_queue; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 466 | struct stedma40_chan_cfg dma_cfg; |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 467 | bool configured; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 468 | struct d40_base *base; |
| 469 | /* Default register configurations */ |
| 470 | u32 src_def_cfg; |
| 471 | u32 dst_def_cfg; |
| 472 | struct d40_def_lcsp log_def; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 473 | struct d40_log_lli_full *lcpa; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 474 | /* Runtime reconfiguration */ |
| 475 | dma_addr_t runtime_addr; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 476 | enum dma_transfer_direction runtime_direction; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 477 | }; |
| 478 | |
| 479 | /** |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 480 | * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA |
| 481 | * controller |
| 482 | * |
| 483 | * @backup: the pointer to the registers address array for backup |
| 484 | * @backup_size: the size of the registers address array for backup |
| 485 | * @realtime_en: the realtime enable register |
| 486 | * @realtime_clear: the realtime clear register |
| 487 | * @high_prio_en: the high priority enable register |
| 488 | * @high_prio_clear: the high priority clear register |
| 489 | * @interrupt_en: the interrupt enable register |
| 490 | * @interrupt_clear: the interrupt clear register |
| 491 | * @il: the pointer to struct d40_interrupt_lookup |
| 492 | * @il_size: the size of d40_interrupt_lookup array |
| 493 | * @init_reg: the pointer to the struct d40_reg_val |
| 494 | * @init_reg_size: the size of d40_reg_val array |
| 495 | */ |
| 496 | struct d40_gen_dmac { |
| 497 | u32 *backup; |
| 498 | u32 backup_size; |
| 499 | u32 realtime_en; |
| 500 | u32 realtime_clear; |
| 501 | u32 high_prio_en; |
| 502 | u32 high_prio_clear; |
| 503 | u32 interrupt_en; |
| 504 | u32 interrupt_clear; |
| 505 | struct d40_interrupt_lookup *il; |
| 506 | u32 il_size; |
| 507 | struct d40_reg_val *init_reg; |
| 508 | u32 init_reg_size; |
| 509 | }; |
| 510 | |
| 511 | /** |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 512 | * struct d40_base - The big global struct, one for each probe'd instance. |
| 513 | * |
| 514 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. |
| 515 | * @execmd_lock: Lock for execute command usage since several channels share |
| 516 | * the same physical register. |
| 517 | * @dev: The device structure. |
| 518 | * @virtbase: The virtual base address of the DMA's register. |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 519 | * @rev: silicon revision detected. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 520 | * @clk: Pointer to the DMA clock structure. |
| 521 | * @phy_start: Physical memory start of the DMA registers. |
| 522 | * @phy_size: Size of the DMA register map. |
| 523 | * @irq: The IRQ number. |
| 524 | * @num_phy_chans: The number of physical channels. Read from HW. This |
| 525 | * is the number of available channels for this driver, not counting "Secure |
| 526 | * mode" allocated physical channels. |
| 527 | * @num_log_chans: The number of logical channels. Calculated from |
| 528 | * num_phy_chans. |
| 529 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. |
| 530 | * @dma_slave: dma_device channels that can do only do slave transfers. |
| 531 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 532 | * @phy_chans: Room for all possible physical channels in system. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 533 | * @log_chans: Room for all possible logical channels in system. |
| 534 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points |
| 535 | * to log_chans entries. |
| 536 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points |
| 537 | * to phy_chans entries. |
| 538 | * @plat_data: Pointer to provided platform_data which is the driver |
| 539 | * configuration. |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 540 | * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 541 | * @phy_res: Vector containing all physical channels. |
| 542 | * @lcla_pool: lcla pool settings and data. |
| 543 | * @lcpa_base: The virtual mapped address of LCPA. |
| 544 | * @phy_lcpa: The physical address of the LCPA. |
| 545 | * @lcpa_size: The size of the LCPA area. |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 546 | * @desc_slab: cache for descriptors. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 547 | * @reg_val_backup: Here the values of some hardware registers are stored |
| 548 | * before the DMA is powered off. They are restored when the power is back on. |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 549 | * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and |
| 550 | * later |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 551 | * @reg_val_backup_chan: Backup data for standard channel parameter registers. |
| 552 | * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off. |
| 553 | * @initialized: true if the dma has been initialized |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 554 | * @gen_dmac: the struct for generic registers values to represent u8500/8540 |
| 555 | * DMA controller |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 556 | */ |
| 557 | struct d40_base { |
| 558 | spinlock_t interrupt_lock; |
| 559 | spinlock_t execmd_lock; |
| 560 | struct device *dev; |
| 561 | void __iomem *virtbase; |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 562 | u8 rev:4; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 563 | struct clk *clk; |
| 564 | phys_addr_t phy_start; |
| 565 | resource_size_t phy_size; |
| 566 | int irq; |
| 567 | int num_phy_chans; |
| 568 | int num_log_chans; |
Per Forlin | b96710e | 2011-10-18 18:39:47 +0200 | [diff] [blame] | 569 | struct device_dma_parameters dma_parms; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 570 | struct dma_device dma_both; |
| 571 | struct dma_device dma_slave; |
| 572 | struct dma_device dma_memcpy; |
| 573 | struct d40_chan *phy_chans; |
| 574 | struct d40_chan *log_chans; |
| 575 | struct d40_chan **lookup_log_chans; |
| 576 | struct d40_chan **lookup_phy_chans; |
| 577 | struct stedma40_platform_data *plat_data; |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 578 | struct regulator *lcpa_regulator; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 579 | /* Physical half channels */ |
| 580 | struct d40_phy_res *phy_res; |
| 581 | struct d40_lcla_pool lcla_pool; |
| 582 | void *lcpa_base; |
| 583 | dma_addr_t phy_lcpa; |
| 584 | resource_size_t lcpa_size; |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 585 | struct kmem_cache *desc_slab; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 586 | u32 reg_val_backup[BACKUP_REGS_SZ]; |
Lee Jones | 84b3da1 | 2013-05-03 15:31:58 +0100 | [diff] [blame] | 587 | u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX]; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 588 | u32 *reg_val_backup_chan; |
| 589 | u16 gcc_pwr_off_mask; |
| 590 | bool initialized; |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 591 | struct d40_gen_dmac gen_dmac; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 592 | }; |
| 593 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 594 | static struct device *chan2dev(struct d40_chan *d40c) |
| 595 | { |
| 596 | return &d40c->chan.dev->device; |
| 597 | } |
| 598 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 599 | static bool chan_is_physical(struct d40_chan *chan) |
| 600 | { |
| 601 | return chan->log_num == D40_PHY_CHAN; |
| 602 | } |
| 603 | |
| 604 | static bool chan_is_logical(struct d40_chan *chan) |
| 605 | { |
| 606 | return !chan_is_physical(chan); |
| 607 | } |
| 608 | |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 609 | static void __iomem *chan_base(struct d40_chan *chan) |
| 610 | { |
| 611 | return chan->base->virtbase + D40_DREG_PCBASE + |
| 612 | chan->phy_chan->num * D40_DREG_PCDELTA; |
| 613 | } |
| 614 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 615 | #define d40_err(dev, format, arg...) \ |
| 616 | dev_err(dev, "[%s] " format, __func__, ## arg) |
| 617 | |
| 618 | #define chan_err(d40c, format, arg...) \ |
| 619 | d40_err(chan2dev(d40c), format, ## arg) |
| 620 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 621 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 622 | int lli_len) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 623 | { |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 624 | bool is_log = chan_is_logical(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 625 | u32 align; |
| 626 | void *base; |
| 627 | |
| 628 | if (is_log) |
| 629 | align = sizeof(struct d40_log_lli); |
| 630 | else |
| 631 | align = sizeof(struct d40_phy_lli); |
| 632 | |
| 633 | if (lli_len == 1) { |
| 634 | base = d40d->lli_pool.pre_alloc_lli; |
| 635 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); |
| 636 | d40d->lli_pool.base = NULL; |
| 637 | } else { |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 638 | d40d->lli_pool.size = lli_len * 2 * align; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 639 | |
| 640 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); |
| 641 | d40d->lli_pool.base = base; |
| 642 | |
| 643 | if (d40d->lli_pool.base == NULL) |
| 644 | return -ENOMEM; |
| 645 | } |
| 646 | |
| 647 | if (is_log) { |
Rabin Vincent | d924aba | 2011-01-25 11:18:16 +0100 | [diff] [blame] | 648 | d40d->lli_log.src = PTR_ALIGN(base, align); |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 649 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 650 | |
| 651 | d40d->lli_pool.dma_addr = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 652 | } else { |
Rabin Vincent | d924aba | 2011-01-25 11:18:16 +0100 | [diff] [blame] | 653 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 654 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 655 | |
| 656 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, |
| 657 | d40d->lli_phy.src, |
| 658 | d40d->lli_pool.size, |
| 659 | DMA_TO_DEVICE); |
| 660 | |
| 661 | if (dma_mapping_error(d40c->base->dev, |
| 662 | d40d->lli_pool.dma_addr)) { |
| 663 | kfree(d40d->lli_pool.base); |
| 664 | d40d->lli_pool.base = NULL; |
| 665 | d40d->lli_pool.dma_addr = 0; |
| 666 | return -ENOMEM; |
| 667 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 668 | } |
| 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 673 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 674 | { |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 675 | if (d40d->lli_pool.dma_addr) |
| 676 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, |
| 677 | d40d->lli_pool.size, DMA_TO_DEVICE); |
| 678 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 679 | kfree(d40d->lli_pool.base); |
| 680 | d40d->lli_pool.base = NULL; |
| 681 | d40d->lli_pool.size = 0; |
| 682 | d40d->lli_log.src = NULL; |
| 683 | d40d->lli_log.dst = NULL; |
| 684 | d40d->lli_phy.src = NULL; |
| 685 | d40d->lli_phy.dst = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 686 | } |
| 687 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 688 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
| 689 | struct d40_desc *d40d) |
| 690 | { |
| 691 | unsigned long flags; |
| 692 | int i; |
| 693 | int ret = -EINVAL; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 694 | |
| 695 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
| 696 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 697 | /* |
| 698 | * Allocate both src and dst at the same time, therefore the half |
| 699 | * start on 1 since 0 can't be used since zero is used as end marker. |
| 700 | */ |
| 701 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { |
Fabio Baltieri | 7ce529e | 2012-12-18 16:59:09 +0100 | [diff] [blame] | 702 | int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i; |
| 703 | |
| 704 | if (!d40c->base->lcla_pool.alloc_map[idx]) { |
| 705 | d40c->base->lcla_pool.alloc_map[idx] = d40d; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 706 | d40d->lcla_alloc++; |
| 707 | ret = i; |
| 708 | break; |
| 709 | } |
| 710 | } |
| 711 | |
| 712 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
| 713 | |
| 714 | return ret; |
| 715 | } |
| 716 | |
| 717 | static int d40_lcla_free_all(struct d40_chan *d40c, |
| 718 | struct d40_desc *d40d) |
| 719 | { |
| 720 | unsigned long flags; |
| 721 | int i; |
| 722 | int ret = -EINVAL; |
| 723 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 724 | if (chan_is_physical(d40c)) |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 725 | return 0; |
| 726 | |
| 727 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
| 728 | |
| 729 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { |
Fabio Baltieri | 7ce529e | 2012-12-18 16:59:09 +0100 | [diff] [blame] | 730 | int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i; |
| 731 | |
| 732 | if (d40c->base->lcla_pool.alloc_map[idx] == d40d) { |
| 733 | d40c->base->lcla_pool.alloc_map[idx] = NULL; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 734 | d40d->lcla_alloc--; |
| 735 | if (d40d->lcla_alloc == 0) { |
| 736 | ret = 0; |
| 737 | break; |
| 738 | } |
| 739 | } |
| 740 | } |
| 741 | |
| 742 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
| 743 | |
| 744 | return ret; |
| 745 | |
| 746 | } |
| 747 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 748 | static void d40_desc_remove(struct d40_desc *d40d) |
| 749 | { |
| 750 | list_del(&d40d->node); |
| 751 | } |
| 752 | |
| 753 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) |
| 754 | { |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 755 | struct d40_desc *desc = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 756 | |
| 757 | if (!list_empty(&d40c->client)) { |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 758 | struct d40_desc *d; |
| 759 | struct d40_desc *_d; |
| 760 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 761 | list_for_each_entry_safe(d, _d, &d40c->client, node) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 762 | if (async_tx_test_ack(&d->txd)) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 763 | d40_desc_remove(d); |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 764 | desc = d; |
| 765 | memset(desc, 0, sizeof(*desc)); |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 766 | break; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 767 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 768 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 769 | } |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 770 | |
| 771 | if (!desc) |
| 772 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); |
| 773 | |
| 774 | if (desc) |
| 775 | INIT_LIST_HEAD(&desc->node); |
| 776 | |
| 777 | return desc; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 778 | } |
| 779 | |
| 780 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) |
| 781 | { |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 782 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 783 | d40_pool_lli_free(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 784 | d40_lcla_free_all(d40c, d40d); |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 785 | kmem_cache_free(d40c->base->desc_slab, d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 786 | } |
| 787 | |
| 788 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) |
| 789 | { |
| 790 | list_add_tail(&desc->node, &d40c->active); |
| 791 | } |
| 792 | |
Rabin Vincent | 1c4b092 | 2011-01-25 11:18:24 +0100 | [diff] [blame] | 793 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
| 794 | { |
| 795 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; |
| 796 | struct d40_phy_lli *lli_src = desc->lli_phy.src; |
| 797 | void __iomem *base = chan_base(chan); |
| 798 | |
| 799 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); |
| 800 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); |
| 801 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); |
| 802 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); |
| 803 | |
| 804 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); |
| 805 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); |
| 806 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); |
| 807 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); |
| 808 | } |
| 809 | |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 810 | static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc) |
| 811 | { |
| 812 | list_add_tail(&desc->node, &d40c->done); |
| 813 | } |
| 814 | |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 815 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
| 816 | { |
| 817 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
| 818 | struct d40_log_lli_bidir *lli = &desc->lli_log; |
| 819 | int lli_current = desc->lli_current; |
| 820 | int lli_len = desc->lli_len; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 821 | bool cyclic = desc->cyclic; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 822 | int curr_lcla = -EINVAL; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 823 | int first_lcla = 0; |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 824 | bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 825 | bool linkback; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 826 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 827 | /* |
| 828 | * We may have partially running cyclic transfers, in case we did't get |
| 829 | * enough LCLA entries. |
| 830 | */ |
| 831 | linkback = cyclic && lli_current == 0; |
| 832 | |
| 833 | /* |
| 834 | * For linkback, we need one LCLA even with only one link, because we |
| 835 | * can't link back to the one in LCPA space |
| 836 | */ |
| 837 | if (linkback || (lli_len - lli_current > 1)) { |
Fabio Baltieri | 7407048 | 2012-12-18 12:25:14 +0100 | [diff] [blame] | 838 | /* |
| 839 | * If the channel is expected to use only soft_lli don't |
| 840 | * allocate a lcla. This is to avoid a HW issue that exists |
| 841 | * in some controller during a peripheral to memory transfer |
| 842 | * that uses linked lists. |
| 843 | */ |
| 844 | if (!(chan->phy_chan->use_soft_lli && |
| 845 | chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)) |
| 846 | curr_lcla = d40_lcla_alloc_one(chan, desc); |
| 847 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 848 | first_lcla = curr_lcla; |
| 849 | } |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 850 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 851 | /* |
| 852 | * For linkback, we normally load the LCPA in the loop since we need to |
| 853 | * link it to the second LCLA and not the first. However, if we |
| 854 | * couldn't even get a first LCLA, then we have to run in LCPA and |
| 855 | * reload manually. |
| 856 | */ |
| 857 | if (!linkback || curr_lcla == -EINVAL) { |
| 858 | unsigned int flags = 0; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 859 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 860 | if (curr_lcla == -EINVAL) |
| 861 | flags |= LLI_TERM_INT; |
| 862 | |
| 863 | d40_log_lli_lcpa_write(chan->lcpa, |
| 864 | &lli->dst[lli_current], |
| 865 | &lli->src[lli_current], |
| 866 | curr_lcla, |
| 867 | flags); |
| 868 | lli_current++; |
| 869 | } |
Rabin Vincent | 6045f0b | 2011-01-25 11:18:32 +0100 | [diff] [blame] | 870 | |
| 871 | if (curr_lcla < 0) |
| 872 | goto out; |
| 873 | |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 874 | for (; lli_current < lli_len; lli_current++) { |
| 875 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + |
| 876 | 8 * curr_lcla * 2; |
| 877 | struct d40_log_lli *lcla = pool->base + lcla_offset; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 878 | unsigned int flags = 0; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 879 | int next_lcla; |
| 880 | |
| 881 | if (lli_current + 1 < lli_len) |
| 882 | next_lcla = d40_lcla_alloc_one(chan, desc); |
| 883 | else |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 884 | next_lcla = linkback ? first_lcla : -EINVAL; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 885 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 886 | if (cyclic || next_lcla == -EINVAL) |
| 887 | flags |= LLI_TERM_INT; |
| 888 | |
| 889 | if (linkback && curr_lcla == first_lcla) { |
| 890 | /* First link goes in both LCPA and LCLA */ |
| 891 | d40_log_lli_lcpa_write(chan->lcpa, |
| 892 | &lli->dst[lli_current], |
| 893 | &lli->src[lli_current], |
| 894 | next_lcla, flags); |
| 895 | } |
| 896 | |
| 897 | /* |
| 898 | * One unused LCLA in the cyclic case if the very first |
| 899 | * next_lcla fails... |
| 900 | */ |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 901 | d40_log_lli_lcla_write(lcla, |
| 902 | &lli->dst[lli_current], |
| 903 | &lli->src[lli_current], |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 904 | next_lcla, flags); |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 905 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 906 | /* |
| 907 | * Cache maintenance is not needed if lcla is |
| 908 | * mapped in esram |
| 909 | */ |
| 910 | if (!use_esram_lcla) { |
| 911 | dma_sync_single_range_for_device(chan->base->dev, |
| 912 | pool->dma_addr, lcla_offset, |
| 913 | 2 * sizeof(struct d40_log_lli), |
| 914 | DMA_TO_DEVICE); |
| 915 | } |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 916 | curr_lcla = next_lcla; |
| 917 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 918 | if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 919 | lli_current++; |
| 920 | break; |
| 921 | } |
| 922 | } |
| 923 | |
Rabin Vincent | 6045f0b | 2011-01-25 11:18:32 +0100 | [diff] [blame] | 924 | out: |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 925 | desc->lli_current = lli_current; |
| 926 | } |
| 927 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 928 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
| 929 | { |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 930 | if (chan_is_physical(d40c)) { |
Rabin Vincent | 1c4b092 | 2011-01-25 11:18:24 +0100 | [diff] [blame] | 931 | d40_phy_lli_load(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 932 | d40d->lli_current = d40d->lli_len; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 933 | } else |
| 934 | d40_log_lli_to_lcxa(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 935 | } |
| 936 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 937 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
| 938 | { |
| 939 | struct d40_desc *d; |
| 940 | |
| 941 | if (list_empty(&d40c->active)) |
| 942 | return NULL; |
| 943 | |
| 944 | d = list_first_entry(&d40c->active, |
| 945 | struct d40_desc, |
| 946 | node); |
| 947 | return d; |
| 948 | } |
| 949 | |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 950 | /* remove desc from current queue and add it to the pending_queue */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 951 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) |
| 952 | { |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 953 | d40_desc_remove(desc); |
| 954 | desc->is_in_client_list = false; |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 955 | list_add_tail(&desc->node, &d40c->pending_queue); |
| 956 | } |
| 957 | |
| 958 | static struct d40_desc *d40_first_pending(struct d40_chan *d40c) |
| 959 | { |
| 960 | struct d40_desc *d; |
| 961 | |
| 962 | if (list_empty(&d40c->pending_queue)) |
| 963 | return NULL; |
| 964 | |
| 965 | d = list_first_entry(&d40c->pending_queue, |
| 966 | struct d40_desc, |
| 967 | node); |
| 968 | return d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 969 | } |
| 970 | |
| 971 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) |
| 972 | { |
| 973 | struct d40_desc *d; |
| 974 | |
| 975 | if (list_empty(&d40c->queue)) |
| 976 | return NULL; |
| 977 | |
| 978 | d = list_first_entry(&d40c->queue, |
| 979 | struct d40_desc, |
| 980 | node); |
| 981 | return d; |
| 982 | } |
| 983 | |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 984 | static struct d40_desc *d40_first_done(struct d40_chan *d40c) |
| 985 | { |
| 986 | if (list_empty(&d40c->done)) |
| 987 | return NULL; |
| 988 | |
| 989 | return list_first_entry(&d40c->done, struct d40_desc, node); |
| 990 | } |
| 991 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 992 | static int d40_psize_2_burst_size(bool is_log, int psize) |
| 993 | { |
| 994 | if (is_log) { |
| 995 | if (psize == STEDMA40_PSIZE_LOG_1) |
| 996 | return 1; |
| 997 | } else { |
| 998 | if (psize == STEDMA40_PSIZE_PHY_1) |
| 999 | return 1; |
| 1000 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1001 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1002 | return 2 << psize; |
| 1003 | } |
| 1004 | |
| 1005 | /* |
| 1006 | * The dma only supports transmitting packages up to |
| 1007 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of |
| 1008 | * dma elements required to send the entire sg list |
| 1009 | */ |
| 1010 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) |
| 1011 | { |
| 1012 | int dmalen; |
| 1013 | u32 max_w = max(data_width1, data_width2); |
| 1014 | u32 min_w = min(data_width1, data_width2); |
| 1015 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); |
| 1016 | |
| 1017 | if (seg_max > STEDMA40_MAX_SEG_SIZE) |
| 1018 | seg_max -= (1 << max_w); |
| 1019 | |
| 1020 | if (!IS_ALIGNED(size, 1 << max_w)) |
| 1021 | return -EINVAL; |
| 1022 | |
| 1023 | if (size <= seg_max) |
| 1024 | dmalen = 1; |
| 1025 | else { |
| 1026 | dmalen = size / seg_max; |
| 1027 | if (dmalen * seg_max < size) |
| 1028 | dmalen++; |
| 1029 | } |
| 1030 | return dmalen; |
| 1031 | } |
| 1032 | |
| 1033 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, |
| 1034 | u32 data_width1, u32 data_width2) |
| 1035 | { |
| 1036 | struct scatterlist *sg; |
| 1037 | int i; |
| 1038 | int len = 0; |
| 1039 | int ret; |
| 1040 | |
| 1041 | for_each_sg(sgl, sg, sg_len, i) { |
| 1042 | ret = d40_size_2_dmalen(sg_dma_len(sg), |
| 1043 | data_width1, data_width2); |
| 1044 | if (ret < 0) |
| 1045 | return ret; |
| 1046 | len += ret; |
| 1047 | } |
| 1048 | return len; |
| 1049 | } |
| 1050 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1051 | |
| 1052 | #ifdef CONFIG_PM |
| 1053 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, |
| 1054 | u32 *regaddr, int num, bool save) |
| 1055 | { |
| 1056 | int i; |
| 1057 | |
| 1058 | for (i = 0; i < num; i++) { |
| 1059 | void __iomem *addr = baseaddr + regaddr[i]; |
| 1060 | |
| 1061 | if (save) |
| 1062 | backup[i] = readl_relaxed(addr); |
| 1063 | else |
| 1064 | writel_relaxed(backup[i], addr); |
| 1065 | } |
| 1066 | } |
| 1067 | |
| 1068 | static void d40_save_restore_registers(struct d40_base *base, bool save) |
| 1069 | { |
| 1070 | int i; |
| 1071 | |
| 1072 | /* Save/Restore channel specific registers */ |
| 1073 | for (i = 0; i < base->num_phy_chans; i++) { |
| 1074 | void __iomem *addr; |
| 1075 | int idx; |
| 1076 | |
| 1077 | if (base->phy_res[i].reserved) |
| 1078 | continue; |
| 1079 | |
| 1080 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; |
| 1081 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); |
| 1082 | |
| 1083 | dma40_backup(addr, &base->reg_val_backup_chan[idx], |
| 1084 | d40_backup_regs_chan, |
| 1085 | ARRAY_SIZE(d40_backup_regs_chan), |
| 1086 | save); |
| 1087 | } |
| 1088 | |
| 1089 | /* Save/Restore global registers */ |
| 1090 | dma40_backup(base->virtbase, base->reg_val_backup, |
| 1091 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), |
| 1092 | save); |
| 1093 | |
| 1094 | /* Save/Restore registers only existing on dma40 v3 and later */ |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 1095 | if (base->gen_dmac.backup) |
| 1096 | dma40_backup(base->virtbase, base->reg_val_backup_v4, |
| 1097 | base->gen_dmac.backup, |
| 1098 | base->gen_dmac.backup_size, |
| 1099 | save); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1100 | } |
| 1101 | #else |
| 1102 | static void d40_save_restore_registers(struct d40_base *base, bool save) |
| 1103 | { |
| 1104 | } |
| 1105 | #endif |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1106 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1107 | static int __d40_execute_command_phy(struct d40_chan *d40c, |
| 1108 | enum d40_command command) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1109 | { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1110 | u32 status; |
| 1111 | int i; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1112 | void __iomem *active_reg; |
| 1113 | int ret = 0; |
| 1114 | unsigned long flags; |
Jonas Aaberg | 1d392a7 | 2010-06-20 21:26:01 +0000 | [diff] [blame] | 1115 | u32 wmask; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1116 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1117 | if (command == D40_DMA_STOP) { |
| 1118 | ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ); |
| 1119 | if (ret) |
| 1120 | return ret; |
| 1121 | } |
| 1122 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1123 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); |
| 1124 | |
| 1125 | if (d40c->phy_chan->num % 2 == 0) |
| 1126 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 1127 | else |
| 1128 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 1129 | |
| 1130 | if (command == D40_DMA_SUSPEND_REQ) { |
| 1131 | status = (readl(active_reg) & |
| 1132 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 1133 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1134 | |
| 1135 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) |
| 1136 | goto done; |
| 1137 | } |
| 1138 | |
Jonas Aaberg | 1d392a7 | 2010-06-20 21:26:01 +0000 | [diff] [blame] | 1139 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
| 1140 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), |
| 1141 | active_reg); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1142 | |
| 1143 | if (command == D40_DMA_SUSPEND_REQ) { |
| 1144 | |
| 1145 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { |
| 1146 | status = (readl(active_reg) & |
| 1147 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 1148 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1149 | |
| 1150 | cpu_relax(); |
| 1151 | /* |
| 1152 | * Reduce the number of bus accesses while |
| 1153 | * waiting for the DMA to suspend. |
| 1154 | */ |
| 1155 | udelay(3); |
| 1156 | |
| 1157 | if (status == D40_DMA_STOP || |
| 1158 | status == D40_DMA_SUSPENDED) |
| 1159 | break; |
| 1160 | } |
| 1161 | |
| 1162 | if (i == D40_SUSPEND_MAX_IT) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1163 | chan_err(d40c, |
| 1164 | "unable to suspend the chl %d (log: %d) status %x\n", |
| 1165 | d40c->phy_chan->num, d40c->log_num, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1166 | status); |
| 1167 | dump_stack(); |
| 1168 | ret = -EBUSY; |
| 1169 | } |
| 1170 | |
| 1171 | } |
| 1172 | done: |
| 1173 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); |
| 1174 | return ret; |
| 1175 | } |
| 1176 | |
| 1177 | static void d40_term_all(struct d40_chan *d40c) |
| 1178 | { |
| 1179 | struct d40_desc *d40d; |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 1180 | struct d40_desc *_d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1181 | |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 1182 | /* Release completed descriptors */ |
| 1183 | while ((d40d = d40_first_done(d40c))) { |
| 1184 | d40_desc_remove(d40d); |
| 1185 | d40_desc_free(d40c, d40d); |
| 1186 | } |
| 1187 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1188 | /* Release active descriptors */ |
| 1189 | while ((d40d = d40_first_active_get(d40c))) { |
| 1190 | d40_desc_remove(d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1191 | d40_desc_free(d40c, d40d); |
| 1192 | } |
| 1193 | |
| 1194 | /* Release queued descriptors waiting for transfer */ |
| 1195 | while ((d40d = d40_first_queued(d40c))) { |
| 1196 | d40_desc_remove(d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1197 | d40_desc_free(d40c, d40d); |
| 1198 | } |
| 1199 | |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 1200 | /* Release pending descriptors */ |
| 1201 | while ((d40d = d40_first_pending(d40c))) { |
| 1202 | d40_desc_remove(d40d); |
| 1203 | d40_desc_free(d40c, d40d); |
| 1204 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1205 | |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 1206 | /* Release client owned descriptors */ |
| 1207 | if (!list_empty(&d40c->client)) |
| 1208 | list_for_each_entry_safe(d40d, _d, &d40c->client, node) { |
| 1209 | d40_desc_remove(d40d); |
| 1210 | d40_desc_free(d40c, d40d); |
| 1211 | } |
| 1212 | |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 1213 | /* Release descriptors in prepare queue */ |
| 1214 | if (!list_empty(&d40c->prepare_queue)) |
| 1215 | list_for_each_entry_safe(d40d, _d, |
| 1216 | &d40c->prepare_queue, node) { |
| 1217 | d40_desc_remove(d40d); |
| 1218 | d40_desc_free(d40c, d40d); |
| 1219 | } |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 1220 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1221 | d40c->pending_tx = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1222 | } |
| 1223 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1224 | static void __d40_config_set_event(struct d40_chan *d40c, |
| 1225 | enum d40_events event_type, u32 event, |
| 1226 | int reg) |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1227 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1228 | void __iomem *addr = chan_base(d40c) + reg; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1229 | int tries; |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1230 | u32 status; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1231 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1232 | switch (event_type) { |
| 1233 | |
| 1234 | case D40_DEACTIVATE_EVENTLINE: |
| 1235 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1236 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) |
| 1237 | | ~D40_EVENTLINE_MASK(event), addr); |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1238 | break; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1239 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1240 | case D40_SUSPEND_REQ_EVENTLINE: |
| 1241 | status = (readl(addr) & D40_EVENTLINE_MASK(event)) >> |
| 1242 | D40_EVENTLINE_POS(event); |
| 1243 | |
| 1244 | if (status == D40_DEACTIVATE_EVENTLINE || |
| 1245 | status == D40_SUSPEND_REQ_EVENTLINE) |
| 1246 | break; |
| 1247 | |
| 1248 | writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event)) |
| 1249 | | ~D40_EVENTLINE_MASK(event), addr); |
| 1250 | |
| 1251 | for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) { |
| 1252 | |
| 1253 | status = (readl(addr) & D40_EVENTLINE_MASK(event)) >> |
| 1254 | D40_EVENTLINE_POS(event); |
| 1255 | |
| 1256 | cpu_relax(); |
| 1257 | /* |
| 1258 | * Reduce the number of bus accesses while |
| 1259 | * waiting for the DMA to suspend. |
| 1260 | */ |
| 1261 | udelay(3); |
| 1262 | |
| 1263 | if (status == D40_DEACTIVATE_EVENTLINE) |
| 1264 | break; |
| 1265 | } |
| 1266 | |
| 1267 | if (tries == D40_SUSPEND_MAX_IT) { |
| 1268 | chan_err(d40c, |
| 1269 | "unable to stop the event_line chl %d (log: %d)" |
| 1270 | "status %x\n", d40c->phy_chan->num, |
| 1271 | d40c->log_num, status); |
| 1272 | } |
| 1273 | break; |
| 1274 | |
| 1275 | case D40_ACTIVATE_EVENTLINE: |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1276 | /* |
| 1277 | * The hardware sometimes doesn't register the enable when src and dst |
| 1278 | * event lines are active on the same logical channel. Retry to ensure |
| 1279 | * it does. Usually only one retry is sufficient. |
| 1280 | */ |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1281 | tries = 100; |
| 1282 | while (--tries) { |
| 1283 | writel((D40_ACTIVATE_EVENTLINE << |
| 1284 | D40_EVENTLINE_POS(event)) | |
| 1285 | ~D40_EVENTLINE_MASK(event), addr); |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1286 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1287 | if (readl(addr) & D40_EVENTLINE_MASK(event)) |
| 1288 | break; |
| 1289 | } |
| 1290 | |
| 1291 | if (tries != 99) |
| 1292 | dev_dbg(chan2dev(d40c), |
| 1293 | "[%s] workaround enable S%cLNK (%d tries)\n", |
| 1294 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', |
| 1295 | 100 - tries); |
| 1296 | |
| 1297 | WARN_ON(!tries); |
| 1298 | break; |
| 1299 | |
| 1300 | case D40_ROUND_EVENTLINE: |
| 1301 | BUG(); |
| 1302 | break; |
| 1303 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1304 | } |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1305 | } |
| 1306 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1307 | static void d40_config_set_event(struct d40_chan *d40c, |
| 1308 | enum d40_events event_type) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1309 | { |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1310 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); |
| 1311 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1312 | /* Enable event line connected to device (or memcpy) */ |
| 1313 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1314 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1315 | __d40_config_set_event(d40c, event_type, event, |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1316 | D40_CHAN_REG_SSLNK); |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1317 | |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1318 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1319 | __d40_config_set_event(d40c, event_type, event, |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1320 | D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1321 | } |
| 1322 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1323 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1324 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1325 | void __iomem *chanbase = chan_base(d40c); |
Jonas Aaberg | be8cb7d | 2010-08-09 12:07:44 +0000 | [diff] [blame] | 1326 | u32 val; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1327 | |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1328 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
| 1329 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1330 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1331 | return val; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1332 | } |
| 1333 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1334 | static int |
| 1335 | __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command) |
| 1336 | { |
| 1337 | unsigned long flags; |
| 1338 | int ret = 0; |
| 1339 | u32 active_status; |
| 1340 | void __iomem *active_reg; |
| 1341 | |
| 1342 | if (d40c->phy_chan->num % 2 == 0) |
| 1343 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 1344 | else |
| 1345 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 1346 | |
| 1347 | |
| 1348 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
| 1349 | |
| 1350 | switch (command) { |
| 1351 | case D40_DMA_STOP: |
| 1352 | case D40_DMA_SUSPEND_REQ: |
| 1353 | |
| 1354 | active_status = (readl(active_reg) & |
| 1355 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 1356 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1357 | |
| 1358 | if (active_status == D40_DMA_RUN) |
| 1359 | d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE); |
| 1360 | else |
| 1361 | d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE); |
| 1362 | |
| 1363 | if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP)) |
| 1364 | ret = __d40_execute_command_phy(d40c, command); |
| 1365 | |
| 1366 | break; |
| 1367 | |
| 1368 | case D40_DMA_RUN: |
| 1369 | |
| 1370 | d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE); |
| 1371 | ret = __d40_execute_command_phy(d40c, command); |
| 1372 | break; |
| 1373 | |
| 1374 | case D40_DMA_SUSPENDED: |
| 1375 | BUG(); |
| 1376 | break; |
| 1377 | } |
| 1378 | |
| 1379 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); |
| 1380 | return ret; |
| 1381 | } |
| 1382 | |
| 1383 | static int d40_channel_execute_command(struct d40_chan *d40c, |
| 1384 | enum d40_command command) |
| 1385 | { |
| 1386 | if (chan_is_logical(d40c)) |
| 1387 | return __d40_execute_command_log(d40c, command); |
| 1388 | else |
| 1389 | return __d40_execute_command_phy(d40c, command); |
| 1390 | } |
| 1391 | |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1392 | static u32 d40_get_prmo(struct d40_chan *d40c) |
| 1393 | { |
| 1394 | static const unsigned int phy_map[] = { |
| 1395 | [STEDMA40_PCHAN_BASIC_MODE] |
| 1396 | = D40_DREG_PRMO_PCHAN_BASIC, |
| 1397 | [STEDMA40_PCHAN_MODULO_MODE] |
| 1398 | = D40_DREG_PRMO_PCHAN_MODULO, |
| 1399 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] |
| 1400 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, |
| 1401 | }; |
| 1402 | static const unsigned int log_map[] = { |
| 1403 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] |
| 1404 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, |
| 1405 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] |
| 1406 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, |
| 1407 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] |
| 1408 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, |
| 1409 | }; |
| 1410 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1411 | if (chan_is_physical(d40c)) |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1412 | return phy_map[d40c->dma_cfg.mode_opt]; |
| 1413 | else |
| 1414 | return log_map[d40c->dma_cfg.mode_opt]; |
| 1415 | } |
| 1416 | |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 1417 | static void d40_config_write(struct d40_chan *d40c) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1418 | { |
| 1419 | u32 addr_base; |
| 1420 | u32 var; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1421 | |
| 1422 | /* Odd addresses are even addresses + 4 */ |
| 1423 | addr_base = (d40c->phy_chan->num % 2) * 4; |
| 1424 | /* Setup channel mode to logical or physical */ |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1425 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1426 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1427 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); |
| 1428 | |
| 1429 | /* Setup operational mode option register */ |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1430 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1431 | |
| 1432 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); |
| 1433 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1434 | if (chan_is_logical(d40c)) { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1435 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
| 1436 | & D40_SREG_ELEM_LOG_LIDX_MASK; |
| 1437 | void __iomem *chanbase = chan_base(d40c); |
| 1438 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1439 | /* Set default config for CFG reg */ |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1440 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
| 1441 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1442 | |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 1443 | /* Set LIDX for lcla */ |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1444 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
| 1445 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); |
Rabin Vincent | e9f3a49 | 2011-12-28 11:27:40 +0530 | [diff] [blame] | 1446 | |
| 1447 | /* Clear LNK which will be used by d40_chan_has_events() */ |
| 1448 | writel(0, chanbase + D40_CHAN_REG_SSLNK); |
| 1449 | writel(0, chanbase + D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1450 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1451 | } |
| 1452 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1453 | static u32 d40_residue(struct d40_chan *d40c) |
| 1454 | { |
| 1455 | u32 num_elt; |
| 1456 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1457 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1458 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
| 1459 | >> D40_MEM_LCSP2_ECNT_POS; |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1460 | else { |
| 1461 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); |
| 1462 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) |
| 1463 | >> D40_SREG_ELEM_PHY_ECNT_POS; |
| 1464 | } |
| 1465 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1466 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
| 1467 | } |
| 1468 | |
| 1469 | static bool d40_tx_is_linked(struct d40_chan *d40c) |
| 1470 | { |
| 1471 | bool is_link; |
| 1472 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1473 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1474 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
| 1475 | else |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1476 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
| 1477 | & D40_SREG_LNK_PHYS_LNK_MASK; |
| 1478 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1479 | return is_link; |
| 1480 | } |
| 1481 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1482 | static int d40_pause(struct d40_chan *d40c) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1483 | { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1484 | int res = 0; |
| 1485 | unsigned long flags; |
| 1486 | |
Jonas Aaberg | 3ac012a | 2010-08-09 12:09:12 +0000 | [diff] [blame] | 1487 | if (!d40c->busy) |
| 1488 | return 0; |
| 1489 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1490 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1491 | spin_lock_irqsave(&d40c->lock, flags); |
| 1492 | |
| 1493 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1494 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1495 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1496 | pm_runtime_put_autosuspend(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1497 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1498 | return res; |
| 1499 | } |
| 1500 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1501 | static int d40_resume(struct d40_chan *d40c) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1502 | { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1503 | int res = 0; |
| 1504 | unsigned long flags; |
| 1505 | |
Jonas Aaberg | 3ac012a | 2010-08-09 12:09:12 +0000 | [diff] [blame] | 1506 | if (!d40c->busy) |
| 1507 | return 0; |
| 1508 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1509 | spin_lock_irqsave(&d40c->lock, flags); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1510 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1511 | |
| 1512 | /* If bytes left to transfer or linked tx resume job */ |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1513 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1514 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1515 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1516 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1517 | pm_runtime_put_autosuspend(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1518 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1519 | return res; |
| 1520 | } |
| 1521 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1522 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
| 1523 | { |
| 1524 | struct d40_chan *d40c = container_of(tx->chan, |
| 1525 | struct d40_chan, |
| 1526 | chan); |
| 1527 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); |
| 1528 | unsigned long flags; |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 1529 | dma_cookie_t cookie; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1530 | |
| 1531 | spin_lock_irqsave(&d40c->lock, flags); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 1532 | cookie = dma_cookie_assign(tx); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1533 | d40_desc_queue(d40c, d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1534 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1535 | |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 1536 | return cookie; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1537 | } |
| 1538 | |
| 1539 | static int d40_start(struct d40_chan *d40c) |
| 1540 | { |
Jonas Aaberg | 0c32269 | 2010-06-20 21:25:46 +0000 | [diff] [blame] | 1541 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1542 | } |
| 1543 | |
| 1544 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) |
| 1545 | { |
| 1546 | struct d40_desc *d40d; |
| 1547 | int err; |
| 1548 | |
| 1549 | /* Start queued jobs, if any */ |
| 1550 | d40d = d40_first_queued(d40c); |
| 1551 | |
| 1552 | if (d40d != NULL) { |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1553 | if (!d40c->busy) { |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1554 | d40c->busy = true; |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1555 | pm_runtime_get_sync(d40c->base->dev); |
| 1556 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1557 | |
| 1558 | /* Remove from queue */ |
| 1559 | d40_desc_remove(d40d); |
| 1560 | |
| 1561 | /* Add to active queue */ |
| 1562 | d40_desc_submit(d40c, d40d); |
| 1563 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1564 | /* Initiate DMA job */ |
| 1565 | d40_desc_load(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 1566 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1567 | /* Start dma job */ |
| 1568 | err = d40_start(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1569 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1570 | if (err) |
| 1571 | return NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1572 | } |
| 1573 | |
| 1574 | return d40d; |
| 1575 | } |
| 1576 | |
| 1577 | /* called from interrupt context */ |
| 1578 | static void dma_tc_handle(struct d40_chan *d40c) |
| 1579 | { |
| 1580 | struct d40_desc *d40d; |
| 1581 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1582 | /* Get first active entry from list */ |
| 1583 | d40d = d40_first_active_get(d40c); |
| 1584 | |
| 1585 | if (d40d == NULL) |
| 1586 | return; |
| 1587 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1588 | if (d40d->cyclic) { |
| 1589 | /* |
| 1590 | * If this was a paritially loaded list, we need to reloaded |
| 1591 | * it, and only when the list is completed. We need to check |
| 1592 | * for done because the interrupt will hit for every link, and |
| 1593 | * not just the last one. |
| 1594 | */ |
| 1595 | if (d40d->lli_current < d40d->lli_len |
| 1596 | && !d40_tx_is_linked(d40c) |
| 1597 | && !d40_residue(d40c)) { |
| 1598 | d40_lcla_free_all(d40c, d40d); |
| 1599 | d40_desc_load(d40c, d40d); |
| 1600 | (void) d40_start(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1601 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1602 | if (d40d->lli_current == d40d->lli_len) |
| 1603 | d40d->lli_current = 0; |
| 1604 | } |
| 1605 | } else { |
| 1606 | d40_lcla_free_all(d40c, d40d); |
| 1607 | |
| 1608 | if (d40d->lli_current < d40d->lli_len) { |
| 1609 | d40_desc_load(d40c, d40d); |
| 1610 | /* Start dma job */ |
| 1611 | (void) d40_start(d40c); |
| 1612 | return; |
| 1613 | } |
| 1614 | |
| 1615 | if (d40_queue_start(d40c) == NULL) |
| 1616 | d40c->busy = false; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1617 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1618 | pm_runtime_put_autosuspend(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1619 | |
Fabio Baltieri | 7dd1452 | 2013-02-14 10:03:10 +0100 | [diff] [blame] | 1620 | d40_desc_remove(d40d); |
| 1621 | d40_desc_done(d40c, d40d); |
| 1622 | } |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 1623 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1624 | d40c->pending_tx++; |
| 1625 | tasklet_schedule(&d40c->tasklet); |
| 1626 | |
| 1627 | } |
| 1628 | |
| 1629 | static void dma_tasklet(unsigned long data) |
| 1630 | { |
| 1631 | struct d40_chan *d40c = (struct d40_chan *) data; |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1632 | struct d40_desc *d40d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1633 | unsigned long flags; |
| 1634 | dma_async_tx_callback callback; |
| 1635 | void *callback_param; |
| 1636 | |
| 1637 | spin_lock_irqsave(&d40c->lock, flags); |
| 1638 | |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 1639 | /* Get first entry from the done list */ |
| 1640 | d40d = d40_first_done(d40c); |
| 1641 | if (d40d == NULL) { |
| 1642 | /* Check if we have reached here for cyclic job */ |
| 1643 | d40d = d40_first_active_get(d40c); |
| 1644 | if (d40d == NULL || !d40d->cyclic) |
| 1645 | goto err; |
| 1646 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1647 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1648 | if (!d40d->cyclic) |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 1649 | dma_cookie_complete(&d40d->txd); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1650 | |
| 1651 | /* |
| 1652 | * If terminating a channel pending_tx is set to zero. |
| 1653 | * This prevents any finished active jobs to return to the client. |
| 1654 | */ |
| 1655 | if (d40c->pending_tx == 0) { |
| 1656 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1657 | return; |
| 1658 | } |
| 1659 | |
| 1660 | /* Callback to client */ |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1661 | callback = d40d->txd.callback; |
| 1662 | callback_param = d40d->txd.callback_param; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1663 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1664 | if (!d40d->cyclic) { |
| 1665 | if (async_tx_test_ack(&d40d->txd)) { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1666 | d40_desc_remove(d40d); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1667 | d40_desc_free(d40c, d40d); |
Fabio Baltieri | f26e03a | 2012-12-13 17:12:37 +0100 | [diff] [blame] | 1668 | } else if (!d40d->is_in_client_list) { |
| 1669 | d40_desc_remove(d40d); |
| 1670 | d40_lcla_free_all(d40c, d40d); |
| 1671 | list_add_tail(&d40d->node, &d40c->client); |
| 1672 | d40d->is_in_client_list = true; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1673 | } |
| 1674 | } |
| 1675 | |
| 1676 | d40c->pending_tx--; |
| 1677 | |
| 1678 | if (d40c->pending_tx) |
| 1679 | tasklet_schedule(&d40c->tasklet); |
| 1680 | |
| 1681 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1682 | |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1683 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1684 | callback(callback_param); |
| 1685 | |
| 1686 | return; |
| 1687 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1688 | err: |
| 1689 | /* Rescue manouver if receiving double interrupts */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1690 | if (d40c->pending_tx > 0) |
| 1691 | d40c->pending_tx--; |
| 1692 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1693 | } |
| 1694 | |
| 1695 | static irqreturn_t d40_handle_interrupt(int irq, void *data) |
| 1696 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1697 | int i; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1698 | u32 idx; |
| 1699 | u32 row; |
| 1700 | long chan = -1; |
| 1701 | struct d40_chan *d40c; |
| 1702 | unsigned long flags; |
| 1703 | struct d40_base *base = data; |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 1704 | u32 regs[base->gen_dmac.il_size]; |
| 1705 | struct d40_interrupt_lookup *il = base->gen_dmac.il; |
| 1706 | u32 il_size = base->gen_dmac.il_size; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1707 | |
| 1708 | spin_lock_irqsave(&base->interrupt_lock, flags); |
| 1709 | |
| 1710 | /* Read interrupt status of both logical and physical channels */ |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 1711 | for (i = 0; i < il_size; i++) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1712 | regs[i] = readl(base->virtbase + il[i].src); |
| 1713 | |
| 1714 | for (;;) { |
| 1715 | |
| 1716 | chan = find_next_bit((unsigned long *)regs, |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 1717 | BITS_PER_LONG * il_size, chan + 1); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1718 | |
| 1719 | /* No more set bits found? */ |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 1720 | if (chan == BITS_PER_LONG * il_size) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1721 | break; |
| 1722 | |
| 1723 | row = chan / BITS_PER_LONG; |
| 1724 | idx = chan & (BITS_PER_LONG - 1); |
| 1725 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1726 | if (il[row].offset == D40_PHY_CHAN) |
| 1727 | d40c = base->lookup_phy_chans[idx]; |
| 1728 | else |
| 1729 | d40c = base->lookup_log_chans[il[row].offset + idx]; |
Fabio Baltieri | 53d6d68 | 2012-12-19 14:41:56 +0100 | [diff] [blame] | 1730 | |
| 1731 | if (!d40c) { |
| 1732 | /* |
| 1733 | * No error because this can happen if something else |
| 1734 | * in the system is using the channel. |
| 1735 | */ |
| 1736 | continue; |
| 1737 | } |
| 1738 | |
| 1739 | /* ACK interrupt */ |
| 1740 | writel(1 << idx, base->virtbase + il[row].clr); |
| 1741 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1742 | spin_lock(&d40c->lock); |
| 1743 | |
| 1744 | if (!il[row].is_error) |
| 1745 | dma_tc_handle(d40c); |
| 1746 | else |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1747 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
| 1748 | chan, il[row].offset, idx); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1749 | |
| 1750 | spin_unlock(&d40c->lock); |
| 1751 | } |
| 1752 | |
| 1753 | spin_unlock_irqrestore(&base->interrupt_lock, flags); |
| 1754 | |
| 1755 | return IRQ_HANDLED; |
| 1756 | } |
| 1757 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1758 | static int d40_validate_conf(struct d40_chan *d40c, |
| 1759 | struct stedma40_chan_cfg *conf) |
| 1760 | { |
| 1761 | int res = 0; |
Rabin Vincent | 38bdbf0 | 2010-10-12 13:00:51 +0000 | [diff] [blame] | 1762 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1763 | |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1764 | if (!conf->dir) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1765 | chan_err(d40c, "Invalid direction.\n"); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1766 | res = -EINVAL; |
| 1767 | } |
| 1768 | |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1769 | if ((is_log && conf->dev_type > d40c->base->num_log_chans) || |
| 1770 | (!is_log && conf->dev_type > d40c->base->num_phy_chans) || |
| 1771 | (conf->dev_type < 0)) { |
| 1772 | chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1773 | res = -EINVAL; |
| 1774 | } |
| 1775 | |
| 1776 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1777 | d40c->base->plat_data->dev_tx[conf->dev_type] == 0 && |
| 1778 | d40c->runtime_addr == 0) { |
| 1779 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
| 1780 | conf->dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1781 | res = -EINVAL; |
| 1782 | } |
| 1783 | |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1784 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1785 | d40c->base->plat_data->dev_rx[conf->dev_type] == 0 && |
| 1786 | d40c->runtime_addr == 0) { |
| 1787 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
| 1788 | conf->dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1789 | res = -EINVAL; |
| 1790 | } |
| 1791 | |
| 1792 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { |
| 1793 | /* |
| 1794 | * DMAC HW supports it. Will be added to this driver, |
| 1795 | * in case any dma client requires it. |
| 1796 | */ |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1797 | chan_err(d40c, "periph to periph not supported\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1798 | res = -EINVAL; |
| 1799 | } |
| 1800 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1801 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
| 1802 | (1 << conf->src_info.data_width) != |
| 1803 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * |
| 1804 | (1 << conf->dst_info.data_width)) { |
| 1805 | /* |
| 1806 | * The DMAC hardware only supports |
| 1807 | * src (burst x width) == dst (burst x width) |
| 1808 | */ |
| 1809 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1810 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1811 | res = -EINVAL; |
| 1812 | } |
| 1813 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1814 | return res; |
| 1815 | } |
| 1816 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1817 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, |
| 1818 | bool is_src, int log_event_line, bool is_log, |
| 1819 | bool *first_user) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1820 | { |
| 1821 | unsigned long flags; |
| 1822 | spin_lock_irqsave(&phy->lock, flags); |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1823 | |
| 1824 | *first_user = ((phy->allocated_src | phy->allocated_dst) |
| 1825 | == D40_ALLOC_FREE); |
| 1826 | |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1827 | if (!is_log) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1828 | /* Physical interrupts are masked per physical full channel */ |
| 1829 | if (phy->allocated_src == D40_ALLOC_FREE && |
| 1830 | phy->allocated_dst == D40_ALLOC_FREE) { |
| 1831 | phy->allocated_dst = D40_ALLOC_PHY; |
| 1832 | phy->allocated_src = D40_ALLOC_PHY; |
| 1833 | goto found; |
| 1834 | } else |
| 1835 | goto not_found; |
| 1836 | } |
| 1837 | |
| 1838 | /* Logical channel */ |
| 1839 | if (is_src) { |
| 1840 | if (phy->allocated_src == D40_ALLOC_PHY) |
| 1841 | goto not_found; |
| 1842 | |
| 1843 | if (phy->allocated_src == D40_ALLOC_FREE) |
| 1844 | phy->allocated_src = D40_ALLOC_LOG_FREE; |
| 1845 | |
| 1846 | if (!(phy->allocated_src & (1 << log_event_line))) { |
| 1847 | phy->allocated_src |= 1 << log_event_line; |
| 1848 | goto found; |
| 1849 | } else |
| 1850 | goto not_found; |
| 1851 | } else { |
| 1852 | if (phy->allocated_dst == D40_ALLOC_PHY) |
| 1853 | goto not_found; |
| 1854 | |
| 1855 | if (phy->allocated_dst == D40_ALLOC_FREE) |
| 1856 | phy->allocated_dst = D40_ALLOC_LOG_FREE; |
| 1857 | |
| 1858 | if (!(phy->allocated_dst & (1 << log_event_line))) { |
| 1859 | phy->allocated_dst |= 1 << log_event_line; |
| 1860 | goto found; |
| 1861 | } else |
| 1862 | goto not_found; |
| 1863 | } |
| 1864 | |
| 1865 | not_found: |
| 1866 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1867 | return false; |
| 1868 | found: |
| 1869 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1870 | return true; |
| 1871 | } |
| 1872 | |
| 1873 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, |
| 1874 | int log_event_line) |
| 1875 | { |
| 1876 | unsigned long flags; |
| 1877 | bool is_free = false; |
| 1878 | |
| 1879 | spin_lock_irqsave(&phy->lock, flags); |
| 1880 | if (!log_event_line) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1881 | phy->allocated_dst = D40_ALLOC_FREE; |
| 1882 | phy->allocated_src = D40_ALLOC_FREE; |
| 1883 | is_free = true; |
| 1884 | goto out; |
| 1885 | } |
| 1886 | |
| 1887 | /* Logical channel */ |
| 1888 | if (is_src) { |
| 1889 | phy->allocated_src &= ~(1 << log_event_line); |
| 1890 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) |
| 1891 | phy->allocated_src = D40_ALLOC_FREE; |
| 1892 | } else { |
| 1893 | phy->allocated_dst &= ~(1 << log_event_line); |
| 1894 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) |
| 1895 | phy->allocated_dst = D40_ALLOC_FREE; |
| 1896 | } |
| 1897 | |
| 1898 | is_free = ((phy->allocated_src | phy->allocated_dst) == |
| 1899 | D40_ALLOC_FREE); |
| 1900 | |
| 1901 | out: |
| 1902 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1903 | |
| 1904 | return is_free; |
| 1905 | } |
| 1906 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1907 | static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1908 | { |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 1909 | int dev_type = d40c->dma_cfg.dev_type; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1910 | int event_group; |
| 1911 | int event_line; |
| 1912 | struct d40_phy_res *phys; |
| 1913 | int i; |
| 1914 | int j; |
| 1915 | int log_num; |
Gerald Baeza | f000df8 | 2012-11-08 14:39:07 +0100 | [diff] [blame] | 1916 | int num_phy_chans; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1917 | bool is_src; |
Rabin Vincent | 38bdbf0 | 2010-10-12 13:00:51 +0000 | [diff] [blame] | 1918 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1919 | |
| 1920 | phys = d40c->base->phy_res; |
Gerald Baeza | f000df8 | 2012-11-08 14:39:07 +0100 | [diff] [blame] | 1921 | num_phy_chans = d40c->base->num_phy_chans; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1922 | |
| 1923 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1924 | log_num = 2 * dev_type; |
| 1925 | is_src = true; |
| 1926 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
| 1927 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1928 | /* dst event lines are used for logical memcpy */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1929 | log_num = 2 * dev_type + 1; |
| 1930 | is_src = false; |
| 1931 | } else |
| 1932 | return -EINVAL; |
| 1933 | |
| 1934 | event_group = D40_TYPE_TO_GROUP(dev_type); |
| 1935 | event_line = D40_TYPE_TO_EVENT(dev_type); |
| 1936 | |
| 1937 | if (!is_log) { |
| 1938 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1939 | /* Find physical half channel */ |
Gerald Baeza | f000df8 | 2012-11-08 14:39:07 +0100 | [diff] [blame] | 1940 | if (d40c->dma_cfg.use_fixed_channel) { |
| 1941 | i = d40c->dma_cfg.phy_channel; |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1942 | if (d40_alloc_mask_set(&phys[i], is_src, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1943 | 0, is_log, |
| 1944 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1945 | goto found_phy; |
Gerald Baeza | f000df8 | 2012-11-08 14:39:07 +0100 | [diff] [blame] | 1946 | } else { |
| 1947 | for (i = 0; i < num_phy_chans; i++) { |
| 1948 | if (d40_alloc_mask_set(&phys[i], is_src, |
| 1949 | 0, is_log, |
| 1950 | first_phy_user)) |
| 1951 | goto found_phy; |
| 1952 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1953 | } |
| 1954 | } else |
| 1955 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { |
| 1956 | int phy_num = j + event_group * 2; |
| 1957 | for (i = phy_num; i < phy_num + 2; i++) { |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 1958 | if (d40_alloc_mask_set(&phys[i], |
| 1959 | is_src, |
| 1960 | 0, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1961 | is_log, |
| 1962 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1963 | goto found_phy; |
| 1964 | } |
| 1965 | } |
| 1966 | return -EINVAL; |
| 1967 | found_phy: |
| 1968 | d40c->phy_chan = &phys[i]; |
| 1969 | d40c->log_num = D40_PHY_CHAN; |
| 1970 | goto out; |
| 1971 | } |
| 1972 | if (dev_type == -1) |
| 1973 | return -EINVAL; |
| 1974 | |
| 1975 | /* Find logical channel */ |
| 1976 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { |
| 1977 | int phy_num = j + event_group * 2; |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1978 | |
| 1979 | if (d40c->dma_cfg.use_fixed_channel) { |
| 1980 | i = d40c->dma_cfg.phy_channel; |
| 1981 | |
| 1982 | if ((i != phy_num) && (i != phy_num + 1)) { |
| 1983 | dev_err(chan2dev(d40c), |
| 1984 | "invalid fixed phy channel %d\n", i); |
| 1985 | return -EINVAL; |
| 1986 | } |
| 1987 | |
| 1988 | if (d40_alloc_mask_set(&phys[i], is_src, event_line, |
| 1989 | is_log, first_phy_user)) |
| 1990 | goto found_log; |
| 1991 | |
| 1992 | dev_err(chan2dev(d40c), |
| 1993 | "could not allocate fixed phy channel %d\n", i); |
| 1994 | return -EINVAL; |
| 1995 | } |
| 1996 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1997 | /* |
| 1998 | * Spread logical channels across all available physical rather |
| 1999 | * than pack every logical channel at the first available phy |
| 2000 | * channels. |
| 2001 | */ |
| 2002 | if (is_src) { |
| 2003 | for (i = phy_num; i < phy_num + 2; i++) { |
| 2004 | if (d40_alloc_mask_set(&phys[i], is_src, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 2005 | event_line, is_log, |
| 2006 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2007 | goto found_log; |
| 2008 | } |
| 2009 | } else { |
| 2010 | for (i = phy_num + 1; i >= phy_num; i--) { |
| 2011 | if (d40_alloc_mask_set(&phys[i], is_src, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 2012 | event_line, is_log, |
| 2013 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2014 | goto found_log; |
| 2015 | } |
| 2016 | } |
| 2017 | } |
| 2018 | return -EINVAL; |
| 2019 | |
| 2020 | found_log: |
| 2021 | d40c->phy_chan = &phys[i]; |
| 2022 | d40c->log_num = log_num; |
| 2023 | out: |
| 2024 | |
| 2025 | if (is_log) |
| 2026 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; |
| 2027 | else |
| 2028 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; |
| 2029 | |
| 2030 | return 0; |
| 2031 | |
| 2032 | } |
| 2033 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2034 | static int d40_config_memcpy(struct d40_chan *d40c) |
| 2035 | { |
| 2036 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; |
| 2037 | |
| 2038 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { |
Lee Jones | 29027a1 | 2013-05-03 15:31:54 +0100 | [diff] [blame] | 2039 | d40c->dma_cfg = dma40_memcpy_conf_log; |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2040 | d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id]; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2041 | |
| 2042 | } else if (dma_has_cap(DMA_MEMCPY, cap) && |
| 2043 | dma_has_cap(DMA_SLAVE, cap)) { |
Lee Jones | 29027a1 | 2013-05-03 15:31:54 +0100 | [diff] [blame] | 2044 | d40c->dma_cfg = dma40_memcpy_conf_phy; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2045 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2046 | chan_err(d40c, "No memcpy\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2047 | return -EINVAL; |
| 2048 | } |
| 2049 | |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2053 | static int d40_free_dma(struct d40_chan *d40c) |
| 2054 | { |
| 2055 | |
| 2056 | int res = 0; |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2057 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2058 | struct d40_phy_res *phy = d40c->phy_chan; |
| 2059 | bool is_src; |
| 2060 | |
| 2061 | /* Terminate all queued and active transfers */ |
| 2062 | d40_term_all(d40c); |
| 2063 | |
| 2064 | if (phy == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2065 | chan_err(d40c, "phy == null\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2066 | return -EINVAL; |
| 2067 | } |
| 2068 | |
| 2069 | if (phy->allocated_src == D40_ALLOC_FREE && |
| 2070 | phy->allocated_dst == D40_ALLOC_FREE) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2071 | chan_err(d40c, "channel already free\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2072 | return -EINVAL; |
| 2073 | } |
| 2074 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2075 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2076 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2077 | is_src = false; |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2078 | else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2079 | is_src = true; |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2080 | else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2081 | chan_err(d40c, "Unknown direction\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2082 | return -EINVAL; |
| 2083 | } |
| 2084 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2085 | pm_runtime_get_sync(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2086 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); |
| 2087 | if (res) { |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2088 | chan_err(d40c, "stop failed\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2089 | goto out; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2090 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2091 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2092 | d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0); |
| 2093 | |
| 2094 | if (chan_is_logical(d40c)) |
| 2095 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
| 2096 | else |
| 2097 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
| 2098 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2099 | if (d40c->busy) { |
| 2100 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2101 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 2102 | } |
| 2103 | |
| 2104 | d40c->busy = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2105 | d40c->phy_chan = NULL; |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2106 | d40c->configured = false; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2107 | out: |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2108 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2109 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2110 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 2111 | return res; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2112 | } |
| 2113 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2114 | static bool d40_is_paused(struct d40_chan *d40c) |
| 2115 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 2116 | void __iomem *chanbase = chan_base(d40c); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2117 | bool is_paused = false; |
| 2118 | unsigned long flags; |
| 2119 | void __iomem *active_reg; |
| 2120 | u32 status; |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2121 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2122 | |
| 2123 | spin_lock_irqsave(&d40c->lock, flags); |
| 2124 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2125 | if (chan_is_physical(d40c)) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2126 | if (d40c->phy_chan->num % 2 == 0) |
| 2127 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 2128 | else |
| 2129 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 2130 | |
| 2131 | status = (readl(active_reg) & |
| 2132 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 2133 | D40_CHAN_POS(d40c->phy_chan->num); |
| 2134 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) |
| 2135 | is_paused = true; |
| 2136 | |
| 2137 | goto _exit; |
| 2138 | } |
| 2139 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2140 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 2141 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 2142 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 2143 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 2144 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 2145 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2146 | chan_err(d40c, "Unknown direction\n"); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2147 | goto _exit; |
| 2148 | } |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 2149 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2150 | status = (status & D40_EVENTLINE_MASK(event)) >> |
| 2151 | D40_EVENTLINE_POS(event); |
| 2152 | |
| 2153 | if (status != D40_DMA_RUN) |
| 2154 | is_paused = true; |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2155 | _exit: |
| 2156 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2157 | return is_paused; |
| 2158 | |
| 2159 | } |
| 2160 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2161 | static u32 stedma40_residue(struct dma_chan *chan) |
| 2162 | { |
| 2163 | struct d40_chan *d40c = |
| 2164 | container_of(chan, struct d40_chan, chan); |
| 2165 | u32 bytes_left; |
| 2166 | unsigned long flags; |
| 2167 | |
| 2168 | spin_lock_irqsave(&d40c->lock, flags); |
| 2169 | bytes_left = d40_residue(d40c); |
| 2170 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2171 | |
| 2172 | return bytes_left; |
| 2173 | } |
| 2174 | |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2175 | static int |
| 2176 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, |
| 2177 | struct scatterlist *sg_src, struct scatterlist *sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2178 | unsigned int sg_len, dma_addr_t src_dev_addr, |
| 2179 | dma_addr_t dst_dev_addr) |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2180 | { |
| 2181 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 2182 | struct stedma40_half_channel_info *src_info = &cfg->src_info; |
| 2183 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 2184 | int ret; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2185 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 2186 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
| 2187 | src_dev_addr, |
| 2188 | desc->lli_log.src, |
| 2189 | chan->log_def.lcsp1, |
| 2190 | src_info->data_width, |
| 2191 | dst_info->data_width); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2192 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 2193 | ret = d40_log_sg_to_lli(sg_dst, sg_len, |
| 2194 | dst_dev_addr, |
| 2195 | desc->lli_log.dst, |
| 2196 | chan->log_def.lcsp3, |
| 2197 | dst_info->data_width, |
| 2198 | src_info->data_width); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2199 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 2200 | return ret < 0 ? ret : 0; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2201 | } |
| 2202 | |
| 2203 | static int |
| 2204 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, |
| 2205 | struct scatterlist *sg_src, struct scatterlist *sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2206 | unsigned int sg_len, dma_addr_t src_dev_addr, |
| 2207 | dma_addr_t dst_dev_addr) |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2208 | { |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2209 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 2210 | struct stedma40_half_channel_info *src_info = &cfg->src_info; |
| 2211 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2212 | unsigned long flags = 0; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2213 | int ret; |
| 2214 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2215 | if (desc->cyclic) |
| 2216 | flags |= LLI_CYCLIC | LLI_TERM_INT; |
| 2217 | |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2218 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, |
| 2219 | desc->lli_phy.src, |
| 2220 | virt_to_phys(desc->lli_phy.src), |
| 2221 | chan->src_def_cfg, |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2222 | src_info, dst_info, flags); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2223 | |
| 2224 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, |
| 2225 | desc->lli_phy.dst, |
| 2226 | virt_to_phys(desc->lli_phy.dst), |
| 2227 | chan->dst_def_cfg, |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2228 | dst_info, src_info, flags); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2229 | |
| 2230 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, |
| 2231 | desc->lli_pool.size, DMA_TO_DEVICE); |
| 2232 | |
| 2233 | return ret < 0 ? ret : 0; |
| 2234 | } |
| 2235 | |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2236 | static struct d40_desc * |
| 2237 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, |
| 2238 | unsigned int sg_len, unsigned long dma_flags) |
| 2239 | { |
| 2240 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 2241 | struct d40_desc *desc; |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2242 | int ret; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2243 | |
| 2244 | desc = d40_desc_get(chan); |
| 2245 | if (!desc) |
| 2246 | return NULL; |
| 2247 | |
| 2248 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, |
| 2249 | cfg->dst_info.data_width); |
| 2250 | if (desc->lli_len < 0) { |
| 2251 | chan_err(chan, "Unaligned size\n"); |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2252 | goto err; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2253 | } |
| 2254 | |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2255 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
| 2256 | if (ret < 0) { |
| 2257 | chan_err(chan, "Could not allocate lli\n"); |
| 2258 | goto err; |
| 2259 | } |
| 2260 | |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2261 | desc->lli_current = 0; |
| 2262 | desc->txd.flags = dma_flags; |
| 2263 | desc->txd.tx_submit = d40_tx_submit; |
| 2264 | |
| 2265 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); |
| 2266 | |
| 2267 | return desc; |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2268 | |
| 2269 | err: |
| 2270 | d40_desc_free(chan, desc); |
| 2271 | return NULL; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2272 | } |
| 2273 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2274 | static dma_addr_t |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2275 | d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2276 | { |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2277 | struct stedma40_platform_data *plat = chan->base->plat_data; |
| 2278 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
Philippe Langlais | 711b9ce | 2011-05-07 17:09:43 +0200 | [diff] [blame] | 2279 | dma_addr_t addr = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2280 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2281 | if (chan->runtime_addr) |
| 2282 | return chan->runtime_addr; |
| 2283 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2284 | if (direction == DMA_DEV_TO_MEM) |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2285 | addr = plat->dev_rx[cfg->dev_type]; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2286 | else if (direction == DMA_MEM_TO_DEV) |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2287 | addr = plat->dev_tx[cfg->dev_type]; |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2288 | |
| 2289 | return addr; |
| 2290 | } |
| 2291 | |
| 2292 | static struct dma_async_tx_descriptor * |
| 2293 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, |
| 2294 | struct scatterlist *sg_dst, unsigned int sg_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2295 | enum dma_transfer_direction direction, unsigned long dma_flags) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2296 | { |
| 2297 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2298 | dma_addr_t src_dev_addr = 0; |
| 2299 | dma_addr_t dst_dev_addr = 0; |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2300 | struct d40_desc *desc; |
| 2301 | unsigned long flags; |
| 2302 | int ret; |
| 2303 | |
| 2304 | if (!chan->phy_chan) { |
| 2305 | chan_err(chan, "Cannot prepare unallocated channel\n"); |
| 2306 | return NULL; |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2307 | } |
| 2308 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2309 | spin_lock_irqsave(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2310 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2311 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
| 2312 | if (desc == NULL) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2313 | goto err; |
| 2314 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2315 | if (sg_next(&sg_src[sg_len - 1]) == sg_src) |
| 2316 | desc->cyclic = true; |
| 2317 | |
Linus Walleij | 7e426da | 2012-04-12 18:12:52 +0200 | [diff] [blame] | 2318 | if (direction != DMA_TRANS_NONE) { |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2319 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); |
| 2320 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2321 | if (direction == DMA_DEV_TO_MEM) |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2322 | src_dev_addr = dev_addr; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2323 | else if (direction == DMA_MEM_TO_DEV) |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2324 | dst_dev_addr = dev_addr; |
| 2325 | } |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2326 | |
| 2327 | if (chan_is_logical(chan)) |
| 2328 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2329 | sg_len, src_dev_addr, dst_dev_addr); |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2330 | else |
| 2331 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2332 | sg_len, src_dev_addr, dst_dev_addr); |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2333 | |
| 2334 | if (ret) { |
| 2335 | chan_err(chan, "Failed to prepare %s sg job: %d\n", |
| 2336 | chan_is_logical(chan) ? "log" : "phy", ret); |
| 2337 | goto err; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2338 | } |
| 2339 | |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 2340 | /* |
| 2341 | * add descriptor to the prepare queue in order to be able |
| 2342 | * to free them later in terminate_all |
| 2343 | */ |
| 2344 | list_add_tail(&desc->node, &chan->prepare_queue); |
| 2345 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2346 | spin_unlock_irqrestore(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2347 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2348 | return &desc->txd; |
| 2349 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2350 | err: |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2351 | if (desc) |
| 2352 | d40_desc_free(chan, desc); |
| 2353 | spin_unlock_irqrestore(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2354 | return NULL; |
| 2355 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2356 | |
| 2357 | bool stedma40_filter(struct dma_chan *chan, void *data) |
| 2358 | { |
| 2359 | struct stedma40_chan_cfg *info = data; |
| 2360 | struct d40_chan *d40c = |
| 2361 | container_of(chan, struct d40_chan, chan); |
| 2362 | int err; |
| 2363 | |
| 2364 | if (data) { |
| 2365 | err = d40_validate_conf(d40c, info); |
| 2366 | if (!err) |
| 2367 | d40c->dma_cfg = *info; |
| 2368 | } else |
| 2369 | err = d40_config_memcpy(d40c); |
| 2370 | |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2371 | if (!err) |
| 2372 | d40c->configured = true; |
| 2373 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2374 | return err == 0; |
| 2375 | } |
| 2376 | EXPORT_SYMBOL(stedma40_filter); |
| 2377 | |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2378 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
| 2379 | { |
| 2380 | bool realtime = d40c->dma_cfg.realtime; |
| 2381 | bool highprio = d40c->dma_cfg.high_priority; |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 2382 | u32 rtreg; |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2383 | u32 event = D40_TYPE_TO_EVENT(dev_type); |
| 2384 | u32 group = D40_TYPE_TO_GROUP(dev_type); |
| 2385 | u32 bit = 1 << event; |
Rabin Vincent | ccc3d69 | 2012-05-17 13:47:38 +0530 | [diff] [blame] | 2386 | u32 prioreg; |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 2387 | struct d40_gen_dmac *dmac = &d40c->base->gen_dmac; |
Rabin Vincent | ccc3d69 | 2012-05-17 13:47:38 +0530 | [diff] [blame] | 2388 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 2389 | rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear; |
Rabin Vincent | ccc3d69 | 2012-05-17 13:47:38 +0530 | [diff] [blame] | 2390 | /* |
| 2391 | * Due to a hardware bug, in some cases a logical channel triggered by |
| 2392 | * a high priority destination event line can generate extra packet |
| 2393 | * transactions. |
| 2394 | * |
| 2395 | * The workaround is to not set the high priority level for the |
| 2396 | * destination event lines that trigger logical channels. |
| 2397 | */ |
| 2398 | if (!src && chan_is_logical(d40c)) |
| 2399 | highprio = false; |
| 2400 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 2401 | prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear; |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2402 | |
| 2403 | /* Destination event lines are stored in the upper halfword */ |
| 2404 | if (!src) |
| 2405 | bit <<= 16; |
| 2406 | |
| 2407 | writel(bit, d40c->base->virtbase + prioreg + group * 4); |
| 2408 | writel(bit, d40c->base->virtbase + rtreg + group * 4); |
| 2409 | } |
| 2410 | |
| 2411 | static void d40_set_prio_realtime(struct d40_chan *d40c) |
| 2412 | { |
| 2413 | if (d40c->base->rev < 3) |
| 2414 | return; |
| 2415 | |
| 2416 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || |
| 2417 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2418 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true); |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2419 | |
| 2420 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || |
| 2421 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2422 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false); |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2423 | } |
| 2424 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2425 | /* DMA ENGINE functions */ |
| 2426 | static int d40_alloc_chan_resources(struct dma_chan *chan) |
| 2427 | { |
| 2428 | int err; |
| 2429 | unsigned long flags; |
| 2430 | struct d40_chan *d40c = |
| 2431 | container_of(chan, struct d40_chan, chan); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2432 | bool is_free_phy; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2433 | spin_lock_irqsave(&d40c->lock, flags); |
| 2434 | |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 2435 | dma_cookie_init(chan); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2436 | |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2437 | /* If no dma configuration is set use default configuration (memcpy) */ |
| 2438 | if (!d40c->configured) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2439 | err = d40_config_memcpy(d40c); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2440 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2441 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2442 | goto fail; |
| 2443 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2444 | } |
| 2445 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 2446 | err = d40_allocate_channel(d40c, &is_free_phy); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2447 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2448 | chan_err(d40c, "Failed to allocate channel\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2449 | d40c->configured = false; |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2450 | goto fail; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2451 | } |
| 2452 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2453 | pm_runtime_get_sync(d40c->base->dev); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2454 | /* Fill in basic CFG register values */ |
| 2455 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2456 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2457 | |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2458 | d40_set_prio_realtime(d40c); |
| 2459 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2460 | if (chan_is_logical(d40c)) { |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2461 | d40_log_cfg(&d40c->dma_cfg, |
| 2462 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
| 2463 | |
| 2464 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) |
| 2465 | d40c->lcpa = d40c->base->lcpa_base + |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2466 | d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE; |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2467 | else |
| 2468 | d40c->lcpa = d40c->base->lcpa_base + |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2469 | d40c->dma_cfg.dev_type * |
Fabio Baltieri | f26e03a | 2012-12-13 17:12:37 +0100 | [diff] [blame] | 2470 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2471 | } |
| 2472 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 2473 | dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", |
| 2474 | chan_is_logical(d40c) ? "logical" : "physical", |
| 2475 | d40c->phy_chan->num, |
| 2476 | d40c->dma_cfg.use_fixed_channel ? ", fixed" : ""); |
| 2477 | |
| 2478 | |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2479 | /* |
| 2480 | * Only write channel configuration to the DMA if the physical |
| 2481 | * resource is free. In case of multiple logical channels |
| 2482 | * on the same physical resource, only the first write is necessary. |
| 2483 | */ |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 2484 | if (is_free_phy) |
| 2485 | d40_config_write(d40c); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2486 | fail: |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2487 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2488 | pm_runtime_put_autosuspend(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2489 | spin_unlock_irqrestore(&d40c->lock, flags); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2490 | return err; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2491 | } |
| 2492 | |
| 2493 | static void d40_free_chan_resources(struct dma_chan *chan) |
| 2494 | { |
| 2495 | struct d40_chan *d40c = |
| 2496 | container_of(chan, struct d40_chan, chan); |
| 2497 | int err; |
| 2498 | unsigned long flags; |
| 2499 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2500 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2501 | chan_err(d40c, "Cannot free unallocated channel\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2502 | return; |
| 2503 | } |
| 2504 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2505 | spin_lock_irqsave(&d40c->lock, flags); |
| 2506 | |
| 2507 | err = d40_free_dma(d40c); |
| 2508 | |
| 2509 | if (err) |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2510 | chan_err(d40c, "Failed to free channel\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2511 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2512 | } |
| 2513 | |
| 2514 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, |
| 2515 | dma_addr_t dst, |
| 2516 | dma_addr_t src, |
| 2517 | size_t size, |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 2518 | unsigned long dma_flags) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2519 | { |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2520 | struct scatterlist dst_sg; |
| 2521 | struct scatterlist src_sg; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2522 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2523 | sg_init_table(&dst_sg, 1); |
| 2524 | sg_init_table(&src_sg, 1); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2525 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2526 | sg_dma_address(&dst_sg) = dst; |
| 2527 | sg_dma_address(&src_sg) = src; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2528 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2529 | sg_dma_len(&dst_sg) = size; |
| 2530 | sg_dma_len(&src_sg) = size; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2531 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2532 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2533 | } |
| 2534 | |
Ira Snyder | 0d68866 | 2010-09-30 11:46:47 +0000 | [diff] [blame] | 2535 | static struct dma_async_tx_descriptor * |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2536 | d40_prep_memcpy_sg(struct dma_chan *chan, |
| 2537 | struct scatterlist *dst_sg, unsigned int dst_nents, |
| 2538 | struct scatterlist *src_sg, unsigned int src_nents, |
| 2539 | unsigned long dma_flags) |
Ira Snyder | 0d68866 | 2010-09-30 11:46:47 +0000 | [diff] [blame] | 2540 | { |
| 2541 | if (dst_nents != src_nents) |
| 2542 | return NULL; |
| 2543 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2544 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
Rabin Vincent | 00ac034 | 2011-01-25 11:18:20 +0100 | [diff] [blame] | 2545 | } |
| 2546 | |
Fabio Baltieri | f26e03a | 2012-12-13 17:12:37 +0100 | [diff] [blame] | 2547 | static struct dma_async_tx_descriptor * |
| 2548 | d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
| 2549 | unsigned int sg_len, enum dma_transfer_direction direction, |
| 2550 | unsigned long dma_flags, void *context) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2551 | { |
Andy Shevchenko | a725dcc | 2013-01-10 10:53:01 +0200 | [diff] [blame] | 2552 | if (!is_slave_direction(direction)) |
Rabin Vincent | 00ac034 | 2011-01-25 11:18:20 +0100 | [diff] [blame] | 2553 | return NULL; |
| 2554 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2555 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2556 | } |
| 2557 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2558 | static struct dma_async_tx_descriptor * |
| 2559 | dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, |
| 2560 | size_t buf_len, size_t period_len, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 2561 | enum dma_transfer_direction direction, unsigned long flags, |
| 2562 | void *context) |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2563 | { |
| 2564 | unsigned int periods = buf_len / period_len; |
| 2565 | struct dma_async_tx_descriptor *txd; |
| 2566 | struct scatterlist *sg; |
| 2567 | int i; |
| 2568 | |
Robert Marklund | 79ca7ec | 2011-06-27 11:33:24 +0200 | [diff] [blame] | 2569 | sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2570 | for (i = 0; i < periods; i++) { |
| 2571 | sg_dma_address(&sg[i]) = dma_addr; |
| 2572 | sg_dma_len(&sg[i]) = period_len; |
| 2573 | dma_addr += period_len; |
| 2574 | } |
| 2575 | |
| 2576 | sg[periods].offset = 0; |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 2577 | sg_dma_len(&sg[periods]) = 0; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2578 | sg[periods].page_link = |
| 2579 | ((unsigned long)sg | 0x01) & ~0x02; |
| 2580 | |
| 2581 | txd = d40_prep_sg(chan, sg, sg, periods, direction, |
| 2582 | DMA_PREP_INTERRUPT); |
| 2583 | |
| 2584 | kfree(sg); |
| 2585 | |
| 2586 | return txd; |
| 2587 | } |
| 2588 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2589 | static enum dma_status d40_tx_status(struct dma_chan *chan, |
| 2590 | dma_cookie_t cookie, |
| 2591 | struct dma_tx_state *txstate) |
| 2592 | { |
| 2593 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 2594 | enum dma_status ret; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2595 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2596 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2597 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2598 | return -EINVAL; |
| 2599 | } |
| 2600 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 2601 | ret = dma_cookie_status(chan, cookie, txstate); |
| 2602 | if (ret != DMA_SUCCESS) |
| 2603 | dma_set_residue(txstate, stedma40_residue(chan)); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2604 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2605 | if (d40_is_paused(d40c)) |
| 2606 | ret = DMA_PAUSED; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2607 | |
| 2608 | return ret; |
| 2609 | } |
| 2610 | |
| 2611 | static void d40_issue_pending(struct dma_chan *chan) |
| 2612 | { |
| 2613 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2614 | unsigned long flags; |
| 2615 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2616 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2617 | chan_err(d40c, "Channel is not allocated!\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2618 | return; |
| 2619 | } |
| 2620 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2621 | spin_lock_irqsave(&d40c->lock, flags); |
| 2622 | |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 2623 | list_splice_tail_init(&d40c->pending_queue, &d40c->queue); |
| 2624 | |
| 2625 | /* Busy means that queued jobs are already being processed */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2626 | if (!d40c->busy) |
| 2627 | (void) d40_queue_start(d40c); |
| 2628 | |
| 2629 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2630 | } |
| 2631 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2632 | static void d40_terminate_all(struct dma_chan *chan) |
| 2633 | { |
| 2634 | unsigned long flags; |
| 2635 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2636 | int ret; |
| 2637 | |
| 2638 | spin_lock_irqsave(&d40c->lock, flags); |
| 2639 | |
| 2640 | pm_runtime_get_sync(d40c->base->dev); |
| 2641 | ret = d40_channel_execute_command(d40c, D40_DMA_STOP); |
| 2642 | if (ret) |
| 2643 | chan_err(d40c, "Failed to stop channel\n"); |
| 2644 | |
| 2645 | d40_term_all(d40c); |
| 2646 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2647 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 2648 | if (d40c->busy) { |
| 2649 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2650 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 2651 | } |
| 2652 | d40c->busy = false; |
| 2653 | |
| 2654 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2655 | } |
| 2656 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2657 | static int |
| 2658 | dma40_config_to_halfchannel(struct d40_chan *d40c, |
| 2659 | struct stedma40_half_channel_info *info, |
| 2660 | enum dma_slave_buswidth width, |
| 2661 | u32 maxburst) |
| 2662 | { |
| 2663 | enum stedma40_periph_data_width addr_width; |
| 2664 | int psize; |
| 2665 | |
| 2666 | switch (width) { |
| 2667 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 2668 | addr_width = STEDMA40_BYTE_WIDTH; |
| 2669 | break; |
| 2670 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 2671 | addr_width = STEDMA40_HALFWORD_WIDTH; |
| 2672 | break; |
| 2673 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 2674 | addr_width = STEDMA40_WORD_WIDTH; |
| 2675 | break; |
| 2676 | case DMA_SLAVE_BUSWIDTH_8_BYTES: |
| 2677 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; |
| 2678 | break; |
| 2679 | default: |
| 2680 | dev_err(d40c->base->dev, |
| 2681 | "illegal peripheral address width " |
| 2682 | "requested (%d)\n", |
| 2683 | width); |
| 2684 | return -EINVAL; |
| 2685 | } |
| 2686 | |
| 2687 | if (chan_is_logical(d40c)) { |
| 2688 | if (maxburst >= 16) |
| 2689 | psize = STEDMA40_PSIZE_LOG_16; |
| 2690 | else if (maxburst >= 8) |
| 2691 | psize = STEDMA40_PSIZE_LOG_8; |
| 2692 | else if (maxburst >= 4) |
| 2693 | psize = STEDMA40_PSIZE_LOG_4; |
| 2694 | else |
| 2695 | psize = STEDMA40_PSIZE_LOG_1; |
| 2696 | } else { |
| 2697 | if (maxburst >= 16) |
| 2698 | psize = STEDMA40_PSIZE_PHY_16; |
| 2699 | else if (maxburst >= 8) |
| 2700 | psize = STEDMA40_PSIZE_PHY_8; |
| 2701 | else if (maxburst >= 4) |
| 2702 | psize = STEDMA40_PSIZE_PHY_4; |
| 2703 | else |
| 2704 | psize = STEDMA40_PSIZE_PHY_1; |
| 2705 | } |
| 2706 | |
| 2707 | info->data_width = addr_width; |
| 2708 | info->psize = psize; |
| 2709 | info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; |
| 2710 | |
| 2711 | return 0; |
| 2712 | } |
| 2713 | |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2714 | /* Runtime reconfiguration extension */ |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2715 | static int d40_set_runtime_config(struct dma_chan *chan, |
| 2716 | struct dma_slave_config *config) |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2717 | { |
| 2718 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2719 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2720 | enum dma_slave_buswidth src_addr_width, dst_addr_width; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2721 | dma_addr_t config_addr; |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2722 | u32 src_maxburst, dst_maxburst; |
| 2723 | int ret; |
| 2724 | |
| 2725 | src_addr_width = config->src_addr_width; |
| 2726 | src_maxburst = config->src_maxburst; |
| 2727 | dst_addr_width = config->dst_addr_width; |
| 2728 | dst_maxburst = config->dst_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2729 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2730 | if (config->direction == DMA_DEV_TO_MEM) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2731 | dma_addr_t dev_addr_rx = |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2732 | d40c->base->plat_data->dev_rx[cfg->dev_type]; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2733 | |
| 2734 | config_addr = config->src_addr; |
| 2735 | if (dev_addr_rx) |
| 2736 | dev_dbg(d40c->base->dev, |
| 2737 | "channel has a pre-wired RX address %08x " |
| 2738 | "overriding with %08x\n", |
| 2739 | dev_addr_rx, config_addr); |
| 2740 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) |
| 2741 | dev_dbg(d40c->base->dev, |
| 2742 | "channel was not configured for peripheral " |
| 2743 | "to memory transfer (%d) overriding\n", |
| 2744 | cfg->dir); |
| 2745 | cfg->dir = STEDMA40_PERIPH_TO_MEM; |
| 2746 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2747 | /* Configure the memory side */ |
| 2748 | if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 2749 | dst_addr_width = src_addr_width; |
| 2750 | if (dst_maxburst == 0) |
| 2751 | dst_maxburst = src_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2752 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2753 | } else if (config->direction == DMA_MEM_TO_DEV) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2754 | dma_addr_t dev_addr_tx = |
Lee Jones | 26955c07d | 2013-05-03 15:31:56 +0100 | [diff] [blame] | 2755 | d40c->base->plat_data->dev_tx[cfg->dev_type]; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2756 | |
| 2757 | config_addr = config->dst_addr; |
| 2758 | if (dev_addr_tx) |
| 2759 | dev_dbg(d40c->base->dev, |
| 2760 | "channel has a pre-wired TX address %08x " |
| 2761 | "overriding with %08x\n", |
| 2762 | dev_addr_tx, config_addr); |
| 2763 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) |
| 2764 | dev_dbg(d40c->base->dev, |
| 2765 | "channel was not configured for memory " |
| 2766 | "to peripheral transfer (%d) overriding\n", |
| 2767 | cfg->dir); |
| 2768 | cfg->dir = STEDMA40_MEM_TO_PERIPH; |
| 2769 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2770 | /* Configure the memory side */ |
| 2771 | if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 2772 | src_addr_width = dst_addr_width; |
| 2773 | if (src_maxburst == 0) |
| 2774 | src_maxburst = dst_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2775 | } else { |
| 2776 | dev_err(d40c->base->dev, |
| 2777 | "unrecognized channel direction %d\n", |
| 2778 | config->direction); |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2779 | return -EINVAL; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2780 | } |
| 2781 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2782 | if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2783 | dev_err(d40c->base->dev, |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2784 | "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", |
| 2785 | src_maxburst, |
| 2786 | src_addr_width, |
| 2787 | dst_maxburst, |
| 2788 | dst_addr_width); |
| 2789 | return -EINVAL; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2790 | } |
| 2791 | |
Per Forlin | 92bb6cd | 2011-10-13 12:11:36 +0200 | [diff] [blame] | 2792 | if (src_maxburst > 16) { |
| 2793 | src_maxburst = 16; |
| 2794 | dst_maxburst = src_maxburst * src_addr_width / dst_addr_width; |
| 2795 | } else if (dst_maxburst > 16) { |
| 2796 | dst_maxburst = 16; |
| 2797 | src_maxburst = dst_maxburst * dst_addr_width / src_addr_width; |
| 2798 | } |
| 2799 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2800 | ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, |
| 2801 | src_addr_width, |
| 2802 | src_maxburst); |
| 2803 | if (ret) |
| 2804 | return ret; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2805 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2806 | ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, |
| 2807 | dst_addr_width, |
| 2808 | dst_maxburst); |
| 2809 | if (ret) |
| 2810 | return ret; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2811 | |
Per Forlin | a59670a | 2010-10-06 09:05:27 +0000 | [diff] [blame] | 2812 | /* Fill in register values */ |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2813 | if (chan_is_logical(d40c)) |
Per Forlin | a59670a | 2010-10-06 09:05:27 +0000 | [diff] [blame] | 2814 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
| 2815 | else |
| 2816 | d40_phy_cfg(cfg, &d40c->src_def_cfg, |
| 2817 | &d40c->dst_def_cfg, false); |
| 2818 | |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2819 | /* These settings will take precedence later */ |
| 2820 | d40c->runtime_addr = config_addr; |
| 2821 | d40c->runtime_direction = config->direction; |
| 2822 | dev_dbg(d40c->base->dev, |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2823 | "configured channel %s for %s, data width %d/%d, " |
| 2824 | "maxburst %d/%d elements, LE, no flow control\n", |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2825 | dma_chan_name(chan), |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2826 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2827 | src_addr_width, dst_addr_width, |
| 2828 | src_maxburst, dst_maxburst); |
| 2829 | |
| 2830 | return 0; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2831 | } |
| 2832 | |
Linus Walleij | 0582763 | 2010-05-17 16:30:42 -0700 | [diff] [blame] | 2833 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 2834 | unsigned long arg) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2835 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2836 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2837 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2838 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2839 | chan_err(d40c, "Channel is not allocated!\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2840 | return -EINVAL; |
| 2841 | } |
| 2842 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2843 | switch (cmd) { |
| 2844 | case DMA_TERMINATE_ALL: |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2845 | d40_terminate_all(chan); |
| 2846 | return 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2847 | case DMA_PAUSE: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2848 | return d40_pause(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2849 | case DMA_RESUME: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2850 | return d40_resume(d40c); |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2851 | case DMA_SLAVE_CONFIG: |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2852 | return d40_set_runtime_config(chan, |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2853 | (struct dma_slave_config *) arg); |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2854 | default: |
| 2855 | break; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2856 | } |
| 2857 | |
| 2858 | /* Other commands are unimplemented */ |
| 2859 | return -ENXIO; |
| 2860 | } |
| 2861 | |
| 2862 | /* Initialization functions */ |
| 2863 | |
| 2864 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, |
| 2865 | struct d40_chan *chans, int offset, |
| 2866 | int num_chans) |
| 2867 | { |
| 2868 | int i = 0; |
| 2869 | struct d40_chan *d40c; |
| 2870 | |
| 2871 | INIT_LIST_HEAD(&dma->channels); |
| 2872 | |
| 2873 | for (i = offset; i < offset + num_chans; i++) { |
| 2874 | d40c = &chans[i]; |
| 2875 | d40c->base = base; |
| 2876 | d40c->chan.device = dma; |
| 2877 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2878 | spin_lock_init(&d40c->lock); |
| 2879 | |
| 2880 | d40c->log_num = D40_PHY_CHAN; |
| 2881 | |
Fabio Baltieri | 4226dd8 | 2012-12-13 13:46:16 +0100 | [diff] [blame] | 2882 | INIT_LIST_HEAD(&d40c->done); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2883 | INIT_LIST_HEAD(&d40c->active); |
| 2884 | INIT_LIST_HEAD(&d40c->queue); |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 2885 | INIT_LIST_HEAD(&d40c->pending_queue); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2886 | INIT_LIST_HEAD(&d40c->client); |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 2887 | INIT_LIST_HEAD(&d40c->prepare_queue); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2888 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2889 | tasklet_init(&d40c->tasklet, dma_tasklet, |
| 2890 | (unsigned long) d40c); |
| 2891 | |
| 2892 | list_add_tail(&d40c->chan.device_node, |
| 2893 | &dma->channels); |
| 2894 | } |
| 2895 | } |
| 2896 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2897 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
| 2898 | { |
| 2899 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) |
| 2900 | dev->device_prep_slave_sg = d40_prep_slave_sg; |
| 2901 | |
| 2902 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { |
| 2903 | dev->device_prep_dma_memcpy = d40_prep_memcpy; |
| 2904 | |
| 2905 | /* |
| 2906 | * This controller can only access address at even |
| 2907 | * 32bit boundaries, i.e. 2^2 |
| 2908 | */ |
| 2909 | dev->copy_align = 2; |
| 2910 | } |
| 2911 | |
| 2912 | if (dma_has_cap(DMA_SG, dev->cap_mask)) |
| 2913 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; |
| 2914 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2915 | if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) |
| 2916 | dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; |
| 2917 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2918 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; |
| 2919 | dev->device_free_chan_resources = d40_free_chan_resources; |
| 2920 | dev->device_issue_pending = d40_issue_pending; |
| 2921 | dev->device_tx_status = d40_tx_status; |
| 2922 | dev->device_control = d40_control; |
| 2923 | dev->dev = base->dev; |
| 2924 | } |
| 2925 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2926 | static int __init d40_dmaengine_init(struct d40_base *base, |
| 2927 | int num_reserved_chans) |
| 2928 | { |
| 2929 | int err ; |
| 2930 | |
| 2931 | d40_chan_init(base, &base->dma_slave, base->log_chans, |
| 2932 | 0, base->num_log_chans); |
| 2933 | |
| 2934 | dma_cap_zero(base->dma_slave.cap_mask); |
| 2935 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2936 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2937 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2938 | d40_ops_init(base, &base->dma_slave); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2939 | |
| 2940 | err = dma_async_device_register(&base->dma_slave); |
| 2941 | |
| 2942 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2943 | d40_err(base->dev, "Failed to register slave channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2944 | goto failure1; |
| 2945 | } |
| 2946 | |
| 2947 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, |
Lee Jones | 664a57e | 2013-05-03 15:31:53 +0100 | [diff] [blame] | 2948 | base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels)); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2949 | |
| 2950 | dma_cap_zero(base->dma_memcpy.cap_mask); |
| 2951 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2952 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2953 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2954 | d40_ops_init(base, &base->dma_memcpy); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2955 | |
| 2956 | err = dma_async_device_register(&base->dma_memcpy); |
| 2957 | |
| 2958 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2959 | d40_err(base->dev, |
| 2960 | "Failed to regsiter memcpy only channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2961 | goto failure2; |
| 2962 | } |
| 2963 | |
| 2964 | d40_chan_init(base, &base->dma_both, base->phy_chans, |
| 2965 | 0, num_reserved_chans); |
| 2966 | |
| 2967 | dma_cap_zero(base->dma_both.cap_mask); |
| 2968 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); |
| 2969 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2970 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2971 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2972 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2973 | d40_ops_init(base, &base->dma_both); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2974 | err = dma_async_device_register(&base->dma_both); |
| 2975 | |
| 2976 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2977 | d40_err(base->dev, |
| 2978 | "Failed to register logical and physical capable channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2979 | goto failure3; |
| 2980 | } |
| 2981 | return 0; |
| 2982 | failure3: |
| 2983 | dma_async_device_unregister(&base->dma_memcpy); |
| 2984 | failure2: |
| 2985 | dma_async_device_unregister(&base->dma_slave); |
| 2986 | failure1: |
| 2987 | return err; |
| 2988 | } |
| 2989 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2990 | /* Suspend resume functionality */ |
| 2991 | #ifdef CONFIG_PM |
| 2992 | static int dma40_pm_suspend(struct device *dev) |
| 2993 | { |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 2994 | struct platform_device *pdev = to_platform_device(dev); |
| 2995 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2996 | int ret = 0; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2997 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 2998 | if (base->lcpa_regulator) |
| 2999 | ret = regulator_disable(base->lcpa_regulator); |
| 3000 | return ret; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3001 | } |
| 3002 | |
| 3003 | static int dma40_runtime_suspend(struct device *dev) |
| 3004 | { |
| 3005 | struct platform_device *pdev = to_platform_device(dev); |
| 3006 | struct d40_base *base = platform_get_drvdata(pdev); |
| 3007 | |
| 3008 | d40_save_restore_registers(base, true); |
| 3009 | |
| 3010 | /* Don't disable/enable clocks for v1 due to HW bugs */ |
| 3011 | if (base->rev != 1) |
| 3012 | writel_relaxed(base->gcc_pwr_off_mask, |
| 3013 | base->virtbase + D40_DREG_GCC); |
| 3014 | |
| 3015 | return 0; |
| 3016 | } |
| 3017 | |
| 3018 | static int dma40_runtime_resume(struct device *dev) |
| 3019 | { |
| 3020 | struct platform_device *pdev = to_platform_device(dev); |
| 3021 | struct d40_base *base = platform_get_drvdata(pdev); |
| 3022 | |
| 3023 | if (base->initialized) |
| 3024 | d40_save_restore_registers(base, false); |
| 3025 | |
| 3026 | writel_relaxed(D40_DREG_GCC_ENABLE_ALL, |
| 3027 | base->virtbase + D40_DREG_GCC); |
| 3028 | return 0; |
| 3029 | } |
| 3030 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3031 | static int dma40_resume(struct device *dev) |
| 3032 | { |
| 3033 | struct platform_device *pdev = to_platform_device(dev); |
| 3034 | struct d40_base *base = platform_get_drvdata(pdev); |
| 3035 | int ret = 0; |
| 3036 | |
| 3037 | if (base->lcpa_regulator) |
| 3038 | ret = regulator_enable(base->lcpa_regulator); |
| 3039 | |
| 3040 | return ret; |
| 3041 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3042 | |
| 3043 | static const struct dev_pm_ops dma40_pm_ops = { |
| 3044 | .suspend = dma40_pm_suspend, |
| 3045 | .runtime_suspend = dma40_runtime_suspend, |
| 3046 | .runtime_resume = dma40_runtime_resume, |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3047 | .resume = dma40_resume, |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3048 | }; |
| 3049 | #define DMA40_PM_OPS (&dma40_pm_ops) |
| 3050 | #else |
| 3051 | #define DMA40_PM_OPS NULL |
| 3052 | #endif |
| 3053 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3054 | /* Initialization functions. */ |
| 3055 | |
| 3056 | static int __init d40_phy_res_init(struct d40_base *base) |
| 3057 | { |
| 3058 | int i; |
| 3059 | int num_phy_chans_avail = 0; |
| 3060 | u32 val[2]; |
| 3061 | int odd_even_bit = -2; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3062 | int gcc = D40_DREG_GCC_ENA; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3063 | |
| 3064 | val[0] = readl(base->virtbase + D40_DREG_PRSME); |
| 3065 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); |
| 3066 | |
| 3067 | for (i = 0; i < base->num_phy_chans; i++) { |
| 3068 | base->phy_res[i].num = i; |
| 3069 | odd_even_bit += 2 * ((i % 2) == 0); |
| 3070 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { |
| 3071 | /* Mark security only channels as occupied */ |
| 3072 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; |
| 3073 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3074 | base->phy_res[i].reserved = true; |
| 3075 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), |
| 3076 | D40_DREG_GCC_SRC); |
| 3077 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), |
| 3078 | D40_DREG_GCC_DST); |
| 3079 | |
| 3080 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3081 | } else { |
| 3082 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; |
| 3083 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3084 | base->phy_res[i].reserved = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3085 | num_phy_chans_avail++; |
| 3086 | } |
| 3087 | spin_lock_init(&base->phy_res[i].lock); |
| 3088 | } |
Jonas Aaberg | 6b7acd8 | 2010-06-20 21:26:59 +0000 | [diff] [blame] | 3089 | |
| 3090 | /* Mark disabled channels as occupied */ |
| 3091 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { |
Rabin Vincent | f57b407 | 2010-10-06 08:20:35 +0000 | [diff] [blame] | 3092 | int chan = base->plat_data->disabled_channels[i]; |
| 3093 | |
| 3094 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; |
| 3095 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3096 | base->phy_res[chan].reserved = true; |
| 3097 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), |
| 3098 | D40_DREG_GCC_SRC); |
| 3099 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), |
| 3100 | D40_DREG_GCC_DST); |
Rabin Vincent | f57b407 | 2010-10-06 08:20:35 +0000 | [diff] [blame] | 3101 | num_phy_chans_avail--; |
Jonas Aaberg | 6b7acd8 | 2010-06-20 21:26:59 +0000 | [diff] [blame] | 3102 | } |
| 3103 | |
Fabio Baltieri | 7407048 | 2012-12-18 12:25:14 +0100 | [diff] [blame] | 3104 | /* Mark soft_lli channels */ |
| 3105 | for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) { |
| 3106 | int chan = base->plat_data->soft_lli_chans[i]; |
| 3107 | |
| 3108 | base->phy_res[chan].use_soft_lli = true; |
| 3109 | } |
| 3110 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3111 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
| 3112 | num_phy_chans_avail, base->num_phy_chans); |
| 3113 | |
| 3114 | /* Verify settings extended vs standard */ |
| 3115 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); |
| 3116 | |
| 3117 | for (i = 0; i < base->num_phy_chans; i++) { |
| 3118 | |
| 3119 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && |
| 3120 | (val[0] & 0x3) != 1) |
| 3121 | dev_info(base->dev, |
| 3122 | "[%s] INFO: channel %d is misconfigured (%d)\n", |
| 3123 | __func__, i, val[0] & 0x3); |
| 3124 | |
| 3125 | val[0] = val[0] >> 2; |
| 3126 | } |
| 3127 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3128 | /* |
| 3129 | * To keep things simple, Enable all clocks initially. |
| 3130 | * The clocks will get managed later post channel allocation. |
| 3131 | * The clocks for the event lines on which reserved channels exists |
| 3132 | * are not managed here. |
| 3133 | */ |
| 3134 | writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); |
| 3135 | base->gcc_pwr_off_mask = gcc; |
| 3136 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3137 | return num_phy_chans_avail; |
| 3138 | } |
| 3139 | |
| 3140 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) |
| 3141 | { |
Lee Jones | bb75d93 | 2013-05-03 15:32:10 +0100 | [diff] [blame] | 3142 | struct stedma40_platform_data *plat_data = pdev->dev.platform_data; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3143 | struct clk *clk = NULL; |
| 3144 | void __iomem *virtbase = NULL; |
| 3145 | struct resource *res = NULL; |
| 3146 | struct d40_base *base = NULL; |
| 3147 | int num_log_chans = 0; |
| 3148 | int num_phy_chans; |
Ulf Hansson | b707c658 | 2012-08-23 13:41:58 +0200 | [diff] [blame] | 3149 | int clk_ret = -EINVAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3150 | int i; |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 3151 | u32 pid; |
| 3152 | u32 cid; |
| 3153 | u8 rev; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3154 | |
| 3155 | clk = clk_get(&pdev->dev, NULL); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3156 | if (IS_ERR(clk)) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3157 | d40_err(&pdev->dev, "No matching clock found\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3158 | goto failure; |
| 3159 | } |
| 3160 | |
Ulf Hansson | b707c658 | 2012-08-23 13:41:58 +0200 | [diff] [blame] | 3161 | clk_ret = clk_prepare_enable(clk); |
| 3162 | if (clk_ret) { |
| 3163 | d40_err(&pdev->dev, "Failed to prepare/enable clock\n"); |
| 3164 | goto failure; |
| 3165 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3166 | |
| 3167 | /* Get IO for DMAC base address */ |
| 3168 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); |
| 3169 | if (!res) |
| 3170 | goto failure; |
| 3171 | |
| 3172 | if (request_mem_region(res->start, resource_size(res), |
| 3173 | D40_NAME " I/O base") == NULL) |
| 3174 | goto failure; |
| 3175 | |
| 3176 | virtbase = ioremap(res->start, resource_size(res)); |
| 3177 | if (!virtbase) |
| 3178 | goto failure; |
| 3179 | |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 3180 | /* This is just a regular AMBA PrimeCell ID actually */ |
| 3181 | for (pid = 0, i = 0; i < 4; i++) |
| 3182 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) |
| 3183 | & 255) << (i * 8); |
| 3184 | for (cid = 0, i = 0; i < 4; i++) |
| 3185 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) |
| 3186 | & 255) << (i * 8); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3187 | |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 3188 | if (cid != AMBA_CID) { |
| 3189 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3190 | goto failure; |
| 3191 | } |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 3192 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { |
| 3193 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
| 3194 | AMBA_MANF_BITS(pid), |
| 3195 | AMBA_VENDOR_ST); |
| 3196 | goto failure; |
| 3197 | } |
| 3198 | /* |
| 3199 | * HW revision: |
| 3200 | * DB8500ed has revision 0 |
| 3201 | * ? has revision 1 |
| 3202 | * DB8500v1 has revision 2 |
| 3203 | * DB8500v2 has revision 3 |
Gerald Baeza | 47db92f | 2012-09-21 21:21:37 +0200 | [diff] [blame] | 3204 | * AP9540v1 has revision 4 |
| 3205 | * DB8540v1 has revision 4 |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 3206 | */ |
| 3207 | rev = AMBA_REV_BITS(pid); |
Lee Jones | 8b2fe9b | 2013-05-03 15:32:08 +0100 | [diff] [blame] | 3208 | if (rev < 2) { |
| 3209 | d40_err(&pdev->dev, "hardware revision: %d is not supported", rev); |
| 3210 | goto failure; |
| 3211 | } |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 3212 | |
Gerald Baeza | 47db92f | 2012-09-21 21:21:37 +0200 | [diff] [blame] | 3213 | /* The number of physical channels on this HW */ |
| 3214 | if (plat_data->num_of_phy_chans) |
| 3215 | num_phy_chans = plat_data->num_of_phy_chans; |
| 3216 | else |
| 3217 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; |
| 3218 | |
Lee Jones | db72da9 | 2013-05-03 15:32:03 +0100 | [diff] [blame] | 3219 | num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY; |
| 3220 | |
Lee Jones | b2abb24 | 2013-05-03 15:32:09 +0100 | [diff] [blame] | 3221 | dev_info(&pdev->dev, |
| 3222 | "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n", |
| 3223 | rev, res->start, num_phy_chans, num_log_chans); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3224 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3225 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + |
Lee Jones | 664a57e | 2013-05-03 15:31:53 +0100 | [diff] [blame] | 3226 | (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) * |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3227 | sizeof(struct d40_chan), GFP_KERNEL); |
| 3228 | |
| 3229 | if (base == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3230 | d40_err(&pdev->dev, "Out of memory\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3231 | goto failure; |
| 3232 | } |
| 3233 | |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 3234 | base->rev = rev; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3235 | base->clk = clk; |
| 3236 | base->num_phy_chans = num_phy_chans; |
| 3237 | base->num_log_chans = num_log_chans; |
| 3238 | base->phy_start = res->start; |
| 3239 | base->phy_size = resource_size(res); |
| 3240 | base->virtbase = virtbase; |
| 3241 | base->plat_data = plat_data; |
| 3242 | base->dev = &pdev->dev; |
| 3243 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); |
| 3244 | base->log_chans = &base->phy_chans[num_phy_chans]; |
| 3245 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 3246 | if (base->plat_data->num_of_phy_chans == 14) { |
| 3247 | base->gen_dmac.backup = d40_backup_regs_v4b; |
| 3248 | base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B; |
| 3249 | base->gen_dmac.interrupt_en = D40_DREG_CPCMIS; |
| 3250 | base->gen_dmac.interrupt_clear = D40_DREG_CPCICR; |
| 3251 | base->gen_dmac.realtime_en = D40_DREG_CRSEG1; |
| 3252 | base->gen_dmac.realtime_clear = D40_DREG_CRCEG1; |
| 3253 | base->gen_dmac.high_prio_en = D40_DREG_CPSEG1; |
| 3254 | base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1; |
| 3255 | base->gen_dmac.il = il_v4b; |
| 3256 | base->gen_dmac.il_size = ARRAY_SIZE(il_v4b); |
| 3257 | base->gen_dmac.init_reg = dma_init_reg_v4b; |
| 3258 | base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b); |
| 3259 | } else { |
| 3260 | if (base->rev >= 3) { |
| 3261 | base->gen_dmac.backup = d40_backup_regs_v4a; |
| 3262 | base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A; |
| 3263 | } |
| 3264 | base->gen_dmac.interrupt_en = D40_DREG_PCMIS; |
| 3265 | base->gen_dmac.interrupt_clear = D40_DREG_PCICR; |
| 3266 | base->gen_dmac.realtime_en = D40_DREG_RSEG1; |
| 3267 | base->gen_dmac.realtime_clear = D40_DREG_RCEG1; |
| 3268 | base->gen_dmac.high_prio_en = D40_DREG_PSEG1; |
| 3269 | base->gen_dmac.high_prio_clear = D40_DREG_PCEG1; |
| 3270 | base->gen_dmac.il = il_v4a; |
| 3271 | base->gen_dmac.il_size = ARRAY_SIZE(il_v4a); |
| 3272 | base->gen_dmac.init_reg = dma_init_reg_v4a; |
| 3273 | base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a); |
| 3274 | } |
| 3275 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3276 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), |
| 3277 | GFP_KERNEL); |
| 3278 | if (!base->phy_res) |
| 3279 | goto failure; |
| 3280 | |
| 3281 | base->lookup_phy_chans = kzalloc(num_phy_chans * |
| 3282 | sizeof(struct d40_chan *), |
| 3283 | GFP_KERNEL); |
| 3284 | if (!base->lookup_phy_chans) |
| 3285 | goto failure; |
| 3286 | |
Lee Jones | 8a59fed | 2013-05-03 15:32:04 +0100 | [diff] [blame] | 3287 | base->lookup_log_chans = kzalloc(num_log_chans * |
| 3288 | sizeof(struct d40_chan *), |
| 3289 | GFP_KERNEL); |
| 3290 | if (!base->lookup_log_chans) |
| 3291 | goto failure; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 3292 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3293 | base->reg_val_backup_chan = kmalloc(base->num_phy_chans * |
| 3294 | sizeof(d40_backup_regs_chan), |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3295 | GFP_KERNEL); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3296 | if (!base->reg_val_backup_chan) |
| 3297 | goto failure; |
| 3298 | |
| 3299 | base->lcla_pool.alloc_map = |
| 3300 | kzalloc(num_phy_chans * sizeof(struct d40_desc *) |
| 3301 | * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3302 | if (!base->lcla_pool.alloc_map) |
| 3303 | goto failure; |
| 3304 | |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 3305 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
| 3306 | 0, SLAB_HWCACHE_ALIGN, |
| 3307 | NULL); |
| 3308 | if (base->desc_slab == NULL) |
| 3309 | goto failure; |
| 3310 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3311 | return base; |
| 3312 | |
| 3313 | failure: |
Ulf Hansson | b707c658 | 2012-08-23 13:41:58 +0200 | [diff] [blame] | 3314 | if (!clk_ret) |
| 3315 | clk_disable_unprepare(clk); |
| 3316 | if (!IS_ERR(clk)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3317 | clk_put(clk); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3318 | if (virtbase) |
| 3319 | iounmap(virtbase); |
| 3320 | if (res) |
| 3321 | release_mem_region(res->start, |
| 3322 | resource_size(res)); |
| 3323 | if (virtbase) |
| 3324 | iounmap(virtbase); |
| 3325 | |
| 3326 | if (base) { |
| 3327 | kfree(base->lcla_pool.alloc_map); |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 3328 | kfree(base->reg_val_backup_chan); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3329 | kfree(base->lookup_log_chans); |
| 3330 | kfree(base->lookup_phy_chans); |
| 3331 | kfree(base->phy_res); |
| 3332 | kfree(base); |
| 3333 | } |
| 3334 | |
| 3335 | return NULL; |
| 3336 | } |
| 3337 | |
| 3338 | static void __init d40_hw_init(struct d40_base *base) |
| 3339 | { |
| 3340 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3341 | int i; |
| 3342 | u32 prmseo[2] = {0, 0}; |
| 3343 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; |
| 3344 | u32 pcmis = 0; |
| 3345 | u32 pcicr = 0; |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 3346 | struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg; |
| 3347 | u32 reg_size = base->gen_dmac.init_reg_size; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3348 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 3349 | for (i = 0; i < reg_size; i++) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3350 | writel(dma_init_reg[i].val, |
| 3351 | base->virtbase + dma_init_reg[i].reg); |
| 3352 | |
| 3353 | /* Configure all our dma channels to default settings */ |
| 3354 | for (i = 0; i < base->num_phy_chans; i++) { |
| 3355 | |
| 3356 | activeo[i % 2] = activeo[i % 2] << 2; |
| 3357 | |
| 3358 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src |
| 3359 | == D40_ALLOC_PHY) { |
| 3360 | activeo[i % 2] |= 3; |
| 3361 | continue; |
| 3362 | } |
| 3363 | |
| 3364 | /* Enable interrupt # */ |
| 3365 | pcmis = (pcmis << 1) | 1; |
| 3366 | |
| 3367 | /* Clear interrupt # */ |
| 3368 | pcicr = (pcicr << 1) | 1; |
| 3369 | |
| 3370 | /* Set channel to physical mode */ |
| 3371 | prmseo[i % 2] = prmseo[i % 2] << 2; |
| 3372 | prmseo[i % 2] |= 1; |
| 3373 | |
| 3374 | } |
| 3375 | |
| 3376 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); |
| 3377 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); |
| 3378 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); |
| 3379 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); |
| 3380 | |
| 3381 | /* Write which interrupt to enable */ |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 3382 | writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3383 | |
| 3384 | /* Write which interrupt to clear */ |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 3385 | writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3386 | |
Tong Liu | 3cb645d | 2012-09-26 10:07:30 +0000 | [diff] [blame] | 3387 | /* These are __initdata and cannot be accessed after init */ |
| 3388 | base->gen_dmac.init_reg = NULL; |
| 3389 | base->gen_dmac.init_reg_size = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3390 | } |
| 3391 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3392 | static int __init d40_lcla_allocate(struct d40_base *base) |
| 3393 | { |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3394 | struct d40_lcla_pool *pool = &base->lcla_pool; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3395 | unsigned long *page_list; |
| 3396 | int i, j; |
| 3397 | int ret = 0; |
| 3398 | |
| 3399 | /* |
| 3400 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, |
| 3401 | * To full fill this hardware requirement without wasting 256 kb |
| 3402 | * we allocate pages until we get an aligned one. |
| 3403 | */ |
| 3404 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, |
| 3405 | GFP_KERNEL); |
| 3406 | |
| 3407 | if (!page_list) { |
| 3408 | ret = -ENOMEM; |
| 3409 | goto failure; |
| 3410 | } |
| 3411 | |
| 3412 | /* Calculating how many pages that are required */ |
| 3413 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; |
| 3414 | |
| 3415 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { |
| 3416 | page_list[i] = __get_free_pages(GFP_KERNEL, |
| 3417 | base->lcla_pool.pages); |
| 3418 | if (!page_list[i]) { |
| 3419 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3420 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
| 3421 | base->lcla_pool.pages); |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3422 | |
| 3423 | for (j = 0; j < i; j++) |
| 3424 | free_pages(page_list[j], base->lcla_pool.pages); |
| 3425 | goto failure; |
| 3426 | } |
| 3427 | |
| 3428 | if ((virt_to_phys((void *)page_list[i]) & |
| 3429 | (LCLA_ALIGNMENT - 1)) == 0) |
| 3430 | break; |
| 3431 | } |
| 3432 | |
| 3433 | for (j = 0; j < i; j++) |
| 3434 | free_pages(page_list[j], base->lcla_pool.pages); |
| 3435 | |
| 3436 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { |
| 3437 | base->lcla_pool.base = (void *)page_list[i]; |
| 3438 | } else { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 3439 | /* |
| 3440 | * After many attempts and no succees with finding the correct |
| 3441 | * alignment, try with allocating a big buffer. |
| 3442 | */ |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3443 | dev_warn(base->dev, |
| 3444 | "[%s] Failed to get %d pages @ 18 bit align.\n", |
| 3445 | __func__, base->lcla_pool.pages); |
| 3446 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * |
| 3447 | base->num_phy_chans + |
| 3448 | LCLA_ALIGNMENT, |
| 3449 | GFP_KERNEL); |
| 3450 | if (!base->lcla_pool.base_unaligned) { |
| 3451 | ret = -ENOMEM; |
| 3452 | goto failure; |
| 3453 | } |
| 3454 | |
| 3455 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, |
| 3456 | LCLA_ALIGNMENT); |
| 3457 | } |
| 3458 | |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3459 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
| 3460 | SZ_1K * base->num_phy_chans, |
| 3461 | DMA_TO_DEVICE); |
| 3462 | if (dma_mapping_error(base->dev, pool->dma_addr)) { |
| 3463 | pool->dma_addr = 0; |
| 3464 | ret = -ENOMEM; |
| 3465 | goto failure; |
| 3466 | } |
| 3467 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3468 | writel(virt_to_phys(base->lcla_pool.base), |
| 3469 | base->virtbase + D40_DREG_LCLA); |
| 3470 | failure: |
| 3471 | kfree(page_list); |
| 3472 | return ret; |
| 3473 | } |
| 3474 | |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3475 | static int __init d40_of_probe(struct platform_device *pdev, |
| 3476 | struct device_node *np) |
| 3477 | { |
| 3478 | struct stedma40_platform_data *pdata; |
| 3479 | |
| 3480 | /* |
| 3481 | * FIXME: Fill in this routine as more support is added. |
| 3482 | * First platform enabled (u8500) doens't need any extra |
| 3483 | * properties to run, so this is fairly sparce currently. |
| 3484 | */ |
| 3485 | |
| 3486 | pdata = devm_kzalloc(&pdev->dev, |
| 3487 | sizeof(struct stedma40_platform_data), |
| 3488 | GFP_KERNEL); |
| 3489 | if (!pdata) |
| 3490 | return -ENOMEM; |
| 3491 | |
| 3492 | pdev->dev.platform_data = pdata; |
| 3493 | |
| 3494 | return 0; |
| 3495 | } |
| 3496 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3497 | static int __init d40_probe(struct platform_device *pdev) |
| 3498 | { |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3499 | struct stedma40_platform_data *plat_data = pdev->dev.platform_data; |
| 3500 | struct device_node *np = pdev->dev.of_node; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3501 | int err; |
| 3502 | int ret = -ENOENT; |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3503 | struct d40_base *base = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3504 | struct resource *res = NULL; |
| 3505 | int num_reserved_chans; |
| 3506 | u32 val; |
| 3507 | |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3508 | if (!plat_data) { |
| 3509 | if (np) { |
| 3510 | if(d40_of_probe(pdev, np)) { |
| 3511 | ret = -ENOMEM; |
| 3512 | goto failure; |
| 3513 | } |
| 3514 | } else { |
| 3515 | d40_err(&pdev->dev, "No pdata or Device Tree provided\n"); |
| 3516 | goto failure; |
| 3517 | } |
| 3518 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3519 | |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3520 | base = d40_hw_detect_init(pdev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3521 | if (!base) |
| 3522 | goto failure; |
| 3523 | |
| 3524 | num_reserved_chans = d40_phy_res_init(base); |
| 3525 | |
| 3526 | platform_set_drvdata(pdev, base); |
| 3527 | |
| 3528 | spin_lock_init(&base->interrupt_lock); |
| 3529 | spin_lock_init(&base->execmd_lock); |
| 3530 | |
| 3531 | /* Get IO for logical channel parameter address */ |
| 3532 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); |
| 3533 | if (!res) { |
| 3534 | ret = -ENOENT; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3535 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3536 | goto failure; |
| 3537 | } |
| 3538 | base->lcpa_size = resource_size(res); |
| 3539 | base->phy_lcpa = res->start; |
| 3540 | |
| 3541 | if (request_mem_region(res->start, resource_size(res), |
| 3542 | D40_NAME " I/O lcpa") == NULL) { |
| 3543 | ret = -EBUSY; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3544 | d40_err(&pdev->dev, |
| 3545 | "Failed to request LCPA region 0x%x-0x%x\n", |
| 3546 | res->start, res->end); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3547 | goto failure; |
| 3548 | } |
| 3549 | |
| 3550 | /* We make use of ESRAM memory for this. */ |
| 3551 | val = readl(base->virtbase + D40_DREG_LCPA); |
| 3552 | if (res->start != val && val != 0) { |
| 3553 | dev_warn(&pdev->dev, |
| 3554 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", |
| 3555 | __func__, val, res->start); |
| 3556 | } else |
| 3557 | writel(res->start, base->virtbase + D40_DREG_LCPA); |
| 3558 | |
| 3559 | base->lcpa_base = ioremap(res->start, resource_size(res)); |
| 3560 | if (!base->lcpa_base) { |
| 3561 | ret = -ENOMEM; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3562 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3563 | goto failure; |
| 3564 | } |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3565 | /* If lcla has to be located in ESRAM we don't need to allocate */ |
| 3566 | if (base->plat_data->use_esram_lcla) { |
| 3567 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 3568 | "lcla_esram"); |
| 3569 | if (!res) { |
| 3570 | ret = -ENOENT; |
| 3571 | d40_err(&pdev->dev, |
| 3572 | "No \"lcla_esram\" memory resource\n"); |
| 3573 | goto failure; |
| 3574 | } |
| 3575 | base->lcla_pool.base = ioremap(res->start, |
| 3576 | resource_size(res)); |
| 3577 | if (!base->lcla_pool.base) { |
| 3578 | ret = -ENOMEM; |
| 3579 | d40_err(&pdev->dev, "Failed to ioremap LCLA region\n"); |
| 3580 | goto failure; |
| 3581 | } |
| 3582 | writel(res->start, base->virtbase + D40_DREG_LCLA); |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3583 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3584 | } else { |
| 3585 | ret = d40_lcla_allocate(base); |
| 3586 | if (ret) { |
| 3587 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); |
| 3588 | goto failure; |
| 3589 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3590 | } |
| 3591 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3592 | spin_lock_init(&base->lcla_pool.lock); |
| 3593 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3594 | base->irq = platform_get_irq(pdev, 0); |
| 3595 | |
| 3596 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3597 | if (ret) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3598 | d40_err(&pdev->dev, "No IRQ defined\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3599 | goto failure; |
| 3600 | } |
| 3601 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3602 | pm_runtime_irq_safe(base->dev); |
| 3603 | pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); |
| 3604 | pm_runtime_use_autosuspend(base->dev); |
| 3605 | pm_runtime_enable(base->dev); |
| 3606 | pm_runtime_resume(base->dev); |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3607 | |
| 3608 | if (base->plat_data->use_esram_lcla) { |
| 3609 | |
| 3610 | base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); |
| 3611 | if (IS_ERR(base->lcpa_regulator)) { |
| 3612 | d40_err(&pdev->dev, "Failed to get lcpa_regulator\n"); |
| 3613 | base->lcpa_regulator = NULL; |
| 3614 | goto failure; |
| 3615 | } |
| 3616 | |
| 3617 | ret = regulator_enable(base->lcpa_regulator); |
| 3618 | if (ret) { |
| 3619 | d40_err(&pdev->dev, |
| 3620 | "Failed to enable lcpa_regulator\n"); |
| 3621 | regulator_put(base->lcpa_regulator); |
| 3622 | base->lcpa_regulator = NULL; |
| 3623 | goto failure; |
| 3624 | } |
| 3625 | } |
| 3626 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3627 | base->initialized = true; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3628 | err = d40_dmaengine_init(base, num_reserved_chans); |
| 3629 | if (err) |
| 3630 | goto failure; |
| 3631 | |
Per Forlin | b96710e | 2011-10-18 18:39:47 +0200 | [diff] [blame] | 3632 | base->dev->dma_parms = &base->dma_parms; |
| 3633 | err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE); |
| 3634 | if (err) { |
| 3635 | d40_err(&pdev->dev, "Failed to set dma max seg size\n"); |
| 3636 | goto failure; |
| 3637 | } |
| 3638 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3639 | d40_hw_init(base); |
| 3640 | |
| 3641 | dev_info(base->dev, "initialized\n"); |
| 3642 | return 0; |
| 3643 | |
| 3644 | failure: |
| 3645 | if (base) { |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 3646 | if (base->desc_slab) |
| 3647 | kmem_cache_destroy(base->desc_slab); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3648 | if (base->virtbase) |
| 3649 | iounmap(base->virtbase); |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3650 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3651 | if (base->lcla_pool.base && base->plat_data->use_esram_lcla) { |
| 3652 | iounmap(base->lcla_pool.base); |
| 3653 | base->lcla_pool.base = NULL; |
| 3654 | } |
| 3655 | |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3656 | if (base->lcla_pool.dma_addr) |
| 3657 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, |
| 3658 | SZ_1K * base->num_phy_chans, |
| 3659 | DMA_TO_DEVICE); |
| 3660 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3661 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
| 3662 | free_pages((unsigned long)base->lcla_pool.base, |
| 3663 | base->lcla_pool.pages); |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 3664 | |
| 3665 | kfree(base->lcla_pool.base_unaligned); |
| 3666 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3667 | if (base->phy_lcpa) |
| 3668 | release_mem_region(base->phy_lcpa, |
| 3669 | base->lcpa_size); |
| 3670 | if (base->phy_start) |
| 3671 | release_mem_region(base->phy_start, |
| 3672 | base->phy_size); |
| 3673 | if (base->clk) { |
Fabio Baltieri | da2ac56 | 2013-01-07 10:58:35 +0100 | [diff] [blame] | 3674 | clk_disable_unprepare(base->clk); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3675 | clk_put(base->clk); |
| 3676 | } |
| 3677 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3678 | if (base->lcpa_regulator) { |
| 3679 | regulator_disable(base->lcpa_regulator); |
| 3680 | regulator_put(base->lcpa_regulator); |
| 3681 | } |
| 3682 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3683 | kfree(base->lcla_pool.alloc_map); |
| 3684 | kfree(base->lookup_log_chans); |
| 3685 | kfree(base->lookup_phy_chans); |
| 3686 | kfree(base->phy_res); |
| 3687 | kfree(base); |
| 3688 | } |
| 3689 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3690 | d40_err(&pdev->dev, "probe failed\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3691 | return ret; |
| 3692 | } |
| 3693 | |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3694 | static const struct of_device_id d40_match[] = { |
| 3695 | { .compatible = "stericsson,dma40", }, |
| 3696 | {} |
| 3697 | }; |
| 3698 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3699 | static struct platform_driver d40_driver = { |
| 3700 | .driver = { |
| 3701 | .owner = THIS_MODULE, |
| 3702 | .name = D40_NAME, |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3703 | .pm = DMA40_PM_OPS, |
Lee Jones | 1814a17 | 2013-05-03 15:32:11 +0100 | [diff] [blame^] | 3704 | .of_match_table = d40_match, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3705 | }, |
| 3706 | }; |
| 3707 | |
Rabin Vincent | cb9ab2d | 2011-01-25 11:18:04 +0100 | [diff] [blame] | 3708 | static int __init stedma40_init(void) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3709 | { |
| 3710 | return platform_driver_probe(&d40_driver, d40_probe); |
| 3711 | } |
Linus Walleij | a0eb221 | 2011-05-18 14:18:57 +0200 | [diff] [blame] | 3712 | subsys_initcall(stedma40_init); |