Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration |
| 3 | # |
| 4 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" |
Dan Williams | 04ce9ab | 2009-06-03 14:22:28 -0700 | [diff] [blame] | 7 | depends on HAS_DMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 8 | help |
Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 9 | DMA engines can do asynchronous data transfers without |
| 10 | involving the host CPU. Currently, this framework can be |
| 11 | used to offload memory copies in the network stack and |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 12 | RAID operations in the MD driver. This menu only presents |
| 13 | DMA Device drivers supported by the configured arch, it may |
| 14 | be empty in some cases. |
Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 15 | |
Linus Walleij | 6c664a8 | 2010-02-09 22:34:54 +0100 | [diff] [blame] | 16 | config DMADEVICES_DEBUG |
| 17 | bool "DMA Engine debugging" |
| 18 | depends on DMADEVICES != n |
| 19 | help |
| 20 | This is an option for use by developers; most people should |
| 21 | say N here. This enables DMA engine core and driver debugging. |
| 22 | |
| 23 | config DMADEVICES_VDEBUG |
| 24 | bool "DMA Engine verbose debugging" |
| 25 | depends on DMADEVICES_DEBUG != n |
| 26 | help |
| 27 | This is an option for use by developers; most people should |
| 28 | say N here. This enables deeper (more verbose) debugging of |
| 29 | the DMA engine core and drivers. |
| 30 | |
| 31 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 32 | if DMADEVICES |
Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 33 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 34 | comment "DMA Devices" |
| 35 | |
Vinod Koul | b3c567e | 2010-07-21 13:28:10 +0530 | [diff] [blame] | 36 | config INTEL_MID_DMAC |
| 37 | tristate "Intel MID DMA support for Peripheral DMA controllers" |
| 38 | depends on PCI && X86 |
| 39 | select DMA_ENGINE |
| 40 | default n |
| 41 | help |
| 42 | Enable support for the Intel(R) MID DMA engine present |
| 43 | in Intel MID chipsets. |
| 44 | |
| 45 | Say Y here if you have such a chipset. |
| 46 | |
| 47 | If unsure, say N. |
| 48 | |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 49 | config ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Dan Williams | 138f4c3 | 2009-09-08 17:42:51 -0700 | [diff] [blame] | 50 | bool |
| 51 | |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 52 | config AMBA_PL08X |
| 53 | bool "ARM PrimeCell PL080 or PL081 support" |
Kees Cook | c6a0aec | 2012-10-23 13:01:54 -0700 | [diff] [blame] | 54 | depends on ARM_AMBA |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 55 | select DMA_ENGINE |
Russell King | 083be28 | 2012-05-26 14:09:53 +0100 | [diff] [blame] | 56 | select DMA_VIRTUAL_CHANNELS |
Linus Walleij | e8689e6 | 2010-09-28 15:57:37 +0200 | [diff] [blame] | 57 | help |
| 58 | Platform has a PL08x DMAC device |
| 59 | which can provide DMA engine support |
| 60 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 61 | config INTEL_IOATDMA |
| 62 | tristate "Intel I/OAT DMA support" |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 63 | depends on PCI && X86 |
| 64 | select DMA_ENGINE |
| 65 | select DCA |
| 66 | help |
| 67 | Enable support for the Intel(R) I/OAT DMA engine present |
| 68 | in recent Intel Xeon chipsets. |
| 69 | |
| 70 | Say Y here if you have such a chipset. |
| 71 | |
| 72 | If unsure, say N. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 73 | |
| 74 | config INTEL_IOP_ADMA |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 75 | tristate "Intel IOP ADMA support" |
| 76 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 77 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 78 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 79 | help |
| 80 | Enable support for the Intel(R) IOP Series RAID engines. |
Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 81 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 82 | config DW_DMAC |
| 83 | tristate "Synopsys DesignWare AHB DMA support" |
Heiko Carstens | 6c43a51 | 2013-03-20 09:45:22 +0100 | [diff] [blame] | 84 | depends on GENERIC_HARDIRQS |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 85 | select DMA_ENGINE |
| 86 | default y if CPU_AT32AP7000 |
| 87 | help |
| 88 | Support the Synopsys DesignWare AHB DMA controller. This |
| 89 | can be integrated in chips such as the Atmel AT32ap7000. |
| 90 | |
Hein Tibosch | d5ea7b5 | 2012-10-25 13:38:05 -0700 | [diff] [blame] | 91 | config DW_DMAC_BIG_ENDIAN_IO |
| 92 | bool "Use big endian I/O register access" |
| 93 | default y if AVR32 |
| 94 | depends on DW_DMAC |
| 95 | help |
| 96 | Say yes here to use big endian I/O access when reading and writing |
| 97 | to the DMA controller registers. This is needed on some platforms, |
| 98 | like the Atmel AVR32 architecture. |
| 99 | |
| 100 | If unsure, use the default setting. |
| 101 | |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 102 | config AT_HDMAC |
| 103 | tristate "Atmel AHB DMA support" |
Nicolas Ferre | f898fed | 2012-03-15 11:31:58 +0100 | [diff] [blame] | 104 | depends on ARCH_AT91 |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 105 | select DMA_ENGINE |
| 106 | help |
Nicolas Ferre | f898fed | 2012-03-15 11:31:58 +0100 | [diff] [blame] | 107 | Support the Atmel AHB DMA controller. |
Nicolas Ferre | dc78baa | 2009-07-03 19:24:33 +0200 | [diff] [blame] | 108 | |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 109 | config FSL_DMA |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 110 | tristate "Freescale Elo and Elo Plus DMA support" |
| 111 | depends on FSL_SOC |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 112 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 113 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 114 | ---help--- |
Timur Tabi | 77cd62e | 2008-09-26 17:00:11 -0700 | [diff] [blame] | 115 | Enable support for the Freescale Elo and Elo Plus DMA controllers. |
| 116 | The Elo is the DMA controller on some 82xx and 83xx parts, and the |
| 117 | Elo Plus is the DMA controller on 85xx and 86xx parts. |
Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 118 | |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 119 | config MPC512X_DMA |
| 120 | tristate "Freescale MPC512x built-in DMA engine support" |
Ilya Yanok | ba2eea2 | 2010-10-27 01:52:57 +0200 | [diff] [blame] | 121 | depends on PPC_MPC512x || PPC_MPC831x |
Piotr Ziecik | 0fb6f73 | 2010-02-05 03:42:52 +0000 | [diff] [blame] | 122 | select DMA_ENGINE |
| 123 | ---help--- |
| 124 | Enable support for the Freescale MPC512x built-in DMA engine. |
| 125 | |
Philippe De Muyter | 9a32299 | 2012-10-12 17:52:45 +0200 | [diff] [blame] | 126 | source "drivers/dma/bestcomm/Kconfig" |
| 127 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 128 | config MV_XOR |
| 129 | bool "Marvell XOR engine support" |
| 130 | depends on PLAT_ORION |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 131 | select DMA_ENGINE |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 132 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 133 | ---help--- |
| 134 | Enable support for the Marvell XOR engine. |
| 135 | |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 136 | config MX3_IPU |
| 137 | bool "MX3x Image Processing Unit support" |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 138 | depends on ARCH_MXC |
Guennadi Liakhovetski | 5296b56 | 2009-01-19 15:36:21 -0700 | [diff] [blame] | 139 | select DMA_ENGINE |
| 140 | default y |
| 141 | help |
| 142 | If you plan to use the Image Processing unit in the i.MX3x, say |
| 143 | Y here. If unsure, select Y. |
| 144 | |
| 145 | config MX3_IPU_IRQS |
| 146 | int "Number of dynamically mapped interrupts for IPU" |
| 147 | depends on MX3_IPU |
| 148 | range 2 137 |
| 149 | default 4 |
| 150 | help |
| 151 | Out of 137 interrupt sources on i.MX31 IPU only very few are used. |
| 152 | To avoid bloating the irq_desc[] array we allocate a sufficient |
| 153 | number of IRQ slots and map them dynamically to specific sources. |
| 154 | |
Atsushi Nemoto | ea76f0b | 2009-04-23 00:40:30 +0900 | [diff] [blame] | 155 | config TXX9_DMAC |
| 156 | tristate "Toshiba TXx9 SoC DMA support" |
| 157 | depends on MACH_TX49XX || MACH_TX39XX |
| 158 | select DMA_ENGINE |
| 159 | help |
| 160 | Support the TXx9 SoC internal DMA controller. This can be |
| 161 | integrated in chips such as the Toshiba TX4927/38/39. |
| 162 | |
Laxman Dewangan | ec8a158 | 2012-06-06 10:55:27 +0530 | [diff] [blame] | 163 | config TEGRA20_APB_DMA |
| 164 | bool "NVIDIA Tegra20 APB DMA support" |
| 165 | depends on ARCH_TEGRA |
| 166 | select DMA_ENGINE |
| 167 | help |
| 168 | Support for the NVIDIA Tegra20 APB DMA controller driver. The |
| 169 | DMA controller is having multiple DMA channel which can be |
| 170 | configured for different peripherals like audio, UART, SPI, |
| 171 | I2C etc which is in APB bus. |
| 172 | This DMA controller transfers data from memory to peripheral fifo |
| 173 | or vice versa. It does not support memory to memory data transfer. |
| 174 | |
Shimoda, Yoshihiro | 189b4ee | 2013-04-23 20:00:06 +0900 | [diff] [blame^] | 175 | source "drivers/dma/sh/Kconfig" |
Nobuhiro Iwamatsu | d8902ad | 2009-09-07 03:26:23 +0000 | [diff] [blame] | 176 | |
Linus Walleij | 61f135b | 2009-11-19 19:49:17 +0100 | [diff] [blame] | 177 | config COH901318 |
| 178 | bool "ST-Ericsson COH901318 DMA support" |
| 179 | select DMA_ENGINE |
| 180 | depends on ARCH_U300 |
| 181 | help |
| 182 | Enable support for ST-Ericsson COH 901 318 DMA. |
| 183 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 184 | config STE_DMA40 |
| 185 | bool "ST-Ericsson DMA40 support" |
| 186 | depends on ARCH_U8500 |
| 187 | select DMA_ENGINE |
| 188 | help |
| 189 | Support for ST-Ericsson DMA40 controller |
| 190 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 191 | config AMCC_PPC440SPE_ADMA |
| 192 | tristate "AMCC PPC440SPe ADMA support" |
| 193 | depends on 440SPe || 440SP |
| 194 | select DMA_ENGINE |
| 195 | select ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
Dan Williams | 5fc6d89 | 2010-10-07 16:44:50 -0700 | [diff] [blame] | 196 | select ASYNC_TX_ENABLE_CHANNEL_SWITCH |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 197 | help |
| 198 | Enable support for the AMCC PPC440SPe RAID engines. |
| 199 | |
Richard Röjfors | de5d445 | 2010-03-25 19:44:21 +0100 | [diff] [blame] | 200 | config TIMB_DMA |
| 201 | tristate "Timberdale FPGA DMA support" |
| 202 | depends on MFD_TIMBERDALE || HAS_IOMEM |
| 203 | select DMA_ENGINE |
| 204 | help |
| 205 | Enable support for the Timberdale FPGA DMA engine. |
| 206 | |
Rongjun Ying | ca21a14 | 2011-10-27 19:22:39 -0700 | [diff] [blame] | 207 | config SIRF_DMA |
Barry Song | f7d935d | 2012-11-01 22:54:43 +0800 | [diff] [blame] | 208 | tristate "CSR SiRFprimaII/SiRFmarco DMA support" |
| 209 | depends on ARCH_SIRF |
Rongjun Ying | ca21a14 | 2011-10-27 19:22:39 -0700 | [diff] [blame] | 210 | select DMA_ENGINE |
| 211 | help |
| 212 | Enable support for the CSR SiRFprimaII DMA engine. |
| 213 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 214 | config TI_EDMA |
| 215 | tristate "TI EDMA support" |
| 216 | depends on ARCH_DAVINCI |
| 217 | select DMA_ENGINE |
| 218 | select DMA_VIRTUAL_CHANNELS |
| 219 | default n |
| 220 | help |
| 221 | Enable support for the TI EDMA controller. This DMA |
| 222 | engine is found on TI DaVinci and AM33xx parts. |
| 223 | |
Anatolij Gustschin | 12458ea | 2009-12-11 21:24:44 -0700 | [diff] [blame] | 224 | config ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
| 225 | bool |
| 226 | |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 227 | config PL330_DMA |
| 228 | tristate "DMA API Driver for PL330" |
| 229 | select DMA_ENGINE |
Boojin Kim | 1b9bb71 | 2011-09-02 09:44:30 +0900 | [diff] [blame] | 230 | depends on ARM_AMBA |
Jassi Brar | b3040e4 | 2010-05-23 20:28:19 -0700 | [diff] [blame] | 231 | help |
| 232 | Select if your platform has one or more PL330 DMACs. |
| 233 | You need to provide platform specific settings via |
| 234 | platform_data for a dma-pl330 device. |
| 235 | |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 236 | config PCH_DMA |
Tomoya MORINAGA | ca7fe2d | 2011-11-17 16:14:23 +0900 | [diff] [blame] | 237 | tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA" |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 238 | depends on PCI && X86 |
| 239 | select DMA_ENGINE |
| 240 | help |
Tomoya MORINAGA | 2cdf245 | 2011-01-05 17:43:52 +0900 | [diff] [blame] | 241 | Enable support for Intel EG20T PCH DMA engine. |
| 242 | |
Tomoya MORINAGA | e79e72b | 2011-11-17 16:14:22 +0900 | [diff] [blame] | 243 | This driver also can be used for LAPIS Semiconductor IOH(Input/ |
Tomoya MORINAGA | ca7fe2d | 2011-11-17 16:14:23 +0900 | [diff] [blame] | 244 | Output Hub), ML7213, ML7223 and ML7831. |
| 245 | ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is |
| 246 | for MP(Media Phone) use and ML7831 IOH is for general purpose use. |
| 247 | ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. |
| 248 | ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. |
Yong Wang | 0c42bd0 | 2010-07-30 16:23:03 +0800 | [diff] [blame] | 249 | |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 250 | config IMX_SDMA |
| 251 | tristate "i.MX SDMA support" |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 252 | depends on ARCH_MXC |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 253 | select DMA_ENGINE |
| 254 | help |
| 255 | Support the i.MX SDMA engine. This engine is integrated into |
Sascha Hauer | 8e2d41f | 2011-08-24 08:41:09 +0200 | [diff] [blame] | 256 | Freescale i.MX25/31/35/51/53 chips. |
Sascha Hauer | 1ec1e82 | 2010-09-30 13:56:34 +0000 | [diff] [blame] | 257 | |
Sascha Hauer | 1f1846c | 2010-10-06 10:25:55 +0200 | [diff] [blame] | 258 | config IMX_DMA |
| 259 | tristate "i.MX DMA support" |
Vinod Koul | 5b2e02e | 2012-03-27 13:53:00 +0530 | [diff] [blame] | 260 | depends on ARCH_MXC |
Sascha Hauer | 1f1846c | 2010-10-06 10:25:55 +0200 | [diff] [blame] | 261 | select DMA_ENGINE |
| 262 | help |
| 263 | Support the i.MX DMA engine. This engine is integrated into |
| 264 | Freescale i.MX1/21/27 chips. |
| 265 | |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 266 | config MXS_DMA |
| 267 | bool "MXS DMA support" |
Huang Shijie | f5c5584 | 2012-06-06 21:22:59 -0400 | [diff] [blame] | 268 | depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q |
Dong Aisheng | f5b7efc | 2012-05-04 20:12:15 +0800 | [diff] [blame] | 269 | select STMP_DEVICE |
Shawn Guo | a580b8c | 2011-02-27 00:47:42 +0800 | [diff] [blame] | 270 | select DMA_ENGINE |
| 271 | help |
| 272 | Support the MXS DMA engine. This engine including APBH-DMA |
| 273 | and APBX-DMA is integrated into Freescale i.MX23/28 chips. |
| 274 | |
Mika Westerberg | 760ee1c | 2011-05-29 13:10:02 +0300 | [diff] [blame] | 275 | config EP93XX_DMA |
| 276 | bool "Cirrus Logic EP93xx DMA support" |
| 277 | depends on ARCH_EP93XX |
| 278 | select DMA_ENGINE |
| 279 | help |
| 280 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. |
| 281 | |
Russell King | 6365bea | 2012-01-09 21:44:07 +0000 | [diff] [blame] | 282 | config DMA_SA11X0 |
| 283 | tristate "SA-11x0 DMA support" |
| 284 | depends on ARCH_SA1100 |
| 285 | select DMA_ENGINE |
Russell King | 50437bf | 2012-04-13 12:07:23 +0100 | [diff] [blame] | 286 | select DMA_VIRTUAL_CHANNELS |
Russell King | 6365bea | 2012-01-09 21:44:07 +0000 | [diff] [blame] | 287 | help |
| 288 | Support the DMA engine found on Intel StrongARM SA-1100 and |
| 289 | SA-1110 SoCs. This DMA engine can only be used with on-chip |
| 290 | devices. |
| 291 | |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame] | 292 | config MMP_TDMA |
| 293 | bool "MMP Two-Channel DMA support" |
Vinod Koul | 49d57b5 | 2012-06-22 10:29:53 +0530 | [diff] [blame] | 294 | depends on ARCH_MMP |
Zhangfei Gao | c6da0ba | 2012-06-15 11:04:08 +0800 | [diff] [blame] | 295 | select DMA_ENGINE |
| 296 | help |
| 297 | Support the MMP Two-Channel DMA engine. |
| 298 | This engine used for MMP Audio DMA and pxa910 SQU. |
| 299 | |
| 300 | Say Y here if you enabled MMP ADMA, otherwise say N. |
| 301 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 302 | config DMA_OMAP |
| 303 | tristate "OMAP DMA support" |
| 304 | depends on ARCH_OMAP |
| 305 | select DMA_ENGINE |
| 306 | select DMA_VIRTUAL_CHANNELS |
| 307 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 308 | config MMP_PDMA |
| 309 | bool "MMP PDMA support" |
| 310 | depends on (ARCH_MMP || ARCH_PXA) |
| 311 | select DMA_ENGINE |
| 312 | help |
| 313 | Support the MMP PDMA engine for PXA and MMP platfrom. |
| 314 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 315 | config DMA_ENGINE |
| 316 | bool |
| 317 | |
Russell King | 50437bf | 2012-04-13 12:07:23 +0100 | [diff] [blame] | 318 | config DMA_VIRTUAL_CHANNELS |
| 319 | tristate |
| 320 | |
Andy Shevchenko | 1b2e98b | 2013-04-09 14:05:43 +0300 | [diff] [blame] | 321 | config DMA_ACPI |
| 322 | def_bool y |
| 323 | depends on ACPI |
| 324 | |
Vinod Koul | 5fa422c | 2013-02-12 09:15:02 -0800 | [diff] [blame] | 325 | config DMA_OF |
| 326 | def_bool y |
| 327 | depends on OF |
| 328 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 329 | comment "DMA Clients" |
| 330 | depends on DMA_ENGINE |
| 331 | |
| 332 | config NET_DMA |
| 333 | bool "Network: TCP receive copy offload" |
| 334 | depends on DMA_ENGINE && NET |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 335 | default (INTEL_IOATDMA || FSL_DMA) |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 336 | help |
| 337 | This enables the use of DMA engines in the network stack to |
| 338 | offload receive copy-to-user operations, freeing CPU cycles. |
Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 339 | |
| 340 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise |
| 341 | say N. |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 342 | |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 343 | config ASYNC_TX_DMA |
| 344 | bool "Async_tx: Offload support for the async_tx api" |
Dan Williams | 9a8de63 | 2009-09-08 15:06:10 -0700 | [diff] [blame] | 345 | depends on DMA_ENGINE |
Dan Williams | 729b5d1 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 346 | help |
| 347 | This allows the async_tx api to take advantage of offload engines for |
| 348 | memcpy, memset, xor, and raid6 p+q operations. If your platform has |
| 349 | a dma engine that can perform raid operations and you have enabled |
| 350 | MD_RAID456 say Y. |
| 351 | |
| 352 | If unsure, say N. |
| 353 | |
Haavard Skinnemoen | 4a776f0 | 2008-07-08 11:58:45 -0700 | [diff] [blame] | 354 | config DMATEST |
| 355 | tristate "DMA Test client" |
| 356 | depends on DMA_ENGINE |
| 357 | help |
| 358 | Simple DMA test client. Say N unless you're debugging a |
| 359 | DMA Device driver. |
| 360 | |
Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 361 | endif |