Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Driver for DBRI sound chip found on Sparcs. |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 3 | * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 4 | * |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 5 | * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl) |
| 6 | * |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 7 | * Based entirely upon drivers/sbus/audio/dbri.c which is: |
| 8 | * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) |
| 9 | * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) |
| 10 | * |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 11 | * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO |
| 12 | * on Sun SPARCStation 10, 20, LX and Voyager models. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 13 | * |
| 14 | * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel |
| 15 | * data time multiplexer with ISDN support (aka T7259) |
| 16 | * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. |
| 17 | * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). |
| 18 | * Documentation: |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 19 | * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 20 | * Sparc Technology Business (courtesy of Sun Support) |
| 21 | * - Data sheet of the T7903, a newer but very similar ISA bus equivalent |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 22 | * available from the Lucent (formerly AT&T microelectronics) home |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 23 | * page. |
| 24 | * - http://www.freesoft.org/Linux/DBRI/ |
| 25 | * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec |
| 26 | * Interfaces: CHI, Audio In & Out, 2 bits parallel |
| 27 | * Documentation: from the Crystal Semiconductor home page. |
| 28 | * |
| 29 | * The DBRI is a 32 pipe machine, each pipe can transfer some bits between |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 30 | * memory and a serial device (long pipes, no. 0-15) or between two serial |
| 31 | * devices (short pipes, no. 16-31), or simply send a fixed data to a serial |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 32 | * device (short pipes). |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 33 | * A timeslot defines the bit-offset and no. of bits read from a serial device. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 34 | * The timeslots are linked to 6 circular lists, one for each direction for |
| 35 | * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes |
| 36 | * (the second one is a monitor/tee pipe, valid only for serial input). |
| 37 | * |
| 38 | * The mmcodec is connected via the CHI bus and needs the data & some |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 39 | * parameters (volume, output selection) time multiplexed in 8 byte |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 40 | * chunks. It also has a control mode, which serves for audio format setting. |
| 41 | * |
| 42 | * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 43 | * the same CHI bus, so I thought perhaps it is possible to use the on-board |
| 44 | * & the speakerbox codec simultaneously, giving 2 (not very independent :-) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 45 | * audio devices. But the SUN HW group decided against it, at least on my |
| 46 | * LX the speakerbox connector has at least 1 pin missing and 1 wrongly |
| 47 | * connected. |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 48 | * |
| 49 | * I've tried to stick to the following function naming conventions: |
| 50 | * snd_* ALSA stuff |
Adrian Bunk | d254c8f | 2006-06-30 18:29:51 +0200 | [diff] [blame] | 51 | * cs4215_* CS4215 codec specific stuff |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 52 | * dbri_* DBRI high-level stuff |
| 53 | * other DBRI low-level stuff |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 54 | */ |
| 55 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 56 | #include <linux/interrupt.h> |
| 57 | #include <linux/delay.h> |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 58 | #include <linux/irq.h> |
| 59 | #include <linux/io.h> |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 60 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 61 | #include <linux/gfp.h> |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 62 | |
| 63 | #include <sound/core.h> |
| 64 | #include <sound/pcm.h> |
| 65 | #include <sound/pcm_params.h> |
| 66 | #include <sound/info.h> |
| 67 | #include <sound/control.h> |
| 68 | #include <sound/initval.h> |
| 69 | |
Krzysztof Helt | ef285fe | 2007-09-06 15:02:33 +0200 | [diff] [blame] | 70 | #include <linux/of.h> |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 71 | #include <linux/of_device.h> |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 72 | #include <asm/atomic.h> |
| 73 | |
| 74 | MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); |
| 75 | MODULE_DESCRIPTION("Sun DBRI"); |
| 76 | MODULE_LICENSE("GPL"); |
| 77 | MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}"); |
| 78 | |
| 79 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
| 80 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 81 | /* Enable this card */ |
| 82 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 83 | |
| 84 | module_param_array(index, int, NULL, 0444); |
| 85 | MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); |
| 86 | module_param_array(id, charp, NULL, 0444); |
| 87 | MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); |
| 88 | module_param_array(enable, bool, NULL, 0444); |
| 89 | MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); |
| 90 | |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 91 | #undef DBRI_DEBUG |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 92 | |
| 93 | #define D_INT (1<<0) |
| 94 | #define D_GEN (1<<1) |
| 95 | #define D_CMD (1<<2) |
| 96 | #define D_MM (1<<3) |
| 97 | #define D_USR (1<<4) |
| 98 | #define D_DESC (1<<5) |
| 99 | |
Takashi Iwai | 6581f4e | 2006-05-17 17:14:51 +0200 | [diff] [blame] | 100 | static int dbri_debug; |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 101 | module_param(dbri_debug, int, 0644); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 102 | MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); |
| 103 | |
| 104 | #ifdef DBRI_DEBUG |
| 105 | static char *cmds[] = { |
| 106 | "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", |
| 107 | "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" |
| 108 | }; |
| 109 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 110 | #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 111 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 112 | #else |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 113 | #define dprintk(a, x...) do { } while (0) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 114 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 115 | #endif /* DBRI_DEBUG */ |
| 116 | |
Krzysztof Helt | 42fe764 | 2006-08-16 12:53:34 +0200 | [diff] [blame] | 117 | #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ |
| 118 | (intr << 27) | \ |
| 119 | value) |
| 120 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 121 | /*************************************************************************** |
| 122 | CS4215 specific definitions and structures |
| 123 | ****************************************************************************/ |
| 124 | |
| 125 | struct cs4215 { |
| 126 | __u8 data[4]; /* Data mode: Time slots 5-8 */ |
| 127 | __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ |
| 128 | __u8 onboard; |
| 129 | __u8 offset; /* Bit offset from frame sync to time slot 1 */ |
| 130 | volatile __u32 status; |
| 131 | volatile __u32 version; |
| 132 | __u8 precision; /* In bits, either 8 or 16 */ |
| 133 | __u8 channels; /* 1 or 2 */ |
| 134 | }; |
| 135 | |
| 136 | /* |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 137 | * Control mode first |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 138 | */ |
| 139 | |
| 140 | /* Time Slot 1, Status register */ |
| 141 | #define CS4215_CLB (1<<2) /* Control Latch Bit */ |
| 142 | #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ |
| 143 | /* 0: line: 2.8V, speaker 8V */ |
| 144 | #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ |
| 145 | #define CS4215_RSRVD_1 (1<<5) |
| 146 | |
| 147 | /* Time Slot 2, Data Format Register */ |
| 148 | #define CS4215_DFR_LINEAR16 0 |
| 149 | #define CS4215_DFR_ULAW 1 |
| 150 | #define CS4215_DFR_ALAW 2 |
| 151 | #define CS4215_DFR_LINEAR8 3 |
| 152 | #define CS4215_DFR_STEREO (1<<2) |
| 153 | static struct { |
| 154 | unsigned short freq; |
| 155 | unsigned char xtal; |
| 156 | unsigned char csval; |
| 157 | } CS4215_FREQ[] = { |
| 158 | { 8000, (1 << 4), (0 << 3) }, |
| 159 | { 16000, (1 << 4), (1 << 3) }, |
| 160 | { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ |
| 161 | { 32000, (1 << 4), (3 << 3) }, |
| 162 | /* { NA, (1 << 4), (4 << 3) }, */ |
| 163 | /* { NA, (1 << 4), (5 << 3) }, */ |
| 164 | { 48000, (1 << 4), (6 << 3) }, |
| 165 | { 9600, (1 << 4), (7 << 3) }, |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 166 | { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 167 | { 11025, (2 << 4), (1 << 3) }, |
| 168 | { 18900, (2 << 4), (2 << 3) }, |
| 169 | { 22050, (2 << 4), (3 << 3) }, |
| 170 | { 37800, (2 << 4), (4 << 3) }, |
| 171 | { 44100, (2 << 4), (5 << 3) }, |
| 172 | { 33075, (2 << 4), (6 << 3) }, |
| 173 | { 6615, (2 << 4), (7 << 3) }, |
| 174 | { 0, 0, 0} |
| 175 | }; |
| 176 | |
| 177 | #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ |
| 178 | |
| 179 | #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ |
| 180 | |
| 181 | /* Time Slot 3, Serial Port Control register */ |
| 182 | #define CS4215_XEN (1<<0) /* 0: Enable serial output */ |
| 183 | #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ |
| 184 | #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ |
| 185 | #define CS4215_BSEL_128 (1<<2) |
| 186 | #define CS4215_BSEL_256 (2<<2) |
| 187 | #define CS4215_MCK_MAST (0<<4) /* Master clock */ |
| 188 | #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ |
| 189 | #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ |
| 190 | #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ |
| 191 | #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ |
| 192 | |
| 193 | /* Time Slot 4, Test Register */ |
| 194 | #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ |
| 195 | #define CS4215_ENL (1<<1) /* Enable Loopback Testing */ |
| 196 | |
| 197 | /* Time Slot 5, Parallel Port Register */ |
| 198 | /* Read only here and the same as the in data mode */ |
| 199 | |
| 200 | /* Time Slot 6, Reserved */ |
| 201 | |
| 202 | /* Time Slot 7, Version Register */ |
| 203 | #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ |
| 204 | |
| 205 | /* Time Slot 8, Reserved */ |
| 206 | |
| 207 | /* |
| 208 | * Data mode |
| 209 | */ |
| 210 | /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ |
| 211 | |
| 212 | /* Time Slot 5, Output Setting */ |
| 213 | #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ |
| 214 | #define CS4215_LE (1<<6) /* Line Out Enable */ |
| 215 | #define CS4215_HE (1<<7) /* Headphone Enable */ |
| 216 | |
| 217 | /* Time Slot 6, Output Setting */ |
| 218 | #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ |
| 219 | #define CS4215_SE (1<<6) /* Speaker Enable */ |
| 220 | #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ |
| 221 | |
| 222 | /* Time Slot 7, Input Setting */ |
| 223 | #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ |
| 224 | #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 225 | #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 226 | #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ |
| 227 | #define CS4215_PIO1 (1<<7) |
| 228 | |
| 229 | /* Time Slot 8, Input Setting */ |
| 230 | #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ |
| 231 | #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ |
| 232 | |
| 233 | /*************************************************************************** |
| 234 | DBRI specific definitions and structures |
| 235 | ****************************************************************************/ |
| 236 | |
| 237 | /* DBRI main registers */ |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 238 | #define REG0 0x00 /* Status and Control */ |
| 239 | #define REG1 0x04 /* Mode and Interrupt */ |
| 240 | #define REG2 0x08 /* Parallel IO */ |
| 241 | #define REG3 0x0c /* Test */ |
| 242 | #define REG8 0x20 /* Command Queue Pointer */ |
| 243 | #define REG9 0x24 /* Interrupt Queue Pointer */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 244 | |
| 245 | #define DBRI_NO_CMDS 64 |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 246 | #define DBRI_INT_BLK 64 |
| 247 | #define DBRI_NO_DESCS 64 |
| 248 | #define DBRI_NO_PIPES 32 |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 249 | #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 250 | |
| 251 | #define DBRI_REC 0 |
| 252 | #define DBRI_PLAY 1 |
| 253 | #define DBRI_NO_STREAMS 2 |
| 254 | |
| 255 | /* One transmit/receive descriptor */ |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 256 | /* When ba != 0 descriptor is used */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 257 | struct dbri_mem { |
| 258 | volatile __u32 word1; |
Krzysztof Helt | 16727d9 | 2006-08-17 16:59:28 +0200 | [diff] [blame] | 259 | __u32 ba; /* Transmit/Receive Buffer Address */ |
| 260 | __u32 nda; /* Next Descriptor Address */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 261 | volatile __u32 word4; |
| 262 | }; |
| 263 | |
| 264 | /* This structure is in a DMA region where it can accessed by both |
| 265 | * the CPU and the DBRI |
| 266 | */ |
| 267 | struct dbri_dma { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 268 | s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ |
Krzysztof Helt | 6fb9828 | 2006-08-16 12:54:29 +0200 | [diff] [blame] | 269 | volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 270 | struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ |
| 271 | }; |
| 272 | |
| 273 | #define dbri_dma_off(member, elem) \ |
| 274 | ((u32)(unsigned long) \ |
| 275 | (&(((struct dbri_dma *)0)->member[elem]))) |
| 276 | |
| 277 | enum in_or_out { PIPEinput, PIPEoutput }; |
| 278 | |
| 279 | struct dbri_pipe { |
| 280 | u32 sdp; /* SDP command word */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 281 | int nextpipe; /* Next pipe in linked list */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 282 | int length; /* Length of timeslot (bits) */ |
| 283 | int first_desc; /* Index of first descriptor */ |
| 284 | int desc; /* Index of active descriptor */ |
| 285 | volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ |
| 286 | }; |
| 287 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 288 | /* Per stream (playback or record) information */ |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 289 | struct dbri_streaminfo { |
| 290 | struct snd_pcm_substream *substream; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 291 | u32 dvma_buffer; /* Device view of ALSA DMA buffer */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 292 | int size; /* Size of DMA buffer */ |
| 293 | size_t offset; /* offset in user buffer */ |
| 294 | int pipe; /* Data pipe used */ |
| 295 | int left_gain; /* mixer elements */ |
| 296 | int right_gain; |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 297 | }; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 298 | |
| 299 | /* This structure holds the information for both chips (DBRI & CS4215) */ |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 300 | struct snd_dbri { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 301 | int regs_size, irq; /* Needed for unload */ |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 302 | struct of_device *op; /* OF device info */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 303 | spinlock_t lock; |
| 304 | |
Krzysztof Helt | 16727d9 | 2006-08-17 16:59:28 +0200 | [diff] [blame] | 305 | struct dbri_dma *dma; /* Pointer to our DMA block */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 306 | u32 dma_dvma; /* DBRI visible DMA address */ |
| 307 | |
| 308 | void __iomem *regs; /* dbri HW regs */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 309 | int dbri_irqp; /* intr queue pointer */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 310 | |
| 311 | struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 312 | int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 313 | spinlock_t cmdlock; /* Protects cmd queue accesses */ |
| 314 | s32 *cmdptr; /* Pointer to the last queued cmd */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 315 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 316 | int chi_bpf; |
| 317 | |
| 318 | struct cs4215 mm; /* mmcodec special info */ |
| 319 | /* per stream (playback/record) info */ |
| 320 | struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 321 | }; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 322 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 323 | #define DBRI_MAX_VOLUME 63 /* Output volume */ |
| 324 | #define DBRI_MAX_GAIN 15 /* Input gain */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 325 | |
| 326 | /* DBRI Reg0 - Status Control Register - defines. (Page 17) */ |
| 327 | #define D_P (1<<15) /* Program command & queue pointer valid */ |
| 328 | #define D_G (1<<14) /* Allow 4-Word SBus Burst */ |
| 329 | #define D_S (1<<13) /* Allow 16-Word SBus Burst */ |
| 330 | #define D_E (1<<12) /* Allow 8-Word SBus Burst */ |
| 331 | #define D_X (1<<7) /* Sanity Timer Disable */ |
| 332 | #define D_T (1<<6) /* Permit activation of the TE interface */ |
| 333 | #define D_N (1<<5) /* Permit activation of the NT interface */ |
| 334 | #define D_C (1<<4) /* Permit activation of the CHI interface */ |
| 335 | #define D_F (1<<3) /* Force Sanity Timer Time-Out */ |
| 336 | #define D_D (1<<2) /* Disable Master Mode */ |
| 337 | #define D_H (1<<1) /* Halt for Analysis */ |
| 338 | #define D_R (1<<0) /* Soft Reset */ |
| 339 | |
| 340 | /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ |
| 341 | #define D_LITTLE_END (1<<8) /* Byte Order */ |
| 342 | #define D_BIG_END (0<<8) /* Byte Order */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 343 | #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */ |
| 344 | #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */ |
| 345 | #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */ |
| 346 | #define D_MBE (1<<1) /* Burst Error on SBus (read only) */ |
| 347 | #define D_IR (1<<0) /* Interrupt Indicator (read only) */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 348 | |
| 349 | /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ |
| 350 | #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ |
| 351 | #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ |
| 352 | #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ |
| 353 | #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ |
| 354 | #define D_ENPIO (0xf0) /* Enable all the pins */ |
| 355 | #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ |
| 356 | #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ |
| 357 | #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ |
| 358 | #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ |
| 359 | |
| 360 | /* DBRI Commands (Page 20) */ |
| 361 | #define D_WAIT 0x0 /* Stop execution */ |
| 362 | #define D_PAUSE 0x1 /* Flush long pipes */ |
| 363 | #define D_JUMP 0x2 /* New command queue */ |
| 364 | #define D_IIQ 0x3 /* Initialize Interrupt Queue */ |
| 365 | #define D_REX 0x4 /* Report command execution via interrupt */ |
| 366 | #define D_SDP 0x5 /* Setup Data Pipe */ |
| 367 | #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ |
| 368 | #define D_DTS 0x7 /* Define Time Slot */ |
| 369 | #define D_SSP 0x8 /* Set short Data Pipe */ |
| 370 | #define D_CHI 0x9 /* Set CHI Global Mode */ |
| 371 | #define D_NT 0xa /* NT Command */ |
| 372 | #define D_TE 0xb /* TE Command */ |
| 373 | #define D_CDEC 0xc /* Codec setup */ |
| 374 | #define D_TEST 0xd /* No comment */ |
| 375 | #define D_CDM 0xe /* CHI Data mode command */ |
| 376 | |
| 377 | /* Special bits for some commands */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 378 | #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 379 | |
| 380 | /* Setup Data Pipe */ |
| 381 | /* IRM */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 382 | #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 383 | #define D_SDP_CHANGE (2<<18) /* Report any changes */ |
| 384 | #define D_SDP_EVERY (3<<18) /* Report any changes */ |
| 385 | #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ |
| 386 | #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ |
| 387 | |
| 388 | /* Pipe data MODE */ |
| 389 | #define D_SDP_MEM (0<<13) /* To/from memory */ |
| 390 | #define D_SDP_HDLC (2<<13) |
| 391 | #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ |
| 392 | #define D_SDP_SER (4<<13) /* Serial to serial */ |
| 393 | #define D_SDP_FIXED (6<<13) /* Short only */ |
| 394 | #define D_SDP_MODE(v) ((v)&(7<<13)) |
| 395 | |
| 396 | #define D_SDP_TO_SER (1<<12) /* Direction */ |
| 397 | #define D_SDP_FROM_SER (0<<12) /* Direction */ |
| 398 | #define D_SDP_MSB (1<<11) /* Bit order within Byte */ |
| 399 | #define D_SDP_LSB (0<<11) /* Bit order within Byte */ |
| 400 | #define D_SDP_P (1<<10) /* Pointer Valid */ |
| 401 | #define D_SDP_A (1<<8) /* Abort */ |
| 402 | #define D_SDP_C (1<<7) /* Clear */ |
| 403 | |
| 404 | /* Define Time Slot */ |
| 405 | #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ |
| 406 | #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ |
| 407 | #define D_DTS_INS (1<<15) /* Insert Time Slot */ |
| 408 | #define D_DTS_DEL (0<<15) /* Delete Time Slot */ |
| 409 | #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ |
| 410 | #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ |
| 411 | |
| 412 | /* Time Slot defines */ |
| 413 | #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ |
| 414 | #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ |
| 415 | #define D_TS_DI (1<<13) /* Data Invert */ |
| 416 | #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ |
| 417 | #define D_TS_MONITOR (2<<10) /* Monitor pipe */ |
| 418 | #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ |
| 419 | #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ |
| 420 | #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 421 | #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 422 | |
| 423 | /* Concentration Highway Interface Modes */ |
| 424 | #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ |
| 425 | #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ |
| 426 | #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ |
| 427 | #define D_CHI_OD (1<<13) /* Open Drain Enable */ |
| 428 | #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ |
| 429 | #define D_CHI_FD (1<<11) /* Frame Drive */ |
| 430 | #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ |
| 431 | |
| 432 | /* NT: These are here for completeness */ |
| 433 | #define D_NT_FBIT (1<<17) /* Frame Bit */ |
| 434 | #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ |
| 435 | #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ |
| 436 | #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 437 | #define D_NT_ISNT (1<<13) /* Configure interface as NT */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 438 | #define D_NT_FT (1<<12) /* Fixed Timing */ |
| 439 | #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ |
| 440 | #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ |
| 441 | #define D_NT_ACT (1<<9) /* Activate Interface */ |
| 442 | #define D_NT_MFE (1<<8) /* Multiframe Enable */ |
| 443 | #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ |
| 444 | #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ |
| 445 | #define D_NT_FACT (1<<1) /* Force Activation */ |
| 446 | #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ |
| 447 | |
| 448 | /* Codec Setup */ |
| 449 | #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ |
| 450 | #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ |
| 451 | #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ |
| 452 | |
| 453 | /* Test */ |
| 454 | #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ |
| 455 | #define D_TEST_SIZE(v) ((v)<<11) /* */ |
| 456 | #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 457 | #define D_TEST_PROC 0x6 /* Microprocessor test */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 458 | #define D_TEST_SER 0x7 /* Serial-Controller test */ |
| 459 | #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ |
| 460 | #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ |
| 461 | #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ |
| 462 | #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ |
| 463 | #define D_TEST_DUMP 0xe /* ROM Dump */ |
| 464 | |
| 465 | /* CHI Data Mode */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 466 | #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */ |
| 467 | #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */ |
| 468 | #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */ |
| 469 | #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */ |
| 470 | #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */ |
| 471 | #define D_CDM_REN (1 << 0) /* Receive Highway Enable */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 472 | |
| 473 | /* The Interrupts */ |
| 474 | #define D_INTR_BRDY 1 /* Buffer Ready for processing */ |
| 475 | #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ |
| 476 | #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ |
| 477 | #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ |
| 478 | #define D_INTR_EOL 5 /* End of List */ |
| 479 | #define D_INTR_CMDI 6 /* Command has bean read */ |
| 480 | #define D_INTR_XCMP 8 /* Transmission of frame complete */ |
| 481 | #define D_INTR_SBRI 9 /* BRI status change info */ |
| 482 | #define D_INTR_FXDT 10 /* Fixed data change */ |
| 483 | #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ |
| 484 | #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ |
| 485 | #define D_INTR_DBYT 12 /* Dropped by frame slip */ |
| 486 | #define D_INTR_RBYT 13 /* Repeated by frame slip */ |
| 487 | #define D_INTR_LINT 14 /* Lost Interrupt */ |
| 488 | #define D_INTR_UNDR 15 /* DMA underrun */ |
| 489 | |
| 490 | #define D_INTR_TE 32 |
| 491 | #define D_INTR_NT 34 |
| 492 | #define D_INTR_CHI 36 |
| 493 | #define D_INTR_CMD 38 |
| 494 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 495 | #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) |
| 496 | #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf) |
| 497 | #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 498 | #define D_INTR_GETVAL(v) ((v) & 0xffff) |
| 499 | #define D_INTR_GETRVAL(v) ((v) & 0xfffff) |
| 500 | |
| 501 | #define D_P_0 0 /* TE receive anchor */ |
| 502 | #define D_P_1 1 /* TE transmit anchor */ |
| 503 | #define D_P_2 2 /* NT transmit anchor */ |
| 504 | #define D_P_3 3 /* NT receive anchor */ |
| 505 | #define D_P_4 4 /* CHI send data */ |
| 506 | #define D_P_5 5 /* CHI receive data */ |
| 507 | #define D_P_6 6 /* */ |
| 508 | #define D_P_7 7 /* */ |
| 509 | #define D_P_8 8 /* */ |
| 510 | #define D_P_9 9 /* */ |
| 511 | #define D_P_10 10 /* */ |
| 512 | #define D_P_11 11 /* */ |
| 513 | #define D_P_12 12 /* */ |
| 514 | #define D_P_13 13 /* */ |
| 515 | #define D_P_14 14 /* */ |
| 516 | #define D_P_15 15 /* */ |
| 517 | #define D_P_16 16 /* CHI anchor pipe */ |
| 518 | #define D_P_17 17 /* CHI send */ |
| 519 | #define D_P_18 18 /* CHI receive */ |
| 520 | #define D_P_19 19 /* CHI receive */ |
| 521 | #define D_P_20 20 /* CHI receive */ |
| 522 | #define D_P_21 21 /* */ |
| 523 | #define D_P_22 22 /* */ |
| 524 | #define D_P_23 23 /* */ |
| 525 | #define D_P_24 24 /* */ |
| 526 | #define D_P_25 25 /* */ |
| 527 | #define D_P_26 26 /* */ |
| 528 | #define D_P_27 27 /* */ |
| 529 | #define D_P_28 28 /* */ |
| 530 | #define D_P_29 29 /* */ |
| 531 | #define D_P_30 30 /* */ |
| 532 | #define D_P_31 31 /* */ |
| 533 | |
| 534 | /* Transmit descriptor defines */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 535 | #define DBRI_TD_F (1 << 31) /* End of Frame */ |
| 536 | #define DBRI_TD_D (1 << 30) /* Do not append CRC */ |
| 537 | #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */ |
| 538 | #define DBRI_TD_B (1 << 15) /* Final interrupt */ |
| 539 | #define DBRI_TD_M (1 << 14) /* Marker interrupt */ |
| 540 | #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */ |
| 541 | #define DBRI_TD_FCNT(v) (v) /* Flag Count */ |
| 542 | #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */ |
| 543 | #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */ |
| 544 | #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */ |
| 545 | #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */ |
| 546 | /* Maximum buffer size per TD: almost 8KB */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 547 | #define DBRI_TD_MAXCNT ((1 << 13) - 4) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 548 | |
| 549 | /* Receive descriptor defines */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 550 | #define DBRI_RD_F (1 << 31) /* End of Frame */ |
| 551 | #define DBRI_RD_C (1 << 30) /* Completed buffer */ |
| 552 | #define DBRI_RD_B (1 << 15) /* Final interrupt */ |
| 553 | #define DBRI_RD_M (1 << 14) /* Marker interrupt */ |
| 554 | #define DBRI_RD_BCNT(v) (v) /* Buffer size */ |
| 555 | #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */ |
| 556 | #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */ |
| 557 | #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */ |
| 558 | #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */ |
| 559 | #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */ |
| 560 | #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 561 | |
| 562 | /* stream_info[] access */ |
| 563 | /* Translate the ALSA direction into the array index */ |
| 564 | #define DBRI_STREAMNO(substream) \ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 565 | (substream->stream == \ |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 566 | SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 567 | |
| 568 | /* Return a pointer to dbri_streaminfo */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 569 | #define DBRI_STREAM(dbri, substream) \ |
| 570 | &dbri->stream_info[DBRI_STREAMNO(substream)] |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 571 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 572 | /* |
| 573 | * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. |
| 574 | * So we have to reverse the bits. Note: not all bit lengths are supported |
| 575 | */ |
| 576 | static __u32 reverse_bytes(__u32 b, int len) |
| 577 | { |
| 578 | switch (len) { |
| 579 | case 32: |
| 580 | b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); |
| 581 | case 16: |
| 582 | b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); |
| 583 | case 8: |
| 584 | b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); |
| 585 | case 4: |
| 586 | b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); |
| 587 | case 2: |
| 588 | b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); |
| 589 | case 1: |
| 590 | case 0: |
| 591 | break; |
| 592 | default: |
| 593 | printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n"); |
| 594 | }; |
| 595 | |
| 596 | return b; |
| 597 | } |
| 598 | |
| 599 | /* |
| 600 | **************************************************************************** |
| 601 | ************** DBRI initialization and command synchronization ************* |
| 602 | **************************************************************************** |
| 603 | |
| 604 | Commands are sent to the DBRI by building a list of them in memory, |
| 605 | then writing the address of the first list item to DBRI register 8. |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 606 | The list is terminated with a WAIT command, which generates a |
| 607 | CPU interrupt to signal completion. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 608 | |
| 609 | Since the DBRI can run in parallel with the CPU, several means of |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 610 | synchronization present themselves. The method implemented here uses |
| 611 | the dbri_cmdwait() to wait for execution of batch of sent commands. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 612 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 613 | A circular command buffer is used here. A new command is being added |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 614 | while another can be executed. The scheme works by adding two WAIT commands |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 615 | after each sent batch of commands. When the next batch is prepared it is |
| 616 | added after the WAIT commands then the WAITs are replaced with single JUMP |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 617 | command to the new batch. The the DBRI is forced to reread the last WAIT |
| 618 | command (replaced by the JUMP by then). If the DBRI is still executing |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 619 | previous commands the request to reread the WAIT command is ignored. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 620 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 621 | Every time a routine wants to write commands to the DBRI, it must |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 622 | first call dbri_cmdlock() and get pointer to a free space in |
| 623 | dbri->dma->cmd buffer. After this, the commands can be written to |
| 624 | the buffer, and dbri_cmdsend() is called with the final pointer value |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 625 | to send them to the DBRI. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 626 | |
| 627 | */ |
| 628 | |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 629 | #define MAXLOOPS 20 |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 630 | /* |
| 631 | * Wait for the current command string to execute |
| 632 | */ |
| 633 | static void dbri_cmdwait(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 634 | { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 635 | int maxloops = MAXLOOPS; |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 636 | unsigned long flags; |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 637 | |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 638 | /* Delay if previous commands are still being processed */ |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 639 | spin_lock_irqsave(&dbri->lock, flags); |
| 640 | while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) { |
| 641 | spin_unlock_irqrestore(&dbri->lock, flags); |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 642 | msleep_interruptible(1); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 643 | spin_lock_irqsave(&dbri->lock, flags); |
| 644 | } |
| 645 | spin_unlock_irqrestore(&dbri->lock, flags); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 646 | |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 647 | if (maxloops == 0) |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 648 | printk(KERN_ERR "DBRI: Chip never completed command buffer\n"); |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 649 | else |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 650 | dprintk(D_CMD, "Chip completed command buffer (%d)\n", |
| 651 | MAXLOOPS - maxloops - 1); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 652 | } |
| 653 | /* |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 654 | * Lock the command queue and return pointer to space for len cmd words |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 655 | * It locks the cmdlock spinlock. |
| 656 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 657 | static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len) |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 658 | { |
| 659 | /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */ |
| 660 | len += 2; |
| 661 | spin_lock(&dbri->cmdlock); |
| 662 | if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2) |
| 663 | return dbri->cmdptr + 2; |
| 664 | else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma) |
| 665 | return dbri->dma->cmd; |
| 666 | else |
| 667 | printk(KERN_ERR "DBRI: no space for commands."); |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 668 | |
Al Viro | ae97dd9 | 2006-09-24 23:42:57 +0100 | [diff] [blame] | 669 | return NULL; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 670 | } |
| 671 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 672 | /* |
Robert P. J. Day | beb7dd8 | 2007-05-09 07:14:03 +0200 | [diff] [blame] | 673 | * Send prepared cmd string. It works by writing a JUMP cmd into |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 674 | * the last WAIT cmd and force DBRI to reread the cmd. |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 675 | * The JUMP cmd points to the new cmd string. |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 676 | * It also releases the cmdlock spinlock. |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 677 | * |
Krzysztof Helt | ca40587 | 2006-12-18 14:41:03 +0100 | [diff] [blame] | 678 | * Lock must be held before calling this. |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 679 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 680 | static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 681 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 682 | s32 tmp, addr; |
| 683 | static int wait_id = 0; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 684 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 685 | wait_id++; |
| 686 | wait_id &= 0xffff; /* restrict it to a 16 bit counter. */ |
| 687 | *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id); |
| 688 | *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id); |
| 689 | |
| 690 | /* Replace the last command with JUMP */ |
| 691 | addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32); |
| 692 | *(dbri->cmdptr+1) = addr; |
| 693 | *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0); |
| 694 | |
| 695 | #ifdef DBRI_DEBUG |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 696 | if (cmd > dbri->cmdptr) { |
| 697 | s32 *ptr; |
| 698 | |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 699 | for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++) |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 700 | dprintk(D_CMD, "cmd: %lx:%08x\n", |
| 701 | (unsigned long)ptr, *ptr); |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 702 | } else { |
| 703 | s32 *ptr = dbri->cmdptr; |
| 704 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 705 | dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 706 | ptr++; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 707 | dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 708 | for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) |
| 709 | dprintk(D_CMD, "cmd: %lx:%08x\n", |
| 710 | (unsigned long)ptr, *ptr); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 711 | } |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 712 | #endif |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 713 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 714 | /* Reread the last command */ |
| 715 | tmp = sbus_readl(dbri->regs + REG0); |
| 716 | tmp |= D_P; |
| 717 | sbus_writel(tmp, dbri->regs + REG0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 718 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 719 | dbri->cmdptr = cmd; |
| 720 | spin_unlock(&dbri->cmdlock); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | /* Lock must be held when calling this */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 724 | static void dbri_reset(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 725 | { |
| 726 | int i; |
Krzysztof Helt | d1fdf07 | 2006-08-21 19:29:18 +0200 | [diff] [blame] | 727 | u32 tmp; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 728 | |
| 729 | dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n", |
| 730 | sbus_readl(dbri->regs + REG0), |
| 731 | sbus_readl(dbri->regs + REG2), |
| 732 | sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); |
| 733 | |
| 734 | sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ |
| 735 | for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) |
| 736 | udelay(10); |
Krzysztof Helt | d1fdf07 | 2006-08-21 19:29:18 +0200 | [diff] [blame] | 737 | |
| 738 | /* A brute approach - DBRI falls back to working burst size by itself |
| 739 | * On SS20 D_S does not work, so do not try so high. */ |
| 740 | tmp = sbus_readl(dbri->regs + REG0); |
| 741 | tmp |= D_G | D_E; |
| 742 | tmp &= ~D_S; |
| 743 | sbus_writel(tmp, dbri->regs + REG0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 744 | } |
| 745 | |
| 746 | /* Lock must not be held before calling this */ |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 747 | static void __devinit dbri_initialize(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 748 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 749 | s32 *cmd; |
Krzysztof Helt | d1fdf07 | 2006-08-21 19:29:18 +0200 | [diff] [blame] | 750 | u32 dma_addr; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 751 | unsigned long flags; |
| 752 | int n; |
| 753 | |
| 754 | spin_lock_irqsave(&dbri->lock, flags); |
| 755 | |
| 756 | dbri_reset(dbri); |
| 757 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 758 | /* Initialize pipes */ |
| 759 | for (n = 0; n < DBRI_NO_PIPES; n++) |
| 760 | dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; |
| 761 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 762 | spin_lock_init(&dbri->cmdlock); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 763 | /* |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 764 | * Initialize the interrupt ring buffer. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 765 | */ |
| 766 | dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); |
Krzysztof Helt | 6fb9828 | 2006-08-16 12:54:29 +0200 | [diff] [blame] | 767 | dbri->dma->intr[0] = dma_addr; |
| 768 | dbri->dbri_irqp = 1; |
| 769 | /* |
| 770 | * Set up the interrupt queue |
| 771 | */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 772 | spin_lock(&dbri->cmdlock); |
| 773 | cmd = dbri->cmdptr = dbri->dma->cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 774 | *(cmd++) = DBRI_CMD(D_IIQ, 0, 0); |
| 775 | *(cmd++) = dma_addr; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 776 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
| 777 | dbri->cmdptr = cmd; |
| 778 | *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); |
| 779 | *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); |
| 780 | dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0); |
| 781 | sbus_writel(dma_addr, dbri->regs + REG8); |
| 782 | spin_unlock(&dbri->cmdlock); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 783 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 784 | spin_unlock_irqrestore(&dbri->lock, flags); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 785 | dbri_cmdwait(dbri); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 786 | } |
| 787 | |
| 788 | /* |
| 789 | **************************************************************************** |
| 790 | ************************** DBRI data pipe management *********************** |
| 791 | **************************************************************************** |
| 792 | |
| 793 | While DBRI control functions use the command and interrupt buffers, the |
| 794 | main data path takes the form of data pipes, which can be short (command |
| 795 | and interrupt driven), or long (attached to DMA buffers). These functions |
| 796 | provide a rudimentary means of setting up and managing the DBRI's pipes, |
| 797 | but the calling functions have to make sure they respect the pipes' linked |
| 798 | list ordering, among other things. The transmit and receive functions |
| 799 | here interface closely with the transmit and receive interrupt code. |
| 800 | |
| 801 | */ |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 802 | static inline int pipe_active(struct snd_dbri *dbri, int pipe) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 803 | { |
| 804 | return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); |
| 805 | } |
| 806 | |
| 807 | /* reset_pipe(dbri, pipe) |
| 808 | * |
| 809 | * Called on an in-use pipe to clear anything being transmitted or received |
| 810 | * Lock must be held before calling this. |
| 811 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 812 | static void reset_pipe(struct snd_dbri *dbri, int pipe) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 813 | { |
| 814 | int sdp; |
| 815 | int desc; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 816 | s32 *cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 817 | |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 818 | if (pipe < 0 || pipe > DBRI_MAX_PIPE) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 819 | printk(KERN_ERR "DBRI: reset_pipe called with " |
| 820 | "illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 821 | return; |
| 822 | } |
| 823 | |
| 824 | sdp = dbri->pipes[pipe].sdp; |
| 825 | if (sdp == 0) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 826 | printk(KERN_ERR "DBRI: reset_pipe called " |
| 827 | "on uninitialized pipe\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 828 | return; |
| 829 | } |
| 830 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 831 | cmd = dbri_cmdlock(dbri, 3); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 832 | *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); |
| 833 | *(cmd++) = 0; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 834 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
| 835 | dbri_cmdsend(dbri, cmd, 3); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 836 | |
| 837 | desc = dbri->pipes[pipe].first_desc; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 838 | if (desc >= 0) |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 839 | do { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 840 | dbri->dma->desc[desc].ba = 0; |
| 841 | dbri->dma->desc[desc].nda = 0; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 842 | desc = dbri->next_desc[desc]; |
| 843 | } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 844 | |
| 845 | dbri->pipes[pipe].desc = -1; |
| 846 | dbri->pipes[pipe].first_desc = -1; |
| 847 | } |
| 848 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 849 | /* |
| 850 | * Lock must be held before calling this. |
| 851 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 852 | static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 853 | { |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 854 | if (pipe < 0 || pipe > DBRI_MAX_PIPE) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 855 | printk(KERN_ERR "DBRI: setup_pipe called " |
| 856 | "with illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 857 | return; |
| 858 | } |
| 859 | |
| 860 | if ((sdp & 0xf800) != sdp) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 861 | printk(KERN_ERR "DBRI: setup_pipe called " |
| 862 | "with strange SDP value\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 863 | /* sdp &= 0xf800; */ |
| 864 | } |
| 865 | |
| 866 | /* If this is a fixed receive pipe, arrange for an interrupt |
| 867 | * every time its data changes |
| 868 | */ |
| 869 | if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) |
| 870 | sdp |= D_SDP_CHANGE; |
| 871 | |
| 872 | sdp |= D_PIPE(pipe); |
| 873 | dbri->pipes[pipe].sdp = sdp; |
| 874 | dbri->pipes[pipe].desc = -1; |
| 875 | dbri->pipes[pipe].first_desc = -1; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 876 | |
| 877 | reset_pipe(dbri, pipe); |
| 878 | } |
| 879 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 880 | /* |
| 881 | * Lock must be held before calling this. |
| 882 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 883 | static void link_time_slot(struct snd_dbri *dbri, int pipe, |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 884 | int prevpipe, int nextpipe, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 885 | int length, int cycle) |
| 886 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 887 | s32 *cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 888 | int val; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 889 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 890 | if (pipe < 0 || pipe > DBRI_MAX_PIPE |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 891 | || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE |
| 892 | || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 893 | printk(KERN_ERR |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 894 | "DBRI: link_time_slot called with illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 895 | return; |
| 896 | } |
| 897 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 898 | if (dbri->pipes[pipe].sdp == 0 |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 899 | || dbri->pipes[prevpipe].sdp == 0 |
| 900 | || dbri->pipes[nextpipe].sdp == 0) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 901 | printk(KERN_ERR "DBRI: link_time_slot called " |
| 902 | "on uninitialized pipe\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 903 | return; |
| 904 | } |
| 905 | |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 906 | dbri->pipes[prevpipe].nextpipe = pipe; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 907 | dbri->pipes[pipe].nextpipe = nextpipe; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 908 | dbri->pipes[pipe].length = length; |
| 909 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 910 | cmd = dbri_cmdlock(dbri, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 911 | |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 912 | if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { |
| 913 | /* Deal with CHI special case: |
| 914 | * "If transmission on edges 0 or 1 is desired, then cycle n |
| 915 | * (where n = # of bit times per frame...) must be used." |
| 916 | * - DBRI data sheet, page 11 |
| 917 | */ |
| 918 | if (prevpipe == 16 && cycle == 0) |
| 919 | cycle = dbri->chi_bpf; |
| 920 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 921 | val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; |
| 922 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 923 | *(cmd++) = 0; |
| 924 | *(cmd++) = |
| 925 | D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 926 | } else { |
| 927 | val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; |
| 928 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 929 | *(cmd++) = |
| 930 | D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); |
| 931 | *(cmd++) = 0; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 932 | } |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 933 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 934 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 935 | dbri_cmdsend(dbri, cmd, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 936 | } |
| 937 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 938 | #if 0 |
| 939 | /* |
| 940 | * Lock must be held before calling this. |
| 941 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 942 | static void unlink_time_slot(struct snd_dbri *dbri, int pipe, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 943 | enum in_or_out direction, int prevpipe, |
| 944 | int nextpipe) |
| 945 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 946 | s32 *cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 947 | int val; |
| 948 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 949 | if (pipe < 0 || pipe > DBRI_MAX_PIPE |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 950 | || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE |
| 951 | || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 952 | printk(KERN_ERR |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 953 | "DBRI: unlink_time_slot called with illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 954 | return; |
| 955 | } |
| 956 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 957 | cmd = dbri_cmdlock(dbri, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 958 | |
| 959 | if (direction == PIPEinput) { |
| 960 | val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; |
| 961 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 962 | *(cmd++) = D_TS_NEXT(nextpipe); |
| 963 | *(cmd++) = 0; |
| 964 | } else { |
| 965 | val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; |
| 966 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 967 | *(cmd++) = 0; |
| 968 | *(cmd++) = D_TS_NEXT(nextpipe); |
| 969 | } |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 970 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 971 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 972 | dbri_cmdsend(dbri, cmd, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 973 | } |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 974 | #endif |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 975 | |
| 976 | /* xmit_fixed() / recv_fixed() |
| 977 | * |
| 978 | * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not |
| 979 | * expected to change much, and which we don't need to buffer. |
| 980 | * The DBRI only interrupts us when the data changes (receive pipes), |
| 981 | * or only changes the data when this function is called (transmit pipes). |
| 982 | * Only short pipes (numbers 16-31) can be used in fixed data mode. |
| 983 | * |
| 984 | * These function operate on a 32-bit field, no matter how large |
| 985 | * the actual time slot is. The interrupt handler takes care of bit |
| 986 | * ordering and alignment. An 8-bit time slot will always end up |
| 987 | * in the low-order 8 bits, filled either MSB-first or LSB-first, |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 988 | * depending on the settings passed to setup_pipe(). |
| 989 | * |
| 990 | * Lock must not be held before calling it. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 991 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 992 | static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 993 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 994 | s32 *cmd; |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 995 | unsigned long flags; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 996 | |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 997 | if (pipe < 16 || pipe > DBRI_MAX_PIPE) { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 998 | printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 999 | return; |
| 1000 | } |
| 1001 | |
| 1002 | if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1003 | printk(KERN_ERR "DBRI: xmit_fixed: " |
| 1004 | "Uninitialized pipe %d\n", pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1005 | return; |
| 1006 | } |
| 1007 | |
| 1008 | if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1009 | printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1010 | return; |
| 1011 | } |
| 1012 | |
| 1013 | if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1014 | printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", |
| 1015 | pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1016 | return; |
| 1017 | } |
| 1018 | |
| 1019 | /* DBRI short pipes always transmit LSB first */ |
| 1020 | |
| 1021 | if (dbri->pipes[pipe].sdp & D_SDP_MSB) |
| 1022 | data = reverse_bytes(data, dbri->pipes[pipe].length); |
| 1023 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1024 | cmd = dbri_cmdlock(dbri, 3); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1025 | |
| 1026 | *(cmd++) = DBRI_CMD(D_SSP, 0, pipe); |
| 1027 | *(cmd++) = data; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1028 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1029 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1030 | spin_lock_irqsave(&dbri->lock, flags); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1031 | dbri_cmdsend(dbri, cmd, 3); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1032 | spin_unlock_irqrestore(&dbri->lock, flags); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1033 | dbri_cmdwait(dbri); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1034 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1035 | } |
| 1036 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1037 | static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1038 | { |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 1039 | if (pipe < 16 || pipe > DBRI_MAX_PIPE) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1040 | printk(KERN_ERR "DBRI: recv_fixed called with " |
| 1041 | "illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1042 | return; |
| 1043 | } |
| 1044 | |
| 1045 | if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1046 | printk(KERN_ERR "DBRI: recv_fixed called on " |
| 1047 | "non-fixed pipe %d\n", pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1048 | return; |
| 1049 | } |
| 1050 | |
| 1051 | if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1052 | printk(KERN_ERR "DBRI: recv_fixed called on " |
| 1053 | "transmit pipe %d\n", pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1054 | return; |
| 1055 | } |
| 1056 | |
| 1057 | dbri->pipes[pipe].recv_fixed_ptr = ptr; |
| 1058 | } |
| 1059 | |
| 1060 | /* setup_descs() |
| 1061 | * |
| 1062 | * Setup transmit/receive data on a "long" pipe - i.e, one associated |
| 1063 | * with a DMA buffer. |
| 1064 | * |
| 1065 | * Only pipe numbers 0-15 can be used in this mode. |
| 1066 | * |
| 1067 | * This function takes a stream number pointing to a data buffer, |
| 1068 | * and work by building chains of descriptors which identify the |
| 1069 | * data buffers. Buffers too large for a single descriptor will |
| 1070 | * be spread across multiple descriptors. |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1071 | * |
| 1072 | * All descriptors create a ring buffer. |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1073 | * |
| 1074 | * Lock must be held before calling this. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1075 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1076 | static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1077 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 1078 | struct dbri_streaminfo *info = &dbri->stream_info[streamno]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1079 | __u32 dvma_buffer; |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 1080 | int desc; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1081 | int len; |
| 1082 | int first_desc = -1; |
| 1083 | int last_desc = -1; |
| 1084 | |
| 1085 | if (info->pipe < 0 || info->pipe > 15) { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1086 | printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1087 | return -2; |
| 1088 | } |
| 1089 | |
| 1090 | if (dbri->pipes[info->pipe].sdp == 0) { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1091 | printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n", |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1092 | info->pipe); |
| 1093 | return -2; |
| 1094 | } |
| 1095 | |
| 1096 | dvma_buffer = info->dvma_buffer; |
| 1097 | len = info->size; |
| 1098 | |
| 1099 | if (streamno == DBRI_PLAY) { |
| 1100 | if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1101 | printk(KERN_ERR "DBRI: setup_descs: " |
| 1102 | "Called on receive pipe %d\n", info->pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1103 | return -2; |
| 1104 | } |
| 1105 | } else { |
| 1106 | if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1107 | printk(KERN_ERR |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1108 | "DBRI: setup_descs: Called on transmit pipe %d\n", |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1109 | info->pipe); |
| 1110 | return -2; |
| 1111 | } |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1112 | /* Should be able to queue multiple buffers |
| 1113 | * to receive on a pipe |
| 1114 | */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1115 | if (pipe_active(dbri, info->pipe)) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1116 | printk(KERN_ERR "DBRI: recv_on_pipe: " |
| 1117 | "Called on active pipe %d\n", info->pipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1118 | return -2; |
| 1119 | } |
| 1120 | |
| 1121 | /* Make sure buffer size is multiple of four */ |
| 1122 | len &= ~3; |
| 1123 | } |
| 1124 | |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 1125 | /* Free descriptors if pipe has any */ |
| 1126 | desc = dbri->pipes[info->pipe].first_desc; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1127 | if (desc >= 0) |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 1128 | do { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1129 | dbri->dma->desc[desc].ba = 0; |
| 1130 | dbri->dma->desc[desc].nda = 0; |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 1131 | desc = dbri->next_desc[desc]; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1132 | } while (desc != -1 && |
| 1133 | desc != dbri->pipes[info->pipe].first_desc); |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 1134 | |
| 1135 | dbri->pipes[info->pipe].desc = -1; |
| 1136 | dbri->pipes[info->pipe].first_desc = -1; |
| 1137 | |
| 1138 | desc = 0; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1139 | while (len > 0) { |
| 1140 | int mylen; |
| 1141 | |
| 1142 | for (; desc < DBRI_NO_DESCS; desc++) { |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 1143 | if (!dbri->dma->desc[desc].ba) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1144 | break; |
| 1145 | } |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 1146 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1147 | if (desc == DBRI_NO_DESCS) { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1148 | printk(KERN_ERR "DBRI: setup_descs: No descriptors\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1149 | return -1; |
| 1150 | } |
| 1151 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1152 | if (len > DBRI_TD_MAXCNT) |
| 1153 | mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */ |
| 1154 | else |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1155 | mylen = len; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1156 | |
| 1157 | if (mylen > period) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1158 | mylen = period; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1159 | |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 1160 | dbri->next_desc[desc] = -1; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1161 | dbri->dma->desc[desc].ba = dvma_buffer; |
| 1162 | dbri->dma->desc[desc].nda = 0; |
| 1163 | |
| 1164 | if (streamno == DBRI_PLAY) { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1165 | dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); |
| 1166 | dbri->dma->desc[desc].word4 = 0; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1167 | dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1168 | } else { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1169 | dbri->dma->desc[desc].word1 = 0; |
| 1170 | dbri->dma->desc[desc].word4 = |
| 1171 | DBRI_RD_B | DBRI_RD_BCNT(mylen); |
| 1172 | } |
| 1173 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1174 | if (first_desc == -1) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1175 | first_desc = desc; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1176 | else { |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 1177 | dbri->next_desc[last_desc] = desc; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1178 | dbri->dma->desc[last_desc].nda = |
| 1179 | dbri->dma_dvma + dbri_dma_off(desc, desc); |
| 1180 | } |
| 1181 | |
| 1182 | last_desc = desc; |
| 1183 | dvma_buffer += mylen; |
| 1184 | len -= mylen; |
| 1185 | } |
| 1186 | |
| 1187 | if (first_desc == -1 || last_desc == -1) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1188 | printk(KERN_ERR "DBRI: setup_descs: " |
| 1189 | " Not enough descriptors available\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1190 | return -1; |
| 1191 | } |
| 1192 | |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 1193 | dbri->dma->desc[last_desc].nda = |
| 1194 | dbri->dma_dvma + dbri_dma_off(desc, first_desc); |
| 1195 | dbri->next_desc[last_desc] = first_desc; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1196 | dbri->pipes[info->pipe].first_desc = first_desc; |
| 1197 | dbri->pipes[info->pipe].desc = first_desc; |
| 1198 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1199 | #ifdef DBRI_DEBUG |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1200 | for (desc = first_desc; desc != -1;) { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1201 | dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n", |
| 1202 | desc, |
| 1203 | dbri->dma->desc[desc].word1, |
| 1204 | dbri->dma->desc[desc].ba, |
| 1205 | dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1206 | desc = dbri->next_desc[desc]; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1207 | if (desc == first_desc) |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1208 | break; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1209 | } |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1210 | #endif |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1211 | return 0; |
| 1212 | } |
| 1213 | |
| 1214 | /* |
| 1215 | **************************************************************************** |
| 1216 | ************************** DBRI - CHI interface **************************** |
| 1217 | **************************************************************************** |
| 1218 | |
| 1219 | The CHI is a four-wire (clock, frame sync, data in, data out) time-division |
| 1220 | multiplexed serial interface which the DBRI can operate in either master |
| 1221 | (give clock/frame sync) or slave (take clock/frame sync) mode. |
| 1222 | |
| 1223 | */ |
| 1224 | |
| 1225 | enum master_or_slave { CHImaster, CHIslave }; |
| 1226 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1227 | /* |
| 1228 | * Lock must not be held before calling it. |
| 1229 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1230 | static void reset_chi(struct snd_dbri *dbri, |
| 1231 | enum master_or_slave master_or_slave, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1232 | int bits_per_frame) |
| 1233 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1234 | s32 *cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1235 | int val; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1236 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1237 | /* Set CHI Anchor: Pipe 16 */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1238 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1239 | cmd = dbri_cmdlock(dbri, 4); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1240 | val = D_DTS_VO | D_DTS_VI | D_DTS_INS |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1241 | | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16); |
| 1242 | *(cmd++) = DBRI_CMD(D_DTS, 0, val); |
| 1243 | *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); |
| 1244 | *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); |
| 1245 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
| 1246 | dbri_cmdsend(dbri, cmd, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1247 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1248 | dbri->pipes[16].sdp = 1; |
| 1249 | dbri->pipes[16].nextpipe = 16; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1250 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1251 | cmd = dbri_cmdlock(dbri, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1252 | |
| 1253 | if (master_or_slave == CHIslave) { |
| 1254 | /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) |
| 1255 | * |
| 1256 | * CHICM = 0 (slave mode, 8 kHz frame rate) |
| 1257 | * IR = give immediate CHI status interrupt |
| 1258 | * EN = give CHI status interrupt upon change |
| 1259 | */ |
| 1260 | *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); |
| 1261 | } else { |
| 1262 | /* Setup DBRI for CHI Master - generate clock, FS |
| 1263 | * |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1264 | * BPF = bits per 8 kHz frame |
| 1265 | * 12.288 MHz / CHICM_divisor = clock rate |
| 1266 | * FD = 1 - drive CHIFS on rising edge of CHICK |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1267 | */ |
| 1268 | int clockrate = bits_per_frame * 8; |
| 1269 | int divisor = 12288 / clockrate; |
| 1270 | |
| 1271 | if (divisor > 255 || divisor * clockrate != 12288) |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1272 | printk(KERN_ERR "DBRI: illegal bits_per_frame " |
| 1273 | "in setup_chi\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1274 | |
| 1275 | *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD |
| 1276 | | D_CHI_BPF(bits_per_frame)); |
| 1277 | } |
| 1278 | |
| 1279 | dbri->chi_bpf = bits_per_frame; |
| 1280 | |
| 1281 | /* CHI Data Mode |
| 1282 | * |
| 1283 | * RCE = 0 - receive on falling edge of CHICK |
| 1284 | * XCE = 1 - transmit on rising edge of CHICK |
| 1285 | * XEN = 1 - enable transmitter |
| 1286 | * REN = 1 - enable receiver |
| 1287 | */ |
| 1288 | |
| 1289 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
| 1290 | *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1291 | *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1292 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1293 | dbri_cmdsend(dbri, cmd, 4); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1294 | } |
| 1295 | |
| 1296 | /* |
| 1297 | **************************************************************************** |
| 1298 | *********************** CS4215 audio codec management ********************** |
| 1299 | **************************************************************************** |
| 1300 | |
| 1301 | In the standard SPARC audio configuration, the CS4215 codec is attached |
| 1302 | to the DBRI via the CHI interface and few of the DBRI's PIO pins. |
| 1303 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1304 | * Lock must not be held before calling it. |
| 1305 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1306 | */ |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 1307 | static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1308 | { |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1309 | unsigned long flags; |
| 1310 | |
| 1311 | spin_lock_irqsave(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1312 | /* |
| 1313 | * Data mode: |
| 1314 | * Pipe 4: Send timeslots 1-4 (audio data) |
| 1315 | * Pipe 20: Send timeslots 5-8 (part of ctrl data) |
| 1316 | * Pipe 6: Receive timeslots 1-4 (audio data) |
| 1317 | * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via |
| 1318 | * interrupt, and the rest of the data (slot 5 and 8) is |
| 1319 | * not relevant for us (only for doublechecking). |
| 1320 | * |
| 1321 | * Control mode: |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1322 | * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1323 | * Pipe 18: Receive timeslot 1 (clb). |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1324 | * Pipe 19: Receive timeslot 7 (version). |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1325 | */ |
| 1326 | |
| 1327 | setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); |
| 1328 | setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); |
| 1329 | setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); |
| 1330 | setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
| 1331 | |
| 1332 | setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); |
| 1333 | setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
| 1334 | setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1335 | spin_unlock_irqrestore(&dbri->lock, flags); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1336 | |
| 1337 | dbri_cmdwait(dbri); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1338 | } |
| 1339 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 1340 | static __devinit int cs4215_init_data(struct cs4215 *mm) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1341 | { |
| 1342 | /* |
| 1343 | * No action, memory resetting only. |
| 1344 | * |
| 1345 | * Data Time Slot 5-8 |
| 1346 | * Speaker,Line and Headphone enable. Gain set to the half. |
| 1347 | * Input is mike. |
| 1348 | */ |
| 1349 | mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; |
| 1350 | mm->data[1] = CS4215_RO(0x20) | CS4215_SE; |
| 1351 | mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; |
| 1352 | mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); |
| 1353 | |
| 1354 | /* |
| 1355 | * Control Time Slot 1-4 |
| 1356 | * 0: Default I/O voltage scale |
| 1357 | * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled |
| 1358 | * 2: Serial enable, CHI master, 128 bits per frame, clock 1 |
| 1359 | * 3: Tests disabled |
| 1360 | */ |
| 1361 | mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; |
| 1362 | mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; |
| 1363 | mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; |
| 1364 | mm->ctrl[3] = 0; |
| 1365 | |
| 1366 | mm->status = 0; |
| 1367 | mm->version = 0xff; |
| 1368 | mm->precision = 8; /* For ULAW */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1369 | mm->channels = 1; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1370 | |
| 1371 | return 0; |
| 1372 | } |
| 1373 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1374 | static void cs4215_setdata(struct snd_dbri *dbri, int muted) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1375 | { |
| 1376 | if (muted) { |
| 1377 | dbri->mm.data[0] |= 63; |
| 1378 | dbri->mm.data[1] |= 63; |
| 1379 | dbri->mm.data[2] &= ~15; |
| 1380 | dbri->mm.data[3] &= ~15; |
| 1381 | } else { |
| 1382 | /* Start by setting the playback attenuation. */ |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 1383 | struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 1384 | int left_gain = info->left_gain & 0x3f; |
| 1385 | int right_gain = info->right_gain & 0x3f; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1386 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1387 | dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ |
| 1388 | dbri->mm.data[1] &= ~0x3f; |
| 1389 | dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); |
| 1390 | dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); |
| 1391 | |
| 1392 | /* Now set the recording gain. */ |
| 1393 | info = &dbri->stream_info[DBRI_REC]; |
Krzysztof Helt | 470f1f1a | 2006-08-21 19:28:16 +0200 | [diff] [blame] | 1394 | left_gain = info->left_gain & 0xf; |
| 1395 | right_gain = info->right_gain & 0xf; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1396 | dbri->mm.data[2] |= CS4215_LG(left_gain); |
| 1397 | dbri->mm.data[3] |= CS4215_RG(right_gain); |
| 1398 | } |
| 1399 | |
| 1400 | xmit_fixed(dbri, 20, *(int *)dbri->mm.data); |
| 1401 | } |
| 1402 | |
| 1403 | /* |
| 1404 | * Set the CS4215 to data mode. |
| 1405 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1406 | static void cs4215_open(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1407 | { |
| 1408 | int data_width; |
| 1409 | u32 tmp; |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1410 | unsigned long flags; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1411 | |
| 1412 | dprintk(D_MM, "cs4215_open: %d channels, %d bits\n", |
| 1413 | dbri->mm.channels, dbri->mm.precision); |
| 1414 | |
| 1415 | /* Temporarily mute outputs, and wait 1/8000 sec (125 us) |
| 1416 | * to make sure this takes. This avoids clicking noises. |
| 1417 | */ |
| 1418 | |
| 1419 | cs4215_setdata(dbri, 1); |
| 1420 | udelay(125); |
| 1421 | |
| 1422 | /* |
| 1423 | * Data mode: |
| 1424 | * Pipe 4: Send timeslots 1-4 (audio data) |
| 1425 | * Pipe 20: Send timeslots 5-8 (part of ctrl data) |
| 1426 | * Pipe 6: Receive timeslots 1-4 (audio data) |
| 1427 | * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via |
| 1428 | * interrupt, and the rest of the data (slot 5 and 8) is |
| 1429 | * not relevant for us (only for doublechecking). |
| 1430 | * |
| 1431 | * Just like in control mode, the time slots are all offset by eight |
| 1432 | * bits. The CS4215, it seems, observes TSIN (the delayed signal) |
| 1433 | * even if it's the CHI master. Don't ask me... |
| 1434 | */ |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1435 | spin_lock_irqsave(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1436 | tmp = sbus_readl(dbri->regs + REG0); |
| 1437 | tmp &= ~(D_C); /* Disable CHI */ |
| 1438 | sbus_writel(tmp, dbri->regs + REG0); |
| 1439 | |
| 1440 | /* Switch CS4215 to data mode - set PIO3 to 1 */ |
| 1441 | sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | |
| 1442 | (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); |
| 1443 | |
| 1444 | reset_chi(dbri, CHIslave, 128); |
| 1445 | |
| 1446 | /* Note: this next doesn't work for 8-bit stereo, because the two |
| 1447 | * channels would be on timeslots 1 and 3, with 2 and 4 idle. |
| 1448 | * (See CS4215 datasheet Fig 15) |
| 1449 | * |
| 1450 | * DBRI non-contiguous mode would be required to make this work. |
| 1451 | */ |
| 1452 | data_width = dbri->mm.channels * dbri->mm.precision; |
| 1453 | |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 1454 | link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset); |
| 1455 | link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32); |
| 1456 | link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset); |
| 1457 | link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1458 | |
| 1459 | /* FIXME: enable CHI after _setdata? */ |
| 1460 | tmp = sbus_readl(dbri->regs + REG0); |
| 1461 | tmp |= D_C; /* Enable CHI */ |
| 1462 | sbus_writel(tmp, dbri->regs + REG0); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1463 | spin_unlock_irqrestore(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1464 | |
| 1465 | cs4215_setdata(dbri, 0); |
| 1466 | } |
| 1467 | |
| 1468 | /* |
| 1469 | * Send the control information (i.e. audio format) |
| 1470 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1471 | static int cs4215_setctrl(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1472 | { |
| 1473 | int i, val; |
| 1474 | u32 tmp; |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1475 | unsigned long flags; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1476 | |
| 1477 | /* FIXME - let the CPU do something useful during these delays */ |
| 1478 | |
| 1479 | /* Temporarily mute outputs, and wait 1/8000 sec (125 us) |
| 1480 | * to make sure this takes. This avoids clicking noises. |
| 1481 | */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1482 | cs4215_setdata(dbri, 1); |
| 1483 | udelay(125); |
| 1484 | |
| 1485 | /* |
| 1486 | * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait |
| 1487 | * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec |
| 1488 | */ |
| 1489 | val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); |
| 1490 | sbus_writel(val, dbri->regs + REG2); |
| 1491 | dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val); |
| 1492 | udelay(34); |
| 1493 | |
| 1494 | /* In Control mode, the CS4215 is a slave device, so the DBRI must |
| 1495 | * operate as CHI master, supplying clocking and frame synchronization. |
| 1496 | * |
| 1497 | * In Data mode, however, the CS4215 must be CHI master to insure |
| 1498 | * that its data stream is synchronous with its codec. |
| 1499 | * |
| 1500 | * The upshot of all this? We start by putting the DBRI into master |
| 1501 | * mode, program the CS4215 in Control mode, then switch the CS4215 |
| 1502 | * into Data mode and put the DBRI into slave mode. Various timing |
| 1503 | * requirements must be observed along the way. |
| 1504 | * |
| 1505 | * Oh, and one more thing, on a SPARCStation 20 (and maybe |
| 1506 | * others?), the addressing of the CS4215's time slots is |
| 1507 | * offset by eight bits, so we add eight to all the "cycle" |
| 1508 | * values in the Define Time Slot (DTS) commands. This is |
| 1509 | * done in hardware by a TI 248 that delays the DBRI->4215 |
| 1510 | * frame sync signal by eight clock cycles. Anybody know why? |
| 1511 | */ |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1512 | spin_lock_irqsave(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1513 | tmp = sbus_readl(dbri->regs + REG0); |
| 1514 | tmp &= ~D_C; /* Disable CHI */ |
| 1515 | sbus_writel(tmp, dbri->regs + REG0); |
| 1516 | |
| 1517 | reset_chi(dbri, CHImaster, 128); |
| 1518 | |
| 1519 | /* |
| 1520 | * Control mode: |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1521 | * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1522 | * Pipe 18: Receive timeslot 1 (clb). |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1523 | * Pipe 19: Receive timeslot 7 (version). |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1524 | */ |
| 1525 | |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 1526 | link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset); |
| 1527 | link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset); |
| 1528 | link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1529 | spin_unlock_irqrestore(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1530 | |
| 1531 | /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ |
| 1532 | dbri->mm.ctrl[0] &= ~CS4215_CLB; |
| 1533 | xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); |
| 1534 | |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1535 | spin_lock_irqsave(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1536 | tmp = sbus_readl(dbri->regs + REG0); |
| 1537 | tmp |= D_C; /* Enable CHI */ |
| 1538 | sbus_writel(tmp, dbri->regs + REG0); |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1539 | spin_unlock_irqrestore(&dbri->lock, flags); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1540 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1541 | for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1542 | msleep_interruptible(1); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1543 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1544 | if (i == 0) { |
| 1545 | dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n", |
| 1546 | dbri->mm.status); |
| 1547 | return -1; |
| 1548 | } |
| 1549 | |
| 1550 | /* Disable changes to our copy of the version number, as we are about |
| 1551 | * to leave control mode. |
| 1552 | */ |
| 1553 | recv_fixed(dbri, 19, NULL); |
| 1554 | |
| 1555 | /* Terminate CS4215 control mode - data sheet says |
| 1556 | * "Set CLB=1 and send two more frames of valid control info" |
| 1557 | */ |
| 1558 | dbri->mm.ctrl[0] |= CS4215_CLB; |
| 1559 | xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); |
| 1560 | |
| 1561 | /* Two frames of control info @ 8kHz frame rate = 250 us delay */ |
| 1562 | udelay(250); |
| 1563 | |
| 1564 | cs4215_setdata(dbri, 0); |
| 1565 | |
| 1566 | return 0; |
| 1567 | } |
| 1568 | |
| 1569 | /* |
| 1570 | * Setup the codec with the sampling rate, audio format and number of |
| 1571 | * channels. |
| 1572 | * As part of the process we resend the settings for the data |
| 1573 | * timeslots as well. |
| 1574 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1575 | static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1576 | snd_pcm_format_t format, unsigned int channels) |
| 1577 | { |
| 1578 | int freq_idx; |
| 1579 | int ret = 0; |
| 1580 | |
| 1581 | /* Lookup index for this rate */ |
| 1582 | for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { |
| 1583 | if (CS4215_FREQ[freq_idx].freq == rate) |
| 1584 | break; |
| 1585 | } |
| 1586 | if (CS4215_FREQ[freq_idx].freq != rate) { |
| 1587 | printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate); |
| 1588 | return -1; |
| 1589 | } |
| 1590 | |
| 1591 | switch (format) { |
| 1592 | case SNDRV_PCM_FORMAT_MU_LAW: |
| 1593 | dbri->mm.ctrl[1] = CS4215_DFR_ULAW; |
| 1594 | dbri->mm.precision = 8; |
| 1595 | break; |
| 1596 | case SNDRV_PCM_FORMAT_A_LAW: |
| 1597 | dbri->mm.ctrl[1] = CS4215_DFR_ALAW; |
| 1598 | dbri->mm.precision = 8; |
| 1599 | break; |
| 1600 | case SNDRV_PCM_FORMAT_U8: |
| 1601 | dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; |
| 1602 | dbri->mm.precision = 8; |
| 1603 | break; |
| 1604 | case SNDRV_PCM_FORMAT_S16_BE: |
| 1605 | dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; |
| 1606 | dbri->mm.precision = 16; |
| 1607 | break; |
| 1608 | default: |
| 1609 | printk(KERN_WARNING "DBRI: Unsupported format %d\n", format); |
| 1610 | return -1; |
| 1611 | } |
| 1612 | |
| 1613 | /* Add rate parameters */ |
| 1614 | dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; |
| 1615 | dbri->mm.ctrl[2] = CS4215_XCLK | |
| 1616 | CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; |
| 1617 | |
| 1618 | dbri->mm.channels = channels; |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 1619 | if (channels == 2) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1620 | dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; |
| 1621 | |
| 1622 | ret = cs4215_setctrl(dbri); |
| 1623 | if (ret == 0) |
| 1624 | cs4215_open(dbri); /* set codec to data mode */ |
| 1625 | |
| 1626 | return ret; |
| 1627 | } |
| 1628 | |
| 1629 | /* |
| 1630 | * |
| 1631 | */ |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 1632 | static __devinit int cs4215_init(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1633 | { |
| 1634 | u32 reg2 = sbus_readl(dbri->regs + REG2); |
| 1635 | dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); |
| 1636 | |
| 1637 | /* Look for the cs4215 chips */ |
| 1638 | if (reg2 & D_PIO2) { |
| 1639 | dprintk(D_MM, "Onboard CS4215 detected\n"); |
| 1640 | dbri->mm.onboard = 1; |
| 1641 | } |
| 1642 | if (reg2 & D_PIO0) { |
| 1643 | dprintk(D_MM, "Speakerbox detected\n"); |
| 1644 | dbri->mm.onboard = 0; |
| 1645 | |
| 1646 | if (reg2 & D_PIO2) { |
| 1647 | printk(KERN_INFO "DBRI: Using speakerbox / " |
| 1648 | "ignoring onboard mmcodec.\n"); |
| 1649 | sbus_writel(D_ENPIO2, dbri->regs + REG2); |
| 1650 | } |
| 1651 | } |
| 1652 | |
| 1653 | if (!(reg2 & (D_PIO0 | D_PIO2))) { |
| 1654 | printk(KERN_ERR "DBRI: no mmcodec found.\n"); |
| 1655 | return -EIO; |
| 1656 | } |
| 1657 | |
| 1658 | cs4215_setup_pipes(dbri); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1659 | cs4215_init_data(&dbri->mm); |
| 1660 | |
| 1661 | /* Enable capture of the status & version timeslots. */ |
| 1662 | recv_fixed(dbri, 18, &dbri->mm.status); |
| 1663 | recv_fixed(dbri, 19, &dbri->mm.version); |
| 1664 | |
| 1665 | dbri->mm.offset = dbri->mm.onboard ? 0 : 8; |
| 1666 | if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { |
| 1667 | dprintk(D_MM, "CS4215 failed probe at offset %d\n", |
| 1668 | dbri->mm.offset); |
| 1669 | return -EIO; |
| 1670 | } |
| 1671 | dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset); |
| 1672 | |
| 1673 | return 0; |
| 1674 | } |
| 1675 | |
| 1676 | /* |
| 1677 | **************************************************************************** |
| 1678 | *************************** DBRI interrupt handler ************************* |
| 1679 | **************************************************************************** |
| 1680 | |
| 1681 | The DBRI communicates with the CPU mainly via a circular interrupt |
| 1682 | buffer. When an interrupt is signaled, the CPU walks through the |
| 1683 | buffer and calls dbri_process_one_interrupt() for each interrupt word. |
| 1684 | Complicated interrupts are handled by dedicated functions (which |
| 1685 | appear first in this file). Any pending interrupts can be serviced by |
| 1686 | calling dbri_process_interrupt_buffer(), which works even if the CPU's |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1687 | interrupts are disabled. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1688 | |
| 1689 | */ |
| 1690 | |
| 1691 | /* xmit_descs() |
| 1692 | * |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1693 | * Starts transmitting the current TD's for recording/playing. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1694 | * For playback, ALSA has filled the DMA memory with new data (we hope). |
| 1695 | */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1696 | static void xmit_descs(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1697 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 1698 | struct dbri_streaminfo *info; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1699 | s32 *cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1700 | unsigned long flags; |
| 1701 | int first_td; |
| 1702 | |
| 1703 | if (dbri == NULL) |
| 1704 | return; /* Disabled */ |
| 1705 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1706 | info = &dbri->stream_info[DBRI_REC]; |
| 1707 | spin_lock_irqsave(&dbri->lock, flags); |
| 1708 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1709 | if (info->pipe >= 0) { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1710 | first_td = dbri->pipes[info->pipe].first_desc; |
| 1711 | |
| 1712 | dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td); |
| 1713 | |
| 1714 | /* Stream could be closed by the time we run. */ |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 1715 | if (first_td >= 0) { |
| 1716 | cmd = dbri_cmdlock(dbri, 2); |
| 1717 | *(cmd++) = DBRI_CMD(D_SDP, 0, |
| 1718 | dbri->pipes[info->pipe].sdp |
| 1719 | | D_SDP_P | D_SDP_EVERY | D_SDP_C); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1720 | *(cmd++) = dbri->dma_dvma + |
| 1721 | dbri_dma_off(desc, first_td); |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 1722 | dbri_cmdsend(dbri, cmd, 2); |
| 1723 | |
| 1724 | /* Reset our admin of the pipe. */ |
| 1725 | dbri->pipes[info->pipe].desc = first_td; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1726 | } |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1727 | } |
| 1728 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1729 | info = &dbri->stream_info[DBRI_PLAY]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1730 | |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1731 | if (info->pipe >= 0) { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1732 | first_td = dbri->pipes[info->pipe].first_desc; |
| 1733 | |
| 1734 | dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td); |
| 1735 | |
| 1736 | /* Stream could be closed by the time we run. */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1737 | if (first_td >= 0) { |
| 1738 | cmd = dbri_cmdlock(dbri, 2); |
| 1739 | *(cmd++) = DBRI_CMD(D_SDP, 0, |
| 1740 | dbri->pipes[info->pipe].sdp |
| 1741 | | D_SDP_P | D_SDP_EVERY | D_SDP_C); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1742 | *(cmd++) = dbri->dma_dvma + |
| 1743 | dbri_dma_off(desc, first_td); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1744 | dbri_cmdsend(dbri, cmd, 2); |
| 1745 | |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 1746 | /* Reset our admin of the pipe. */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1747 | dbri->pipes[info->pipe].desc = first_td; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1748 | } |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1749 | } |
Krzysztof Helt | ea543f1 | 2006-09-05 20:25:05 +0200 | [diff] [blame] | 1750 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1751 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 1752 | } |
| 1753 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1754 | /* transmission_complete_intr() |
| 1755 | * |
| 1756 | * Called by main interrupt handler when DBRI signals transmission complete |
| 1757 | * on a pipe (interrupt triggered by the B bit in a transmit descriptor). |
| 1758 | * |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1759 | * Walks through the pipe's list of transmit buffer descriptors and marks |
| 1760 | * them as available. Stops when the first descriptor is found without |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1761 | * TBC (Transmit Buffer Complete) set, or we've run through them all. |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1762 | * |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 1763 | * The DMA buffers are not released. They form a ring buffer and |
| 1764 | * they are filled by ALSA while others are transmitted by DMA. |
| 1765 | * |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1766 | */ |
| 1767 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1768 | static void transmission_complete_intr(struct snd_dbri *dbri, int pipe) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1769 | { |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 1770 | struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; |
| 1771 | int td = dbri->pipes[pipe].desc; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1772 | int status; |
| 1773 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1774 | while (td >= 0) { |
| 1775 | if (td >= DBRI_NO_DESCS) { |
| 1776 | printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe); |
| 1777 | return; |
| 1778 | } |
| 1779 | |
| 1780 | status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1781 | if (!(status & DBRI_TD_TBC)) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1782 | break; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1783 | |
| 1784 | dprintk(D_INT, "TD %d, status 0x%02x\n", td, status); |
| 1785 | |
| 1786 | dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1787 | info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1788 | |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 1789 | td = dbri->next_desc[td]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1790 | dbri->pipes[pipe].desc = td; |
| 1791 | } |
| 1792 | |
| 1793 | /* Notify ALSA */ |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 1794 | spin_unlock(&dbri->lock); |
| 1795 | snd_pcm_period_elapsed(info->substream); |
| 1796 | spin_lock(&dbri->lock); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1797 | } |
| 1798 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1799 | static void reception_complete_intr(struct snd_dbri *dbri, int pipe) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1800 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 1801 | struct dbri_streaminfo *info; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1802 | int rd = dbri->pipes[pipe].desc; |
| 1803 | s32 status; |
| 1804 | |
| 1805 | if (rd < 0 || rd >= DBRI_NO_DESCS) { |
| 1806 | printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe); |
| 1807 | return; |
| 1808 | } |
| 1809 | |
Krzysztof Helt | c273544 | 2006-08-21 19:27:35 +0200 | [diff] [blame] | 1810 | dbri->pipes[pipe].desc = dbri->next_desc[rd]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1811 | status = dbri->dma->desc[rd].word1; |
| 1812 | dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ |
| 1813 | |
| 1814 | info = &dbri->stream_info[DBRI_REC]; |
| 1815 | info->offset += DBRI_RD_CNT(status); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1816 | |
| 1817 | /* FIXME: Check status */ |
| 1818 | |
| 1819 | dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n", |
| 1820 | rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); |
| 1821 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1822 | /* Notify ALSA */ |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 1823 | spin_unlock(&dbri->lock); |
| 1824 | snd_pcm_period_elapsed(info->substream); |
| 1825 | spin_lock(&dbri->lock); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1826 | } |
| 1827 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1828 | static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1829 | { |
| 1830 | int val = D_INTR_GETVAL(x); |
| 1831 | int channel = D_INTR_GETCHAN(x); |
| 1832 | int command = D_INTR_GETCMD(x); |
| 1833 | int code = D_INTR_GETCODE(x); |
| 1834 | #ifdef DBRI_DEBUG |
| 1835 | int rval = D_INTR_GETRVAL(x); |
| 1836 | #endif |
| 1837 | |
| 1838 | if (channel == D_INTR_CMD) { |
| 1839 | dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n", |
| 1840 | cmds[command], val); |
| 1841 | } else { |
| 1842 | dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n", |
| 1843 | channel, code, rval); |
| 1844 | } |
| 1845 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1846 | switch (code) { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1847 | case D_INTR_CMDI: |
| 1848 | if (command != D_WAIT) |
| 1849 | printk(KERN_ERR "DBRI: Command read interrupt\n"); |
| 1850 | break; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1851 | case D_INTR_BRDY: |
| 1852 | reception_complete_intr(dbri, channel); |
| 1853 | break; |
| 1854 | case D_INTR_XCMP: |
| 1855 | case D_INTR_MINT: |
| 1856 | transmission_complete_intr(dbri, channel); |
| 1857 | break; |
| 1858 | case D_INTR_UNDR: |
| 1859 | /* UNDR - Transmission underrun |
| 1860 | * resend SDP command with clear pipe bit (C) set |
| 1861 | */ |
| 1862 | { |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1863 | /* FIXME: do something useful in case of underrun */ |
| 1864 | printk(KERN_ERR "DBRI: Underrun error\n"); |
| 1865 | #if 0 |
| 1866 | s32 *cmd; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1867 | int pipe = channel; |
| 1868 | int td = dbri->pipes[pipe].desc; |
| 1869 | |
| 1870 | dbri->dma->desc[td].word4 = 0; |
| 1871 | cmd = dbri_cmdlock(dbri, NoGetLock); |
| 1872 | *(cmd++) = DBRI_CMD(D_SDP, 0, |
| 1873 | dbri->pipes[pipe].sdp |
| 1874 | | D_SDP_P | D_SDP_C | D_SDP_2SAME); |
| 1875 | *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); |
| 1876 | dbri_cmdsend(dbri, cmd); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1877 | #endif |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1878 | } |
| 1879 | break; |
| 1880 | case D_INTR_FXDT: |
| 1881 | /* FXDT - Fixed data change */ |
| 1882 | if (dbri->pipes[channel].sdp & D_SDP_MSB) |
| 1883 | val = reverse_bytes(val, dbri->pipes[channel].length); |
| 1884 | |
| 1885 | if (dbri->pipes[channel].recv_fixed_ptr) |
| 1886 | *(dbri->pipes[channel].recv_fixed_ptr) = val; |
| 1887 | break; |
| 1888 | default: |
| 1889 | if (channel != D_INTR_CMD) |
| 1890 | printk(KERN_WARNING |
| 1891 | "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x); |
| 1892 | } |
| 1893 | } |
| 1894 | |
| 1895 | /* dbri_process_interrupt_buffer advances through the DBRI's interrupt |
| 1896 | * buffer until it finds a zero word (indicating nothing more to do |
| 1897 | * right now). Non-zero words require processing and are handed off |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 1898 | * to dbri_process_one_interrupt AFTER advancing the pointer. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1899 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1900 | static void dbri_process_interrupt_buffer(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1901 | { |
| 1902 | s32 x; |
| 1903 | |
| 1904 | while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { |
| 1905 | dbri->dma->intr[dbri->dbri_irqp] = 0; |
| 1906 | dbri->dbri_irqp++; |
Krzysztof Helt | 6fb9828 | 2006-08-16 12:54:29 +0200 | [diff] [blame] | 1907 | if (dbri->dbri_irqp == DBRI_INT_BLK) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1908 | dbri->dbri_irqp = 1; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1909 | |
| 1910 | dbri_process_one_interrupt(dbri, x); |
| 1911 | } |
| 1912 | } |
| 1913 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1914 | static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1915 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 1916 | struct snd_dbri *dbri = dev_id; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1917 | static int errcnt = 0; |
| 1918 | int x; |
| 1919 | |
| 1920 | if (dbri == NULL) |
| 1921 | return IRQ_NONE; |
| 1922 | spin_lock(&dbri->lock); |
| 1923 | |
| 1924 | /* |
| 1925 | * Read it, so the interrupt goes away. |
| 1926 | */ |
| 1927 | x = sbus_readl(dbri->regs + REG1); |
| 1928 | |
| 1929 | if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { |
| 1930 | u32 tmp; |
| 1931 | |
| 1932 | if (x & D_MRR) |
| 1933 | printk(KERN_ERR |
| 1934 | "DBRI: Multiple Error Ack on SBus reg1=0x%x\n", |
| 1935 | x); |
| 1936 | if (x & D_MLE) |
| 1937 | printk(KERN_ERR |
| 1938 | "DBRI: Multiple Late Error on SBus reg1=0x%x\n", |
| 1939 | x); |
| 1940 | if (x & D_LBG) |
| 1941 | printk(KERN_ERR |
| 1942 | "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x); |
| 1943 | if (x & D_MBE) |
| 1944 | printk(KERN_ERR |
| 1945 | "DBRI: Burst Error on SBus reg1=0x%x\n", x); |
| 1946 | |
| 1947 | /* Some of these SBus errors cause the chip's SBus circuitry |
| 1948 | * to be disabled, so just re-enable and try to keep going. |
| 1949 | * |
| 1950 | * The only one I've seen is MRR, which will be triggered |
| 1951 | * if you let a transmit pipe underrun, then try to CDP it. |
| 1952 | * |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 1953 | * If these things persist, we reset the chip. |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1954 | */ |
| 1955 | if ((++errcnt) % 10 == 0) { |
| 1956 | dprintk(D_INT, "Interrupt errors exceeded.\n"); |
| 1957 | dbri_reset(dbri); |
| 1958 | } else { |
| 1959 | tmp = sbus_readl(dbri->regs + REG0); |
| 1960 | tmp &= ~(D_D); |
| 1961 | sbus_writel(tmp, dbri->regs + REG0); |
| 1962 | } |
| 1963 | } |
| 1964 | |
| 1965 | dbri_process_interrupt_buffer(dbri); |
| 1966 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1967 | spin_unlock(&dbri->lock); |
| 1968 | |
| 1969 | return IRQ_HANDLED; |
| 1970 | } |
| 1971 | |
| 1972 | /**************************************************************************** |
| 1973 | PCM Interface |
| 1974 | ****************************************************************************/ |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 1975 | static struct snd_pcm_hardware snd_dbri_pcm_hw = { |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 1976 | .info = SNDRV_PCM_INFO_MMAP | |
| 1977 | SNDRV_PCM_INFO_INTERLEAVED | |
| 1978 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
Takashi Iwai | 2008f13 | 2009-04-28 12:25:59 +0200 | [diff] [blame] | 1979 | SNDRV_PCM_INFO_MMAP_VALID | |
| 1980 | SNDRV_PCM_INFO_BATCH, |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 1981 | .formats = SNDRV_PCM_FMTBIT_MU_LAW | |
| 1982 | SNDRV_PCM_FMTBIT_A_LAW | |
| 1983 | SNDRV_PCM_FMTBIT_U8 | |
| 1984 | SNDRV_PCM_FMTBIT_S16_BE, |
| 1985 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512, |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 1986 | .rate_min = 5512, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1987 | .rate_max = 48000, |
| 1988 | .channels_min = 1, |
| 1989 | .channels_max = 2, |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 1990 | .buffer_bytes_max = 64 * 1024, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 1991 | .period_bytes_min = 1, |
| 1992 | .period_bytes_max = DBRI_TD_MAXCNT, |
| 1993 | .periods_min = 1, |
| 1994 | .periods_max = 1024, |
| 1995 | }; |
| 1996 | |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 1997 | static int snd_hw_rule_format(struct snd_pcm_hw_params *params, |
| 1998 | struct snd_pcm_hw_rule *rule) |
| 1999 | { |
| 2000 | struct snd_interval *c = hw_param_interval(params, |
| 2001 | SNDRV_PCM_HW_PARAM_CHANNELS); |
| 2002 | struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); |
| 2003 | struct snd_mask fmt; |
| 2004 | |
| 2005 | snd_mask_any(&fmt); |
| 2006 | if (c->min > 1) { |
| 2007 | fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE; |
| 2008 | return snd_mask_refine(f, &fmt); |
| 2009 | } |
| 2010 | return 0; |
| 2011 | } |
| 2012 | |
| 2013 | static int snd_hw_rule_channels(struct snd_pcm_hw_params *params, |
| 2014 | struct snd_pcm_hw_rule *rule) |
| 2015 | { |
| 2016 | struct snd_interval *c = hw_param_interval(params, |
| 2017 | SNDRV_PCM_HW_PARAM_CHANNELS); |
| 2018 | struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); |
| 2019 | struct snd_interval ch; |
| 2020 | |
| 2021 | snd_interval_any(&ch); |
| 2022 | if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) { |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2023 | ch.min = 1; |
| 2024 | ch.max = 1; |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 2025 | ch.integer = 1; |
| 2026 | return snd_interval_refine(c, &ch); |
| 2027 | } |
| 2028 | return 0; |
| 2029 | } |
| 2030 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2031 | static int snd_dbri_open(struct snd_pcm_substream *substream) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2032 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2033 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2034 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 2035 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2036 | unsigned long flags; |
| 2037 | |
| 2038 | dprintk(D_USR, "open audio output.\n"); |
| 2039 | runtime->hw = snd_dbri_pcm_hw; |
| 2040 | |
| 2041 | spin_lock_irqsave(&dbri->lock, flags); |
| 2042 | info->substream = substream; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2043 | info->offset = 0; |
| 2044 | info->dvma_buffer = 0; |
| 2045 | info->pipe = -1; |
| 2046 | spin_unlock_irqrestore(&dbri->lock, flags); |
| 2047 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2048 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, |
Al Viro | ae97dd9 | 2006-09-24 23:42:57 +0100 | [diff] [blame] | 2049 | snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT, |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 2050 | -1); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2051 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT, |
| 2052 | snd_hw_rule_channels, NULL, |
Krzysztof Helt | ab93c7a | 2006-08-23 11:37:36 +0200 | [diff] [blame] | 2053 | SNDRV_PCM_HW_PARAM_CHANNELS, |
| 2054 | -1); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2055 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2056 | cs4215_open(dbri); |
| 2057 | |
| 2058 | return 0; |
| 2059 | } |
| 2060 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2061 | static int snd_dbri_close(struct snd_pcm_substream *substream) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2062 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2063 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2064 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2065 | |
| 2066 | dprintk(D_USR, "close audio output.\n"); |
| 2067 | info->substream = NULL; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2068 | info->offset = 0; |
| 2069 | |
| 2070 | return 0; |
| 2071 | } |
| 2072 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2073 | static int snd_dbri_hw_params(struct snd_pcm_substream *substream, |
| 2074 | struct snd_pcm_hw_params *hw_params) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2075 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2076 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 2077 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2078 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2079 | int direction; |
| 2080 | int ret; |
| 2081 | |
| 2082 | /* set sampling rate, audio format and number of channels */ |
| 2083 | ret = cs4215_prepare(dbri, params_rate(hw_params), |
| 2084 | params_format(hw_params), |
| 2085 | params_channels(hw_params)); |
| 2086 | if (ret != 0) |
| 2087 | return ret; |
| 2088 | |
| 2089 | if ((ret = snd_pcm_lib_malloc_pages(substream, |
| 2090 | params_buffer_bytes(hw_params))) < 0) { |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 2091 | printk(KERN_ERR "malloc_pages failed with %d\n", ret); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2092 | return ret; |
| 2093 | } |
| 2094 | |
| 2095 | /* hw_params can get called multiple times. Only map the DMA once. |
| 2096 | */ |
| 2097 | if (info->dvma_buffer == 0) { |
| 2098 | if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2099 | direction = DMA_TO_DEVICE; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2100 | else |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2101 | direction = DMA_FROM_DEVICE; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2102 | |
David S. Miller | 7a715f4 | 2008-08-27 18:37:58 -0700 | [diff] [blame] | 2103 | info->dvma_buffer = |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2104 | dma_map_single(&dbri->op->dev, |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2105 | runtime->dma_area, |
| 2106 | params_buffer_bytes(hw_params), |
| 2107 | direction); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2108 | } |
| 2109 | |
| 2110 | direction = params_buffer_bytes(hw_params); |
| 2111 | dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n", |
| 2112 | direction, info->dvma_buffer); |
| 2113 | return 0; |
| 2114 | } |
| 2115 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2116 | static int snd_dbri_hw_free(struct snd_pcm_substream *substream) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2117 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2118 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2119 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2120 | int direction; |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 2121 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2122 | dprintk(D_USR, "hw_free.\n"); |
| 2123 | |
| 2124 | /* hw_free can get called multiple times. Only unmap the DMA once. |
| 2125 | */ |
| 2126 | if (info->dvma_buffer) { |
| 2127 | if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2128 | direction = DMA_TO_DEVICE; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2129 | else |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2130 | direction = DMA_FROM_DEVICE; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2131 | |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2132 | dma_unmap_single(&dbri->op->dev, info->dvma_buffer, |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2133 | substream->runtime->buffer_size, direction); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2134 | info->dvma_buffer = 0; |
| 2135 | } |
Krzysztof Helt | 99dabfe | 2006-08-28 13:00:45 +0200 | [diff] [blame] | 2136 | if (info->pipe != -1) { |
| 2137 | reset_pipe(dbri, info->pipe); |
| 2138 | info->pipe = -1; |
| 2139 | } |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2140 | |
| 2141 | return snd_pcm_lib_free_pages(substream); |
| 2142 | } |
| 2143 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2144 | static int snd_dbri_prepare(struct snd_pcm_substream *substream) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2145 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2146 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2147 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2148 | int ret; |
| 2149 | |
| 2150 | info->size = snd_pcm_lib_buffer_bytes(substream); |
| 2151 | if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
| 2152 | info->pipe = 4; /* Send pipe */ |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 2153 | else |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2154 | info->pipe = 6; /* Receive pipe */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2155 | |
| 2156 | spin_lock_irq(&dbri->lock); |
Krzysztof Helt | aaad365 | 2006-08-28 12:59:23 +0200 | [diff] [blame] | 2157 | info->offset = 0; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2158 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2159 | /* Setup the all the transmit/receive descriptors to cover the |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2160 | * whole DMA buffer. |
| 2161 | */ |
| 2162 | ret = setup_descs(dbri, DBRI_STREAMNO(substream), |
| 2163 | snd_pcm_lib_period_bytes(substream)); |
| 2164 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2165 | spin_unlock_irq(&dbri->lock); |
| 2166 | |
| 2167 | dprintk(D_USR, "prepare audio output. %d bytes\n", info->size); |
| 2168 | return ret; |
| 2169 | } |
| 2170 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2171 | static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2172 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2173 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2174 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2175 | int ret = 0; |
| 2176 | |
| 2177 | switch (cmd) { |
| 2178 | case SNDRV_PCM_TRIGGER_START: |
| 2179 | dprintk(D_USR, "start audio, period is %d bytes\n", |
| 2180 | (int)snd_pcm_lib_period_bytes(substream)); |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 2181 | /* Re-submit the TDs. */ |
| 2182 | xmit_descs(dbri); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2183 | break; |
| 2184 | case SNDRV_PCM_TRIGGER_STOP: |
| 2185 | dprintk(D_USR, "stop audio.\n"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2186 | reset_pipe(dbri, info->pipe); |
| 2187 | break; |
| 2188 | default: |
| 2189 | ret = -EINVAL; |
| 2190 | } |
| 2191 | |
| 2192 | return ret; |
| 2193 | } |
| 2194 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2195 | static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2196 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2197 | struct snd_dbri *dbri = snd_pcm_substream_chip(substream); |
| 2198 | struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2199 | snd_pcm_uframes_t ret; |
| 2200 | |
| 2201 | ret = bytes_to_frames(substream->runtime, info->offset) |
| 2202 | % substream->runtime->buffer_size; |
Krzysztof Helt | 1be54c8 | 2006-08-21 19:30:57 +0200 | [diff] [blame] | 2203 | dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n", |
| 2204 | ret, substream->runtime->buffer_size); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2205 | return ret; |
| 2206 | } |
| 2207 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2208 | static struct snd_pcm_ops snd_dbri_ops = { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2209 | .open = snd_dbri_open, |
| 2210 | .close = snd_dbri_close, |
| 2211 | .ioctl = snd_pcm_lib_ioctl, |
| 2212 | .hw_params = snd_dbri_hw_params, |
| 2213 | .hw_free = snd_dbri_hw_free, |
| 2214 | .prepare = snd_dbri_prepare, |
| 2215 | .trigger = snd_dbri_trigger, |
| 2216 | .pointer = snd_dbri_pointer, |
| 2217 | }; |
| 2218 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2219 | static int __devinit snd_dbri_pcm(struct snd_card *card) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2220 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2221 | struct snd_pcm *pcm; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2222 | int err; |
| 2223 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2224 | if ((err = snd_pcm_new(card, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2225 | /* ID */ "sun_dbri", |
| 2226 | /* device */ 0, |
| 2227 | /* playback count */ 1, |
| 2228 | /* capture count */ 1, &pcm)) < 0) |
| 2229 | return err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2230 | |
| 2231 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); |
| 2232 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); |
| 2233 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2234 | pcm->private_data = card->private_data; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2235 | pcm->info_flags = 0; |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2236 | strcpy(pcm->name, card->shortname); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2237 | |
| 2238 | if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm, |
| 2239 | SNDRV_DMA_TYPE_CONTINUOUS, |
| 2240 | snd_dma_continuous_data(GFP_KERNEL), |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2241 | 64 * 1024, 64 * 1024)) < 0) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2242 | return err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2243 | |
| 2244 | return 0; |
| 2245 | } |
| 2246 | |
| 2247 | /***************************************************************************** |
| 2248 | Mixer interface |
| 2249 | *****************************************************************************/ |
| 2250 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2251 | static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol, |
| 2252 | struct snd_ctl_elem_info *uinfo) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2253 | { |
| 2254 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 2255 | uinfo->count = 2; |
| 2256 | uinfo->value.integer.min = 0; |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2257 | if (kcontrol->private_value == DBRI_PLAY) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2258 | uinfo->value.integer.max = DBRI_MAX_VOLUME; |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2259 | else |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2260 | uinfo->value.integer.max = DBRI_MAX_GAIN; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2261 | return 0; |
| 2262 | } |
| 2263 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2264 | static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol, |
| 2265 | struct snd_ctl_elem_value *ucontrol) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2266 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2267 | struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
| 2268 | struct dbri_streaminfo *info; |
Takashi Iwai | 5e246b8 | 2008-08-08 17:12:47 +0200 | [diff] [blame] | 2269 | |
| 2270 | if (snd_BUG_ON(!dbri)) |
| 2271 | return -EINVAL; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2272 | info = &dbri->stream_info[kcontrol->private_value]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2273 | |
| 2274 | ucontrol->value.integer.value[0] = info->left_gain; |
| 2275 | ucontrol->value.integer.value[1] = info->right_gain; |
| 2276 | return 0; |
| 2277 | } |
| 2278 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2279 | static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol, |
| 2280 | struct snd_ctl_elem_value *ucontrol) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2281 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2282 | struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2283 | struct dbri_streaminfo *info = |
| 2284 | &dbri->stream_info[kcontrol->private_value]; |
Takashi Iwai | 3b89246 | 2007-11-15 16:17:24 +0100 | [diff] [blame] | 2285 | unsigned int vol[2]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2286 | int changed = 0; |
| 2287 | |
Takashi Iwai | 3b89246 | 2007-11-15 16:17:24 +0100 | [diff] [blame] | 2288 | vol[0] = ucontrol->value.integer.value[0]; |
| 2289 | vol[1] = ucontrol->value.integer.value[1]; |
| 2290 | if (kcontrol->private_value == DBRI_PLAY) { |
| 2291 | if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME) |
| 2292 | return -EINVAL; |
| 2293 | } else { |
| 2294 | if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN) |
| 2295 | return -EINVAL; |
| 2296 | } |
| 2297 | |
Takashi Iwai | 4581aa3 | 2007-11-20 18:31:22 +0100 | [diff] [blame] | 2298 | if (info->left_gain != vol[0]) { |
| 2299 | info->left_gain = vol[0]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2300 | changed = 1; |
| 2301 | } |
Takashi Iwai | 4581aa3 | 2007-11-20 18:31:22 +0100 | [diff] [blame] | 2302 | if (info->right_gain != vol[1]) { |
| 2303 | info->right_gain = vol[1]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2304 | changed = 1; |
| 2305 | } |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2306 | if (changed) { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2307 | /* First mute outputs, and wait 1/8000 sec (125 us) |
| 2308 | * to make sure this takes. This avoids clicking noises. |
| 2309 | */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2310 | cs4215_setdata(dbri, 1); |
| 2311 | udelay(125); |
| 2312 | cs4215_setdata(dbri, 0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2313 | } |
| 2314 | return changed; |
| 2315 | } |
| 2316 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2317 | static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol, |
| 2318 | struct snd_ctl_elem_info *uinfo) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2319 | { |
| 2320 | int mask = (kcontrol->private_value >> 16) & 0xff; |
| 2321 | |
| 2322 | uinfo->type = (mask == 1) ? |
| 2323 | SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 2324 | uinfo->count = 1; |
| 2325 | uinfo->value.integer.min = 0; |
| 2326 | uinfo->value.integer.max = mask; |
| 2327 | return 0; |
| 2328 | } |
| 2329 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2330 | static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol, |
| 2331 | struct snd_ctl_elem_value *ucontrol) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2332 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2333 | struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2334 | int elem = kcontrol->private_value & 0xff; |
| 2335 | int shift = (kcontrol->private_value >> 8) & 0xff; |
| 2336 | int mask = (kcontrol->private_value >> 16) & 0xff; |
| 2337 | int invert = (kcontrol->private_value >> 24) & 1; |
Takashi Iwai | 5e246b8 | 2008-08-08 17:12:47 +0200 | [diff] [blame] | 2338 | |
| 2339 | if (snd_BUG_ON(!dbri)) |
| 2340 | return -EINVAL; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2341 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2342 | if (elem < 4) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2343 | ucontrol->value.integer.value[0] = |
| 2344 | (dbri->mm.data[elem] >> shift) & mask; |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2345 | else |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2346 | ucontrol->value.integer.value[0] = |
| 2347 | (dbri->mm.ctrl[elem - 4] >> shift) & mask; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2348 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2349 | if (invert == 1) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2350 | ucontrol->value.integer.value[0] = |
| 2351 | mask - ucontrol->value.integer.value[0]; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2352 | return 0; |
| 2353 | } |
| 2354 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2355 | static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol, |
| 2356 | struct snd_ctl_elem_value *ucontrol) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2357 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2358 | struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2359 | int elem = kcontrol->private_value & 0xff; |
| 2360 | int shift = (kcontrol->private_value >> 8) & 0xff; |
| 2361 | int mask = (kcontrol->private_value >> 16) & 0xff; |
| 2362 | int invert = (kcontrol->private_value >> 24) & 1; |
| 2363 | int changed = 0; |
| 2364 | unsigned short val; |
Takashi Iwai | 5e246b8 | 2008-08-08 17:12:47 +0200 | [diff] [blame] | 2365 | |
| 2366 | if (snd_BUG_ON(!dbri)) |
| 2367 | return -EINVAL; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2368 | |
| 2369 | val = (ucontrol->value.integer.value[0] & mask); |
| 2370 | if (invert == 1) |
| 2371 | val = mask - val; |
| 2372 | val <<= shift; |
| 2373 | |
| 2374 | if (elem < 4) { |
| 2375 | dbri->mm.data[elem] = (dbri->mm.data[elem] & |
| 2376 | ~(mask << shift)) | val; |
| 2377 | changed = (val != dbri->mm.data[elem]); |
| 2378 | } else { |
| 2379 | dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & |
| 2380 | ~(mask << shift)) | val; |
| 2381 | changed = (val != dbri->mm.ctrl[elem - 4]); |
| 2382 | } |
| 2383 | |
| 2384 | dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " |
| 2385 | "mixer-value=%ld, mm-value=0x%x\n", |
| 2386 | mask, changed, ucontrol->value.integer.value[0], |
| 2387 | dbri->mm.data[elem & 3]); |
| 2388 | |
| 2389 | if (changed) { |
| 2390 | /* First mute outputs, and wait 1/8000 sec (125 us) |
| 2391 | * to make sure this takes. This avoids clicking noises. |
| 2392 | */ |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2393 | cs4215_setdata(dbri, 1); |
| 2394 | udelay(125); |
| 2395 | cs4215_setdata(dbri, 0); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2396 | } |
| 2397 | return changed; |
| 2398 | } |
| 2399 | |
| 2400 | /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control |
| 2401 | timeslots. Shift is the bit offset in the timeslot, mask defines the |
| 2402 | number of bits. invert is a boolean for use with attenuation. |
| 2403 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2404 | #define CS4215_SINGLE(xname, entry, shift, mask, invert) \ |
| 2405 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ |
| 2406 | .info = snd_cs4215_info_single, \ |
| 2407 | .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ |
| 2408 | .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \ |
| 2409 | ((invert) << 24) }, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2410 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2411 | static struct snd_kcontrol_new dbri_controls[] __devinitdata = { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2412 | { |
| 2413 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 2414 | .name = "Playback Volume", |
| 2415 | .info = snd_cs4215_info_volume, |
| 2416 | .get = snd_cs4215_get_volume, |
| 2417 | .put = snd_cs4215_put_volume, |
| 2418 | .private_value = DBRI_PLAY, |
| 2419 | }, |
| 2420 | CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) |
| 2421 | CS4215_SINGLE("Line out switch", 0, 6, 1, 0) |
| 2422 | CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) |
| 2423 | { |
| 2424 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
| 2425 | .name = "Capture Volume", |
| 2426 | .info = snd_cs4215_info_volume, |
| 2427 | .get = snd_cs4215_get_volume, |
| 2428 | .put = snd_cs4215_put_volume, |
| 2429 | .private_value = DBRI_REC, |
| 2430 | }, |
| 2431 | /* FIXME: mic/line switch */ |
| 2432 | CS4215_SINGLE("Line in switch", 2, 4, 1, 0) |
| 2433 | CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) |
| 2434 | CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) |
| 2435 | CS4215_SINGLE("Mic boost", 4, 4, 1, 1) |
| 2436 | }; |
| 2437 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2438 | static int __devinit snd_dbri_mixer(struct snd_card *card) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2439 | { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2440 | int idx, err; |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2441 | struct snd_dbri *dbri; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2442 | |
Takashi Iwai | 5e246b8 | 2008-08-08 17:12:47 +0200 | [diff] [blame] | 2443 | if (snd_BUG_ON(!card || !card->private_data)) |
| 2444 | return -EINVAL; |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2445 | dbri = card->private_data; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2446 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2447 | strcpy(card->mixername, card->shortname); |
| 2448 | |
Tobias Klauser | 6c2d8b5 | 2006-09-29 02:00:21 -0700 | [diff] [blame] | 2449 | for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) { |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2450 | err = snd_ctl_add(card, |
| 2451 | snd_ctl_new1(&dbri_controls[idx], dbri)); |
| 2452 | if (err < 0) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2453 | return err; |
| 2454 | } |
| 2455 | |
| 2456 | for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { |
| 2457 | dbri->stream_info[idx].left_gain = 0; |
| 2458 | dbri->stream_info[idx].right_gain = 0; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2459 | } |
| 2460 | |
| 2461 | return 0; |
| 2462 | } |
| 2463 | |
| 2464 | /**************************************************************************** |
| 2465 | /proc interface |
| 2466 | ****************************************************************************/ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2467 | static void dbri_regs_read(struct snd_info_entry *entry, |
| 2468 | struct snd_info_buffer *buffer) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2469 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2470 | struct snd_dbri *dbri = entry->private_data; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2471 | |
| 2472 | snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0)); |
| 2473 | snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2)); |
| 2474 | snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8)); |
| 2475 | snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9)); |
| 2476 | } |
| 2477 | |
| 2478 | #ifdef DBRI_DEBUG |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2479 | static void dbri_debug_read(struct snd_info_entry *entry, |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2480 | struct snd_info_buffer *buffer) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2481 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2482 | struct snd_dbri *dbri = entry->private_data; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2483 | int pipe; |
| 2484 | snd_iprintf(buffer, "debug=%d\n", dbri_debug); |
| 2485 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2486 | for (pipe = 0; pipe < 32; pipe++) { |
| 2487 | if (pipe_active(dbri, pipe)) { |
| 2488 | struct dbri_pipe *pptr = &dbri->pipes[pipe]; |
| 2489 | snd_iprintf(buffer, |
| 2490 | "Pipe %d: %s SDP=0x%x desc=%d, " |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 2491 | "len=%d next %d\n", |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2492 | pipe, |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2493 | (pptr->sdp & D_SDP_TO_SER) ? "output" : |
| 2494 | "input", |
Krzysztof Helt | 5fc3a2b | 2006-08-17 16:58:45 +0200 | [diff] [blame] | 2495 | pptr->sdp, pptr->desc, |
Krzysztof Helt | 294a30d | 2006-08-21 19:29:59 +0200 | [diff] [blame] | 2496 | pptr->length, pptr->nextpipe); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2497 | } |
| 2498 | } |
| 2499 | } |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2500 | #endif |
| 2501 | |
Adrian Bunk | e7bd3de | 2008-06-05 21:29:18 +0300 | [diff] [blame] | 2502 | static void __devinit snd_dbri_proc(struct snd_card *card) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2503 | { |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2504 | struct snd_dbri *dbri = card->private_data; |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2505 | struct snd_info_entry *entry; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2506 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2507 | if (!snd_card_proc_new(card, "regs", &entry)) |
Takashi Iwai | bf85020 | 2006-04-28 15:13:41 +0200 | [diff] [blame] | 2508 | snd_info_set_text_ops(entry, dbri, dbri_regs_read); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2509 | |
| 2510 | #ifdef DBRI_DEBUG |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2511 | if (!snd_card_proc_new(card, "debug", &entry)) { |
Takashi Iwai | bf85020 | 2006-04-28 15:13:41 +0200 | [diff] [blame] | 2512 | snd_info_set_text_ops(entry, dbri, dbri_debug_read); |
Takashi Iwai | 8cb7b63 | 2005-12-01 10:48:37 +0100 | [diff] [blame] | 2513 | entry->mode = S_IFREG | S_IRUGO; /* Readable only. */ |
| 2514 | } |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2515 | #endif |
| 2516 | } |
| 2517 | |
| 2518 | /* |
| 2519 | **************************************************************************** |
| 2520 | **************************** Initialization ******************************** |
| 2521 | **************************************************************************** |
| 2522 | */ |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2523 | static void snd_dbri_free(struct snd_dbri *dbri); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2524 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2525 | static int __devinit snd_dbri_create(struct snd_card *card, |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2526 | struct of_device *op, |
| 2527 | int irq, int dev) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2528 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2529 | struct snd_dbri *dbri = card->private_data; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2530 | int err; |
| 2531 | |
| 2532 | spin_lock_init(&dbri->lock); |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2533 | dbri->op = op; |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2534 | dbri->irq = irq; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2535 | |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2536 | dbri->dma = dma_alloc_coherent(&op->dev, |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2537 | sizeof(struct dbri_dma), |
| 2538 | &dbri->dma_dvma, GFP_ATOMIC); |
FUJITA Tomonori | be37664 | 2008-10-29 15:34:39 -0700 | [diff] [blame] | 2539 | if (!dbri->dma) |
| 2540 | return -ENOMEM; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2541 | memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); |
| 2542 | |
| 2543 | dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n", |
| 2544 | dbri->dma, dbri->dma_dvma); |
| 2545 | |
| 2546 | /* Map the registers into memory. */ |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2547 | dbri->regs_size = resource_size(&op->resource[0]); |
| 2548 | dbri->regs = of_ioremap(&op->resource[0], 0, |
| 2549 | dbri->regs_size, "DBRI Registers"); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2550 | if (!dbri->regs) { |
| 2551 | printk(KERN_ERR "DBRI: could not allocate registers\n"); |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2552 | dma_free_coherent(&op->dev, sizeof(struct dbri_dma), |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2553 | (void *)dbri->dma, dbri->dma_dvma); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2554 | return -EIO; |
| 2555 | } |
| 2556 | |
Thomas Gleixner | 65ca68b | 2006-07-01 19:29:46 -0700 | [diff] [blame] | 2557 | err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED, |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2558 | "DBRI audio", dbri); |
| 2559 | if (err) { |
| 2560 | printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq); |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2561 | of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size); |
| 2562 | dma_free_coherent(&op->dev, sizeof(struct dbri_dma), |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2563 | (void *)dbri->dma, dbri->dma_dvma); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2564 | return err; |
| 2565 | } |
| 2566 | |
| 2567 | /* Do low level initialization of the DBRI and CS4215 chips */ |
| 2568 | dbri_initialize(dbri); |
| 2569 | err = cs4215_init(dbri); |
| 2570 | if (err) { |
| 2571 | snd_dbri_free(dbri); |
| 2572 | return err; |
| 2573 | } |
| 2574 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2575 | return 0; |
| 2576 | } |
| 2577 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2578 | static void snd_dbri_free(struct snd_dbri *dbri) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2579 | { |
| 2580 | dprintk(D_GEN, "snd_dbri_free\n"); |
| 2581 | dbri_reset(dbri); |
| 2582 | |
| 2583 | if (dbri->irq) |
| 2584 | free_irq(dbri->irq, dbri); |
| 2585 | |
| 2586 | if (dbri->regs) |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2587 | of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2588 | |
| 2589 | if (dbri->dma) |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2590 | dma_free_coherent(&dbri->op->dev, |
David S. Miller | 738f2b7 | 2008-08-27 18:09:11 -0700 | [diff] [blame] | 2591 | sizeof(struct dbri_dma), |
| 2592 | (void *)dbri->dma, dbri->dma_dvma); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2593 | } |
| 2594 | |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2595 | static int __devinit dbri_probe(struct of_device *op, const struct of_device_id *match) |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2596 | { |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2597 | struct snd_dbri *dbri; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2598 | struct resource *rp; |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2599 | struct snd_card *card; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2600 | static int dev = 0; |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2601 | int irq; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2602 | int err; |
| 2603 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2604 | if (dev >= SNDRV_CARDS) |
| 2605 | return -ENODEV; |
| 2606 | if (!enable[dev]) { |
| 2607 | dev++; |
| 2608 | return -ENOENT; |
| 2609 | } |
| 2610 | |
Grant Likely | 1636f8a | 2010-06-18 11:09:58 -0600 | [diff] [blame] | 2611 | irq = op->archdata.irqs[0]; |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2612 | if (irq <= 0) { |
| 2613 | printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev); |
Martin Habets | 4338829 | 2005-09-10 15:39:00 +0200 | [diff] [blame] | 2614 | return -ENODEV; |
| 2615 | } |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2616 | |
Takashi Iwai | bd7dd77 | 2008-12-28 16:45:02 +0100 | [diff] [blame] | 2617 | err = snd_card_create(index[dev], id[dev], THIS_MODULE, |
| 2618 | sizeof(struct snd_dbri), &card); |
| 2619 | if (err < 0) |
| 2620 | return err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2621 | |
| 2622 | strcpy(card->driver, "DBRI"); |
| 2623 | strcpy(card->shortname, "Sun DBRI"); |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2624 | rp = &op->resource[0]; |
Andrew Morton | 5863aa6 | 2006-07-03 00:24:22 -0700 | [diff] [blame] | 2625 | sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d", |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2626 | card->shortname, |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2627 | rp->flags & 0xffL, (unsigned long long)rp->start, irq); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2628 | |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2629 | err = snd_dbri_create(card, op, irq, dev); |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2630 | if (err < 0) { |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2631 | snd_card_free(card); |
| 2632 | return err; |
| 2633 | } |
| 2634 | |
Takashi Iwai | 475675d | 2005-11-17 15:11:51 +0100 | [diff] [blame] | 2635 | dbri = card->private_data; |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2636 | err = snd_dbri_pcm(card); |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2637 | if (err < 0) |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame] | 2638 | goto _err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2639 | |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2640 | err = snd_dbri_mixer(card); |
Krzysztof Helt | cf68d21 | 2007-09-04 13:09:20 +0200 | [diff] [blame] | 2641 | if (err < 0) |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame] | 2642 | goto _err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2643 | |
| 2644 | /* /proc file handling */ |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2645 | snd_dbri_proc(card); |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2646 | dev_set_drvdata(&op->dev, card); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2647 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2648 | err = snd_card_register(card); |
| 2649 | if (err < 0) |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame] | 2650 | goto _err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2651 | |
| 2652 | printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n", |
| 2653 | dev, dbri->regs, |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 2654 | dbri->irq, op->dev.of_node->name[9], dbri->mm.version); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2655 | dev++; |
| 2656 | |
| 2657 | return 0; |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame] | 2658 | |
Krzysztof Helt | 098ccbc | 2007-08-20 12:30:54 +0200 | [diff] [blame] | 2659 | _err: |
Takashi Iwai | 16dab54 | 2005-09-05 17:17:58 +0200 | [diff] [blame] | 2660 | snd_dbri_free(dbri); |
| 2661 | snd_card_free(card); |
| 2662 | return err; |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2663 | } |
| 2664 | |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2665 | static int __devexit dbri_remove(struct of_device *op) |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2666 | { |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2667 | struct snd_card *card = dev_get_drvdata(&op->dev); |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2668 | |
| 2669 | snd_dbri_free(card->private_data); |
| 2670 | snd_card_free(card); |
| 2671 | |
David S. Miller | 2bd320f | 2008-08-27 00:30:59 -0700 | [diff] [blame] | 2672 | dev_set_drvdata(&op->dev, NULL); |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2673 | |
| 2674 | return 0; |
| 2675 | } |
| 2676 | |
David S. Miller | fd09831 | 2008-08-31 01:23:17 -0700 | [diff] [blame] | 2677 | static const struct of_device_id dbri_match[] = { |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2678 | { |
| 2679 | .name = "SUNW,DBRIe", |
| 2680 | }, |
| 2681 | { |
| 2682 | .name = "SUNW,DBRIf", |
| 2683 | }, |
| 2684 | {}, |
| 2685 | }; |
| 2686 | |
| 2687 | MODULE_DEVICE_TABLE(of, dbri_match); |
| 2688 | |
| 2689 | static struct of_platform_driver dbri_sbus_driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 2690 | .driver = { |
| 2691 | .name = "dbri", |
| 2692 | .owner = THIS_MODULE, |
| 2693 | .of_match_table = dbri_match, |
| 2694 | }, |
Krzysztof Helt | afeacfd | 2007-09-05 15:05:08 +0200 | [diff] [blame] | 2695 | .probe = dbri_probe, |
| 2696 | .remove = __devexit_p(dbri_remove), |
| 2697 | }; |
| 2698 | |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2699 | /* Probe for the dbri chip and then attach the driver. */ |
| 2700 | static int __init dbri_init(void) |
| 2701 | { |
Grant Likely | 1ab1d63 | 2010-06-24 15:14:37 -0600 | [diff] [blame^] | 2702 | return of_register_platform_driver(&dbri_sbus_driver); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2703 | } |
| 2704 | |
| 2705 | static void __exit dbri_exit(void) |
| 2706 | { |
Grant Likely | 1ab1d63 | 2010-06-24 15:14:37 -0600 | [diff] [blame^] | 2707 | of_unregister_platform_driver(&dbri_sbus_driver); |
Takashi Iwai | 1bd9deb | 2005-06-30 18:26:20 +0200 | [diff] [blame] | 2708 | } |
| 2709 | |
| 2710 | module_init(dbri_init); |
| 2711 | module_exit(dbri_exit); |