Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 1 | /* |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
| 3 | * Jaswinder Singh <jassi.brar@samsung.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/workqueue.h> |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 23 | #include <linux/interrupt.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 24 | #include <linux/delay.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/platform_device.h> |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 28 | #include <linux/pm_runtime.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 29 | #include <linux/spi/spi.h> |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 30 | #include <linux/gpio.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 31 | |
| 32 | #include <mach/dma.h> |
Jassi Brar | e6b873c | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 33 | #include <plat/s3c64xx-spi.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 34 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 35 | #define MAX_SPI_PORTS 3 |
| 36 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 37 | /* Registers and bit-fields */ |
| 38 | |
| 39 | #define S3C64XX_SPI_CH_CFG 0x00 |
| 40 | #define S3C64XX_SPI_CLK_CFG 0x04 |
| 41 | #define S3C64XX_SPI_MODE_CFG 0x08 |
| 42 | #define S3C64XX_SPI_SLAVE_SEL 0x0C |
| 43 | #define S3C64XX_SPI_INT_EN 0x10 |
| 44 | #define S3C64XX_SPI_STATUS 0x14 |
| 45 | #define S3C64XX_SPI_TX_DATA 0x18 |
| 46 | #define S3C64XX_SPI_RX_DATA 0x1C |
| 47 | #define S3C64XX_SPI_PACKET_CNT 0x20 |
| 48 | #define S3C64XX_SPI_PENDING_CLR 0x24 |
| 49 | #define S3C64XX_SPI_SWAP_CFG 0x28 |
| 50 | #define S3C64XX_SPI_FB_CLK 0x2C |
| 51 | |
| 52 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ |
| 53 | #define S3C64XX_SPI_CH_SW_RST (1<<5) |
| 54 | #define S3C64XX_SPI_CH_SLAVE (1<<4) |
| 55 | #define S3C64XX_SPI_CPOL_L (1<<3) |
| 56 | #define S3C64XX_SPI_CPHA_B (1<<2) |
| 57 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) |
| 58 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) |
| 59 | |
| 60 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) |
| 61 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 |
| 62 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) |
| 63 | #define S3C64XX_SPI_PSR_MASK 0xff |
| 64 | |
| 65 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) |
| 66 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) |
| 67 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) |
| 68 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) |
| 69 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) |
| 70 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) |
| 71 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) |
| 72 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) |
| 73 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) |
| 74 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) |
| 75 | #define S3C64XX_SPI_MODE_4BURST (1<<0) |
| 76 | |
| 77 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) |
| 78 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) |
| 79 | |
| 80 | #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL) |
| 81 | |
| 82 | #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \ |
| 83 | (c)->regs + S3C64XX_SPI_SLAVE_SEL) |
| 84 | |
| 85 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
| 86 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) |
| 87 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) |
| 88 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) |
| 89 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) |
| 90 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) |
| 91 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) |
| 92 | |
| 93 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) |
| 94 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) |
| 95 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) |
| 96 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) |
| 97 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) |
| 98 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) |
| 99 | |
| 100 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) |
| 101 | |
| 102 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) |
| 103 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) |
| 104 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) |
| 105 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) |
| 106 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) |
| 107 | |
| 108 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) |
| 109 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) |
| 110 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) |
| 111 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) |
| 112 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) |
| 113 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) |
| 114 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) |
| 115 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) |
| 116 | |
| 117 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) |
| 118 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 119 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
| 120 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ |
| 121 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) |
| 122 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) |
| 123 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ |
| 124 | FIFO_LVL_MASK(i)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 125 | |
| 126 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff |
| 127 | #define S3C64XX_SPI_TRAILCNT_OFF 19 |
| 128 | |
| 129 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT |
| 130 | |
| 131 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
| 132 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 133 | #define RXBUSY (1<<2) |
| 134 | #define TXBUSY (1<<3) |
| 135 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 136 | struct s3c64xx_spi_dma_data { |
| 137 | unsigned ch; |
| 138 | enum dma_data_direction direction; |
| 139 | enum dma_ch dmach; |
| 140 | }; |
| 141 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 142 | /** |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 143 | * struct s3c64xx_spi_info - SPI Controller hardware info |
| 144 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. |
| 145 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. |
| 146 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. |
| 147 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. |
| 148 | * @clk_from_cmu: True, if the controller does not include a clock mux and |
| 149 | * prescaler unit. |
| 150 | * |
| 151 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but |
| 152 | * differ in some aspects such as the size of the fifo and spi bus clock |
| 153 | * setup. Such differences are specified to the driver using this structure |
| 154 | * which is provided as driver data to the driver. |
| 155 | */ |
| 156 | struct s3c64xx_spi_port_config { |
| 157 | int fifo_lvl_mask[MAX_SPI_PORTS]; |
| 158 | int rx_lvl_offset; |
| 159 | int tx_st_done; |
| 160 | bool high_speed; |
| 161 | bool clk_from_cmu; |
| 162 | }; |
| 163 | |
| 164 | /** |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 165 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. |
| 166 | * @clk: Pointer to the spi clock. |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 167 | * @src_clk: Pointer to the clock used to generate SPI signals. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 168 | * @master: Pointer to the SPI Protocol master. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 169 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
| 170 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 171 | * @queue: To log SPI xfer requests. |
| 172 | * @lock: Controller specific lock. |
| 173 | * @state: Set of FLAGS to indicate status. |
| 174 | * @rx_dmach: Controller's DMA channel for Rx. |
| 175 | * @tx_dmach: Controller's DMA channel for Tx. |
| 176 | * @sfr_start: BUS address of SPI controller regs. |
| 177 | * @regs: Pointer to ioremap'ed controller registers. |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 178 | * @irq: interrupt |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 179 | * @xfer_completion: To indicate completion of xfer task. |
| 180 | * @cur_mode: Stores the active configuration of the controller. |
| 181 | * @cur_bpw: Stores the active bits per word settings. |
| 182 | * @cur_speed: Stores the active xfer clock speed. |
| 183 | */ |
| 184 | struct s3c64xx_spi_driver_data { |
| 185 | void __iomem *regs; |
| 186 | struct clk *clk; |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 187 | struct clk *src_clk; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 188 | struct platform_device *pdev; |
| 189 | struct spi_master *master; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 190 | struct s3c64xx_spi_info *cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 191 | struct spi_device *tgl_spi; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 192 | struct list_head queue; |
| 193 | spinlock_t lock; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 194 | unsigned long sfr_start; |
| 195 | struct completion xfer_completion; |
| 196 | unsigned state; |
| 197 | unsigned cur_mode, cur_bpw; |
| 198 | unsigned cur_speed; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 199 | struct s3c64xx_spi_dma_data rx_dma; |
| 200 | struct s3c64xx_spi_dma_data tx_dma; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 201 | struct samsung_dma_ops *ops; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 202 | struct s3c64xx_spi_port_config *port_conf; |
| 203 | unsigned int port_id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | static struct s3c2410_dma_client s3c64xx_spi_dma_client = { |
| 207 | .name = "samsung-spi-dma", |
| 208 | }; |
| 209 | |
| 210 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
| 211 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 212 | void __iomem *regs = sdd->regs; |
| 213 | unsigned long loops; |
| 214 | u32 val; |
| 215 | |
| 216 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 217 | |
| 218 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 219 | val |= S3C64XX_SPI_CH_SW_RST; |
| 220 | val &= ~S3C64XX_SPI_CH_HS_EN; |
| 221 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 222 | |
| 223 | /* Flush TxFIFO*/ |
| 224 | loops = msecs_to_loops(1); |
| 225 | do { |
| 226 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 227 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 228 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 229 | if (loops == 0) |
| 230 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); |
| 231 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 232 | /* Flush RxFIFO*/ |
| 233 | loops = msecs_to_loops(1); |
| 234 | do { |
| 235 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 236 | if (RX_FIFO_LVL(val, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 237 | readl(regs + S3C64XX_SPI_RX_DATA); |
| 238 | else |
| 239 | break; |
| 240 | } while (loops--); |
| 241 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 242 | if (loops == 0) |
| 243 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); |
| 244 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 245 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 246 | val &= ~S3C64XX_SPI_CH_SW_RST; |
| 247 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 248 | |
| 249 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 250 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 251 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 252 | |
| 253 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 254 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); |
| 255 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 256 | } |
| 257 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 258 | static void s3c64xx_spi_dmacb(void *data) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 259 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 260 | struct s3c64xx_spi_driver_data *sdd; |
| 261 | struct s3c64xx_spi_dma_data *dma = data; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 262 | unsigned long flags; |
| 263 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 264 | if (dma->direction == DMA_DEV_TO_MEM) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 265 | sdd = container_of(data, |
| 266 | struct s3c64xx_spi_driver_data, rx_dma); |
| 267 | else |
| 268 | sdd = container_of(data, |
| 269 | struct s3c64xx_spi_driver_data, tx_dma); |
| 270 | |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 271 | spin_lock_irqsave(&sdd->lock, flags); |
| 272 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 273 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 274 | sdd->state &= ~RXBUSY; |
| 275 | if (!(sdd->state & TXBUSY)) |
| 276 | complete(&sdd->xfer_completion); |
| 277 | } else { |
| 278 | sdd->state &= ~TXBUSY; |
| 279 | if (!(sdd->state & RXBUSY)) |
| 280 | complete(&sdd->xfer_completion); |
| 281 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 282 | |
| 283 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 284 | } |
| 285 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 286 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
| 287 | unsigned len, dma_addr_t buf) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 288 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 289 | struct s3c64xx_spi_driver_data *sdd; |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 290 | struct samsung_dma_prep info; |
| 291 | struct samsung_dma_config config; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 292 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 293 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 294 | sdd = container_of((void *)dma, |
| 295 | struct s3c64xx_spi_driver_data, rx_dma); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 296 | config.direction = sdd->rx_dma.direction; |
| 297 | config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA; |
| 298 | config.width = sdd->cur_bpw / 8; |
| 299 | sdd->ops->config(sdd->rx_dma.ch, &config); |
| 300 | } else { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 301 | sdd = container_of((void *)dma, |
| 302 | struct s3c64xx_spi_driver_data, tx_dma); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 303 | config.direction = sdd->tx_dma.direction; |
| 304 | config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA; |
| 305 | config.width = sdd->cur_bpw / 8; |
| 306 | sdd->ops->config(sdd->tx_dma.ch, &config); |
| 307 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 308 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 309 | info.cap = DMA_SLAVE; |
| 310 | info.len = len; |
| 311 | info.fp = s3c64xx_spi_dmacb; |
| 312 | info.fp_param = dma; |
| 313 | info.direction = dma->direction; |
| 314 | info.buf = buf; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 315 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 316 | sdd->ops->prepare(dma->ch, &info); |
| 317 | sdd->ops->trigger(dma->ch); |
| 318 | } |
| 319 | |
| 320 | static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) |
| 321 | { |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 322 | struct samsung_dma_req req; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 323 | |
| 324 | sdd->ops = samsung_dma_get_ops(); |
| 325 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 326 | req.cap = DMA_SLAVE; |
| 327 | req.client = &s3c64xx_spi_dma_client; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 328 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 329 | sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req); |
| 330 | sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 331 | |
| 332 | return 1; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 333 | } |
| 334 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 335 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
| 336 | struct spi_device *spi, |
| 337 | struct spi_transfer *xfer, int dma_mode) |
| 338 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 339 | void __iomem *regs = sdd->regs; |
| 340 | u32 modecfg, chcfg; |
| 341 | |
| 342 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 343 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 344 | |
| 345 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); |
| 346 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; |
| 347 | |
| 348 | if (dma_mode) { |
| 349 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; |
| 350 | } else { |
| 351 | /* Always shift in data in FIFO, even if xfer is Tx only, |
| 352 | * this helps setting PCKT_CNT value for generating clocks |
| 353 | * as exactly needed. |
| 354 | */ |
| 355 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 356 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 357 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 358 | regs + S3C64XX_SPI_PACKET_CNT); |
| 359 | } |
| 360 | |
| 361 | if (xfer->tx_buf != NULL) { |
| 362 | sdd->state |= TXBUSY; |
| 363 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; |
| 364 | if (dma_mode) { |
| 365 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 366 | prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 367 | } else { |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 368 | switch (sdd->cur_bpw) { |
| 369 | case 32: |
| 370 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, |
| 371 | xfer->tx_buf, xfer->len / 4); |
| 372 | break; |
| 373 | case 16: |
| 374 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, |
| 375 | xfer->tx_buf, xfer->len / 2); |
| 376 | break; |
| 377 | default: |
| 378 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, |
| 379 | xfer->tx_buf, xfer->len); |
| 380 | break; |
| 381 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 382 | } |
| 383 | } |
| 384 | |
| 385 | if (xfer->rx_buf != NULL) { |
| 386 | sdd->state |= RXBUSY; |
| 387 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 388 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 389 | && !(sdd->cur_mode & SPI_CPHA)) |
| 390 | chcfg |= S3C64XX_SPI_CH_HS_EN; |
| 391 | |
| 392 | if (dma_mode) { |
| 393 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; |
| 394 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 395 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 396 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 397 | regs + S3C64XX_SPI_PACKET_CNT); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 398 | prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 399 | } |
| 400 | } |
| 401 | |
| 402 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); |
| 403 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); |
| 404 | } |
| 405 | |
| 406 | static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, |
| 407 | struct spi_device *spi) |
| 408 | { |
| 409 | struct s3c64xx_spi_csinfo *cs; |
| 410 | |
| 411 | if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */ |
| 412 | if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ |
| 413 | /* Deselect the last toggled device */ |
| 414 | cs = sdd->tgl_spi->controller_data; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 415 | gpio_set_value(cs->line, |
| 416 | spi->mode & SPI_CS_HIGH ? 0 : 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 417 | } |
| 418 | sdd->tgl_spi = NULL; |
| 419 | } |
| 420 | |
| 421 | cs = spi->controller_data; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 422 | gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, |
| 426 | struct spi_transfer *xfer, int dma_mode) |
| 427 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 428 | void __iomem *regs = sdd->regs; |
| 429 | unsigned long val; |
| 430 | int ms; |
| 431 | |
| 432 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
| 433 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; |
Mark Brown | 9d8f86b | 2010-09-07 16:37:52 +0100 | [diff] [blame] | 434 | ms += 10; /* some tolerance */ |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 435 | |
| 436 | if (dma_mode) { |
| 437 | val = msecs_to_jiffies(ms) + 10; |
| 438 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); |
| 439 | } else { |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 440 | u32 status; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 441 | val = msecs_to_loops(ms); |
| 442 | do { |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 443 | status = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 444 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 445 | } |
| 446 | |
| 447 | if (!val) |
| 448 | return -EIO; |
| 449 | |
| 450 | if (dma_mode) { |
| 451 | u32 status; |
| 452 | |
| 453 | /* |
| 454 | * DmaTx returns after simply writing data in the FIFO, |
| 455 | * w/o waiting for real transmission on the bus to finish. |
| 456 | * DmaRx returns only after Dma read data from FIFO which |
| 457 | * needs bus transmission to finish, so we don't worry if |
| 458 | * Xfer involved Rx(with or without Tx). |
| 459 | */ |
| 460 | if (xfer->rx_buf == NULL) { |
| 461 | val = msecs_to_loops(10); |
| 462 | status = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 463 | while ((TX_FIFO_LVL(status, sdd) |
| 464 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 465 | && --val) { |
| 466 | cpu_relax(); |
| 467 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 468 | } |
| 469 | |
| 470 | if (!val) |
| 471 | return -EIO; |
| 472 | } |
| 473 | } else { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 474 | /* If it was only Tx */ |
| 475 | if (xfer->rx_buf == NULL) { |
| 476 | sdd->state &= ~TXBUSY; |
| 477 | return 0; |
| 478 | } |
| 479 | |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 480 | switch (sdd->cur_bpw) { |
| 481 | case 32: |
| 482 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, |
| 483 | xfer->rx_buf, xfer->len / 4); |
| 484 | break; |
| 485 | case 16: |
| 486 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, |
| 487 | xfer->rx_buf, xfer->len / 2); |
| 488 | break; |
| 489 | default: |
| 490 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, |
| 491 | xfer->rx_buf, xfer->len); |
| 492 | break; |
| 493 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 494 | sdd->state &= ~RXBUSY; |
| 495 | } |
| 496 | |
| 497 | return 0; |
| 498 | } |
| 499 | |
| 500 | static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, |
| 501 | struct spi_device *spi) |
| 502 | { |
| 503 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 504 | |
| 505 | if (sdd->tgl_spi == spi) |
| 506 | sdd->tgl_spi = NULL; |
| 507 | |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 508 | gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 509 | } |
| 510 | |
| 511 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
| 512 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 513 | void __iomem *regs = sdd->regs; |
| 514 | u32 val; |
| 515 | |
| 516 | /* Disable Clock */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 517 | if (sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 518 | clk_disable(sdd->src_clk); |
| 519 | } else { |
| 520 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 521 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; |
| 522 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 523 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 524 | |
| 525 | /* Set Polarity and Phase */ |
| 526 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 527 | val &= ~(S3C64XX_SPI_CH_SLAVE | |
| 528 | S3C64XX_SPI_CPOL_L | |
| 529 | S3C64XX_SPI_CPHA_B); |
| 530 | |
| 531 | if (sdd->cur_mode & SPI_CPOL) |
| 532 | val |= S3C64XX_SPI_CPOL_L; |
| 533 | |
| 534 | if (sdd->cur_mode & SPI_CPHA) |
| 535 | val |= S3C64XX_SPI_CPHA_B; |
| 536 | |
| 537 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 538 | |
| 539 | /* Set Channel & DMA Mode */ |
| 540 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 541 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK |
| 542 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); |
| 543 | |
| 544 | switch (sdd->cur_bpw) { |
| 545 | case 32: |
| 546 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 547 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 548 | break; |
| 549 | case 16: |
| 550 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 551 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 552 | break; |
| 553 | default: |
| 554 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 555 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 556 | break; |
| 557 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 558 | |
| 559 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 560 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 561 | if (sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 562 | /* Configure Clock */ |
| 563 | /* There is half-multiplier before the SPI */ |
| 564 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
| 565 | /* Enable Clock */ |
| 566 | clk_enable(sdd->src_clk); |
| 567 | } else { |
| 568 | /* Configure Clock */ |
| 569 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 570 | val &= ~S3C64XX_SPI_PSR_MASK; |
| 571 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) |
| 572 | & S3C64XX_SPI_PSR_MASK); |
| 573 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 574 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 575 | /* Enable Clock */ |
| 576 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 577 | val |= S3C64XX_SPI_ENCLK_ENABLE; |
| 578 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 579 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 580 | } |
| 581 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 582 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
| 583 | |
| 584 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 585 | struct spi_message *msg) |
| 586 | { |
| 587 | struct device *dev = &sdd->pdev->dev; |
| 588 | struct spi_transfer *xfer; |
| 589 | |
| 590 | if (msg->is_dma_mapped) |
| 591 | return 0; |
| 592 | |
| 593 | /* First mark all xfer unmapped */ |
| 594 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 595 | xfer->rx_dma = XFER_DMAADDR_INVALID; |
| 596 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 597 | } |
| 598 | |
| 599 | /* Map until end or first fail */ |
| 600 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 601 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 602 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | e02ddd4 | 2010-09-29 17:31:31 +0900 | [diff] [blame] | 603 | continue; |
| 604 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 605 | if (xfer->tx_buf != NULL) { |
Jassi Brar | 251ee47 | 2010-09-03 10:36:26 +0900 | [diff] [blame] | 606 | xfer->tx_dma = dma_map_single(dev, |
| 607 | (void *)xfer->tx_buf, xfer->len, |
| 608 | DMA_TO_DEVICE); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 609 | if (dma_mapping_error(dev, xfer->tx_dma)) { |
| 610 | dev_err(dev, "dma_map_single Tx failed\n"); |
| 611 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 612 | return -ENOMEM; |
| 613 | } |
| 614 | } |
| 615 | |
| 616 | if (xfer->rx_buf != NULL) { |
| 617 | xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, |
| 618 | xfer->len, DMA_FROM_DEVICE); |
| 619 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
| 620 | dev_err(dev, "dma_map_single Rx failed\n"); |
| 621 | dma_unmap_single(dev, xfer->tx_dma, |
| 622 | xfer->len, DMA_TO_DEVICE); |
| 623 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 624 | xfer->rx_dma = XFER_DMAADDR_INVALID; |
| 625 | return -ENOMEM; |
| 626 | } |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | return 0; |
| 631 | } |
| 632 | |
| 633 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 634 | struct spi_message *msg) |
| 635 | { |
| 636 | struct device *dev = &sdd->pdev->dev; |
| 637 | struct spi_transfer *xfer; |
| 638 | |
| 639 | if (msg->is_dma_mapped) |
| 640 | return; |
| 641 | |
| 642 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 643 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 644 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | e02ddd4 | 2010-09-29 17:31:31 +0900 | [diff] [blame] | 645 | continue; |
| 646 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 647 | if (xfer->rx_buf != NULL |
| 648 | && xfer->rx_dma != XFER_DMAADDR_INVALID) |
| 649 | dma_unmap_single(dev, xfer->rx_dma, |
| 650 | xfer->len, DMA_FROM_DEVICE); |
| 651 | |
| 652 | if (xfer->tx_buf != NULL |
| 653 | && xfer->tx_dma != XFER_DMAADDR_INVALID) |
| 654 | dma_unmap_single(dev, xfer->tx_dma, |
| 655 | xfer->len, DMA_TO_DEVICE); |
| 656 | } |
| 657 | } |
| 658 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 659 | static int s3c64xx_spi_transfer_one_message(struct spi_master *master, |
| 660 | struct spi_message *msg) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 661 | { |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 662 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 663 | struct spi_device *spi = msg->spi; |
| 664 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 665 | struct spi_transfer *xfer; |
| 666 | int status = 0, cs_toggle = 0; |
| 667 | u32 speed; |
| 668 | u8 bpw; |
| 669 | |
| 670 | /* If Master's(controller) state differs from that needed by Slave */ |
| 671 | if (sdd->cur_speed != spi->max_speed_hz |
| 672 | || sdd->cur_mode != spi->mode |
| 673 | || sdd->cur_bpw != spi->bits_per_word) { |
| 674 | sdd->cur_bpw = spi->bits_per_word; |
| 675 | sdd->cur_speed = spi->max_speed_hz; |
| 676 | sdd->cur_mode = spi->mode; |
| 677 | s3c64xx_spi_config(sdd); |
| 678 | } |
| 679 | |
| 680 | /* Map all the transfers if needed */ |
| 681 | if (s3c64xx_spi_map_mssg(sdd, msg)) { |
| 682 | dev_err(&spi->dev, |
| 683 | "Xfer: Unable to map message buffers!\n"); |
| 684 | status = -ENOMEM; |
| 685 | goto out; |
| 686 | } |
| 687 | |
| 688 | /* Configure feedback delay */ |
| 689 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); |
| 690 | |
| 691 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 692 | |
| 693 | unsigned long flags; |
| 694 | int use_dma; |
| 695 | |
| 696 | INIT_COMPLETION(sdd->xfer_completion); |
| 697 | |
| 698 | /* Only BPW and Speed may change across transfers */ |
| 699 | bpw = xfer->bits_per_word ? : spi->bits_per_word; |
| 700 | speed = xfer->speed_hz ? : spi->max_speed_hz; |
| 701 | |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 702 | if (xfer->len % (bpw / 8)) { |
| 703 | dev_err(&spi->dev, |
| 704 | "Xfer length(%u) not a multiple of word size(%u)\n", |
| 705 | xfer->len, bpw / 8); |
| 706 | status = -EIO; |
| 707 | goto out; |
| 708 | } |
| 709 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 710 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
| 711 | sdd->cur_bpw = bpw; |
| 712 | sdd->cur_speed = speed; |
| 713 | s3c64xx_spi_config(sdd); |
| 714 | } |
| 715 | |
| 716 | /* Polling method for xfers not bigger than FIFO capacity */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 717 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 718 | use_dma = 0; |
| 719 | else |
| 720 | use_dma = 1; |
| 721 | |
| 722 | spin_lock_irqsave(&sdd->lock, flags); |
| 723 | |
| 724 | /* Pending only which is to be done */ |
| 725 | sdd->state &= ~RXBUSY; |
| 726 | sdd->state &= ~TXBUSY; |
| 727 | |
| 728 | enable_datapath(sdd, spi, xfer, use_dma); |
| 729 | |
| 730 | /* Slave Select */ |
| 731 | enable_cs(sdd, spi); |
| 732 | |
| 733 | /* Start the signals */ |
| 734 | S3C64XX_SPI_ACT(sdd); |
| 735 | |
| 736 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 737 | |
| 738 | status = wait_for_xfer(sdd, xfer, use_dma); |
| 739 | |
| 740 | /* Quiese the signals */ |
| 741 | S3C64XX_SPI_DEACT(sdd); |
| 742 | |
| 743 | if (status) { |
Joe Perches | 8a349d4 | 2010-02-02 07:22:13 +0000 | [diff] [blame] | 744 | dev_err(&spi->dev, "I/O Error: " |
| 745 | "rx-%d tx-%d res:rx-%c tx-%c len-%d\n", |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 746 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
| 747 | (sdd->state & RXBUSY) ? 'f' : 'p', |
| 748 | (sdd->state & TXBUSY) ? 'f' : 'p', |
| 749 | xfer->len); |
| 750 | |
| 751 | if (use_dma) { |
| 752 | if (xfer->tx_buf != NULL |
| 753 | && (sdd->state & TXBUSY)) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 754 | sdd->ops->stop(sdd->tx_dma.ch); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 755 | if (xfer->rx_buf != NULL |
| 756 | && (sdd->state & RXBUSY)) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 757 | sdd->ops->stop(sdd->rx_dma.ch); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 758 | } |
| 759 | |
| 760 | goto out; |
| 761 | } |
| 762 | |
| 763 | if (xfer->delay_usecs) |
| 764 | udelay(xfer->delay_usecs); |
| 765 | |
| 766 | if (xfer->cs_change) { |
| 767 | /* Hint that the next mssg is gonna be |
| 768 | for the same device */ |
| 769 | if (list_is_last(&xfer->transfer_list, |
| 770 | &msg->transfers)) |
| 771 | cs_toggle = 1; |
| 772 | else |
| 773 | disable_cs(sdd, spi); |
| 774 | } |
| 775 | |
| 776 | msg->actual_length += xfer->len; |
| 777 | |
| 778 | flush_fifo(sdd); |
| 779 | } |
| 780 | |
| 781 | out: |
| 782 | if (!cs_toggle || status) |
| 783 | disable_cs(sdd, spi); |
| 784 | else |
| 785 | sdd->tgl_spi = spi; |
| 786 | |
| 787 | s3c64xx_spi_unmap_mssg(sdd, msg); |
| 788 | |
| 789 | msg->status = status; |
| 790 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 791 | spi_finalize_current_message(master); |
| 792 | |
| 793 | return 0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 794 | } |
| 795 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 796 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 797 | { |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 798 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 799 | |
| 800 | /* Acquire DMA channels */ |
| 801 | while (!acquire_dma(sdd)) |
| 802 | msleep(10); |
| 803 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 804 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 805 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 806 | return 0; |
| 807 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 808 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 809 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) |
| 810 | { |
| 811 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 812 | |
| 813 | /* Free DMA channels */ |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 814 | sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client); |
| 815 | sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 816 | |
| 817 | pm_runtime_put(&sdd->pdev->dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 818 | |
| 819 | return 0; |
| 820 | } |
| 821 | |
| 822 | /* |
| 823 | * Here we only check the validity of requested configuration |
| 824 | * and save the configuration in a local data-structure. |
| 825 | * The controller is actually configured only just before we |
| 826 | * get a message to transfer. |
| 827 | */ |
| 828 | static int s3c64xx_spi_setup(struct spi_device *spi) |
| 829 | { |
| 830 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 831 | struct s3c64xx_spi_driver_data *sdd; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 832 | struct s3c64xx_spi_info *sci; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 833 | struct spi_message *msg; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 834 | unsigned long flags; |
| 835 | int err = 0; |
| 836 | |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 837 | if (cs == NULL) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 838 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
| 839 | return -ENODEV; |
| 840 | } |
| 841 | |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 842 | if (!spi_get_ctldata(spi)) { |
| 843 | err = gpio_request(cs->line, dev_name(&spi->dev)); |
| 844 | if (err) { |
| 845 | dev_err(&spi->dev, "request for slave select gpio " |
| 846 | "line [%d] failed\n", cs->line); |
| 847 | return -EBUSY; |
| 848 | } |
| 849 | spi_set_ctldata(spi, cs); |
| 850 | } |
| 851 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 852 | sdd = spi_master_get_devdata(spi->master); |
| 853 | sci = sdd->cntrlr_info; |
| 854 | |
| 855 | spin_lock_irqsave(&sdd->lock, flags); |
| 856 | |
| 857 | list_for_each_entry(msg, &sdd->queue, queue) { |
| 858 | /* Is some mssg is already queued for this device */ |
| 859 | if (msg->spi == spi) { |
| 860 | dev_err(&spi->dev, |
| 861 | "setup: attempt while mssg in queue!\n"); |
| 862 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 863 | return -EBUSY; |
| 864 | } |
| 865 | } |
| 866 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 867 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 868 | |
| 869 | if (spi->bits_per_word != 8 |
| 870 | && spi->bits_per_word != 16 |
| 871 | && spi->bits_per_word != 32) { |
| 872 | dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", |
| 873 | spi->bits_per_word); |
| 874 | err = -EINVAL; |
| 875 | goto setup_exit; |
| 876 | } |
| 877 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 878 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 879 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 880 | /* Check if we can provide the requested rate */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 881 | if (!sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 882 | u32 psr, speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 883 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 884 | /* Max possible */ |
| 885 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 886 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 887 | if (spi->max_speed_hz > speed) |
| 888 | spi->max_speed_hz = speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 889 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 890 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; |
| 891 | psr &= S3C64XX_SPI_PSR_MASK; |
| 892 | if (psr == S3C64XX_SPI_PSR_MASK) |
| 893 | psr--; |
| 894 | |
| 895 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
| 896 | if (spi->max_speed_hz < speed) { |
| 897 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { |
| 898 | psr++; |
| 899 | } else { |
| 900 | err = -EINVAL; |
| 901 | goto setup_exit; |
| 902 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 903 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 904 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 905 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
| 906 | if (spi->max_speed_hz >= speed) |
| 907 | spi->max_speed_hz = speed; |
| 908 | else |
| 909 | err = -EINVAL; |
| 910 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 911 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 912 | pm_runtime_put(&sdd->pdev->dev); |
| 913 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 914 | setup_exit: |
| 915 | |
| 916 | /* setup() returns with device de-selected */ |
| 917 | disable_cs(sdd, spi); |
| 918 | |
| 919 | return err; |
| 920 | } |
| 921 | |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 922 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
| 923 | { |
| 924 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); |
| 925 | |
| 926 | if (cs) |
| 927 | gpio_free(cs->line); |
| 928 | spi_set_ctldata(spi, NULL); |
| 929 | } |
| 930 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 931 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
| 932 | { |
| 933 | struct s3c64xx_spi_driver_data *sdd = data; |
| 934 | struct spi_master *spi = sdd->master; |
| 935 | unsigned int val; |
| 936 | |
| 937 | val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR); |
| 938 | |
| 939 | val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR | |
| 940 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | |
| 941 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | |
| 942 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
| 943 | |
| 944 | writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR); |
| 945 | |
| 946 | if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR) |
| 947 | dev_err(&spi->dev, "RX overrun\n"); |
| 948 | if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR) |
| 949 | dev_err(&spi->dev, "RX underrun\n"); |
| 950 | if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR) |
| 951 | dev_err(&spi->dev, "TX overrun\n"); |
| 952 | if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR) |
| 953 | dev_err(&spi->dev, "TX underrun\n"); |
| 954 | |
| 955 | return IRQ_HANDLED; |
| 956 | } |
| 957 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 958 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
| 959 | { |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 960 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 961 | void __iomem *regs = sdd->regs; |
| 962 | unsigned int val; |
| 963 | |
| 964 | sdd->cur_speed = 0; |
| 965 | |
| 966 | S3C64XX_SPI_DEACT(sdd); |
| 967 | |
| 968 | /* Disable Interrupts - we use Polling if not DMA mode */ |
| 969 | writel(0, regs + S3C64XX_SPI_INT_EN); |
| 970 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 971 | if (!sdd->port_conf->clk_from_cmu) |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 972 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 973 | regs + S3C64XX_SPI_CLK_CFG); |
| 974 | writel(0, regs + S3C64XX_SPI_MODE_CFG); |
| 975 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 976 | |
| 977 | /* Clear any irq pending bits */ |
| 978 | writel(readl(regs + S3C64XX_SPI_PENDING_CLR), |
| 979 | regs + S3C64XX_SPI_PENDING_CLR); |
| 980 | |
| 981 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); |
| 982 | |
| 983 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 984 | val &= ~S3C64XX_SPI_MODE_4BURST; |
| 985 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 986 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 987 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 988 | |
| 989 | flush_fifo(sdd); |
| 990 | } |
| 991 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 992 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
| 993 | struct platform_device *pdev) |
| 994 | { |
| 995 | return (struct s3c64xx_spi_port_config *) |
| 996 | platform_get_device_id(pdev)->driver_data; |
| 997 | } |
| 998 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 999 | static int __init s3c64xx_spi_probe(struct platform_device *pdev) |
| 1000 | { |
| 1001 | struct resource *mem_res, *dmatx_res, *dmarx_res; |
| 1002 | struct s3c64xx_spi_driver_data *sdd; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1003 | struct s3c64xx_spi_info *sci; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1004 | struct spi_master *master; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1005 | int ret, irq; |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1006 | char clk_name[16]; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1007 | |
| 1008 | if (pdev->id < 0) { |
| 1009 | dev_err(&pdev->dev, |
| 1010 | "Invalid platform device id-%d\n", pdev->id); |
| 1011 | return -ENODEV; |
| 1012 | } |
| 1013 | |
| 1014 | if (pdev->dev.platform_data == NULL) { |
| 1015 | dev_err(&pdev->dev, "platform_data missing!\n"); |
| 1016 | return -ENODEV; |
| 1017 | } |
| 1018 | |
Mark Brown | cc0fc0b | 2010-09-01 08:55:22 -0600 | [diff] [blame] | 1019 | sci = pdev->dev.platform_data; |
Mark Brown | cc0fc0b | 2010-09-01 08:55:22 -0600 | [diff] [blame] | 1020 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1021 | /* Check for availability of necessary resource */ |
| 1022 | |
| 1023 | dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 1024 | if (dmatx_res == NULL) { |
| 1025 | dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); |
| 1026 | return -ENXIO; |
| 1027 | } |
| 1028 | |
| 1029 | dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 1030 | if (dmarx_res == NULL) { |
| 1031 | dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); |
| 1032 | return -ENXIO; |
| 1033 | } |
| 1034 | |
| 1035 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1036 | if (mem_res == NULL) { |
| 1037 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); |
| 1038 | return -ENXIO; |
| 1039 | } |
| 1040 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1041 | irq = platform_get_irq(pdev, 0); |
| 1042 | if (irq < 0) { |
| 1043 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); |
| 1044 | return irq; |
| 1045 | } |
| 1046 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1047 | master = spi_alloc_master(&pdev->dev, |
| 1048 | sizeof(struct s3c64xx_spi_driver_data)); |
| 1049 | if (master == NULL) { |
| 1050 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
| 1051 | return -ENOMEM; |
| 1052 | } |
| 1053 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1054 | platform_set_drvdata(pdev, master); |
| 1055 | |
| 1056 | sdd = spi_master_get_devdata(master); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1057 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1058 | sdd->master = master; |
| 1059 | sdd->cntrlr_info = sci; |
| 1060 | sdd->pdev = pdev; |
| 1061 | sdd->sfr_start = mem_res->start; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1062 | sdd->tx_dma.dmach = dmatx_res->start; |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 1063 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1064 | sdd->rx_dma.dmach = dmarx_res->start; |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 1065 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1066 | sdd->port_id = pdev->id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1067 | |
| 1068 | sdd->cur_bpw = 8; |
| 1069 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1070 | master->bus_num = sdd->port_id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1071 | master->setup = s3c64xx_spi_setup; |
Thomas Abraham | 1c20c20 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1072 | master->cleanup = s3c64xx_spi_cleanup; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1073 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
| 1074 | master->transfer_one_message = s3c64xx_spi_transfer_one_message; |
| 1075 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1076 | master->num_chipselect = sci->num_cs; |
| 1077 | master->dma_alignment = 8; |
| 1078 | /* the spi->mode bits understood by this driver: */ |
| 1079 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1080 | |
| 1081 | if (request_mem_region(mem_res->start, |
| 1082 | resource_size(mem_res), pdev->name) == NULL) { |
| 1083 | dev_err(&pdev->dev, "Req mem region failed\n"); |
| 1084 | ret = -ENXIO; |
| 1085 | goto err0; |
| 1086 | } |
| 1087 | |
| 1088 | sdd->regs = ioremap(mem_res->start, resource_size(mem_res)); |
| 1089 | if (sdd->regs == NULL) { |
| 1090 | dev_err(&pdev->dev, "Unable to remap IO\n"); |
| 1091 | ret = -ENXIO; |
| 1092 | goto err1; |
| 1093 | } |
| 1094 | |
Thomas Abraham | 868dee9 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1095 | if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1096 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
| 1097 | ret = -EBUSY; |
| 1098 | goto err2; |
| 1099 | } |
| 1100 | |
| 1101 | /* Setup clocks */ |
| 1102 | sdd->clk = clk_get(&pdev->dev, "spi"); |
| 1103 | if (IS_ERR(sdd->clk)) { |
| 1104 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); |
| 1105 | ret = PTR_ERR(sdd->clk); |
| 1106 | goto err3; |
| 1107 | } |
| 1108 | |
| 1109 | if (clk_enable(sdd->clk)) { |
| 1110 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
| 1111 | ret = -EBUSY; |
| 1112 | goto err4; |
| 1113 | } |
| 1114 | |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1115 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
| 1116 | sdd->src_clk = clk_get(&pdev->dev, clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1117 | if (IS_ERR(sdd->src_clk)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1118 | dev_err(&pdev->dev, |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1119 | "Unable to acquire clock '%s'\n", clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1120 | ret = PTR_ERR(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1121 | goto err5; |
| 1122 | } |
| 1123 | |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1124 | if (clk_enable(sdd->src_clk)) { |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1125 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1126 | ret = -EBUSY; |
| 1127 | goto err6; |
| 1128 | } |
| 1129 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1130 | /* Setup Deufult Mode */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1131 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1132 | |
| 1133 | spin_lock_init(&sdd->lock); |
| 1134 | init_completion(&sdd->xfer_completion); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1135 | INIT_LIST_HEAD(&sdd->queue); |
| 1136 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1137 | ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd); |
| 1138 | if (ret != 0) { |
| 1139 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", |
| 1140 | irq, ret); |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1141 | goto err7; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1142 | } |
| 1143 | |
| 1144 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
| 1145 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, |
| 1146 | sdd->regs + S3C64XX_SPI_INT_EN); |
| 1147 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1148 | if (spi_register_master(master)) { |
| 1149 | dev_err(&pdev->dev, "cannot register SPI master\n"); |
| 1150 | ret = -EBUSY; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1151 | goto err8; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1152 | } |
| 1153 | |
Joe Perches | 8a349d4 | 2010-02-02 07:22:13 +0000 | [diff] [blame] | 1154 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " |
| 1155 | "with %d Slaves attached\n", |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1156 | sdd->port_id, master->num_chipselect); |
Joe Perches | 8a349d4 | 2010-02-02 07:22:13 +0000 | [diff] [blame] | 1157 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1158 | mem_res->end, mem_res->start, |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1159 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1160 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1161 | pm_runtime_enable(&pdev->dev); |
| 1162 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1163 | return 0; |
| 1164 | |
| 1165 | err8: |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1166 | free_irq(irq, sdd); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1167 | err7: |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1168 | clk_disable(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1169 | err6: |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1170 | clk_put(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1171 | err5: |
| 1172 | clk_disable(sdd->clk); |
| 1173 | err4: |
| 1174 | clk_put(sdd->clk); |
| 1175 | err3: |
| 1176 | err2: |
| 1177 | iounmap((void *) sdd->regs); |
| 1178 | err1: |
| 1179 | release_mem_region(mem_res->start, resource_size(mem_res)); |
| 1180 | err0: |
| 1181 | platform_set_drvdata(pdev, NULL); |
| 1182 | spi_master_put(master); |
| 1183 | |
| 1184 | return ret; |
| 1185 | } |
| 1186 | |
| 1187 | static int s3c64xx_spi_remove(struct platform_device *pdev) |
| 1188 | { |
| 1189 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
| 1190 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1191 | struct resource *mem_res; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1192 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1193 | pm_runtime_disable(&pdev->dev); |
| 1194 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1195 | spi_unregister_master(master); |
| 1196 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1197 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
| 1198 | |
| 1199 | free_irq(platform_get_irq(pdev, 0), sdd); |
| 1200 | |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1201 | clk_disable(sdd->src_clk); |
| 1202 | clk_put(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1203 | |
| 1204 | clk_disable(sdd->clk); |
| 1205 | clk_put(sdd->clk); |
| 1206 | |
| 1207 | iounmap((void *) sdd->regs); |
| 1208 | |
| 1209 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jassi Brar | ef6c680 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1210 | if (mem_res != NULL) |
| 1211 | release_mem_region(mem_res->start, resource_size(mem_res)); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1212 | |
| 1213 | platform_set_drvdata(pdev, NULL); |
| 1214 | spi_master_put(master); |
| 1215 | |
| 1216 | return 0; |
| 1217 | } |
| 1218 | |
| 1219 | #ifdef CONFIG_PM |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1220 | static int s3c64xx_spi_suspend(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1221 | { |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1222 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1223 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1224 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1225 | spi_master_suspend(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1226 | |
| 1227 | /* Disable the clock */ |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1228 | clk_disable(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1229 | clk_disable(sdd->clk); |
| 1230 | |
| 1231 | sdd->cur_speed = 0; /* Output Clock is stopped */ |
| 1232 | |
| 1233 | return 0; |
| 1234 | } |
| 1235 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1236 | static int s3c64xx_spi_resume(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1237 | { |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1238 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1239 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1240 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1241 | |
Thomas Abraham | 868dee9 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1242 | sci->cfg_gpio(); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1243 | |
| 1244 | /* Enable the clock */ |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1245 | clk_enable(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1246 | clk_enable(sdd->clk); |
| 1247 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1248 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1249 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1250 | spi_master_resume(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1251 | |
| 1252 | return 0; |
| 1253 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1254 | #endif /* CONFIG_PM */ |
| 1255 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1256 | #ifdef CONFIG_PM_RUNTIME |
| 1257 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
| 1258 | { |
| 1259 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
| 1260 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1261 | |
| 1262 | clk_disable(sdd->clk); |
| 1263 | clk_disable(sdd->src_clk); |
| 1264 | |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
| 1268 | static int s3c64xx_spi_runtime_resume(struct device *dev) |
| 1269 | { |
| 1270 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
| 1271 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1272 | |
| 1273 | clk_enable(sdd->src_clk); |
| 1274 | clk_enable(sdd->clk); |
| 1275 | |
| 1276 | return 0; |
| 1277 | } |
| 1278 | #endif /* CONFIG_PM_RUNTIME */ |
| 1279 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1280 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
| 1281 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1282 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
| 1283 | s3c64xx_spi_runtime_resume, NULL) |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1284 | }; |
| 1285 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1286 | struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
| 1287 | .fifo_lvl_mask = { 0x7f }, |
| 1288 | .rx_lvl_offset = 13, |
| 1289 | .tx_st_done = 21, |
| 1290 | .high_speed = true, |
| 1291 | }; |
| 1292 | |
| 1293 | struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
| 1294 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1295 | .rx_lvl_offset = 13, |
| 1296 | .tx_st_done = 21, |
| 1297 | }; |
| 1298 | |
| 1299 | struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { |
| 1300 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1301 | .rx_lvl_offset = 15, |
| 1302 | .tx_st_done = 25, |
| 1303 | }; |
| 1304 | |
| 1305 | struct s3c64xx_spi_port_config s5pc100_spi_port_config = { |
| 1306 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1307 | .rx_lvl_offset = 13, |
| 1308 | .tx_st_done = 21, |
| 1309 | .high_speed = true, |
| 1310 | }; |
| 1311 | |
| 1312 | struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
| 1313 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1314 | .rx_lvl_offset = 15, |
| 1315 | .tx_st_done = 25, |
| 1316 | .high_speed = true, |
| 1317 | }; |
| 1318 | |
| 1319 | struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
| 1320 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
| 1321 | .rx_lvl_offset = 15, |
| 1322 | .tx_st_done = 25, |
| 1323 | .high_speed = true, |
| 1324 | .clk_from_cmu = true, |
| 1325 | }; |
| 1326 | |
| 1327 | static struct platform_device_id s3c64xx_spi_driver_ids[] = { |
| 1328 | { |
| 1329 | .name = "s3c2443-spi", |
| 1330 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, |
| 1331 | }, { |
| 1332 | .name = "s3c6410-spi", |
| 1333 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, |
| 1334 | }, { |
| 1335 | .name = "s5p64x0-spi", |
| 1336 | .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, |
| 1337 | }, { |
| 1338 | .name = "s5pc100-spi", |
| 1339 | .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, |
| 1340 | }, { |
| 1341 | .name = "s5pv210-spi", |
| 1342 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, |
| 1343 | }, { |
| 1344 | .name = "exynos4210-spi", |
| 1345 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, |
| 1346 | }, |
| 1347 | { }, |
| 1348 | }; |
| 1349 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1350 | static struct platform_driver s3c64xx_spi_driver = { |
| 1351 | .driver = { |
| 1352 | .name = "s3c64xx-spi", |
| 1353 | .owner = THIS_MODULE, |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1354 | .pm = &s3c64xx_spi_pm, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1355 | }, |
| 1356 | .remove = s3c64xx_spi_remove, |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame] | 1357 | .id_table = s3c64xx_spi_driver_ids, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1358 | }; |
| 1359 | MODULE_ALIAS("platform:s3c64xx-spi"); |
| 1360 | |
| 1361 | static int __init s3c64xx_spi_init(void) |
| 1362 | { |
| 1363 | return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe); |
| 1364 | } |
Mark Brown | d2a787f | 2010-09-07 11:29:17 +0100 | [diff] [blame] | 1365 | subsys_initcall(s3c64xx_spi_init); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1366 | |
| 1367 | static void __exit s3c64xx_spi_exit(void) |
| 1368 | { |
| 1369 | platform_driver_unregister(&s3c64xx_spi_driver); |
| 1370 | } |
| 1371 | module_exit(s3c64xx_spi_exit); |
| 1372 | |
| 1373 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); |
| 1374 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); |
| 1375 | MODULE_LICENSE("GPL"); |