blob: 7688868557b95e7bd2231599178134bd3b13d6f9 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 *
13 * TODO
Sergei Shtylyovd8178982009-12-07 23:39:38 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt366"
Sergei Shtylyov859faa82009-12-07 23:36:15 +040028#define DRV_VERSION "0.6.8"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30struct hpt_clock {
Tejun Heo6ecb6f22009-01-08 16:29:20 -050031 u8 xfer_mode;
Jeff Garzik669a5db2006-08-29 18:12:40 -040032 u32 timing;
33};
34
35/* key for bus clock timings
36 * bit
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040037 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
38 * cycles = value + 1
39 * 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
40 * cycles = value + 1
41 * 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040042 * register access.
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040043 * 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040044 * register access.
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040045 * 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
46 * 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
47 * 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040048 * register access.
Sergei Shtylyov82beb5d2009-11-25 00:17:31 +040049 * 28 UDMA enable.
50 * 29 DMA enable.
51 * 30 PIO_MST enable. If set, the chip is in bus master mode during
52 * PIO xfer.
Jeff Garzik669a5db2006-08-29 18:12:40 -040053 * 31 FIFO enable.
54 */
55
56static const struct hpt_clock hpt366_40[] = {
57 { XFER_UDMA_4, 0x900fd943 },
58 { XFER_UDMA_3, 0x900ad943 },
59 { XFER_UDMA_2, 0x900bd943 },
60 { XFER_UDMA_1, 0x9008d943 },
61 { XFER_UDMA_0, 0x9008d943 },
62
63 { XFER_MW_DMA_2, 0xa008d943 },
64 { XFER_MW_DMA_1, 0xa010d955 },
65 { XFER_MW_DMA_0, 0xa010d9fc },
66
67 { XFER_PIO_4, 0xc008d963 },
68 { XFER_PIO_3, 0xc010d974 },
69 { XFER_PIO_2, 0xc010d997 },
70 { XFER_PIO_1, 0xc010d9c7 },
71 { XFER_PIO_0, 0xc018d9d9 },
72 { 0, 0x0120d9d9 }
73};
74
75static const struct hpt_clock hpt366_33[] = {
76 { XFER_UDMA_4, 0x90c9a731 },
77 { XFER_UDMA_3, 0x90cfa731 },
78 { XFER_UDMA_2, 0x90caa731 },
79 { XFER_UDMA_1, 0x90cba731 },
80 { XFER_UDMA_0, 0x90c8a731 },
81
82 { XFER_MW_DMA_2, 0xa0c8a731 },
83 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
84 { XFER_MW_DMA_0, 0xa0c8a797 },
85
86 { XFER_PIO_4, 0xc0c8a731 },
87 { XFER_PIO_3, 0xc0c8a742 },
88 { XFER_PIO_2, 0xc0d0a753 },
89 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
90 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
91 { 0, 0x0120a7a7 }
92};
93
94static const struct hpt_clock hpt366_25[] = {
95 { XFER_UDMA_4, 0x90c98521 },
96 { XFER_UDMA_3, 0x90cf8521 },
97 { XFER_UDMA_2, 0x90cf8521 },
98 { XFER_UDMA_1, 0x90cb8521 },
99 { XFER_UDMA_0, 0x90cb8521 },
100
101 { XFER_MW_DMA_2, 0xa0ca8521 },
102 { XFER_MW_DMA_1, 0xa0ca8532 },
103 { XFER_MW_DMA_0, 0xa0ca8575 },
104
105 { XFER_PIO_4, 0xc0ca8521 },
106 { XFER_PIO_3, 0xc0ca8532 },
107 { XFER_PIO_2, 0xc0ca8542 },
108 { XFER_PIO_1, 0xc0d08572 },
109 { XFER_PIO_0, 0xc0d08585 },
110 { 0, 0x01208585 }
111};
112
113static const char *bad_ata33[] = {
114 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
115 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
116 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
117 "Maxtor 90510D4",
118 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
119 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
120 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
121 NULL
122};
123
124static const char *bad_ata66_4[] = {
125 "IBM-DTLA-307075",
126 "IBM-DTLA-307060",
127 "IBM-DTLA-307045",
128 "IBM-DTLA-307030",
129 "IBM-DTLA-307020",
130 "IBM-DTLA-307015",
131 "IBM-DTLA-305040",
132 "IBM-DTLA-305030",
133 "IBM-DTLA-305020",
134 "IC35L010AVER07-0",
135 "IC35L020AVER07-0",
136 "IC35L030AVER07-0",
137 "IC35L040AVER07-0",
138 "IC35L060AVER07-0",
139 "WDC AC310200R",
140 NULL
141};
142
143static const char *bad_ata66_3[] = {
144 "WDC AC310200R",
145 NULL
146};
147
148static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
149{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900150 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400151 int i = 0;
152
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900153 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900155 while (list[i] != NULL) {
156 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400157 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158 modestr, list[i]);
159 return 1;
160 }
161 i++;
162 }
163 return 0;
164}
165
166/**
167 * hpt366_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400168 * @adev: ATA device
169 *
170 * Block UDMA on devices that cause trouble with this controller.
171 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400172
Alan Coxa76b62c2007-03-09 09:34:07 -0500173static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400174{
175 if (adev->class == ATA_DEV_ATA) {
176 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
177 mask &= ~ATA_MASK_UDMA;
178 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
Alan Cox6ddd6862008-02-26 13:35:54 -0800179 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400180 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
Alan Cox6ddd6862008-02-26 13:35:54 -0800181 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
Tejun Heo3ee89f12008-12-09 17:14:04 +0900182 } else if (adev->class == ATA_DEV_ATAPI)
183 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
184
Tejun Heoc7087652010-05-10 21:41:34 +0200185 return mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186}
187
Alan Coxfecfda52007-03-08 19:34:28 +0000188static int hpt36x_cable_detect(struct ata_port *ap)
189{
Alan Coxfecfda52007-03-08 19:34:28 +0000190 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heobab5b322008-12-09 17:13:19 +0900191 u8 ata66;
Alan Coxfecfda52007-03-08 19:34:28 +0000192
Tejun Heobab5b322008-12-09 17:13:19 +0900193 /*
194 * Each channel of pata_hpt366 occupies separate PCI function
195 * as the primary channel and bit1 indicates the cable type.
196 */
Alan Coxfecfda52007-03-08 19:34:28 +0000197 pci_read_config_byte(pdev, 0x5A, &ata66);
Tejun Heobab5b322008-12-09 17:13:19 +0900198 if (ata66 & 2)
Alan Coxfecfda52007-03-08 19:34:28 +0000199 return ATA_CBL_PATA40;
200 return ATA_CBL_PATA80;
201}
202
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500203static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
204 u8 mode)
205{
206 struct hpt_clock *clocks = ap->host->private_data;
207 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyov859faa82009-12-07 23:36:15 +0400208 u32 addr = 0x40 + 4 * adev->devno;
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500209 u32 mask, reg;
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500210
211 /* determine timing mask and find matching clock entry */
212 if (mode < XFER_MW_DMA_0)
213 mask = 0xc1f8ffff;
214 else if (mode < XFER_UDMA_0)
215 mask = 0x303800ff;
216 else
217 mask = 0x30070000;
218
219 while (clocks->xfer_mode) {
220 if (clocks->xfer_mode == mode)
221 break;
222 clocks++;
223 }
224 if (!clocks->xfer_mode)
225 BUG();
226
227 /*
228 * Combine new mode bits with old config bits and disable
229 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
230 * problems handling I/O errors later.
231 */
Sergei Shtylyov859faa82009-12-07 23:36:15 +0400232 pci_read_config_dword(pdev, addr, &reg);
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500233 reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
Sergei Shtylyov859faa82009-12-07 23:36:15 +0400234 pci_write_config_dword(pdev, addr, reg);
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500235}
236
Jeff Garzik669a5db2006-08-29 18:12:40 -0400237/**
238 * hpt366_set_piomode - PIO setup
239 * @ap: ATA interface
240 * @adev: device on the interface
241 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400242 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400243 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400244
Jeff Garzik669a5db2006-08-29 18:12:40 -0400245static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
246{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500247 hpt366_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400248}
249
250/**
251 * hpt366_set_dmamode - DMA timing setup
252 * @ap: ATA interface
253 * @adev: Device being configured
254 *
255 * Set up the channel for MWDMA or UDMA modes. Much the same as with
256 * PIO, load the mode number and then set MWDMA or UDMA flag.
257 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400258
Jeff Garzik669a5db2006-08-29 18:12:40 -0400259static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
260{
Tejun Heo6ecb6f22009-01-08 16:29:20 -0500261 hpt366_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400262}
263
264static struct scsi_host_template hpt36x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900265 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400266};
267
268/*
269 * Configuration for HPT366/68
270 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400271
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272static struct ata_port_operations hpt366_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900273 .inherits = &ata_bmdma_port_ops,
274 .cable_detect = hpt36x_cable_detect,
275 .mode_filter = hpt366_filter,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400276 .set_piomode = hpt366_set_piomode,
277 .set_dmamode = hpt366_set_dmamode,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400278};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279
280/**
Alanaa54ab12006-11-27 16:24:15 +0000281 * hpt36x_init_chipset - common chip setup
282 * @dev: PCI device
283 *
284 * Perform the chip setup work that must be done at both init and
285 * resume time
286 */
287
288static void hpt36x_init_chipset(struct pci_dev *dev)
289{
290 u8 drive_fast;
291 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
292 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
293 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
294 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
295
296 pci_read_config_byte(dev, 0x51, &drive_fast);
297 if (drive_fast & 0x80)
298 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
299}
300
301/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400302 * hpt36x_init_one - Initialise an HPT366/368
303 * @dev: PCI device
304 * @id: Entry in match table
305 *
306 * Initialise an HPT36x device. There are some interesting complications
307 * here. Firstly the chip may report 366 and be one of several variants.
308 * Secondly all the timings depend on the clock for the chip which we must
309 * detect and look up
310 *
311 * This is the known chip mappings. It may be missing a couple of later
312 * releases.
313 *
314 * Chip version PCI Rev Notes
315 * HPT366 4 (HPT366) 0 UDMA66
316 * HPT366 4 (HPT366) 1 UDMA66
317 * HPT368 4 (HPT366) 2 UDMA66
318 * HPT37x/30x 4 (HPT366) 3+ Other driver
319 *
320 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400321
Jeff Garzik669a5db2006-08-29 18:12:40 -0400322static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
323{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200324 static const struct ata_port_info info_hpt366 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400325 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100326 .pio_mask = ATA_PIO4,
327 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400328 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400329 .port_ops = &hpt366_port_ops
330 };
Tejun Heo887125e2008-03-25 12:22:49 +0900331 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400332
Tejun Heo887125e2008-03-25 12:22:49 +0900333 void *hpriv = NULL;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400334 u32 reg1;
Tejun Heof08048e2008-03-25 12:22:47 +0900335 int rc;
336
337 rc = pcim_enable_device(dev);
338 if (rc)
339 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400340
Jeff Garzik669a5db2006-08-29 18:12:40 -0400341 /* May be a later chip in disguise. Check */
342 /* Newer chips are not in the HPT36x driver. Ignore them */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400343 if (dev->revision > 2)
344 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345
Alanaa54ab12006-11-27 16:24:15 +0000346 hpt36x_init_chipset(dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400347
348 pci_read_config_dword(dev, 0x40, &reg1);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400349
Jeff Garzik669a5db2006-08-29 18:12:40 -0400350 /* PCI clocking determines the ATA timing values to use */
351 /* info_hpt366 is safe against re-entry so we can scribble on it */
OGAWA Hirofumi2c136ef2006-10-03 01:14:03 -0700352 switch((reg1 & 0x700) >> 8) {
Tejun Heo2456eb82008-12-08 18:48:42 +0900353 case 9:
Tejun Heo887125e2008-03-25 12:22:49 +0900354 hpriv = &hpt366_40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400355 break;
Tejun Heo2456eb82008-12-08 18:48:42 +0900356 case 5:
Tejun Heo887125e2008-03-25 12:22:49 +0900357 hpriv = &hpt366_25;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400358 break;
359 default:
Tejun Heo887125e2008-03-25 12:22:49 +0900360 hpriv = &hpt366_33;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400361 break;
362 }
363 /* Now kick off ATA set up */
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200364 return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400365}
366
Tejun Heo438ac6d2007-03-02 17:31:26 +0900367#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000368static int hpt36x_reinit_one(struct pci_dev *dev)
369{
Tejun Heof08048e2008-03-25 12:22:47 +0900370 struct ata_host *host = dev_get_drvdata(&dev->dev);
371 int rc;
372
373 rc = ata_pci_device_do_resume(dev);
374 if (rc)
375 return rc;
Alanaa54ab12006-11-27 16:24:15 +0000376 hpt36x_init_chipset(dev);
Tejun Heof08048e2008-03-25 12:22:47 +0900377 ata_host_resume(host);
378 return 0;
Alanaa54ab12006-11-27 16:24:15 +0000379}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900380#endif
Alanaa54ab12006-11-27 16:24:15 +0000381
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400382static const struct pci_device_id hpt36x[] = {
383 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400384 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400385};
386
387static struct pci_driver hpt36x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400388 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400389 .id_table = hpt36x,
390 .probe = hpt36x_init_one,
Alanaa54ab12006-11-27 16:24:15 +0000391 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900392#ifdef CONFIG_PM
Alanaa54ab12006-11-27 16:24:15 +0000393 .suspend = ata_pci_device_suspend,
394 .resume = hpt36x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900395#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400396};
397
398static int __init hpt36x_init(void)
399{
400 return pci_register_driver(&hpt36x_pci_driver);
401}
402
Jeff Garzik669a5db2006-08-29 18:12:40 -0400403static void __exit hpt36x_exit(void)
404{
405 pci_unregister_driver(&hpt36x_pci_driver);
406}
407
Jeff Garzik669a5db2006-08-29 18:12:40 -0400408MODULE_AUTHOR("Alan Cox");
409MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
410MODULE_LICENSE("GPL");
411MODULE_DEVICE_TABLE(pci, hpt36x);
412MODULE_VERSION(DRV_VERSION);
413
414module_init(hpt36x_init);
415module_exit(hpt36x_exit);