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Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000011config ARM_GIC_V2M
12 bool
13 depends on ARM_GIC
14 depends on PCI && PCI_MSI
15 select PCI_MSI_IRQ_DOMAIN
16
Rob Herring81243e42012-11-20 21:21:40 -060017config GIC_NON_BANKED
18 bool
19
Marc Zyngier021f6532014-06-30 16:01:31 +010020config ARM_GIC_V3
21 bool
22 select IRQ_DOMAIN
23 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000024 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier021f6532014-06-30 16:01:31 +010025
Marc Zyngier19812722014-11-24 14:35:19 +000026config ARM_GIC_V3_ITS
27 bool
28 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020029
Rob Herring44430ec2012-10-27 17:25:26 -050030config ARM_NVIC
31 bool
32 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020033 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050034 select GENERIC_IRQ_CHIP
35
36config ARM_VIC
37 bool
38 select IRQ_DOMAIN
39 select MULTI_IRQ_HANDLER
40
41config ARM_VIC_NR
42 int
43 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050044 default 2
45 depends on ARM_VIC
46 help
47 The maximum number of VICs available in the system, for
48 power management.
49
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020050config ATMEL_AIC_IRQ
51 bool
52 select GENERIC_IRQ_CHIP
53 select IRQ_DOMAIN
54 select MULTI_IRQ_HANDLER
55 select SPARSE_IRQ
56
57config ATMEL_AIC5_IRQ
58 bool
59 select GENERIC_IRQ_CHIP
60 select IRQ_DOMAIN
61 select MULTI_IRQ_HANDLER
62 select SPARSE_IRQ
63
Ralf Baechle0509cfd2015-07-08 14:46:08 +020064config I8259
65 bool
66 select IRQ_DOMAIN
67
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080068config BCM7038_L1_IRQ
69 bool
70 select GENERIC_IRQ_CHIP
71 select IRQ_DOMAIN
72
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -080073config BCM7120_L2_IRQ
74 bool
75 select GENERIC_IRQ_CHIP
76 select IRQ_DOMAIN
77
Florian Fainelli7f646e92014-05-23 17:40:53 -070078config BRCMSTB_L2_IRQ
79 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -070080 select GENERIC_IRQ_CHIP
81 select IRQ_DOMAIN
82
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +020083config DW_APB_ICTL
84 bool
Jisheng Zhange1588492014-10-22 20:59:10 +080085 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +020086 select IRQ_DOMAIN
87
James Hoganb6ef9162013-04-22 15:43:50 +010088config IMGPDC_IRQ
89 bool
90 select GENERIC_IRQ_CHIP
91 select IRQ_DOMAIN
92
Ralf Baechle67e38cf2015-05-26 18:20:06 +020093config IRQ_MIPS_CPU
94 bool
95 select GENERIC_IRQ_CHIP
96 select IRQ_DOMAIN
97
Alexander Shiyanafc98d92014-02-02 12:07:46 +040098config CLPS711X_IRQCHIP
99 bool
100 depends on ARCH_CLPS711X
101 select IRQ_DOMAIN
102 select MULTI_IRQ_HANDLER
103 select SPARSE_IRQ
104 default y
105
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300106config OR1K_PIC
107 bool
108 select IRQ_DOMAIN
109
Felipe Balbi85980662014-09-15 16:15:02 -0500110config OMAP_IRQCHIP
111 bool
112 select GENERIC_IRQ_CHIP
113 select IRQ_DOMAIN
114
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200115config ORION_IRQCHIP
116 bool
117 select IRQ_DOMAIN
118 select MULTI_IRQ_HANDLER
119
Magnus Damm44358042013-02-18 23:28:34 +0900120config RENESAS_INTC_IRQPIN
121 bool
122 select IRQ_DOMAIN
123
Magnus Dammfbc83b72013-02-27 17:15:01 +0900124config RENESAS_IRQC
125 bool
126 select IRQ_DOMAIN
127
Lee Jones07088482015-02-18 15:13:58 +0000128config ST_IRQCHIP
129 bool
130 select REGMAP
131 select MFD_SYSCON
132 help
133 Enables SysCfg Controlled IRQs on STi based platforms.
134
Christian Ruppertb06eb012013-06-25 18:29:57 +0200135config TB10X_IRQC
136 bool
137 select IRQ_DOMAIN
138 select GENERIC_IRQ_CHIP
139
Linus Walleij2389d502012-10-31 22:04:31 +0100140config VERSATILE_FPGA_IRQ
141 bool
142 select IRQ_DOMAIN
143
144config VERSATILE_FPGA_IRQ_NR
145 int
146 default 4
147 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400148
149config XTENSA_MX
150 bool
151 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530152
153config IRQ_CROSSBAR
154 bool
155 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900156 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530157 The primary irqchip invokes the crossbar's callback which inturn allocates
158 a free irq and configures the IP. Thus the peripheral interrupts are
159 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300160
161config KEYSTONE_IRQ
162 tristate "Keystone 2 IRQ controller IP"
163 depends on ARCH_KEYSTONE
164 help
165 Support for Texas Instruments Keystone 2 IRQ controller IP which
166 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700167
168config MIPS_GIC
169 bool
170 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900171
Paul Burton44e08e72015-05-24 16:11:31 +0100172config INGENIC_IRQ
173 bool
174 depends on MACH_INGENIC
175 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700176
Yoshinori Sato8a764482015-05-10 02:30:47 +0900177config RENESAS_H8300H_INTC
178 bool
179 select IRQ_DOMAIN
180
181config RENESAS_H8S_INTC
182 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700183 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500184
185config IMX_GPCV2
186 bool
187 select IRQ_DOMAIN
188 help
189 Enables the wakeup IRQs for IMX platforms with GPCv2 block