blob: cdfc91e37e63ea6d88a1edc420c08ad7aee8bf40 [file] [log] [blame]
Rob Clarkc8afe682013-06-26 12:44:06 -04001/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
Rob Clark060530f2014-03-03 14:19:12 -050025#include <linux/component.h>
Rob Clarkc8afe682013-06-26 12:44:06 -040026#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
Archit Taneja3d6df062015-06-09 14:17:22 +053033#include <linux/of_graph.h>
Archit Tanejae9fbdaf2015-11-18 12:15:14 +053034#include <linux/of_device.h>
Rob Clarkc8afe682013-06-26 12:44:06 -040035#include <asm/sizes.h>
36
Rob Clarkc8afe682013-06-26 12:44:06 -040037#include <drm/drmP.h>
Rob Clarkcf3a7e42014-11-08 13:21:06 -050038#include <drm/drm_atomic.h>
39#include <drm/drm_atomic_helper.h>
Rob Clarkc8afe682013-06-26 12:44:06 -040040#include <drm/drm_crtc_helper.h>
Rob Clarkcf3a7e42014-11-08 13:21:06 -050041#include <drm/drm_plane_helper.h>
Rob Clarkc8afe682013-06-26 12:44:06 -040042#include <drm/drm_fb_helper.h>
Rob Clark7198e6b2013-07-19 12:59:32 -040043#include <drm/msm_drm.h>
Daniel Vetterd9fc9412014-09-23 15:46:53 +020044#include <drm/drm_gem.h>
Rob Clarkc8afe682013-06-26 12:44:06 -040045
Lloyd Atkinson154b6aa2016-05-24 17:11:37 -040046#include "msm_evtlog.h"
47
Rob Clarkc8afe682013-06-26 12:44:06 -040048struct msm_kms;
Rob Clark7198e6b2013-07-19 12:59:32 -040049struct msm_gpu;
Rob Clark871d8122013-11-16 12:56:06 -050050struct msm_mmu;
Archit Taneja990a4002016-05-07 23:11:25 +053051struct msm_mdss;
Rob Clarka7d3c952014-05-30 14:47:38 -040052struct msm_rd_state;
Rob Clark70c70f02014-05-30 14:49:43 -040053struct msm_perf_state;
Rob Clarka7d3c952014-05-30 14:47:38 -040054struct msm_gem_submit;
Rob Clarkca762a82016-03-15 17:22:13 -040055struct msm_fence_context;
Rob Clarkfde5de62016-03-15 15:35:08 -040056struct msm_fence_cb;
Rob Clarkc8afe682013-06-26 12:44:06 -040057
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070058#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
59#define MAX_CRTCS 8
60#define MAX_PLANES 12
61#define MAX_ENCODERS 8
62#define MAX_BRIDGES 8
63#define MAX_CONNECTORS 8
Rob Clark7198e6b2013-07-19 12:59:32 -040064
65struct msm_file_private {
66 /* currently we don't do anything useful with this.. but when
67 * per-context address spaces are supported we'd keep track of
68 * the context's page-tables here.
69 */
70 int dummy;
71};
Rob Clarkc8afe682013-06-26 12:44:06 -040072
jilai wang12987782015-06-25 17:37:42 -040073enum msm_mdp_plane_property {
Clarence Ip5e2a9222016-06-26 22:38:24 -040074 /* blob properties, always put these first */
75 PLANE_PROP_SCALER,
76 PLANE_PROP_CSC,
77
78 /* # of blob properties */
79 PLANE_PROP_BLOBCOUNT,
80
Clarence Ipe78efb72016-06-24 18:35:21 -040081 /* range properties */
Clarence Ip5e2a9222016-06-26 22:38:24 -040082 PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
jilai wang12987782015-06-25 17:37:42 -040083 PLANE_PROP_ALPHA,
Clarence Ipcb410d42016-06-26 22:52:33 -040084 PLANE_PROP_COLOR_FILL,
Clarence Ipcae1bb62016-07-07 12:07:13 -040085 PLANE_PROP_INPUT_FENCE,
Clarence Ipe78efb72016-06-24 18:35:21 -040086
Clarence Ip5e2a9222016-06-26 22:38:24 -040087 /* enum/bitmask properties */
88 PLANE_PROP_ROTATION,
89 PLANE_PROP_BLEND_OP,
90 PLANE_PROP_SRC_CONFIG,
Clarence Ipe78efb72016-06-24 18:35:21 -040091
Clarence Ip5e2a9222016-06-26 22:38:24 -040092 /* total # of properties */
93 PLANE_PROP_COUNT
jilai wang12987782015-06-25 17:37:42 -040094};
95
Clarence Ip7a753bb2016-07-07 11:47:44 -040096enum msm_mdp_crtc_property {
97 /* # of blob properties */
98 CRTC_PROP_BLOBCOUNT,
99
100 /* range properties */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400101 CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT,
Clarence Ip24f80662016-06-13 19:05:32 -0400102 CRTC_PROP_OUTPUT_FENCE,
Clarence Ip7a753bb2016-07-07 11:47:44 -0400103
104 /* total # of properties */
105 CRTC_PROP_COUNT
106};
107
Hai Li78b1d472015-07-27 13:49:45 -0400108struct msm_vblank_ctrl {
109 struct work_struct work;
110 struct list_head event_list;
111 spinlock_t lock;
112};
113
Ajay Singh Parmar64c19192016-06-10 16:44:56 -0700114struct display_manager;
115
Rob Clarkc8afe682013-06-26 12:44:06 -0400116struct msm_drm_private {
117
Rob Clark68209392016-05-17 16:19:32 -0400118 struct drm_device *dev;
119
Rob Clarkc8afe682013-06-26 12:44:06 -0400120 struct msm_kms *kms;
121
Rob Clark060530f2014-03-03 14:19:12 -0500122 /* subordinate devices, if present: */
Rob Clark067fef32014-11-04 13:33:14 -0500123 struct platform_device *gpu_pdev;
124
Archit Taneja990a4002016-05-07 23:11:25 +0530125 /* top level MDSS wrapper device (for MDP5 only) */
126 struct msm_mdss *mdss;
127
Rob Clark067fef32014-11-04 13:33:14 -0500128 /* possibly this should be in the kms component, but it is
129 * shared by both mdp4 and mdp5..
130 */
131 struct hdmi *hdmi;
Rob Clark060530f2014-03-03 14:19:12 -0500132
Hai Liab5b0102015-01-07 18:47:44 -0500133 /* eDP is for mdp5 only, but kms has not been created
134 * when edp_bind() and edp_init() are called. Here is the only
135 * place to keep the edp instance.
136 */
137 struct msm_edp *edp;
138
Hai Lia6895542015-03-31 14:36:33 -0400139 /* DSI is shared by mdp4 and mdp5 */
140 struct msm_dsi *dsi[2];
141
Ajay Singh Parmar64c19192016-06-10 16:44:56 -0700142 /* Display manager for SDE driver */
143 struct display_manager *dm;
144
Rob Clark7198e6b2013-07-19 12:59:32 -0400145 /* when we have more than one 'msm_gpu' these need to be an array: */
146 struct msm_gpu *gpu;
147 struct msm_file_private *lastctx;
148
Rob Clarkc8afe682013-06-26 12:44:06 -0400149 struct drm_fb_helper *fbdev;
150
Rob Clarka7d3c952014-05-30 14:47:38 -0400151 struct msm_rd_state *rd;
Rob Clark70c70f02014-05-30 14:49:43 -0400152 struct msm_perf_state *perf;
Rob Clarka7d3c952014-05-30 14:47:38 -0400153
Rob Clarkc8afe682013-06-26 12:44:06 -0400154 /* list of GEM objects: */
155 struct list_head inactive_list;
156
157 struct workqueue_struct *wq;
Rob Clarkba00c3f2016-03-16 18:18:17 -0400158 struct workqueue_struct *atomic_wq;
Rob Clarkc8afe682013-06-26 12:44:06 -0400159
Rob Clarkf86afec2014-11-25 12:41:18 -0500160 /* crtcs pending async atomic updates: */
161 uint32_t pending_crtcs;
162 wait_queue_head_t pending_crtcs_event;
163
Rob Clark871d8122013-11-16 12:56:06 -0500164 /* registered MMUs: */
165 unsigned int num_mmus;
166 struct msm_mmu *mmus[NUM_DOMAINS];
Rob Clarkc8afe682013-06-26 12:44:06 -0400167
Rob Clarka8623912013-10-08 12:57:48 -0400168 unsigned int num_planes;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700169 struct drm_plane *planes[MAX_PLANES];
Rob Clarka8623912013-10-08 12:57:48 -0400170
Rob Clarkc8afe682013-06-26 12:44:06 -0400171 unsigned int num_crtcs;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700172 struct drm_crtc *crtcs[MAX_CRTCS];
Rob Clarkc8afe682013-06-26 12:44:06 -0400173
174 unsigned int num_encoders;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700175 struct drm_encoder *encoders[MAX_ENCODERS];
Rob Clarkc8afe682013-06-26 12:44:06 -0400176
Rob Clarka3376e32013-08-30 13:02:15 -0400177 unsigned int num_bridges;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700178 struct drm_bridge *bridges[MAX_BRIDGES];
Rob Clarka3376e32013-08-30 13:02:15 -0400179
Rob Clarkc8afe682013-06-26 12:44:06 -0400180 unsigned int num_connectors;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700181 struct drm_connector *connectors[MAX_CONNECTORS];
Rob Clark871d8122013-11-16 12:56:06 -0500182
jilai wang12987782015-06-25 17:37:42 -0400183 /* Properties */
Clarence Ipe78efb72016-06-24 18:35:21 -0400184 struct drm_property *plane_property[PLANE_PROP_COUNT];
Clarence Ip7a753bb2016-07-07 11:47:44 -0400185 struct drm_property *crtc_property[CRTC_PROP_COUNT];
jilai wang12987782015-06-25 17:37:42 -0400186
Rob Clark871d8122013-11-16 12:56:06 -0500187 /* VRAM carveout, used when no IOMMU: */
188 struct {
189 unsigned long size;
190 dma_addr_t paddr;
191 /* NOTE: mm managed at the page level, size is in # of pages
192 * and position mm_node->start is in # of pages:
193 */
194 struct drm_mm mm;
195 } vram;
Hai Li78b1d472015-07-27 13:49:45 -0400196
Rob Clarke1e9db22016-05-27 11:16:28 -0400197 struct notifier_block vmap_notifier;
Rob Clark68209392016-05-17 16:19:32 -0400198 struct shrinker shrinker;
199
Hai Li78b1d472015-07-27 13:49:45 -0400200 struct msm_vblank_ctrl vblank_ctrl;
Rob Clarkd78d3832016-08-22 15:28:38 -0400201
202 /* task holding struct_mutex.. currently only used in submit path
203 * to detect and reject faults from copy_from_user() for submit
204 * ioctl.
205 */
206 struct task_struct *struct_mutex_task;
Lloyd Atkinson154b6aa2016-05-24 17:11:37 -0400207
208 struct msm_evtlog evtlog;
Rob Clarkc8afe682013-06-26 12:44:06 -0400209};
210
Clarence Ip7f23b892016-06-01 10:30:34 -0400211/* Helper macro for accessing msm_drm_private's event log */
212#define MSM_EVTMSG(dev, msg, x, y) do { \
213 if ((dev) && ((struct drm_device *)(dev))->dev_private) \
214 msm_evtlog_sample(&((struct msm_drm_private *) \
215 ((struct drm_device *) \
216 (dev))->dev_private)->evtlog, __func__,\
217 (msg), (uint64_t)(x), (uint64_t)(y), \
218 __LINE__); \
219 } while (0)
220
221/* Helper macro for accessing msm_drm_private's event log */
222#define MSM_EVT(dev, x, y) MSM_EVTMSG((dev), 0, (x), (y))
223
Rob Clarkc8afe682013-06-26 12:44:06 -0400224struct msm_format {
225 uint32_t pixel_format;
226};
227
Daniel Vetterb4274fb2014-11-26 17:02:18 +0100228int msm_atomic_check(struct drm_device *dev,
229 struct drm_atomic_state *state);
Rob Clarkcf3a7e42014-11-08 13:21:06 -0500230int msm_atomic_commit(struct drm_device *dev,
Maarten Lankhorsta3ccfb92016-04-26 16:11:38 +0200231 struct drm_atomic_state *state, bool nonblock);
Rob Clarkcf3a7e42014-11-08 13:21:06 -0500232
Rob Clark871d8122013-11-16 12:56:06 -0500233int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
Rob Clarkc8afe682013-06-26 12:44:06 -0400234
Rob Clark40e68152016-05-03 09:50:26 -0400235void msm_gem_submit_free(struct msm_gem_submit *submit);
Rob Clark7198e6b2013-07-19 12:59:32 -0400236int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
237 struct drm_file *file);
238
Rob Clark68209392016-05-17 16:19:32 -0400239void msm_gem_shrinker_init(struct drm_device *dev);
240void msm_gem_shrinker_cleanup(struct drm_device *dev);
241
Daniel Thompson77a147e2014-11-12 11:38:14 +0000242int msm_gem_mmap_obj(struct drm_gem_object *obj,
243 struct vm_area_struct *vma);
Rob Clarkc8afe682013-06-26 12:44:06 -0400244int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
245int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
246uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
247int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
248 uint32_t *iova);
249int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
Rob Clark2638d902014-11-08 09:13:37 -0500250uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
Rob Clark05b84912013-09-28 11:28:35 -0400251struct page **msm_gem_get_pages(struct drm_gem_object *obj);
252void msm_gem_put_pages(struct drm_gem_object *obj);
Rob Clarkc8afe682013-06-26 12:44:06 -0400253void msm_gem_put_iova(struct drm_gem_object *obj, int id);
254int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
255 struct drm_mode_create_dumb *args);
Rob Clarkc8afe682013-06-26 12:44:06 -0400256int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
257 uint32_t handle, uint64_t *offset);
Rob Clark05b84912013-09-28 11:28:35 -0400258struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
259void *msm_gem_prime_vmap(struct drm_gem_object *obj);
260void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
Daniel Thompson77a147e2014-11-12 11:38:14 +0000261int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
Rob Clark05b84912013-09-28 11:28:35 -0400262struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
Maarten Lankhorstb5e9c1a2014-01-09 11:03:14 +0100263 struct dma_buf_attachment *attach, struct sg_table *sg);
Rob Clark05b84912013-09-28 11:28:35 -0400264int msm_gem_prime_pin(struct drm_gem_object *obj);
265void msm_gem_prime_unpin(struct drm_gem_object *obj);
Rob Clark18f23042016-05-26 16:24:35 -0400266void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
267void *msm_gem_get_vaddr(struct drm_gem_object *obj);
268void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
269void msm_gem_put_vaddr(struct drm_gem_object *obj);
Rob Clark4cd33c42016-05-17 15:44:49 -0400270int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
Rob Clark68209392016-05-17 16:19:32 -0400271void msm_gem_purge(struct drm_gem_object *obj);
Rob Clarke1e9db22016-05-27 11:16:28 -0400272void msm_gem_vunmap(struct drm_gem_object *obj);
Rob Clarkb6295f92016-03-15 18:26:28 -0400273int msm_gem_sync_object(struct drm_gem_object *obj,
274 struct msm_fence_context *fctx, bool exclusive);
Rob Clark7198e6b2013-07-19 12:59:32 -0400275void msm_gem_move_to_active(struct drm_gem_object *obj,
Rob Clarkb6295f92016-03-15 18:26:28 -0400276 struct msm_gpu *gpu, bool exclusive, struct fence *fence);
Rob Clark7198e6b2013-07-19 12:59:32 -0400277void msm_gem_move_to_inactive(struct drm_gem_object *obj);
Rob Clarkba00c3f2016-03-16 18:18:17 -0400278int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
Rob Clark7198e6b2013-07-19 12:59:32 -0400279int msm_gem_cpu_fini(struct drm_gem_object *obj);
Rob Clarkc8afe682013-06-26 12:44:06 -0400280void msm_gem_free_object(struct drm_gem_object *obj);
281int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
282 uint32_t size, uint32_t flags, uint32_t *handle);
283struct drm_gem_object *msm_gem_new(struct drm_device *dev,
284 uint32_t size, uint32_t flags);
Rob Clark05b84912013-09-28 11:28:35 -0400285struct drm_gem_object *msm_gem_import(struct drm_device *dev,
Rob Clark79f0e202016-03-16 12:40:35 -0400286 struct dma_buf *dmabuf, struct sg_table *sgt);
Rob Clarkc8afe682013-06-26 12:44:06 -0400287
Rob Clark2638d902014-11-08 09:13:37 -0500288int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
289void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
290uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
Rob Clarkc8afe682013-06-26 12:44:06 -0400291struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
292const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
293struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
Ville Syrjälä1eb83452015-11-11 19:11:29 +0200294 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
Rob Clarkc8afe682013-06-26 12:44:06 -0400295struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
Ville Syrjälä1eb83452015-11-11 19:11:29 +0200296 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
Rob Clarkc8afe682013-06-26 12:44:06 -0400297
298struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
Archit Taneja1aaa57f2016-02-25 11:19:45 +0530299void msm_fbdev_free(struct drm_device *dev);
Rob Clarkc8afe682013-06-26 12:44:06 -0400300
Rob Clarkdada25b2013-12-01 12:12:54 -0500301struct hdmi;
Arnd Bergmannfcda50c2016-02-22 22:08:35 +0100302int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
Rob Clark067fef32014-11-04 13:33:14 -0500303 struct drm_encoder *encoder);
Arnd Bergmannfcda50c2016-02-22 22:08:35 +0100304void __init msm_hdmi_register(void);
305void __exit msm_hdmi_unregister(void);
Rob Clarkc8afe682013-06-26 12:44:06 -0400306
Hai Li00453982014-12-12 14:41:17 -0500307struct msm_edp;
308void __init msm_edp_register(void);
309void __exit msm_edp_unregister(void);
310int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
311 struct drm_encoder *encoder);
312
Hai Lia6895542015-03-31 14:36:33 -0400313struct msm_dsi;
314enum msm_dsi_encoder_id {
315 MSM_DSI_VIDEO_ENCODER_ID = 0,
316 MSM_DSI_CMD_ENCODER_ID = 1,
317 MSM_DSI_ENCODER_NUM = 2
318};
319#ifdef CONFIG_DRM_MSM_DSI
320void __init msm_dsi_register(void);
321void __exit msm_dsi_unregister(void);
322int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
323 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
324#else
325static inline void __init msm_dsi_register(void)
326{
327}
328static inline void __exit msm_dsi_unregister(void)
329{
330}
331static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
332 struct drm_device *dev,
333 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
334{
335 return -EINVAL;
336}
337#endif
338
Archit Taneja1dd0a0b2016-05-30 16:36:50 +0530339void __init msm_mdp_register(void);
340void __exit msm_mdp_unregister(void);
341
Rob Clarkc8afe682013-06-26 12:44:06 -0400342#ifdef CONFIG_DEBUG_FS
343void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
344void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
345void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
Rob Clarka7d3c952014-05-30 14:47:38 -0400346int msm_debugfs_late_init(struct drm_device *dev);
347int msm_rd_debugfs_init(struct drm_minor *minor);
348void msm_rd_debugfs_cleanup(struct drm_minor *minor);
349void msm_rd_dump_submit(struct msm_gem_submit *submit);
Rob Clark70c70f02014-05-30 14:49:43 -0400350int msm_perf_debugfs_init(struct drm_minor *minor);
351void msm_perf_debugfs_cleanup(struct drm_minor *minor);
Rob Clarka7d3c952014-05-30 14:47:38 -0400352#else
353static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
354static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
Rob Clarkc8afe682013-06-26 12:44:06 -0400355#endif
356
357void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
358 const char *dbgname);
359void msm_writel(u32 data, void __iomem *addr);
360u32 msm_readl(const void __iomem *addr);
361
362#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
363#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
364
365static inline int align_pitch(int width, int bpp)
366{
367 int bytespp = (bpp + 7) / 8;
368 /* adreno needs pitch aligned to 32 pixels: */
369 return bytespp * ALIGN(width, 32);
370}
371
372/* for the generated headers: */
373#define INVALID_IDX(idx) ({BUG(); 0;})
Rob Clark7198e6b2013-07-19 12:59:32 -0400374#define fui(x) ({BUG(); 0;})
375#define util_float_to_half(x) ({BUG(); 0;})
376
Rob Clarkc8afe682013-06-26 12:44:06 -0400377
378#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
379
380/* for conditionally setting boolean flag(s): */
381#define COND(bool, val) ((bool) ? (val) : 0)
382
Rob Clark340ff412016-03-16 14:57:22 -0400383static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
384{
385 ktime_t now = ktime_get();
386 unsigned long remaining_jiffies;
387
388 if (ktime_compare(*timeout, now) < 0) {
389 remaining_jiffies = 0;
390 } else {
391 ktime_t rem = ktime_sub(*timeout, now);
392 struct timespec ts = ktime_to_timespec(rem);
393 remaining_jiffies = timespec_to_jiffies(&ts);
394 }
395
396 return remaining_jiffies;
397}
Rob Clarkc8afe682013-06-26 12:44:06 -0400398
399#endif /* __MSM_DRV_H__ */