Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 1 | /* |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 2 | * intel-mid.h: Intel MID specific setup code |
Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 3 | * |
| 4 | * (C) Copyright 2009 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; version 2 |
| 9 | * of the License. |
| 10 | */ |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 11 | #ifndef _ASM_X86_INTEL_MID_H |
| 12 | #define _ASM_X86_INTEL_MID_H |
Feng Tang | c20b5c3 | 2010-09-13 15:08:55 +0800 | [diff] [blame] | 13 | |
| 14 | #include <linux/sfi.h> |
David Cohen | 40a96d5 | 2013-10-17 15:35:36 -0700 | [diff] [blame] | 15 | #include <linux/platform_device.h> |
Feng Tang | c20b5c3 | 2010-09-13 15:08:55 +0800 | [diff] [blame] | 16 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 17 | extern int intel_mid_pci_init(void); |
David Cohen | 40a96d5 | 2013-10-17 15:35:36 -0700 | [diff] [blame] | 18 | extern int get_gpio_by_name(const char *name); |
| 19 | extern void intel_scu_device_register(struct platform_device *pdev); |
Feng Tang | 7309282 | 2010-11-10 17:29:00 +0000 | [diff] [blame] | 20 | extern int __init sfi_parse_mrtc(struct sfi_table_header *table); |
Kuppuswamy Sathyanarayanan | aeedb37 | 2013-10-17 15:35:33 -0700 | [diff] [blame] | 21 | extern int __init sfi_parse_mtmr(struct sfi_table_header *table); |
Feng Tang | 7309282 | 2010-11-10 17:29:00 +0000 | [diff] [blame] | 22 | extern int sfi_mrtc_num; |
| 23 | extern struct sfi_rtc_table_entry sfi_mrtc_array[]; |
Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 24 | |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 25 | /* |
Kuppuswamy Sathyanarayanan | 49c72a0 | 2013-10-17 15:35:32 -0700 | [diff] [blame] | 26 | * Here defines the array of devices platform data that IAFW would export |
| 27 | * through SFI "DEVS" table, we use name and type to match the device and |
| 28 | * its platform data. |
| 29 | */ |
| 30 | struct devs_id { |
| 31 | char name[SFI_NAME_LEN + 1]; |
| 32 | u8 type; |
| 33 | u8 delay; |
| 34 | void *(*get_platform_data)(void *info); |
| 35 | /* Custom handler for devices */ |
| 36 | void (*device_handler)(struct sfi_device_table_entry *pentry, |
| 37 | struct devs_id *dev); |
| 38 | }; |
| 39 | |
David Cohen | 40a96d5 | 2013-10-17 15:35:36 -0700 | [diff] [blame] | 40 | #define sfi_device(i) \ |
| 41 | static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \ |
| 42 | __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i |
| 43 | |
Kuppuswamy Sathyanarayanan | 49c72a0 | 2013-10-17 15:35:32 -0700 | [diff] [blame] | 44 | /* |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 45 | * Medfield is the follow-up of Moorestown, it combines two chip solution into |
| 46 | * one. Other than that it also added always-on and constant tsc and lapic |
| 47 | * timers. Medfield is the platform name, and the chip name is called Penwell |
| 48 | * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be |
| 49 | * identified via MSRs. |
| 50 | */ |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 51 | enum intel_mid_cpu_type { |
Alan Cox | 1a8359e | 2012-01-26 17:33:30 +0000 | [diff] [blame] | 52 | /* 1 was Moorestown */ |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 53 | INTEL_MID_CPU_CHIP_PENWELL = 2, |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 54 | INTEL_MID_CPU_CHIP_CLOVERVIEW, |
David Cohen | bc20aa48 | 2013-12-16 12:07:38 -0800 | [diff] [blame] | 55 | INTEL_MID_CPU_CHIP_TANGIER, |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 56 | }; |
| 57 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 58 | extern enum intel_mid_cpu_type __intel_mid_cpu_chip; |
Mathias Nyman | 35d4769 | 2011-11-15 14:46:52 -0800 | [diff] [blame] | 59 | |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 60 | /** |
| 61 | * struct intel_mid_ops - Interface between intel-mid & sub archs |
| 62 | * @arch_setup: arch_setup function to re-initialize platform |
| 63 | * structures (x86_init, x86_platform_init) |
| 64 | * |
| 65 | * This structure can be extended if any new interface is required |
| 66 | * between intel-mid & its sub arch files. |
| 67 | */ |
| 68 | struct intel_mid_ops { |
| 69 | void (*arch_setup)(void); |
| 70 | }; |
| 71 | |
| 72 | /* Helper API's for INTEL_MID_OPS_INIT */ |
| 73 | #define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ |
| 74 | [cpuid] = get_##cpuname##_ops |
| 75 | |
| 76 | /* Maximum number of CPU ops */ |
| 77 | #define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) |
| 78 | |
| 79 | /* |
| 80 | * For every new cpu addition, a weak get_<cpuname>_ops() function needs be |
| 81 | * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. |
| 82 | */ |
| 83 | #define INTEL_MID_OPS_INIT {\ |
| 84 | DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ |
| 85 | DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ |
David Cohen | bc20aa48 | 2013-12-16 12:07:38 -0800 | [diff] [blame] | 86 | DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 87 | }; |
| 88 | |
Mathias Nyman | 35d4769 | 2011-11-15 14:46:52 -0800 | [diff] [blame] | 89 | #ifdef CONFIG_X86_INTEL_MID |
| 90 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 91 | static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) |
H. Peter Anvin | a75af58 | 2010-05-19 13:40:14 -0700 | [diff] [blame] | 92 | { |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 93 | return __intel_mid_cpu_chip; |
H. Peter Anvin | a75af58 | 2010-05-19 13:40:14 -0700 | [diff] [blame] | 94 | } |
| 95 | |
David Cohen | 40a96d5 | 2013-10-17 15:35:36 -0700 | [diff] [blame] | 96 | static inline bool intel_mid_has_msic(void) |
| 97 | { |
| 98 | return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL); |
| 99 | } |
| 100 | |
Mathias Nyman | 35d4769 | 2011-11-15 14:46:52 -0800 | [diff] [blame] | 101 | #else /* !CONFIG_X86_INTEL_MID */ |
| 102 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 103 | #define intel_mid_identify_cpu() (0) |
David Cohen | 40a96d5 | 2013-10-17 15:35:36 -0700 | [diff] [blame] | 104 | #define intel_mid_has_msic() (0) |
Mathias Nyman | 35d4769 | 2011-11-15 14:46:52 -0800 | [diff] [blame] | 105 | |
| 106 | #endif /* !CONFIG_X86_INTEL_MID */ |
| 107 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 108 | enum intel_mid_timer_options { |
| 109 | INTEL_MID_TIMER_DEFAULT, |
| 110 | INTEL_MID_TIMER_APBT_ONLY, |
| 111 | INTEL_MID_TIMER_LAPIC_APBT, |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 112 | }; |
| 113 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 114 | extern enum intel_mid_timer_options intel_mid_timer_options; |
H. Peter Anvin | 1467138 | 2010-05-19 14:37:40 -0700 | [diff] [blame] | 115 | |
Dirk Brandewie | 0a91532 | 2011-11-10 13:42:53 +0000 | [diff] [blame] | 116 | /* |
| 117 | * Penwell uses spread spectrum clock, so the freq number is not exactly |
| 118 | * the same as reported by MSR based on SDM. |
| 119 | */ |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 120 | #define FSB_FREQ_83SKU 83200 |
| 121 | #define FSB_FREQ_100SKU 99840 |
| 122 | #define FSB_FREQ_133SKU 133000 |
| 123 | |
| 124 | #define FSB_FREQ_167SKU 167000 |
| 125 | #define FSB_FREQ_200SKU 200000 |
| 126 | #define FSB_FREQ_267SKU 267000 |
| 127 | #define FSB_FREQ_333SKU 333000 |
| 128 | #define FSB_FREQ_400SKU 400000 |
| 129 | |
| 130 | /* Bus Select SoC Fuse value */ |
| 131 | #define BSEL_SOC_FUSE_MASK 0x7 |
| 132 | #define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ |
| 133 | #define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ |
| 134 | #define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ |
Dirk Brandewie | 0a91532 | 2011-11-10 13:42:53 +0000 | [diff] [blame] | 135 | |
Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 136 | #define SFI_MTMR_MAX_NUM 8 |
Feng Tang | cf08945 | 2010-02-12 03:37:38 -0800 | [diff] [blame] | 137 | #define SFI_MRTC_MAX 8 |
Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 138 | |
Feng Tang | 1da4b1c | 2010-11-09 11:22:58 +0000 | [diff] [blame] | 139 | extern void intel_scu_devices_create(void); |
| 140 | extern void intel_scu_devices_destroy(void); |
| 141 | |
Feng Tang | 7309282 | 2010-11-10 17:29:00 +0000 | [diff] [blame] | 142 | /* VRTC timer */ |
| 143 | #define MRST_VRTC_MAP_SZ (1024) |
| 144 | /*#define MRST_VRTC_PGOFFSET (0xc00) */ |
| 145 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 146 | extern void intel_mid_rtc_init(void); |
Feng Tang | 7309282 | 2010-11-10 17:29:00 +0000 | [diff] [blame] | 147 | |
David Cohen | 40a96d5 | 2013-10-17 15:35:36 -0700 | [diff] [blame] | 148 | /* the offset for the mapping of global gpio pin to irq */ |
| 149 | #define INTEL_MID_IRQ_OFFSET 0x100 |
| 150 | |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 151 | #endif /* _ASM_X86_INTEL_MID_H */ |