blob: e1b9ce30429a3dc7c1293b50945d7dff6305b6ef [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010016#include <linux/i2c.h>
Ben Hutchingsf31a45d2008-12-12 21:43:33 -080017#include <linux/mii.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010018#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010022#include "spi.h"
23#include "falcon.h"
Ben Hutchings3e6c4532009-10-23 08:30:36 +000024#include "regs.h"
Ben Hutchings12d00ca2009-10-23 08:30:46 +000025#include "io.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010026#include "mdio_10g.h"
27#include "phy.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010028#include "workarounds.h"
29
Ben Hutchings89863522009-11-25 16:09:04 +000030/* Hardware control for SFC4000 (aka Falcon). */
Ben Hutchings8ceee662008-04-27 12:55:59 +010031
Ben Hutchings8ceee662008-04-27 12:55:59 +010032/**************************************************************************
33 *
34 * Configurable values
35 *
36 **************************************************************************
37 */
38
39static int disable_dma_stats;
40
41/* This is set to 16 for a good reason. In summary, if larger than
42 * 16, the descriptor cache holds more than a default socket
43 * buffer's worth of packets (for UDP we can only have at most one
44 * socket buffer's worth outstanding). This combined with the fact
45 * that we only get 1 TX event per descriptor cache means the NIC
46 * goes idle.
47 */
48#define TX_DC_ENTRIES 16
Ben Hutchings46e1ac02009-11-25 16:08:30 +000049#define TX_DC_ENTRIES_ORDER 1
Ben Hutchings8ceee662008-04-27 12:55:59 +010050#define TX_DC_BASE 0x130000
51
52#define RX_DC_ENTRIES 64
Ben Hutchings46e1ac02009-11-25 16:08:30 +000053#define RX_DC_ENTRIES_ORDER 3
Ben Hutchings8ceee662008-04-27 12:55:59 +010054#define RX_DC_BASE 0x100000
55
Ben Hutchings2f7f5732008-12-12 21:34:25 -080056static const unsigned int
57/* "Large" EEPROM device: Atmel AT25640 or similar
58 * 8 KB, 16-bit address, 32 B write block */
59large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
60 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
61 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
62/* Default flash device: Atmel AT25F1024
63 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
64default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
65 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
66 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
67 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
68 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
69
Ben Hutchings8ceee662008-04-27 12:55:59 +010070/* RX FIFO XOFF watermark
71 *
72 * When the amount of the RX FIFO increases used increases past this
73 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
74 * This also has an effect on RX/TX arbitration
75 */
76static int rx_xoff_thresh_bytes = -1;
77module_param(rx_xoff_thresh_bytes, int, 0644);
78MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
79
80/* RX FIFO XON watermark
81 *
82 * When the amount of the RX FIFO used decreases below this
83 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
84 * This also has an effect on RX/TX arbitration
85 */
86static int rx_xon_thresh_bytes = -1;
87module_param(rx_xon_thresh_bytes, int, 0644);
88MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
89
Ben Hutchings2c3c3d02009-03-04 10:01:57 +000090/* If FALCON_MAX_INT_ERRORS internal errors occur within
91 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
92 * disable it.
93 */
94#define FALCON_INT_ERROR_EXPIRE 3600
95#define FALCON_MAX_INT_ERRORS 5
Ben Hutchings8ceee662008-04-27 12:55:59 +010096
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +010097/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
98 */
99#define FALCON_FLUSH_INTERVAL 10
100#define FALCON_FLUSH_POLL_COUNT 100
Ben Hutchings8ceee662008-04-27 12:55:59 +0100101
102/**************************************************************************
103 *
104 * Falcon constants
105 *
106 **************************************************************************
107 */
108
Ben Hutchings8ceee662008-04-27 12:55:59 +0100109/* Size and alignment of special buffers (4KB) */
110#define FALCON_BUF_SIZE 4096
111
Ben Hutchings127e6e12009-11-25 16:09:55 +0000112/* Depth of RX flush request fifo */
113#define FALCON_RX_FLUSH_COUNT 4
114
Ben Hutchings8ceee662008-04-27 12:55:59 +0100115#define FALCON_IS_DUAL_FUNC(efx) \
Ben Hutchings55668612008-05-16 21:16:10 +0100116 (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100117
118/**************************************************************************
119 *
120 * Falcon hardware access
121 *
122 **************************************************************************/
123
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000124static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
125 unsigned int index)
126{
127 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
128 value, index);
129}
130
Ben Hutchings8ceee662008-04-27 12:55:59 +0100131/* Read the current event from the event queue */
132static inline efx_qword_t *falcon_event(struct efx_channel *channel,
133 unsigned int index)
134{
135 return (((efx_qword_t *) (channel->eventq.addr)) + index);
136}
137
138/* See if an event is present
139 *
140 * We check both the high and low dword of the event for all ones. We
141 * wrote all ones when we cleared the event, and no valid event can
142 * have all ones in either its high or low dwords. This approach is
143 * robust against reordering.
144 *
145 * Note that using a single 64-bit comparison is incorrect; even
146 * though the CPU read will be atomic, the DMA write may not be.
147 */
148static inline int falcon_event_present(efx_qword_t *event)
149{
150 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
151 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
152}
153
154/**************************************************************************
155 *
156 * I2C bus - this is a bit-bashing interface using GPIO pins
157 * Note that it uses the output enables to tristate the outputs
158 * SDA is the data pin and SCL is the clock
159 *
160 **************************************************************************
161 */
Ben Hutchings37b5a602008-05-30 22:27:04 +0100162static void falcon_setsda(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100163{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100164 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100165 efx_oword_t reg;
166
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000167 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000168 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000169 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100170}
171
Ben Hutchings37b5a602008-05-30 22:27:04 +0100172static void falcon_setscl(void *data, int state)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100173{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100174 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100175 efx_oword_t reg;
176
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000177 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000178 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000179 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
Ben Hutchings37b5a602008-05-30 22:27:04 +0100180}
181
182static int falcon_getsda(void *data)
183{
184 struct efx_nic *efx = (struct efx_nic *)data;
185 efx_oword_t reg;
186
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000187 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000188 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100189}
190
Ben Hutchings37b5a602008-05-30 22:27:04 +0100191static int falcon_getscl(void *data)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100192{
Ben Hutchings37b5a602008-05-30 22:27:04 +0100193 struct efx_nic *efx = (struct efx_nic *)data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100194 efx_oword_t reg;
195
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000196 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000197 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100198}
199
Ben Hutchings37b5a602008-05-30 22:27:04 +0100200static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
201 .setsda = falcon_setsda,
202 .setscl = falcon_setscl,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100203 .getsda = falcon_getsda,
204 .getscl = falcon_getscl,
Ben Hutchings62c78322008-05-30 22:27:46 +0100205 .udelay = 5,
Ben Hutchings9dadae62008-07-18 18:59:12 +0100206 /* Wait up to 50 ms for slave to let us pull SCL high */
207 .timeout = DIV_ROUND_UP(HZ, 20),
Ben Hutchings8ceee662008-04-27 12:55:59 +0100208};
209
210/**************************************************************************
211 *
212 * Falcon special buffer handling
213 * Special buffers are used for event queues and the TX and RX
214 * descriptor rings.
215 *
216 *************************************************************************/
217
218/*
219 * Initialise a Falcon special buffer
220 *
221 * This will define a buffer (previously allocated via
222 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
223 * it to be used for event queues, descriptor rings etc.
224 */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100225static void
Ben Hutchings8ceee662008-04-27 12:55:59 +0100226falcon_init_special_buffer(struct efx_nic *efx,
227 struct efx_special_buffer *buffer)
228{
229 efx_qword_t buf_desc;
230 int index;
231 dma_addr_t dma_addr;
232 int i;
233
234 EFX_BUG_ON_PARANOID(!buffer->addr);
235
236 /* Write buffer descriptors to NIC */
237 for (i = 0; i < buffer->entries; i++) {
238 index = buffer->index + i;
239 dma_addr = buffer->dma_addr + (i * 4096);
240 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
241 index, (unsigned long long)dma_addr);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000242 EFX_POPULATE_QWORD_3(buf_desc,
243 FRF_AZ_BUF_ADR_REGION, 0,
244 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
245 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000246 falcon_write_buf_tbl(efx, &buf_desc, index);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100247 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100248}
249
250/* Unmaps a buffer from Falcon and clears the buffer table entries */
251static void
252falcon_fini_special_buffer(struct efx_nic *efx,
253 struct efx_special_buffer *buffer)
254{
255 efx_oword_t buf_tbl_upd;
256 unsigned int start = buffer->index;
257 unsigned int end = (buffer->index + buffer->entries - 1);
258
259 if (!buffer->entries)
260 return;
261
262 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
263 buffer->index, buffer->index + buffer->entries - 1);
264
265 EFX_POPULATE_OWORD_4(buf_tbl_upd,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000266 FRF_AZ_BUF_UPD_CMD, 0,
267 FRF_AZ_BUF_CLR_CMD, 1,
268 FRF_AZ_BUF_CLR_END_ID, end,
269 FRF_AZ_BUF_CLR_START_ID, start);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000270 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100271}
272
273/*
274 * Allocate a new Falcon special buffer
275 *
276 * This allocates memory for a new buffer, clears it and allocates a
277 * new buffer ID range. It does not write into Falcon's buffer table.
278 *
279 * This call will allocate 4KB buffers, since Falcon can't use 8KB
280 * buffers for event queues and descriptor rings.
281 */
282static int falcon_alloc_special_buffer(struct efx_nic *efx,
283 struct efx_special_buffer *buffer,
284 unsigned int len)
285{
Ben Hutchings8ceee662008-04-27 12:55:59 +0100286 len = ALIGN(len, FALCON_BUF_SIZE);
287
288 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
289 &buffer->dma_addr);
290 if (!buffer->addr)
291 return -ENOMEM;
292 buffer->len = len;
293 buffer->entries = len / FALCON_BUF_SIZE;
294 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
295
296 /* All zeros is a potentially valid event so memset to 0xff */
297 memset(buffer->addr, 0xff, len);
298
299 /* Select new buffer ID */
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000300 buffer->index = efx->next_buffer_table;
301 efx->next_buffer_table += buffer->entries;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100302
303 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +0530304 "(virt %p phys %llx)\n", buffer->index,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100305 buffer->index + buffer->entries - 1,
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +0530306 (u64)buffer->dma_addr, len,
307 buffer->addr, (u64)virt_to_phys(buffer->addr));
Ben Hutchings8ceee662008-04-27 12:55:59 +0100308
309 return 0;
310}
311
312static void falcon_free_special_buffer(struct efx_nic *efx,
313 struct efx_special_buffer *buffer)
314{
315 if (!buffer->addr)
316 return;
317
318 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +0530319 "(virt %p phys %llx)\n", buffer->index,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100320 buffer->index + buffer->entries - 1,
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +0530321 (u64)buffer->dma_addr, buffer->len,
322 buffer->addr, (u64)virt_to_phys(buffer->addr));
Ben Hutchings8ceee662008-04-27 12:55:59 +0100323
324 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
325 buffer->dma_addr);
326 buffer->addr = NULL;
327 buffer->entries = 0;
328}
329
330/**************************************************************************
331 *
332 * Falcon generic buffer handling
333 * These buffers are used for interrupt status and MAC stats
334 *
335 **************************************************************************/
336
337static int falcon_alloc_buffer(struct efx_nic *efx,
338 struct efx_buffer *buffer, unsigned int len)
339{
340 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
341 &buffer->dma_addr);
342 if (!buffer->addr)
343 return -ENOMEM;
344 buffer->len = len;
345 memset(buffer->addr, 0, len);
346 return 0;
347}
348
349static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
350{
351 if (buffer->addr) {
352 pci_free_consistent(efx->pci_dev, buffer->len,
353 buffer->addr, buffer->dma_addr);
354 buffer->addr = NULL;
355 }
356}
357
358/**************************************************************************
359 *
360 * Falcon TX path
361 *
362 **************************************************************************/
363
364/* Returns a pointer to the specified transmit descriptor in the TX
365 * descriptor queue belonging to the specified channel.
366 */
367static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
368 unsigned int index)
369{
370 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
371}
372
373/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
374static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
375{
376 unsigned write_ptr;
377 efx_dword_t reg;
378
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000379 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000380 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000381 efx_writed_page(tx_queue->efx, &reg,
382 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100383}
384
385
386/* For each entry inserted into the software descriptor ring, create a
387 * descriptor in the hardware TX descriptor ring (in host memory), and
388 * write a doorbell.
389 */
390void falcon_push_buffers(struct efx_tx_queue *tx_queue)
391{
392
393 struct efx_tx_buffer *buffer;
394 efx_qword_t *txd;
395 unsigned write_ptr;
396
397 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
398
399 do {
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000400 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100401 buffer = &tx_queue->buffer[write_ptr];
402 txd = falcon_tx_desc(tx_queue, write_ptr);
403 ++tx_queue->write_count;
404
405 /* Create TX descriptor ring entry */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000406 EFX_POPULATE_QWORD_4(*txd,
407 FSF_AZ_TX_KER_CONT, buffer->continuation,
408 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
409 FSF_AZ_TX_KER_BUF_REGION, 0,
410 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100411 } while (tx_queue->write_count != tx_queue->insert_count);
412
413 wmb(); /* Ensure descriptors are written before they are fetched */
414 falcon_notify_tx_desc(tx_queue);
415}
416
417/* Allocate hardware resources for a TX queue */
418int falcon_probe_tx(struct efx_tx_queue *tx_queue)
419{
420 struct efx_nic *efx = tx_queue->efx;
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000421 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
422 EFX_TXQ_SIZE & EFX_TXQ_MASK);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100423 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000424 EFX_TXQ_SIZE * sizeof(efx_qword_t));
Ben Hutchings8ceee662008-04-27 12:55:59 +0100425}
426
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100427void falcon_init_tx(struct efx_tx_queue *tx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100428{
429 efx_oword_t tx_desc_ptr;
430 struct efx_nic *efx = tx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100431
Ben Hutchings127e6e12009-11-25 16:09:55 +0000432 tx_queue->flushed = FLUSH_NONE;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100433
Ben Hutchings8ceee662008-04-27 12:55:59 +0100434 /* Pin TX descriptor ring */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100435 falcon_init_special_buffer(efx, &tx_queue->txd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100436
437 /* Push TX descriptor ring to card */
438 EFX_POPULATE_OWORD_10(tx_desc_ptr,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000439 FRF_AZ_TX_DESCQ_EN, 1,
440 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
441 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
442 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
443 FRF_AZ_TX_DESCQ_EVQ_ID,
444 tx_queue->channel->channel,
445 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
446 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000447 FRF_AZ_TX_DESCQ_SIZE,
448 __ffs(tx_queue->txd.entries),
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000449 FRF_AZ_TX_DESCQ_TYPE, 0,
450 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100451
Ben Hutchings55668612008-05-16 21:16:10 +0100452 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings60ac1062008-09-01 12:44:59 +0100453 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000454 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
455 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
456 !csum);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100457 }
458
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000459 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
460 tx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100461
Ben Hutchings55668612008-05-16 21:16:10 +0100462 if (falcon_rev(efx) < FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100463 efx_oword_t reg;
464
Ben Hutchings60ac1062008-09-01 12:44:59 +0100465 /* Only 128 bits in this register */
466 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100467
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000468 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
Ben Hutchings60ac1062008-09-01 12:44:59 +0100469 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100470 clear_bit_le(tx_queue->queue, (void *)&reg);
471 else
472 set_bit_le(tx_queue->queue, (void *)&reg);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000473 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100474 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100475}
476
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100477static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100478{
479 struct efx_nic *efx = tx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100480 efx_oword_t tx_flush_descq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100481
Ben Hutchings127e6e12009-11-25 16:09:55 +0000482 tx_queue->flushed = FLUSH_PENDING;
483
Ben Hutchings8ceee662008-04-27 12:55:59 +0100484 /* Post a flush command */
485 EFX_POPULATE_OWORD_2(tx_flush_descq,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000486 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
487 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000488 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100489}
490
491void falcon_fini_tx(struct efx_tx_queue *tx_queue)
492{
493 struct efx_nic *efx = tx_queue->efx;
494 efx_oword_t tx_desc_ptr;
495
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100496 /* The queue should have been flushed */
Ben Hutchings127e6e12009-11-25 16:09:55 +0000497 WARN_ON(tx_queue->flushed != FLUSH_DONE);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100498
499 /* Remove TX descriptor ring from card */
500 EFX_ZERO_OWORD(tx_desc_ptr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000501 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
502 tx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100503
504 /* Unpin TX descriptor ring */
505 falcon_fini_special_buffer(efx, &tx_queue->txd);
506}
507
508/* Free buffers backing TX queue */
509void falcon_remove_tx(struct efx_tx_queue *tx_queue)
510{
511 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
512}
513
514/**************************************************************************
515 *
516 * Falcon RX path
517 *
518 **************************************************************************/
519
520/* Returns a pointer to the specified descriptor in the RX descriptor queue */
521static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
522 unsigned int index)
523{
524 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
525}
526
527/* This creates an entry in the RX descriptor queue */
528static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
529 unsigned index)
530{
531 struct efx_rx_buffer *rx_buf;
532 efx_qword_t *rxd;
533
534 rxd = falcon_rx_desc(rx_queue, index);
535 rx_buf = efx_rx_buffer(rx_queue, index);
536 EFX_POPULATE_QWORD_3(*rxd,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000537 FSF_AZ_RX_KER_BUF_SIZE,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100538 rx_buf->len -
539 rx_queue->efx->type->rx_buffer_padding,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000540 FSF_AZ_RX_KER_BUF_REGION, 0,
541 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100542}
543
544/* This writes to the RX_DESC_WPTR register for the specified receive
545 * descriptor ring.
546 */
547void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
548{
549 efx_dword_t reg;
550 unsigned write_ptr;
551
552 while (rx_queue->notified_count != rx_queue->added_count) {
553 falcon_build_rx_desc(rx_queue,
554 rx_queue->notified_count &
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000555 EFX_RXQ_MASK);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100556 ++rx_queue->notified_count;
557 }
558
559 wmb();
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000560 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000561 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000562 efx_writed_page(rx_queue->efx, &reg,
563 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100564}
565
566int falcon_probe_rx(struct efx_rx_queue *rx_queue)
567{
568 struct efx_nic *efx = rx_queue->efx;
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000569 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
570 EFX_RXQ_SIZE & EFX_RXQ_MASK);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100571 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000572 EFX_RXQ_SIZE * sizeof(efx_qword_t));
Ben Hutchings8ceee662008-04-27 12:55:59 +0100573}
574
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100575void falcon_init_rx(struct efx_rx_queue *rx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100576{
577 efx_oword_t rx_desc_ptr;
578 struct efx_nic *efx = rx_queue->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100579 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
580 bool iscsi_digest_en = is_b0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100581
582 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
583 rx_queue->queue, rx_queue->rxd.index,
584 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
585
Ben Hutchings127e6e12009-11-25 16:09:55 +0000586 rx_queue->flushed = FLUSH_NONE;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100587
Ben Hutchings8ceee662008-04-27 12:55:59 +0100588 /* Pin RX descriptor ring */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +0100589 falcon_init_special_buffer(efx, &rx_queue->rxd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100590
591 /* Push RX descriptor ring to card */
592 EFX_POPULATE_OWORD_10(rx_desc_ptr,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000593 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
594 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
595 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
596 FRF_AZ_RX_DESCQ_EVQ_ID,
597 rx_queue->channel->channel,
598 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
599 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000600 FRF_AZ_RX_DESCQ_SIZE,
601 __ffs(rx_queue->rxd.entries),
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000602 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100603 /* For >=B0 this is scatter so disable */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000604 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
605 FRF_AZ_RX_DESCQ_EN, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000606 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
607 rx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100608}
609
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100610static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100611{
612 struct efx_nic *efx = rx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100613 efx_oword_t rx_flush_descq;
614
Ben Hutchings127e6e12009-11-25 16:09:55 +0000615 rx_queue->flushed = FLUSH_PENDING;
616
Ben Hutchings8ceee662008-04-27 12:55:59 +0100617 /* Post a flush command */
618 EFX_POPULATE_OWORD_2(rx_flush_descq,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000619 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
620 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000621 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100622}
623
624void falcon_fini_rx(struct efx_rx_queue *rx_queue)
625{
626 efx_oword_t rx_desc_ptr;
627 struct efx_nic *efx = rx_queue->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100628
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100629 /* The queue should already have been flushed */
Ben Hutchings127e6e12009-11-25 16:09:55 +0000630 WARN_ON(rx_queue->flushed != FLUSH_DONE);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100631
632 /* Remove RX descriptor ring from card */
633 EFX_ZERO_OWORD(rx_desc_ptr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000634 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
635 rx_queue->queue);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100636
637 /* Unpin RX descriptor ring */
638 falcon_fini_special_buffer(efx, &rx_queue->rxd);
639}
640
641/* Free buffers backing RX queue */
642void falcon_remove_rx(struct efx_rx_queue *rx_queue)
643{
644 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
645}
646
647/**************************************************************************
648 *
649 * Falcon event queue processing
650 * Event queues are processed by per-channel tasklets.
651 *
652 **************************************************************************/
653
654/* Update a channel's event queue's read pointer (RPTR) register
655 *
656 * This writes the EVQ_RPTR_REG register for the specified channel's
657 * event queue.
658 *
659 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
660 * whereas channel->eventq_read_ptr contains the index of the "next to
661 * read" event.
662 */
663void falcon_eventq_read_ack(struct efx_channel *channel)
664{
665 efx_dword_t reg;
666 struct efx_nic *efx = channel->efx;
667
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000668 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000669 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
Ben Hutchingsd3074022008-09-01 12:48:03 +0100670 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100671}
672
673/* Use HW to insert a SW defined event */
674void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
675{
676 efx_oword_t drv_ev_reg;
677
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000678 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
679 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
680 drv_ev_reg.u32[0] = event->u32[0];
681 drv_ev_reg.u32[1] = event->u32[1];
682 drv_ev_reg.u32[2] = 0;
683 drv_ev_reg.u32[3] = 0;
684 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
Ben Hutchings12d00ca2009-10-23 08:30:46 +0000685 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100686}
687
688/* Handle a transmit completion event
689 *
690 * Falcon batches TX completion events; the message we receive is of
691 * the form "complete all TX events up to this index".
692 */
Ben Hutchings4d566062008-09-01 12:47:12 +0100693static void falcon_handle_tx_event(struct efx_channel *channel,
694 efx_qword_t *event)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100695{
696 unsigned int tx_ev_desc_ptr;
697 unsigned int tx_ev_q_label;
698 struct efx_tx_queue *tx_queue;
699 struct efx_nic *efx = channel->efx;
700
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000701 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100702 /* Transmit completion */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000703 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
704 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100705 tx_queue = &efx->tx_queue[tx_ev_q_label];
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000706 channel->irq_mod_score +=
707 (tx_ev_desc_ptr - tx_queue->read_count) &
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000708 EFX_TXQ_MASK;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100709 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000710 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100711 /* Rewrite the FIFO write pointer */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000712 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100713 tx_queue = &efx->tx_queue[tx_ev_q_label];
714
Ben Hutchings55668612008-05-16 21:16:10 +0100715 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100716 netif_tx_lock(efx->net_dev);
717 falcon_notify_tx_desc(tx_queue);
Ben Hutchings55668612008-05-16 21:16:10 +0100718 if (efx_dev_registered(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100719 netif_tx_unlock(efx->net_dev);
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000720 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
Ben Hutchings8ceee662008-04-27 12:55:59 +0100721 EFX_WORKAROUND_10727(efx)) {
722 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
723 } else {
724 EFX_ERR(efx, "channel %d unexpected TX event "
725 EFX_QWORD_FMT"\n", channel->channel,
726 EFX_QWORD_VAL(*event));
727 }
728}
729
Ben Hutchings8ceee662008-04-27 12:55:59 +0100730/* Detect errors included in the rx_evt_pkt_ok bit. */
731static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
732 const efx_qword_t *event,
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100733 bool *rx_ev_pkt_ok,
734 bool *discard)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100735{
736 struct efx_nic *efx = rx_queue->efx;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100737 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
738 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
739 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
740 bool rx_ev_other_err, rx_ev_pause_frm;
741 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
742 unsigned rx_ev_pkt_type;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100743
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000744 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
745 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
746 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
747 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100748 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000749 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
750 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100751 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000752 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100753 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000754 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
755 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
756 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
Ben Hutchings55668612008-05-16 21:16:10 +0100757 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000758 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
759 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100760
761 /* Every error apart from tobe_disc and pause_frm */
762 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
763 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
764 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
765
Ben Hutchings50050872008-12-12 21:42:42 -0800766 /* Count errors that are not in MAC stats. Ignore expected
767 * checksum errors during self-test. */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100768 if (rx_ev_frm_trunc)
769 ++rx_queue->channel->n_rx_frm_trunc;
770 else if (rx_ev_tobe_disc)
771 ++rx_queue->channel->n_rx_tobe_disc;
Ben Hutchings50050872008-12-12 21:42:42 -0800772 else if (!efx->loopback_selftest) {
773 if (rx_ev_ip_hdr_chksum_err)
774 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
775 else if (rx_ev_tcp_udp_chksum_err)
776 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
777 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100778 if (rx_ev_ip_frag_err)
779 ++rx_queue->channel->n_rx_ip_frag_err;
780
781 /* The frame must be discarded if any of these are true. */
782 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
783 rx_ev_tobe_disc | rx_ev_pause_frm);
784
785 /* TOBE_DISC is expected on unicast mismatches; don't print out an
786 * error message. FRM_TRUNC indicates RXDP dropped the packet due
787 * to a FIFO overflow.
788 */
789#ifdef EFX_ENABLE_DEBUG
790 if (rx_ev_other_err) {
791 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100792 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
Ben Hutchings8ceee662008-04-27 12:55:59 +0100793 rx_queue->queue, EFX_QWORD_VAL(*event),
794 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
795 rx_ev_ip_hdr_chksum_err ?
796 " [IP_HDR_CHKSUM_ERR]" : "",
797 rx_ev_tcp_udp_chksum_err ?
798 " [TCP_UDP_CHKSUM_ERR]" : "",
799 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
800 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
801 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
802 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100803 rx_ev_pause_frm ? " [PAUSE]" : "");
Ben Hutchings8ceee662008-04-27 12:55:59 +0100804 }
805#endif
Ben Hutchings8ceee662008-04-27 12:55:59 +0100806}
807
808/* Handle receive events that are not in-order. */
809static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
810 unsigned index)
811{
812 struct efx_nic *efx = rx_queue->efx;
813 unsigned expected, dropped;
814
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000815 expected = rx_queue->removed_count & EFX_RXQ_MASK;
816 dropped = (index - expected) & EFX_RXQ_MASK;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100817 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
818 dropped, index, expected);
819
820 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
821 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
822}
823
824/* Handle a packet received event
825 *
826 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
827 * wrong destination address
828 * Also "is multicast" and "matches multicast filter" flags can be used to
829 * discard non-matching multicast packets.
830 */
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100831static void falcon_handle_rx_event(struct efx_channel *channel,
832 const efx_qword_t *event)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100833{
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100834 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100835 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100836 unsigned expected_ptr;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100837 bool rx_ev_pkt_ok, discard = false, checksummed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100838 struct efx_rx_queue *rx_queue;
839 struct efx_nic *efx = channel->efx;
840
841 /* Basic packet information */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000842 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
843 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
844 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
845 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
846 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
847 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
848 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100849
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100850 rx_queue = &efx->rx_queue[channel->channel];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100851
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000852 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
Ben Hutchings3ffeabd2009-10-23 08:30:58 +0000853 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100854 if (unlikely(rx_ev_desc_ptr != expected_ptr))
Ben Hutchings8ceee662008-04-27 12:55:59 +0100855 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100856
857 if (likely(rx_ev_pkt_ok)) {
858 /* If packet is marked as OK and packet type is TCP/IPv4 or
859 * UDP/IPv4, then we can rely on the hardware checksum.
860 */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000861 checksummed =
Ben Hutchings9c1bbba2009-10-28 02:50:44 -0700862 efx->rx_checksum_enabled &&
863 (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
864 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100865 } else {
866 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
Ben Hutchings5b39fe32008-09-01 12:46:03 +0100867 &discard);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100868 checksummed = false;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100869 }
870
871 /* Detect multicast packets that didn't match the filter */
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000872 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100873 if (rx_ev_mcast_pkt) {
874 unsigned int rx_ev_mcast_hash_match =
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000875 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100876
877 if (unlikely(!rx_ev_mcast_hash_match))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100878 discard = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100879 }
880
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000881 channel->irq_mod_score += 2;
882
Ben Hutchings8ceee662008-04-27 12:55:59 +0100883 /* Handle received packet */
884 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
885 checksummed, discard);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100886}
887
888/* Global events are basically PHY events */
889static void falcon_handle_global_event(struct efx_channel *channel,
890 efx_qword_t *event)
891{
892 struct efx_nic *efx = channel->efx;
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800893 bool handled = false;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100894
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000895 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
896 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
897 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800898 efx->phy_op->clear_interrupt(efx);
899 queue_work(efx->workqueue, &efx->phy_work);
900 handled = true;
901 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100902
Ben Hutchings55668612008-05-16 21:16:10 +0100903 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000904 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800905 queue_work(efx->workqueue, &efx->mac_work);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100906 handled = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100907 }
908
Ben Hutchings56241ce2009-10-23 08:30:06 +0000909 if (falcon_rev(efx) <= FALCON_REV_A1 ?
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000910 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
911 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +0100912 EFX_ERR(efx, "channel %d seen global RX_RESET "
913 "event. Resetting.\n", channel->channel);
914
915 atomic_inc(&efx->rx_reset);
916 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
917 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100918 handled = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100919 }
920
921 if (!handled)
922 EFX_ERR(efx, "channel %d unknown global event "
923 EFX_QWORD_FMT "\n", channel->channel,
924 EFX_QWORD_VAL(*event));
925}
926
927static void falcon_handle_driver_event(struct efx_channel *channel,
928 efx_qword_t *event)
929{
930 struct efx_nic *efx = channel->efx;
931 unsigned int ev_sub_code;
932 unsigned int ev_sub_data;
933
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000934 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
935 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100936
937 switch (ev_sub_code) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000938 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100939 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
940 channel->channel, ev_sub_data);
941 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000942 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100943 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
944 channel->channel, ev_sub_data);
945 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000946 case FSE_AZ_EVQ_INIT_DONE_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100947 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
948 channel->channel, ev_sub_data);
949 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000950 case FSE_AZ_SRM_UPD_DONE_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100951 EFX_TRACE(efx, "channel %d SRAM update done\n",
952 channel->channel);
953 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000954 case FSE_AZ_WAKE_UP_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100955 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
956 channel->channel, ev_sub_data);
957 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000958 case FSE_AZ_TIMER_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100959 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
960 channel->channel, ev_sub_data);
961 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000962 case FSE_AA_RX_RECOVER_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100963 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
964 "Resetting.\n", channel->channel);
Ben Hutchings05e3ec02008-05-07 13:00:39 +0100965 atomic_inc(&efx->rx_reset);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100966 efx_schedule_reset(efx,
967 EFX_WORKAROUND_6555(efx) ?
968 RESET_TYPE_RX_RECOVERY :
969 RESET_TYPE_DISABLE);
970 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000971 case FSE_BZ_RX_DSC_ERROR_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100972 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
973 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
974 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
975 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +0000976 case FSE_BZ_TX_DSC_ERROR_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +0100977 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
978 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
979 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
980 break;
981 default:
982 EFX_TRACE(efx, "channel %d unknown driver event code %d "
983 "data %04x\n", channel->channel, ev_sub_code,
984 ev_sub_data);
985 break;
986 }
987}
988
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100989int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100990{
991 unsigned int read_ptr;
992 efx_qword_t event, *p_event;
993 int ev_code;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +0100994 int rx_packets = 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100995
996 read_ptr = channel->eventq_read_ptr;
997
998 do {
999 p_event = falcon_event(channel, read_ptr);
1000 event = *p_event;
1001
1002 if (!falcon_event_present(&event))
1003 /* End of events */
1004 break;
1005
1006 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1007 channel->channel, EFX_QWORD_VAL(event));
1008
1009 /* Clear this event by marking it all ones */
1010 EFX_SET_QWORD(*p_event);
1011
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001012 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001013
1014 switch (ev_code) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001015 case FSE_AZ_EV_CODE_RX_EV:
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001016 falcon_handle_rx_event(channel, &event);
1017 ++rx_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001018 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001019 case FSE_AZ_EV_CODE_TX_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +01001020 falcon_handle_tx_event(channel, &event);
1021 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001022 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1023 channel->eventq_magic = EFX_QWORD_FIELD(
1024 event, FSF_AZ_DRV_GEN_EV_MAGIC);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001025 EFX_LOG(channel->efx, "channel %d received generated "
1026 "event "EFX_QWORD_FMT"\n", channel->channel,
1027 EFX_QWORD_VAL(event));
1028 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001029 case FSE_AZ_EV_CODE_GLOBAL_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +01001030 falcon_handle_global_event(channel, &event);
1031 break;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001032 case FSE_AZ_EV_CODE_DRIVER_EV:
Ben Hutchings8ceee662008-04-27 12:55:59 +01001033 falcon_handle_driver_event(channel, &event);
1034 break;
1035 default:
1036 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1037 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1038 ev_code, EFX_QWORD_VAL(event));
1039 }
1040
1041 /* Increment read pointer */
Ben Hutchings3ffeabd2009-10-23 08:30:58 +00001042 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001043
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001044 } while (rx_packets < rx_quota);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001045
1046 channel->eventq_read_ptr = read_ptr;
Ben Hutchings42cbe2d2008-09-01 12:48:08 +01001047 return rx_packets;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001048}
1049
1050void falcon_set_int_moderation(struct efx_channel *channel)
1051{
1052 efx_dword_t timer_cmd;
1053 struct efx_nic *efx = channel->efx;
1054
1055 /* Set timer register */
1056 if (channel->irq_moderation) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001057 EFX_POPULATE_DWORD_2(timer_cmd,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001058 FRF_AB_TC_TIMER_MODE,
1059 FFE_BB_TIMER_MODE_INT_HLDOFF,
1060 FRF_AB_TC_TIMER_VAL,
Ben Hutchings0d86ebd2009-10-23 08:32:13 +00001061 channel->irq_moderation - 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001062 } else {
1063 EFX_POPULATE_DWORD_2(timer_cmd,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001064 FRF_AB_TC_TIMER_MODE,
1065 FFE_BB_TIMER_MODE_DIS,
1066 FRF_AB_TC_TIMER_VAL, 0);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001067 }
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001068 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001069 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1070 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001071
1072}
1073
1074/* Allocate buffer table entries for event queue */
1075int falcon_probe_eventq(struct efx_channel *channel)
1076{
1077 struct efx_nic *efx = channel->efx;
Ben Hutchings3ffeabd2009-10-23 08:30:58 +00001078 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1079 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1080 return falcon_alloc_special_buffer(efx, &channel->eventq,
1081 EFX_EVQ_SIZE * sizeof(efx_qword_t));
Ben Hutchings8ceee662008-04-27 12:55:59 +01001082}
1083
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +01001084void falcon_init_eventq(struct efx_channel *channel)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001085{
1086 efx_oword_t evq_ptr;
1087 struct efx_nic *efx = channel->efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001088
1089 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1090 channel->channel, channel->eventq.index,
1091 channel->eventq.index + channel->eventq.entries - 1);
1092
1093 /* Pin event queue buffer */
Ben Hutchingsbc3c90a2008-09-01 12:48:46 +01001094 falcon_init_special_buffer(efx, &channel->eventq);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001095
1096 /* Fill event queue with all ones (i.e. empty events) */
1097 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1098
1099 /* Push event queue to card */
1100 EFX_POPULATE_OWORD_3(evq_ptr,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001101 FRF_AZ_EVQ_EN, 1,
Ben Hutchings3ffeabd2009-10-23 08:30:58 +00001102 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001103 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001104 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1105 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001106
1107 falcon_set_int_moderation(channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001108}
1109
1110void falcon_fini_eventq(struct efx_channel *channel)
1111{
1112 efx_oword_t eventq_ptr;
1113 struct efx_nic *efx = channel->efx;
1114
1115 /* Remove event queue from card */
1116 EFX_ZERO_OWORD(eventq_ptr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001117 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1118 channel->channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001119
1120 /* Unpin event queue */
1121 falcon_fini_special_buffer(efx, &channel->eventq);
1122}
1123
1124/* Free buffers backing event queue */
1125void falcon_remove_eventq(struct efx_channel *channel)
1126{
1127 falcon_free_special_buffer(channel->efx, &channel->eventq);
1128}
1129
1130
1131/* Generates a test event on the event queue. A subsequent call to
1132 * process_eventq() should pick up the event and place the value of
1133 * "magic" into channel->eventq_magic;
1134 */
1135void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1136{
1137 efx_qword_t test_event;
1138
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001139 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1140 FSE_AZ_EV_CODE_DRV_GEN_EV,
1141 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001142 falcon_generate_event(channel, &test_event);
1143}
1144
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001145void falcon_sim_phy_event(struct efx_nic *efx)
1146{
1147 efx_qword_t phy_event;
1148
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001149 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1150 FSE_AZ_EV_CODE_GLOBAL_EV);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001151 if (EFX_IS10G(efx))
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001152 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001153 else
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001154 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001155
1156 falcon_generate_event(&efx->channel[0], &phy_event);
1157}
1158
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001159/**************************************************************************
1160 *
1161 * Flush handling
1162 *
1163 **************************************************************************/
1164
1165
1166static void falcon_poll_flush_events(struct efx_nic *efx)
1167{
1168 struct efx_channel *channel = &efx->channel[0];
1169 struct efx_tx_queue *tx_queue;
1170 struct efx_rx_queue *rx_queue;
Ben Hutchings4720bc62009-03-04 10:01:15 +00001171 unsigned int read_ptr = channel->eventq_read_ptr;
Ben Hutchings3ffeabd2009-10-23 08:30:58 +00001172 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001173
Ben Hutchings4720bc62009-03-04 10:01:15 +00001174 do {
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001175 efx_qword_t *event = falcon_event(channel, read_ptr);
1176 int ev_code, ev_sub_code, ev_queue;
1177 bool ev_failed;
Ben Hutchings4720bc62009-03-04 10:01:15 +00001178
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001179 if (!falcon_event_present(event))
1180 break;
1181
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001182 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1183 ev_sub_code = EFX_QWORD_FIELD(*event,
1184 FSF_AZ_DRIVER_EV_SUBCODE);
1185 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1186 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001187 ev_queue = EFX_QWORD_FIELD(*event,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001188 FSF_AZ_DRIVER_EV_SUBDATA);
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001189 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1190 tx_queue = efx->tx_queue + ev_queue;
Ben Hutchings127e6e12009-11-25 16:09:55 +00001191 tx_queue->flushed = FLUSH_DONE;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001192 }
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001193 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1194 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1195 ev_queue = EFX_QWORD_FIELD(
1196 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1197 ev_failed = EFX_QWORD_FIELD(
1198 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001199 if (ev_queue < efx->n_rx_queues) {
1200 rx_queue = efx->rx_queue + ev_queue;
Ben Hutchings127e6e12009-11-25 16:09:55 +00001201 rx_queue->flushed =
1202 ev_failed ? FLUSH_FAILED : FLUSH_DONE;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001203 }
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001204 }
1205
Ben Hutchings127e6e12009-11-25 16:09:55 +00001206 /* We're about to destroy the queue anyway, so
1207 * it's ok to throw away every non-flush event */
1208 EFX_SET_QWORD(*event);
1209
Ben Hutchings3ffeabd2009-10-23 08:30:58 +00001210 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
Ben Hutchings4720bc62009-03-04 10:01:15 +00001211 } while (read_ptr != end_ptr);
Ben Hutchings127e6e12009-11-25 16:09:55 +00001212
1213 channel->eventq_read_ptr = read_ptr;
1214}
1215
1216static void falcon_prepare_flush(struct efx_nic *efx)
1217{
1218 falcon_deconfigure_mac_wrapper(efx);
1219
1220 /* Wait for the tx and rx fifo's to get to the next packet boundary
1221 * (~1ms without back-pressure), then to drain the remainder of the
1222 * fifo's at data path speeds (negligible), with a healthy margin. */
1223 msleep(10);
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001224}
1225
1226/* Handle tx and rx flushes at the same time, since they run in
1227 * parallel in the hardware and there's no reason for us to
1228 * serialise them */
1229int falcon_flush_queues(struct efx_nic *efx)
1230{
1231 struct efx_rx_queue *rx_queue;
1232 struct efx_tx_queue *tx_queue;
Ben Hutchings127e6e12009-11-25 16:09:55 +00001233 int i, tx_pending, rx_pending;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001234
Ben Hutchings127e6e12009-11-25 16:09:55 +00001235 falcon_prepare_flush(efx);
1236
1237 /* Flush all tx queues in parallel */
1238 efx_for_each_tx_queue(tx_queue, efx)
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001239 falcon_flush_tx_queue(tx_queue);
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001240
Ben Hutchings127e6e12009-11-25 16:09:55 +00001241 /* The hardware supports four concurrent rx flushes, each of which may
1242 * need to be retried if there is an outstanding descriptor fetch */
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001243 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
Ben Hutchings127e6e12009-11-25 16:09:55 +00001244 rx_pending = tx_pending = 0;
1245 efx_for_each_rx_queue(rx_queue, efx) {
1246 if (rx_queue->flushed == FLUSH_PENDING)
1247 ++rx_pending;
1248 }
1249 efx_for_each_rx_queue(rx_queue, efx) {
1250 if (rx_pending == FALCON_RX_FLUSH_COUNT)
1251 break;
1252 if (rx_queue->flushed == FLUSH_FAILED ||
1253 rx_queue->flushed == FLUSH_NONE) {
1254 falcon_flush_rx_queue(rx_queue);
1255 ++rx_pending;
1256 }
1257 }
1258 efx_for_each_tx_queue(tx_queue, efx) {
1259 if (tx_queue->flushed != FLUSH_DONE)
1260 ++tx_pending;
1261 }
1262
1263 if (rx_pending == 0 && tx_pending == 0)
1264 return 0;
1265
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001266 msleep(FALCON_FLUSH_INTERVAL);
1267 falcon_poll_flush_events(efx);
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001268 }
1269
1270 /* Mark the queues as all flushed. We're going to return failure
Ben Hutchings127e6e12009-11-25 16:09:55 +00001271 * leading to a reset, or fake up success anyway */
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001272 efx_for_each_tx_queue(tx_queue, efx) {
Ben Hutchings127e6e12009-11-25 16:09:55 +00001273 if (tx_queue->flushed != FLUSH_DONE)
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001274 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1275 tx_queue->queue);
Ben Hutchings127e6e12009-11-25 16:09:55 +00001276 tx_queue->flushed = FLUSH_DONE;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001277 }
1278 efx_for_each_rx_queue(rx_queue, efx) {
Ben Hutchings127e6e12009-11-25 16:09:55 +00001279 if (rx_queue->flushed != FLUSH_DONE)
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001280 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1281 rx_queue->queue);
Ben Hutchings127e6e12009-11-25 16:09:55 +00001282 rx_queue->flushed = FLUSH_DONE;
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +01001283 }
1284
1285 if (EFX_WORKAROUND_7803(efx))
1286 return 0;
1287
1288 return -ETIMEDOUT;
1289}
Ben Hutchings8ceee662008-04-27 12:55:59 +01001290
1291/**************************************************************************
1292 *
1293 * Falcon hardware interrupts
1294 * The hardware interrupt handler does very little work; all the event
1295 * queue processing is carried out by per-channel tasklets.
1296 *
1297 **************************************************************************/
1298
1299/* Enable/disable/generate Falcon interrupts */
1300static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1301 int force)
1302{
1303 efx_oword_t int_en_reg_ker;
1304
1305 EFX_POPULATE_OWORD_2(int_en_reg_ker,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001306 FRF_AZ_KER_INT_KER, force,
1307 FRF_AZ_DRV_INT_EN_KER, enabled);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001308 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001309}
1310
1311void falcon_enable_interrupts(struct efx_nic *efx)
1312{
1313 efx_oword_t int_adr_reg_ker;
1314 struct efx_channel *channel;
1315
1316 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1317 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1318
1319 /* Program address */
1320 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001321 FRF_AZ_NORM_INT_VEC_DIS_KER,
1322 EFX_INT_MODE_USE_MSI(efx),
1323 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001324 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001325
1326 /* Enable interrupts */
1327 falcon_interrupts(efx, 1, 0);
1328
1329 /* Force processing of all the channels to get the EVQ RPTRs up to
1330 date */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001331 efx_for_each_channel(channel, efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001332 efx_schedule_channel(channel);
1333}
1334
1335void falcon_disable_interrupts(struct efx_nic *efx)
1336{
1337 /* Disable interrupts */
1338 falcon_interrupts(efx, 0, 0);
1339}
1340
1341/* Generate a Falcon test interrupt
1342 * Interrupt must already have been enabled, otherwise nasty things
1343 * may happen.
1344 */
1345void falcon_generate_interrupt(struct efx_nic *efx)
1346{
1347 falcon_interrupts(efx, 1, 1);
1348}
1349
1350/* Acknowledge a legacy interrupt from Falcon
1351 *
1352 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1353 *
1354 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1355 * BIU. Interrupt acknowledge is read sensitive so must write instead
1356 * (then read to ensure the BIU collector is flushed)
1357 *
1358 * NB most hardware supports MSI interrupts
1359 */
1360static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1361{
1362 efx_dword_t reg;
1363
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001364 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001365 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1366 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001367}
1368
1369/* Process a fatal interrupt
1370 * Disable bus mastering ASAP and schedule a reset
1371 */
1372static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1373{
1374 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001375 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001376 efx_oword_t fatal_intr;
1377 int error, mem_perr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001378
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001379 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001380 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001381
1382 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1383 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1384 EFX_OWORD_VAL(fatal_intr),
1385 error ? "disabling bus mastering" : "no recognised error");
1386 if (error == 0)
1387 goto out;
1388
1389 /* If this is a memory parity error dump which blocks are offending */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001390 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001391 if (mem_perr) {
1392 efx_oword_t reg;
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001393 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001394 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1395 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1396 }
1397
Ben Hutchings0a62f1a2008-09-01 12:50:14 +01001398 /* Disable both devices */
Ben Hutchingsef1bba22008-12-23 03:09:53 +00001399 pci_clear_master(efx->pci_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001400 if (FALCON_IS_DUAL_FUNC(efx))
Ben Hutchingsef1bba22008-12-23 03:09:53 +00001401 pci_clear_master(nic_data->pci_dev2);
Ben Hutchings0a62f1a2008-09-01 12:50:14 +01001402 falcon_disable_interrupts(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001403
Ben Hutchings2c3c3d02009-03-04 10:01:57 +00001404 /* Count errors and reset or disable the NIC accordingly */
Ben Hutchings0484e0d2009-10-23 08:32:04 +00001405 if (efx->int_error_count == 0 ||
1406 time_after(jiffies, efx->int_error_expire)) {
1407 efx->int_error_count = 0;
1408 efx->int_error_expire =
Ben Hutchings2c3c3d02009-03-04 10:01:57 +00001409 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1410 }
Ben Hutchings0484e0d2009-10-23 08:32:04 +00001411 if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001412 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1413 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1414 } else {
1415 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1416 "NIC will be disabled\n");
1417 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1418 }
1419out:
1420 return IRQ_HANDLED;
1421}
1422
1423/* Handle a legacy interrupt from Falcon
1424 * Acknowledges the interrupt and schedule event queue processing.
1425 */
1426static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1427{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001428 struct efx_nic *efx = dev_id;
1429 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchingsa9de9a72009-03-20 13:26:41 +00001430 irqreturn_t result = IRQ_NONE;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001431 struct efx_channel *channel;
1432 efx_dword_t reg;
1433 u32 queues;
1434 int syserr;
1435
1436 /* Read the ISR which also ACKs the interrupts */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001437 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001438 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1439
1440 /* Check to see if we have a serious error condition */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001441 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001442 if (unlikely(syserr))
1443 return falcon_fatal_interrupt(efx);
1444
Ben Hutchings8ceee662008-04-27 12:55:59 +01001445 /* Schedule processing of any interrupting queues */
Ben Hutchingsa9de9a72009-03-20 13:26:41 +00001446 efx_for_each_channel(channel, efx) {
1447 if ((queues & 1) ||
1448 falcon_event_present(
1449 falcon_event(channel, channel->eventq_read_ptr))) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001450 efx_schedule_channel(channel);
Ben Hutchingsa9de9a72009-03-20 13:26:41 +00001451 result = IRQ_HANDLED;
1452 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001453 queues >>= 1;
1454 }
1455
Ben Hutchingsa9de9a72009-03-20 13:26:41 +00001456 if (result == IRQ_HANDLED) {
1457 efx->last_irq_cpu = raw_smp_processor_id();
1458 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1459 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1460 }
1461
1462 return result;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001463}
1464
1465
1466static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1467{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001468 struct efx_nic *efx = dev_id;
1469 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001470 struct efx_channel *channel;
1471 int syserr;
1472 int queues;
1473
1474 /* Check to see if this is our interrupt. If it isn't, we
1475 * exit without having touched the hardware.
1476 */
1477 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1478 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1479 raw_smp_processor_id());
1480 return IRQ_NONE;
1481 }
1482 efx->last_irq_cpu = raw_smp_processor_id();
1483 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1484 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1485
1486 /* Check to see if we have a serious error condition */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001487 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001488 if (unlikely(syserr))
1489 return falcon_fatal_interrupt(efx);
1490
1491 /* Determine interrupting queues, clear interrupt status
1492 * register and acknowledge the device interrupt.
1493 */
1494 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1495 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1496 EFX_ZERO_OWORD(*int_ker);
1497 wmb(); /* Ensure the vector is cleared before interrupt ack */
1498 falcon_irq_ack_a1(efx);
1499
1500 /* Schedule processing of any interrupting queues */
1501 channel = &efx->channel[0];
1502 while (queues) {
1503 if (queues & 0x01)
1504 efx_schedule_channel(channel);
1505 channel++;
1506 queues >>= 1;
1507 }
1508
1509 return IRQ_HANDLED;
1510}
1511
1512/* Handle an MSI interrupt from Falcon
1513 *
1514 * Handle an MSI hardware interrupt. This routine schedules event
1515 * queue processing. No interrupt acknowledgement cycle is necessary.
1516 * Also, we never need to check that the interrupt is for us, since
1517 * MSI interrupts cannot be shared.
1518 */
1519static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1520{
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001521 struct efx_channel *channel = dev_id;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001522 struct efx_nic *efx = channel->efx;
Ben Hutchingsd3208b52008-05-16 21:20:00 +01001523 efx_oword_t *int_ker = efx->irq_status.addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001524 int syserr;
1525
1526 efx->last_irq_cpu = raw_smp_processor_id();
1527 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1528 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1529
1530 /* Check to see if we have a serious error condition */
1531 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1532 if (unlikely(syserr))
1533 return falcon_fatal_interrupt(efx);
1534
1535 /* Schedule processing of the channel */
1536 efx_schedule_channel(channel);
1537
1538 return IRQ_HANDLED;
1539}
1540
1541
1542/* Setup RSS indirection table.
1543 * This maps from the hash value of the packet to RXQ
1544 */
1545static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1546{
1547 int i = 0;
1548 unsigned long offset;
1549 efx_dword_t dword;
1550
Ben Hutchings55668612008-05-16 21:16:10 +01001551 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001552 return;
1553
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001554 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1555 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001556 offset += 0x10) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001557 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
Ben Hutchings8831da72008-09-01 12:47:48 +01001558 i % efx->n_rx_queues);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001559 efx_writed(efx, &dword, offset);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001560 i++;
1561 }
1562}
1563
1564/* Hook interrupt handler(s)
1565 * Try MSI and then legacy interrupts.
1566 */
1567int falcon_init_interrupt(struct efx_nic *efx)
1568{
1569 struct efx_channel *channel;
1570 int rc;
1571
1572 if (!EFX_INT_MODE_USE_MSI(efx)) {
1573 irq_handler_t handler;
Ben Hutchings55668612008-05-16 21:16:10 +01001574 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001575 handler = falcon_legacy_interrupt_b0;
1576 else
1577 handler = falcon_legacy_interrupt_a1;
1578
1579 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1580 efx->name, efx);
1581 if (rc) {
1582 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1583 efx->pci_dev->irq);
1584 goto fail1;
1585 }
1586 return 0;
1587 }
1588
1589 /* Hook MSI or MSI-X interrupt */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001590 efx_for_each_channel(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001591 rc = request_irq(channel->irq, falcon_msi_interrupt,
1592 IRQF_PROBE_SHARED, /* Not shared */
Ben Hutchings56536e92008-12-12 21:37:02 -08001593 channel->name, channel);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001594 if (rc) {
1595 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1596 goto fail2;
1597 }
1598 }
1599
1600 return 0;
1601
1602 fail2:
Ben Hutchings64ee3122008-09-01 12:47:38 +01001603 efx_for_each_channel(channel, efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001604 free_irq(channel->irq, channel);
1605 fail1:
1606 return rc;
1607}
1608
1609void falcon_fini_interrupt(struct efx_nic *efx)
1610{
1611 struct efx_channel *channel;
1612 efx_oword_t reg;
1613
1614 /* Disable MSI/MSI-X interrupts */
Ben Hutchings64ee3122008-09-01 12:47:38 +01001615 efx_for_each_channel(channel, efx) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001616 if (channel->irq)
1617 free_irq(channel->irq, channel);
Ben Hutchingsb3475642008-05-16 21:15:49 +01001618 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001619
1620 /* ACK legacy interrupt */
Ben Hutchings55668612008-05-16 21:16:10 +01001621 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001622 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001623 else
1624 falcon_irq_ack_a1(efx);
1625
1626 /* Disable legacy interrupt */
1627 if (efx->legacy_irq)
1628 free_irq(efx->legacy_irq, efx);
1629}
1630
1631/**************************************************************************
1632 *
1633 * EEPROM/flash
1634 *
1635 **************************************************************************
1636 */
1637
Ben Hutchings23d30f02008-12-12 21:56:11 -08001638#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001639
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001640static int falcon_spi_poll(struct efx_nic *efx)
1641{
1642 efx_oword_t reg;
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001643 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001644 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001645}
1646
Ben Hutchings8ceee662008-04-27 12:55:59 +01001647/* Wait for SPI command completion */
1648static int falcon_spi_wait(struct efx_nic *efx)
1649{
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001650 /* Most commands will finish quickly, so we start polling at
1651 * very short intervals. Sometimes the command may have to
1652 * wait for VPD or expansion ROM access outside of our
1653 * control, so we allow up to 100 ms. */
1654 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1655 int i;
1656
1657 for (i = 0; i < 10; i++) {
1658 if (!falcon_spi_poll(efx))
1659 return 0;
1660 udelay(10);
1661 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001662
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001663 for (;;) {
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001664 if (!falcon_spi_poll(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +01001665 return 0;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001666 if (time_after_eq(jiffies, timeout)) {
1667 EFX_ERR(efx, "timed out waiting for SPI\n");
1668 return -ETIMEDOUT;
1669 }
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001670 schedule_timeout_uninterruptible(1);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001671 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001672}
1673
Ben Hutchingsf4150722008-11-04 20:34:28 +00001674int falcon_spi_cmd(const struct efx_spi_device *spi,
1675 unsigned int command, int address,
Ben Hutchings23d30f02008-12-12 21:56:11 -08001676 const void *in, void *out, size_t len)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001677{
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001678 struct efx_nic *efx = spi->efx;
1679 bool addressed = (address >= 0);
1680 bool reading = (out != NULL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001681 efx_oword_t reg;
1682 int rc;
1683
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001684 /* Input validation */
1685 if (len > FALCON_SPI_MAX_LEN)
1686 return -EINVAL;
Ben Hutchingsf4150722008-11-04 20:34:28 +00001687 BUG_ON(!mutex_is_locked(&efx->spi_lock));
Ben Hutchings8ceee662008-04-27 12:55:59 +01001688
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001689 /* Check that previous command is not still running */
1690 rc = falcon_spi_poll(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001691 if (rc)
1692 return rc;
1693
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001694 /* Program address register, if we have an address */
1695 if (addressed) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001696 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001697 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001698 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001699
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001700 /* Program data register, if we have data */
1701 if (in != NULL) {
1702 memcpy(&reg, in, len);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001703 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001704 }
1705
1706 /* Issue read/write command */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001707 EFX_POPULATE_OWORD_7(reg,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001708 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1709 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1710 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1711 FRF_AB_EE_SPI_HCMD_READ, reading,
1712 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1713 FRF_AB_EE_SPI_HCMD_ADBCNT,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001714 (addressed ? spi->addr_len : 0),
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001715 FRF_AB_EE_SPI_HCMD_ENC, command);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001716 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001717
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001718 /* Wait for read/write to complete */
Ben Hutchings8ceee662008-04-27 12:55:59 +01001719 rc = falcon_spi_wait(efx);
1720 if (rc)
1721 return rc;
1722
1723 /* Read data */
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001724 if (out != NULL) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001725 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001726 memcpy(out, &reg, len);
1727 }
1728
Ben Hutchings8ceee662008-04-27 12:55:59 +01001729 return 0;
1730}
1731
Ben Hutchings23d30f02008-12-12 21:56:11 -08001732static size_t
1733falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001734{
1735 return min(FALCON_SPI_MAX_LEN,
1736 (spi->block_size - (start & (spi->block_size - 1))));
1737}
1738
1739static inline u8
1740efx_spi_munge_command(const struct efx_spi_device *spi,
1741 const u8 command, const unsigned int address)
1742{
1743 return command | (((address >> 8) & spi->munge_address) << 3);
1744}
1745
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001746/* Wait up to 10 ms for buffered write completion */
1747int falcon_spi_wait_write(const struct efx_spi_device *spi)
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001748{
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001749 struct efx_nic *efx = spi->efx;
1750 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001751 u8 status;
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001752 int rc;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001753
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001754 for (;;) {
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001755 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1756 &status, sizeof(status));
1757 if (rc)
1758 return rc;
1759 if (!(status & SPI_STATUS_NRDY))
1760 return 0;
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001761 if (time_after_eq(jiffies, timeout)) {
1762 EFX_ERR(efx, "SPI write timeout on device %d"
1763 " last status=0x%02x\n",
1764 spi->device_id, status);
1765 return -ETIMEDOUT;
1766 }
1767 schedule_timeout_uninterruptible(1);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001768 }
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001769}
1770
1771int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1772 size_t len, size_t *retlen, u8 *buffer)
1773{
Ben Hutchings23d30f02008-12-12 21:56:11 -08001774 size_t block_len, pos = 0;
1775 unsigned int command;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001776 int rc = 0;
1777
1778 while (pos < len) {
Ben Hutchings23d30f02008-12-12 21:56:11 -08001779 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001780
1781 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1782 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1783 buffer + pos, block_len);
1784 if (rc)
1785 break;
1786 pos += block_len;
1787
1788 /* Avoid locking up the system */
1789 cond_resched();
1790 if (signal_pending(current)) {
1791 rc = -EINTR;
1792 break;
1793 }
1794 }
1795
1796 if (retlen)
1797 *retlen = pos;
1798 return rc;
1799}
1800
1801int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1802 size_t len, size_t *retlen, const u8 *buffer)
1803{
1804 u8 verify_buffer[FALCON_SPI_MAX_LEN];
Ben Hutchings23d30f02008-12-12 21:56:11 -08001805 size_t block_len, pos = 0;
1806 unsigned int command;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001807 int rc = 0;
1808
1809 while (pos < len) {
1810 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1811 if (rc)
1812 break;
1813
Ben Hutchings23d30f02008-12-12 21:56:11 -08001814 block_len = min(len - pos,
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001815 falcon_spi_write_limit(spi, start + pos));
1816 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1817 rc = falcon_spi_cmd(spi, command, start + pos,
1818 buffer + pos, NULL, block_len);
1819 if (rc)
1820 break;
1821
Ben Hutchingsbe4ea892008-12-12 21:33:50 -08001822 rc = falcon_spi_wait_write(spi);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01001823 if (rc)
1824 break;
1825
1826 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1827 rc = falcon_spi_cmd(spi, command, start + pos,
1828 NULL, verify_buffer, block_len);
1829 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1830 rc = -EIO;
1831 break;
1832 }
1833
1834 pos += block_len;
1835
1836 /* Avoid locking up the system */
1837 cond_resched();
1838 if (signal_pending(current)) {
1839 rc = -EINTR;
1840 break;
1841 }
1842 }
1843
1844 if (retlen)
1845 *retlen = pos;
1846 return rc;
1847}
1848
Ben Hutchings8ceee662008-04-27 12:55:59 +01001849/**************************************************************************
1850 *
1851 * MAC wrapper
1852 *
1853 **************************************************************************
1854 */
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001855
1856static int falcon_reset_macs(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001857{
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001858 efx_oword_t reg;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001859 int count;
1860
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001861 if (falcon_rev(efx) < FALCON_REV_B0) {
1862 /* It's not safe to use GLB_CTL_REG to reset the
1863 * macs, so instead use the internal MAC resets
1864 */
1865 if (!EFX_IS10G(efx)) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001866 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001867 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001868 udelay(1000);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001869
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001870 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001871 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001872 udelay(1000);
1873 return 0;
1874 } else {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001875 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001876 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001877
1878 for (count = 0; count < 10000; count++) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001879 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001880 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1881 0)
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001882 return 0;
1883 udelay(10);
1884 }
1885
1886 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1887 return -ETIMEDOUT;
1888 }
1889 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001890
1891 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1892 * the drain sequence with the statistics fetch */
Ben Hutchings1974cc22009-01-29 18:00:07 +00001893 efx_stats_disable(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001894
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001895 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001896 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001897 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001898
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001899 efx_reado(efx, &reg, FR_AB_GLB_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001900 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1901 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1902 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001903 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001904
1905 count = 0;
1906 while (1) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001907 efx_reado(efx, &reg, FR_AB_GLB_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001908 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1909 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1910 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01001911 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1912 count);
1913 break;
1914 }
1915 if (count > 20) {
1916 EFX_ERR(efx, "MAC reset failed\n");
1917 break;
1918 }
1919 count++;
1920 udelay(10);
1921 }
1922
Ben Hutchings1974cc22009-01-29 18:00:07 +00001923 efx_stats_enable(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001924
1925 /* If we've reset the EM block and the link is up, then
1926 * we'll have to kick the XAUI link so the PHY can recover */
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00001927 if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
Ben Hutchings8ceee662008-04-27 12:55:59 +01001928 falcon_reset_xaui(efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001929
1930 return 0;
1931}
1932
1933void falcon_drain_tx_fifo(struct efx_nic *efx)
1934{
1935 efx_oword_t reg;
1936
1937 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1938 (efx->loopback_mode != LOOPBACK_NONE))
1939 return;
1940
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001941 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001942 /* There is no point in draining more than once */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001943 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001944 return;
1945
1946 falcon_reset_macs(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001947}
1948
1949void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1950{
Ben Hutchings177dfcd2008-12-12 21:50:08 -08001951 efx_oword_t reg;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001952
Ben Hutchings55668612008-05-16 21:16:10 +01001953 if (falcon_rev(efx) < FALCON_REV_B0)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001954 return;
1955
1956 /* Isolate the MAC -> RX */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001957 efx_reado(efx, &reg, FR_AZ_RX_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001958 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001959 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001960
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00001961 if (!efx->link_state.up)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001962 falcon_drain_tx_fifo(efx);
1963}
1964
1965void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1966{
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00001967 struct efx_link_state *link_state = &efx->link_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001968 efx_oword_t reg;
1969 int link_speed;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +01001970 bool tx_fc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01001971
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00001972 switch (link_state->speed) {
Ben Hutchingsf31a45d2008-12-12 21:43:33 -08001973 case 10000: link_speed = 3; break;
1974 case 1000: link_speed = 2; break;
1975 case 100: link_speed = 1; break;
1976 default: link_speed = 0; break;
1977 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01001978 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1979 * as advertised. Disable to ensure packets are not
1980 * indefinitely held and TX queue can be flushed at any point
1981 * while the link is down. */
1982 EFX_POPULATE_OWORD_5(reg,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001983 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1984 FRF_AB_MAC_BCAD_ACPT, 1,
1985 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1986 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1987 FRF_AB_MAC_SPEED, link_speed);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001988 /* On B0, MAC backpressure can be disabled and packets get
1989 * discarded. */
Ben Hutchings55668612008-05-16 21:16:10 +01001990 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00001991 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00001992 !link_state->up);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001993 }
1994
Ben Hutchings12d00ca2009-10-23 08:30:46 +00001995 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01001996
1997 /* Restore the multicast hash registers. */
1998 falcon_set_multicast_hash(efx);
1999
2000 /* Transmission of pause frames when RX crosses the threshold is
2001 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2002 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00002003 tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002004 efx_reado(efx, &reg, FR_AZ_RX_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002005 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002006
2007 /* Unisolate the MAC -> RX */
Ben Hutchings55668612008-05-16 21:16:10 +01002008 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002009 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002010 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002011}
2012
2013int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2014{
2015 efx_oword_t reg;
2016 u32 *dma_done;
2017 int i;
2018
2019 if (disable_dma_stats)
2020 return 0;
2021
2022 /* Statistics fetch will fail if the MAC is in TX drain */
Ben Hutchings55668612008-05-16 21:16:10 +01002023 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002024 efx_oword_t temp;
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002025 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002026 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
Ben Hutchings8ceee662008-04-27 12:55:59 +01002027 return 0;
2028 }
2029
2030 dma_done = (efx->stats_buffer.addr + done_offset);
2031 *dma_done = FALCON_STATS_NOT_DONE;
2032 wmb(); /* ensure done flag is clear */
2033
2034 /* Initiate DMA transfer of stats */
2035 EFX_POPULATE_OWORD_2(reg,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002036 FRF_AB_MAC_STAT_DMA_CMD, 1,
2037 FRF_AB_MAC_STAT_DMA_ADR,
Ben Hutchings8ceee662008-04-27 12:55:59 +01002038 efx->stats_buffer.dma_addr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002039 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002040
2041 /* Wait for transfer to complete */
2042 for (i = 0; i < 400; i++) {
Ben Hutchings1d0680f2008-09-01 12:50:08 +01002043 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2044 rmb(); /* Ensure the stats are valid. */
Ben Hutchings8ceee662008-04-27 12:55:59 +01002045 return 0;
Ben Hutchings1d0680f2008-09-01 12:50:08 +01002046 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002047 udelay(10);
2048 }
2049
2050 EFX_ERR(efx, "timed out waiting for statistics\n");
2051 return -ETIMEDOUT;
2052}
2053
2054/**************************************************************************
2055 *
2056 * PHY access via GMII
2057 *
2058 **************************************************************************
2059 */
2060
Ben Hutchings8ceee662008-04-27 12:55:59 +01002061/* Wait for GMII access to complete */
2062static int falcon_gmii_wait(struct efx_nic *efx)
2063{
Ben Hutchings80cb9a02009-11-25 16:08:41 +00002064 efx_oword_t md_stat;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002065 int count;
2066
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002067 /* wait upto 50ms - taken max from datasheet */
2068 for (count = 0; count < 5000; count++) {
Ben Hutchings80cb9a02009-11-25 16:08:41 +00002069 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
2070 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2071 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2072 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002073 EFX_ERR(efx, "error from GMII access "
Ben Hutchings80cb9a02009-11-25 16:08:41 +00002074 EFX_OWORD_FMT"\n",
2075 EFX_OWORD_VAL(md_stat));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002076 return -EIO;
2077 }
2078 return 0;
2079 }
2080 udelay(10);
2081 }
2082 EFX_ERR(efx, "timed out waiting for GMII\n");
2083 return -ETIMEDOUT;
2084}
2085
Ben Hutchings68e7f452009-04-29 08:05:08 +00002086/* Write an MDIO register of a PHY connected to Falcon. */
2087static int falcon_mdio_write(struct net_device *net_dev,
2088 int prtad, int devad, u16 addr, u16 value)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002089{
Ben Hutchings767e4682008-09-01 12:43:14 +01002090 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002091 efx_oword_t reg;
Ben Hutchings68e7f452009-04-29 08:05:08 +00002092 int rc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002093
Ben Hutchings68e7f452009-04-29 08:05:08 +00002094 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2095 prtad, devad, addr, value);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002096
2097 spin_lock_bh(&efx->phy_lock);
2098
Ben Hutchings68e7f452009-04-29 08:05:08 +00002099 /* Check MDIO not currently being accessed */
2100 rc = falcon_gmii_wait(efx);
2101 if (rc)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002102 goto out;
2103
2104 /* Write the address/ID register */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002105 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002106 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002107
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002108 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2109 FRF_AB_MD_DEV_ADR, devad);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002110 efx_writeo(efx, &reg, FR_AB_MD_ID);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002111
2112 /* Write data */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002113 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002114 efx_writeo(efx, &reg, FR_AB_MD_TXD);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002115
2116 EFX_POPULATE_OWORD_2(reg,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002117 FRF_AB_MD_WRC, 1,
2118 FRF_AB_MD_GC, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002119 efx_writeo(efx, &reg, FR_AB_MD_CS);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002120
2121 /* Wait for data to be written */
Ben Hutchings68e7f452009-04-29 08:05:08 +00002122 rc = falcon_gmii_wait(efx);
2123 if (rc) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002124 /* Abort the write operation */
2125 EFX_POPULATE_OWORD_2(reg,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002126 FRF_AB_MD_WRC, 0,
2127 FRF_AB_MD_GC, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002128 efx_writeo(efx, &reg, FR_AB_MD_CS);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002129 udelay(10);
2130 }
2131
2132 out:
2133 spin_unlock_bh(&efx->phy_lock);
Ben Hutchings68e7f452009-04-29 08:05:08 +00002134 return rc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002135}
2136
Ben Hutchings68e7f452009-04-29 08:05:08 +00002137/* Read an MDIO register of a PHY connected to Falcon. */
2138static int falcon_mdio_read(struct net_device *net_dev,
2139 int prtad, int devad, u16 addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002140{
Ben Hutchings767e4682008-09-01 12:43:14 +01002141 struct efx_nic *efx = netdev_priv(net_dev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002142 efx_oword_t reg;
Ben Hutchings68e7f452009-04-29 08:05:08 +00002143 int rc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002144
2145 spin_lock_bh(&efx->phy_lock);
2146
Ben Hutchings68e7f452009-04-29 08:05:08 +00002147 /* Check MDIO not currently being accessed */
2148 rc = falcon_gmii_wait(efx);
2149 if (rc)
Ben Hutchings8ceee662008-04-27 12:55:59 +01002150 goto out;
2151
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002152 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002153 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002154
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002155 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2156 FRF_AB_MD_DEV_ADR, devad);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002157 efx_writeo(efx, &reg, FR_AB_MD_ID);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002158
2159 /* Request data to be read */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002160 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002161 efx_writeo(efx, &reg, FR_AB_MD_CS);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002162
2163 /* Wait for data to become available */
Ben Hutchings68e7f452009-04-29 08:05:08 +00002164 rc = falcon_gmii_wait(efx);
2165 if (rc == 0) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002166 efx_reado(efx, &reg, FR_AB_MD_RXD);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002167 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
Ben Hutchings68e7f452009-04-29 08:05:08 +00002168 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2169 prtad, devad, addr, rc);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002170 } else {
2171 /* Abort the read operation */
2172 EFX_POPULATE_OWORD_2(reg,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002173 FRF_AB_MD_RIC, 0,
2174 FRF_AB_MD_GC, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002175 efx_writeo(efx, &reg, FR_AB_MD_CS);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002176
Ben Hutchings68e7f452009-04-29 08:05:08 +00002177 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2178 prtad, devad, addr, rc);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002179 }
2180
2181 out:
2182 spin_unlock_bh(&efx->phy_lock);
Ben Hutchings68e7f452009-04-29 08:05:08 +00002183 return rc;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002184}
2185
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002186int falcon_switch_mac(struct efx_nic *efx)
2187{
2188 struct efx_mac_operations *old_mac_op = efx->mac_op;
2189 efx_oword_t nic_stat;
2190 unsigned strap_val;
Ben Hutchings1974cc22009-01-29 18:00:07 +00002191 int rc = 0;
2192
2193 /* Don't try to fetch MAC stats while we're switching MACs */
2194 efx_stats_disable(efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002195
2196 /* Internal loopbacks override the phy speed setting */
2197 if (efx->loopback_mode == LOOPBACK_GMAC) {
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00002198 efx->link_state.speed = 1000;
2199 efx->link_state.fd = true;
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002200 } else if (LOOPBACK_INTERNAL(efx)) {
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00002201 efx->link_state.speed = 10000;
2202 efx->link_state.fd = true;
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002203 }
2204
Steve Hodgson0cc1283872009-01-29 17:49:59 +00002205 WARN_ON(!mutex_is_locked(&efx->mac_lock));
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002206 efx->mac_op = (EFX_IS10G(efx) ?
2207 &falcon_xmac_operations : &falcon_gmac_operations);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002208
Steve Hodgson0cc1283872009-01-29 17:49:59 +00002209 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2210 * changed, because this function is run post online reset */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002211 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002212 strap_val = EFX_IS10G(efx) ? 5 : 3;
2213 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002214 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2215 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002216 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002217 } else {
2218 /* Falcon A1 does not support 1G/10G speed switching
2219 * and must not be used with a PHY that does. */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002220 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2221 strap_val);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002222 }
2223
Steve Hodgson0cc1283872009-01-29 17:49:59 +00002224 if (old_mac_op == efx->mac_op)
Ben Hutchings1974cc22009-01-29 18:00:07 +00002225 goto out;
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002226
2227 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
Steve Hodgson0cc1283872009-01-29 17:49:59 +00002228 /* Not all macs support a mac-level link state */
2229 efx->mac_up = true;
2230
Ben Hutchings1974cc22009-01-29 18:00:07 +00002231 rc = falcon_reset_macs(efx);
2232out:
2233 efx_stats_enable(efx);
2234 return rc;
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002235}
2236
Ben Hutchings8ceee662008-04-27 12:55:59 +01002237/* This call is responsible for hooking in the MAC and PHY operations */
2238int falcon_probe_port(struct efx_nic *efx)
2239{
2240 int rc;
2241
Ben Hutchings96c457262009-10-23 08:32:42 +00002242 switch (efx->phy_type) {
2243 case PHY_TYPE_SFX7101:
2244 efx->phy_op = &falcon_sfx7101_phy_ops;
2245 break;
2246 case PHY_TYPE_SFT9001A:
2247 case PHY_TYPE_SFT9001B:
2248 efx->phy_op = &falcon_sft9001_phy_ops;
2249 break;
2250 case PHY_TYPE_QT2022C2:
2251 case PHY_TYPE_QT2025C:
Ben Hutchingsb37b62f2009-10-23 08:33:42 +00002252 efx->phy_op = &falcon_qt202x_phy_ops;
Ben Hutchings96c457262009-10-23 08:32:42 +00002253 break;
2254 default:
2255 EFX_ERR(efx, "Unknown PHY type %d\n",
2256 efx->phy_type);
2257 return -ENODEV;
2258 }
2259
2260 if (efx->phy_op->macs & EFX_XMAC)
2261 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2262 (1 << LOOPBACK_XGXS) |
2263 (1 << LOOPBACK_XAUI));
2264 if (efx->phy_op->macs & EFX_GMAC)
2265 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2266 efx->loopback_modes |= efx->phy_op->loopbacks;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002267
Ben Hutchings68e7f452009-04-29 08:05:08 +00002268 /* Set up MDIO structure for PHY */
2269 efx->mdio.mmds = efx->phy_op->mmds;
2270 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2271 efx->mdio.mdio_read = falcon_mdio_read;
2272 efx->mdio.mdio_write = falcon_mdio_write;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002273
2274 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
Ben Hutchings55668612008-05-16 21:16:10 +01002275 if (falcon_rev(efx) >= FALCON_REV_B0)
Ben Hutchings04cc8ca2008-12-12 21:50:46 -08002276 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002277 else
Ben Hutchings04cc8ca2008-12-12 21:50:46 -08002278 efx->wanted_fc = EFX_FC_RX;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002279
2280 /* Allocate buffer for stats */
2281 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2282 FALCON_MAC_STATS_SIZE);
2283 if (rc)
2284 return rc;
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +05302285 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2286 (u64)efx->stats_buffer.dma_addr,
Ben Hutchings8ceee662008-04-27 12:55:59 +01002287 efx->stats_buffer.addr,
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +05302288 (u64)virt_to_phys(efx->stats_buffer.addr));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002289
2290 return 0;
2291}
2292
2293void falcon_remove_port(struct efx_nic *efx)
2294{
2295 falcon_free_buffer(efx, &efx->stats_buffer);
2296}
2297
2298/**************************************************************************
2299 *
2300 * Multicast filtering
2301 *
2302 **************************************************************************
2303 */
2304
2305void falcon_set_multicast_hash(struct efx_nic *efx)
2306{
2307 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2308
2309 /* Broadcast packets go through the multicast hash filter.
2310 * ether_crc_le() of the broadcast address is 0xbe2612ff
2311 * so we always add bit 0xff to the mask.
2312 */
2313 set_bit_le(0xff, mc_hash->byte);
2314
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002315 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2316 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002317}
2318
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002319
2320/**************************************************************************
2321 *
2322 * Falcon test code
2323 *
2324 **************************************************************************/
2325
2326int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2327{
2328 struct falcon_nvconfig *nvconfig;
2329 struct efx_spi_device *spi;
2330 void *region;
2331 int rc, magic_num, struct_ver;
2332 __le16 *word, *limit;
2333 u32 csum;
2334
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002335 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2336 if (!spi)
2337 return -EINVAL;
2338
Ben Hutchings0a95f562008-11-04 20:33:11 +00002339 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002340 if (!region)
2341 return -ENOMEM;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002342 nvconfig = region + FALCON_NVCONFIG_OFFSET;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002343
Ben Hutchingsf4150722008-11-04 20:34:28 +00002344 mutex_lock(&efx->spi_lock);
Ben Hutchings0a95f562008-11-04 20:33:11 +00002345 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
Ben Hutchingsf4150722008-11-04 20:34:28 +00002346 mutex_unlock(&efx->spi_lock);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002347 if (rc) {
2348 EFX_ERR(efx, "Failed to read %s\n",
2349 efx->spi_flash ? "flash" : "EEPROM");
2350 rc = -EIO;
2351 goto out;
2352 }
2353
2354 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2355 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2356
2357 rc = -EINVAL;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002358 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002359 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2360 goto out;
2361 }
2362 if (struct_ver < 2) {
2363 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2364 goto out;
2365 } else if (struct_ver < 4) {
2366 word = &nvconfig->board_magic_num;
2367 limit = (__le16 *) (nvconfig + 1);
2368 } else {
2369 word = region;
Ben Hutchings0a95f562008-11-04 20:33:11 +00002370 limit = region + FALCON_NVCONFIG_END;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002371 }
2372 for (csum = 0; word < limit; ++word)
2373 csum += le16_to_cpu(*word);
2374
2375 if (~csum & 0xffff) {
2376 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2377 goto out;
2378 }
2379
2380 rc = 0;
2381 if (nvconfig_out)
2382 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2383
2384 out:
2385 kfree(region);
2386 return rc;
2387}
2388
2389/* Registers tested in the falcon register test */
2390static struct {
2391 unsigned address;
2392 efx_oword_t mask;
2393} efx_test_registers[] = {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002394 { FR_AZ_ADR_REGION,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002395 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002396 { FR_AZ_RX_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002397 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002398 { FR_AZ_TX_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002399 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002400 { FR_AZ_TX_RESERVED,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002401 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002402 { FR_AB_MAC_CTRL,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002403 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002404 { FR_AZ_SRM_TX_DC_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002405 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002406 { FR_AZ_RX_DC_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002407 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002408 { FR_AZ_RX_DC_PF_WM,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002409 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002410 { FR_BZ_DP_CTRL,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002411 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002412 { FR_AB_GM_CFG2,
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002413 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002414 { FR_AB_GMF_CFG0,
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002415 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002416 { FR_AB_XM_GLB_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002417 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002418 { FR_AB_XM_TX_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002419 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002420 { FR_AB_XM_RX_CFG,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002421 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002422 { FR_AB_XM_RX_PARAM,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002423 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002424 { FR_AB_XM_FC,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002425 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002426 { FR_AB_XM_ADR_LO,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002427 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002428 { FR_AB_XX_SD_CTL,
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002429 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2430};
2431
2432static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2433 const efx_oword_t *mask)
2434{
2435 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2436 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2437}
2438
2439int falcon_test_registers(struct efx_nic *efx)
2440{
2441 unsigned address = 0, i, j;
2442 efx_oword_t mask, imask, original, reg, buf;
2443
2444 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2445 WARN_ON(!LOOPBACK_INTERNAL(efx));
2446
2447 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2448 address = efx_test_registers[i].address;
2449 mask = imask = efx_test_registers[i].mask;
2450 EFX_INVERT_OWORD(imask);
2451
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002452 efx_reado(efx, &original, address);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002453
2454 /* bit sweep on and off */
2455 for (j = 0; j < 128; j++) {
2456 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2457 continue;
2458
2459 /* Test this testable bit can be set in isolation */
2460 EFX_AND_OWORD(reg, original, mask);
2461 EFX_SET_OWORD32(reg, j, j, 1);
2462
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002463 efx_writeo(efx, &reg, address);
2464 efx_reado(efx, &buf, address);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002465
2466 if (efx_masked_compare_oword(&reg, &buf, &mask))
2467 goto fail;
2468
2469 /* Test this testable bit can be cleared in isolation */
2470 EFX_OR_OWORD(reg, original, mask);
2471 EFX_SET_OWORD32(reg, j, j, 0);
2472
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002473 efx_writeo(efx, &reg, address);
2474 efx_reado(efx, &buf, address);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002475
2476 if (efx_masked_compare_oword(&reg, &buf, &mask))
2477 goto fail;
2478 }
2479
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002480 efx_writeo(efx, &original, address);
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002481 }
2482
2483 return 0;
2484
2485fail:
2486 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2487 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2488 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2489 return -EIO;
2490}
2491
Ben Hutchings8ceee662008-04-27 12:55:59 +01002492/**************************************************************************
2493 *
2494 * Device reset
2495 *
2496 **************************************************************************
2497 */
2498
2499/* Resets NIC to known state. This routine must be called in process
2500 * context and is allowed to sleep. */
2501int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2502{
2503 struct falcon_nic_data *nic_data = efx->nic_data;
2504 efx_oword_t glb_ctl_reg_ker;
2505 int rc;
2506
Ben Hutchingsc4593022009-11-23 16:08:17 +00002507 EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002508
2509 /* Initiate device reset */
2510 if (method == RESET_TYPE_WORLD) {
2511 rc = pci_save_state(efx->pci_dev);
2512 if (rc) {
2513 EFX_ERR(efx, "failed to backup PCI state of primary "
2514 "function prior to hardware reset\n");
2515 goto fail1;
2516 }
2517 if (FALCON_IS_DUAL_FUNC(efx)) {
2518 rc = pci_save_state(nic_data->pci_dev2);
2519 if (rc) {
2520 EFX_ERR(efx, "failed to backup PCI state of "
2521 "secondary function prior to "
2522 "hardware reset\n");
2523 goto fail2;
2524 }
2525 }
2526
2527 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002528 FRF_AB_EXT_PHY_RST_DUR,
2529 FFE_AB_EXT_PHY_RST_DUR_10240US,
2530 FRF_AB_SWRST, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002531 } else {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002532 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002533 /* exclude PHY from "invisible" reset */
2534 FRF_AB_EXT_PHY_RST_CTL,
2535 method == RESET_TYPE_INVISIBLE,
2536 /* exclude EEPROM/flash and PCIe */
2537 FRF_AB_PCIE_CORE_RST_CTL, 1,
2538 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2539 FRF_AB_PCIE_SD_RST_CTL, 1,
2540 FRF_AB_EE_RST_CTL, 1,
2541 FRF_AB_EXT_PHY_RST_DUR,
2542 FFE_AB_EXT_PHY_RST_DUR_10240US,
2543 FRF_AB_SWRST, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002544 }
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002545 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002546
2547 EFX_LOG(efx, "waiting for hardware reset\n");
2548 schedule_timeout_uninterruptible(HZ / 20);
2549
2550 /* Restore PCI configuration if needed */
2551 if (method == RESET_TYPE_WORLD) {
2552 if (FALCON_IS_DUAL_FUNC(efx)) {
2553 rc = pci_restore_state(nic_data->pci_dev2);
2554 if (rc) {
2555 EFX_ERR(efx, "failed to restore PCI config for "
2556 "the secondary function\n");
2557 goto fail3;
2558 }
2559 }
2560 rc = pci_restore_state(efx->pci_dev);
2561 if (rc) {
2562 EFX_ERR(efx, "failed to restore PCI config for the "
2563 "primary function\n");
2564 goto fail4;
2565 }
2566 EFX_LOG(efx, "successfully restored PCI config\n");
2567 }
2568
2569 /* Assert that reset complete */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002570 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002571 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002572 rc = -ETIMEDOUT;
2573 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2574 goto fail5;
2575 }
2576 EFX_LOG(efx, "hardware reset complete\n");
2577
2578 return 0;
2579
2580 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2581fail2:
2582fail3:
2583 pci_restore_state(efx->pci_dev);
2584fail1:
2585fail4:
2586fail5:
2587 return rc;
2588}
2589
2590/* Zeroes out the SRAM contents. This routine must be called in
2591 * process context and is allowed to sleep.
2592 */
2593static int falcon_reset_sram(struct efx_nic *efx)
2594{
2595 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2596 int count;
2597
2598 /* Set the SRAM wake/sleep GPIO appropriately. */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002599 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002600 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2601 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002602 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002603
2604 /* Initiate SRAM reset */
2605 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002606 FRF_AZ_SRM_INIT_EN, 1,
2607 FRF_AZ_SRM_NB_SZ, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002608 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002609
2610 /* Wait for SRAM reset to complete */
2611 count = 0;
2612 do {
2613 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2614
2615 /* SRAM reset is slow; expect around 16ms */
2616 schedule_timeout_uninterruptible(HZ / 50);
2617
2618 /* Check for reset complete */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002619 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002620 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002621 EFX_LOG(efx, "SRAM reset complete\n");
2622
2623 return 0;
2624 }
2625 } while (++count < 20); /* wait upto 0.4 sec */
2626
2627 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2628 return -ETIMEDOUT;
2629}
2630
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002631static int falcon_spi_device_init(struct efx_nic *efx,
2632 struct efx_spi_device **spi_device_ret,
2633 unsigned int device_id, u32 device_type)
2634{
2635 struct efx_spi_device *spi_device;
2636
2637 if (device_type != 0) {
Ben Hutchings0c53d8c2008-12-12 22:08:50 -08002638 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002639 if (!spi_device)
2640 return -ENOMEM;
2641 spi_device->device_id = device_id;
2642 spi_device->size =
2643 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2644 spi_device->addr_len =
2645 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2646 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2647 spi_device->addr_len == 1);
Ben Hutchingsf4150722008-11-04 20:34:28 +00002648 spi_device->erase_command =
2649 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2650 spi_device->erase_size =
2651 1 << SPI_DEV_TYPE_FIELD(device_type,
2652 SPI_DEV_TYPE_ERASE_SIZE);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002653 spi_device->block_size =
2654 1 << SPI_DEV_TYPE_FIELD(device_type,
2655 SPI_DEV_TYPE_BLOCK_SIZE);
2656
2657 spi_device->efx = efx;
2658 } else {
2659 spi_device = NULL;
2660 }
2661
2662 kfree(*spi_device_ret);
2663 *spi_device_ret = spi_device;
2664 return 0;
2665}
2666
2667
2668static void falcon_remove_spi_devices(struct efx_nic *efx)
2669{
2670 kfree(efx->spi_eeprom);
2671 efx->spi_eeprom = NULL;
2672 kfree(efx->spi_flash);
2673 efx->spi_flash = NULL;
2674}
2675
Ben Hutchings8ceee662008-04-27 12:55:59 +01002676/* Extract non-volatile configuration */
2677static int falcon_probe_nvconfig(struct efx_nic *efx)
2678{
2679 struct falcon_nvconfig *nvconfig;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002680 int board_rev;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002681 int rc;
2682
Ben Hutchings8ceee662008-04-27 12:55:59 +01002683 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002684 if (!nvconfig)
2685 return -ENOMEM;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002686
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002687 rc = falcon_read_nvram(efx, nvconfig);
2688 if (rc == -EINVAL) {
2689 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
Ben Hutchings8ceee662008-04-27 12:55:59 +01002690 efx->phy_type = PHY_TYPE_NONE;
Ben Hutchings68e7f452009-04-29 08:05:08 +00002691 efx->mdio.prtad = MDIO_PRTAD_NONE;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002692 board_rev = 0;
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002693 rc = 0;
2694 } else if (rc) {
2695 goto fail1;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002696 } else {
2697 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002698 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002699
2700 efx->phy_type = v2->port0_phy_type;
Ben Hutchings68e7f452009-04-29 08:05:08 +00002701 efx->mdio.prtad = v2->port0_phy_addr;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002702 board_rev = le16_to_cpu(v2->board_revision);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002703
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002704 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002705 rc = falcon_spi_device_init(
2706 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2707 le32_to_cpu(v3->spi_device_type
2708 [FFE_AB_SPI_DEVICE_FLASH]));
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002709 if (rc)
2710 goto fail2;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002711 rc = falcon_spi_device_init(
2712 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2713 le32_to_cpu(v3->spi_device_type
2714 [FFE_AB_SPI_DEVICE_EEPROM]));
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002715 if (rc)
2716 goto fail2;
2717 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002718 }
2719
Ben Hutchings8c8661e2008-09-01 12:49:02 +01002720 /* Read the MAC addresses */
2721 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2722
Ben Hutchings68e7f452009-04-29 08:05:08 +00002723 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002724
Ben Hutchings3473a5b2009-10-23 08:29:16 +00002725 falcon_probe_board(efx, board_rev);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002726
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002727 kfree(nvconfig);
2728 return 0;
2729
2730 fail2:
2731 falcon_remove_spi_devices(efx);
2732 fail1:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002733 kfree(nvconfig);
2734 return rc;
2735}
2736
2737/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2738 * count, port speed). Set workaround and feature flags accordingly.
2739 */
2740static int falcon_probe_nic_variant(struct efx_nic *efx)
2741{
2742 efx_oword_t altera_build;
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002743 efx_oword_t nic_stat;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002744
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002745 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002746 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002747 EFX_ERR(efx, "Falcon FPGA not supported\n");
2748 return -ENODEV;
2749 }
2750
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002751 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002752
Ben Hutchings55668612008-05-16 21:16:10 +01002753 switch (falcon_rev(efx)) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002754 case FALCON_REV_A0:
2755 case 0xff:
2756 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2757 return -ENODEV;
2758
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002759 case FALCON_REV_A1:
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002760 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
Ben Hutchings8ceee662008-04-27 12:55:59 +01002761 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2762 return -ENODEV;
2763 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01002764 break;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002765
2766 case FALCON_REV_B0:
2767 break;
2768
2769 default:
Ben Hutchings55668612008-05-16 21:16:10 +01002770 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002771 return -ENODEV;
2772 }
2773
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002774 /* Initial assumed speed */
Ben Hutchingseb50c0d2009-11-23 16:06:30 +00002775 efx->link_state.speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002776
Ben Hutchings8ceee662008-04-27 12:55:59 +01002777 return 0;
2778}
2779
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002780/* Probe all SPI devices on the NIC */
2781static void falcon_probe_spi_devices(struct efx_nic *efx)
2782{
2783 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002784 int boot_dev;
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002785
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002786 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2787 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2788 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002789
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002790 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2791 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2792 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002793 EFX_LOG(efx, "Booted from %s\n",
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002794 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002795 } else {
2796 /* Disable VPD and set clock dividers to safe
2797 * values for initial programming. */
2798 boot_dev = -1;
2799 EFX_LOG(efx, "Booted from internal ASIC settings;"
2800 " setting SPI config\n");
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002801 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002802 /* 125 MHz / 7 ~= 20 MHz */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002803 FRF_AB_EE_SF_CLOCK_DIV, 7,
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002804 /* 125 MHz / 63 ~= 2 MHz */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002805 FRF_AB_EE_EE_CLOCK_DIV, 63);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002806 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002807 }
2808
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002809 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2810 falcon_spi_device_init(efx, &efx->spi_flash,
2811 FFE_AB_SPI_DEVICE_FLASH,
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002812 default_flash_type);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002813 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2814 falcon_spi_device_init(efx, &efx->spi_eeprom,
2815 FFE_AB_SPI_DEVICE_EEPROM,
Ben Hutchings2f7f5732008-12-12 21:34:25 -08002816 large_eeprom_type);
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002817}
2818
Ben Hutchings8ceee662008-04-27 12:55:59 +01002819int falcon_probe_nic(struct efx_nic *efx)
2820{
2821 struct falcon_nic_data *nic_data;
Ben Hutchingse775fb92009-11-23 16:06:02 +00002822 struct falcon_board *board;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002823 int rc;
2824
Ben Hutchings8ceee662008-04-27 12:55:59 +01002825 /* Allocate storage for hardware specific data */
2826 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
Ben Hutchings88c59422008-09-03 15:07:50 +01002827 if (!nic_data)
2828 return -ENOMEM;
Ben Hutchings5daab962008-05-16 21:19:43 +01002829 efx->nic_data = nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002830
2831 /* Determine number of ports etc. */
2832 rc = falcon_probe_nic_variant(efx);
2833 if (rc)
2834 goto fail1;
2835
2836 /* Probe secondary function if expected */
2837 if (FALCON_IS_DUAL_FUNC(efx)) {
2838 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2839
2840 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2841 dev))) {
2842 if (dev->bus == efx->pci_dev->bus &&
2843 dev->devfn == efx->pci_dev->devfn + 1) {
2844 nic_data->pci_dev2 = dev;
2845 break;
2846 }
2847 }
2848 if (!nic_data->pci_dev2) {
2849 EFX_ERR(efx, "failed to find secondary function\n");
2850 rc = -ENODEV;
2851 goto fail2;
2852 }
2853 }
2854
2855 /* Now we can reset the NIC */
2856 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2857 if (rc) {
2858 EFX_ERR(efx, "failed to reset NIC\n");
2859 goto fail3;
2860 }
2861
2862 /* Allocate memory for INT_KER */
2863 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2864 if (rc)
2865 goto fail4;
2866 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2867
Jaswinder Singh Rajput9c8976a2009-02-11 23:49:52 +05302868 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2869 (u64)efx->irq_status.dma_addr,
2870 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002871
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002872 falcon_probe_spi_devices(efx);
2873
Ben Hutchings8ceee662008-04-27 12:55:59 +01002874 /* Read in the non-volatile configuration */
2875 rc = falcon_probe_nvconfig(efx);
2876 if (rc)
2877 goto fail5;
2878
Ben Hutchings37b5a602008-05-30 22:27:04 +01002879 /* Initialise I2C adapter */
Ben Hutchingse775fb92009-11-23 16:06:02 +00002880 board = falcon_board(efx);
2881 board->i2c_adap.owner = THIS_MODULE;
2882 board->i2c_data = falcon_i2c_bit_operations;
2883 board->i2c_data.data = efx;
2884 board->i2c_adap.algo_data = &board->i2c_data;
2885 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2886 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2887 sizeof(board->i2c_adap.name));
2888 rc = i2c_bit_add_bus(&board->i2c_adap);
Ben Hutchings37b5a602008-05-30 22:27:04 +01002889 if (rc)
2890 goto fail5;
2891
Ben Hutchings44838a42009-11-25 16:09:41 +00002892 rc = falcon_board(efx)->type->init(efx);
Ben Hutchings278c0622009-11-23 16:05:12 +00002893 if (rc) {
2894 EFX_ERR(efx, "failed to initialise board\n");
2895 goto fail6;
2896 }
2897
Ben Hutchings8ceee662008-04-27 12:55:59 +01002898 return 0;
2899
Ben Hutchings278c0622009-11-23 16:05:12 +00002900 fail6:
Ben Hutchingse775fb92009-11-23 16:06:02 +00002901 BUG_ON(i2c_del_adapter(&board->i2c_adap));
2902 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
Ben Hutchings8ceee662008-04-27 12:55:59 +01002903 fail5:
Ben Hutchings4a5b5042008-09-01 12:47:16 +01002904 falcon_remove_spi_devices(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002905 falcon_free_buffer(efx, &efx->irq_status);
2906 fail4:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002907 fail3:
2908 if (nic_data->pci_dev2) {
2909 pci_dev_put(nic_data->pci_dev2);
2910 nic_data->pci_dev2 = NULL;
2911 }
2912 fail2:
Ben Hutchings8ceee662008-04-27 12:55:59 +01002913 fail1:
2914 kfree(efx->nic_data);
2915 return rc;
2916}
2917
Ben Hutchings56241ce2009-10-23 08:30:06 +00002918static void falcon_init_rx_cfg(struct efx_nic *efx)
2919{
2920 /* Prior to Siena the RX DMA engine will split each frame at
2921 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2922 * be so large that that never happens. */
2923 const unsigned huge_buf_size = (3 * 4096) >> 5;
2924 /* RX control FIFO thresholds (32 entries) */
2925 const unsigned ctrl_xon_thr = 20;
2926 const unsigned ctrl_xoff_thr = 25;
2927 /* RX data FIFO thresholds (256-byte units; size varies) */
Ben Hutchings625b4512009-10-23 08:30:17 +00002928 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2929 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
Ben Hutchings56241ce2009-10-23 08:30:06 +00002930 efx_oword_t reg;
2931
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002932 efx_reado(efx, &reg, FR_AZ_RX_CFG);
Ben Hutchings56241ce2009-10-23 08:30:06 +00002933 if (falcon_rev(efx) <= FALCON_REV_A1) {
Ben Hutchings625b4512009-10-23 08:30:17 +00002934 /* Data FIFO size is 5.5K */
2935 if (data_xon_thr < 0)
2936 data_xon_thr = 512 >> 8;
2937 if (data_xoff_thr < 0)
2938 data_xoff_thr = 2048 >> 8;
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002939 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2940 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2941 huge_buf_size);
2942 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2943 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2944 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2945 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
Ben Hutchings56241ce2009-10-23 08:30:06 +00002946 } else {
Ben Hutchings625b4512009-10-23 08:30:17 +00002947 /* Data FIFO size is 80K; register fields moved */
2948 if (data_xon_thr < 0)
2949 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2950 if (data_xoff_thr < 0)
2951 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002952 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2953 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2954 huge_buf_size);
2955 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2956 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2957 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2958 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2959 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
Ben Hutchings56241ce2009-10-23 08:30:06 +00002960 }
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002961 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
Ben Hutchings56241ce2009-10-23 08:30:06 +00002962}
2963
Ben Hutchings8ceee662008-04-27 12:55:59 +01002964/* This call performs hardware-specific global initialisation, such as
2965 * defining the descriptor cache sizes and number of RSS channels.
2966 * It does not set up any buffers, descriptor rings or event queues.
2967 */
2968int falcon_init_nic(struct efx_nic *efx)
2969{
Ben Hutchings8ceee662008-04-27 12:55:59 +01002970 efx_oword_t temp;
Ben Hutchings8ceee662008-04-27 12:55:59 +01002971 int rc;
2972
Ben Hutchings8ceee662008-04-27 12:55:59 +01002973 /* Use on-chip SRAM */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002974 efx_reado(efx, &temp, FR_AB_NIC_STAT);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002975 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002976 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002977
Ben Hutchings6f158d52008-12-12 22:00:49 -08002978 /* Set the source of the GMAC clock */
2979 if (falcon_rev(efx) == FALCON_REV_B0) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002980 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002981 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002982 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
Ben Hutchings6f158d52008-12-12 22:00:49 -08002983 }
2984
Ben Hutchings8ceee662008-04-27 12:55:59 +01002985 rc = falcon_reset_sram(efx);
2986 if (rc)
2987 return rc;
2988
2989 /* Set positions of descriptor caches in SRAM. */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002990 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002991 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002992 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002993 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002994
2995 /* Set TX descriptor cache size. */
Ben Hutchings46e1ac02009-11-25 16:08:30 +00002996 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
Ben Hutchings3e6c4532009-10-23 08:30:36 +00002997 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00002998 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01002999
3000 /* Set RX descriptor cache size. Set low watermark to size-8, as
3001 * this allows most efficient prefetching.
3002 */
Ben Hutchings46e1ac02009-11-25 16:08:30 +00003003 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003004 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003005 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003006 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003007 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003008
3009 /* Clear the parity enables on the TX data fifos as
3010 * they produce false parity errors because of timing issues
3011 */
3012 if (EFX_WORKAROUND_5129(efx)) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003013 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003014 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003015 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003016 }
3017
3018 /* Enable all the genuinely fatal interrupts. (They are still
3019 * masked by the overall interrupt mask, controlled by
3020 * falcon_interrupts()).
3021 *
3022 * Note: All other fatal interrupts are enabled
3023 */
3024 EFX_POPULATE_OWORD_3(temp,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003025 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3026 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3027 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003028 EFX_INVERT_OWORD(temp);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003029 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003030
Ben Hutchings8ceee662008-04-27 12:55:59 +01003031 if (EFX_WORKAROUND_7244(efx)) {
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003032 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003033 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3034 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3035 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3036 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003037 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003038 }
Ben Hutchings8ceee662008-04-27 12:55:59 +01003039
3040 falcon_setup_rss_indir_table(efx);
3041
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003042 /* XXX This is documented only for Falcon A0/A1 */
Ben Hutchings8ceee662008-04-27 12:55:59 +01003043 /* Setup RX. Wait for descriptor is broken and must
3044 * be disabled. RXDP recovery shouldn't be needed, but is.
3045 */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003046 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003047 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3048 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003049 if (EFX_WORKAROUND_5583(efx))
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003050 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003051 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003052
3053 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3054 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3055 */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003056 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003057 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3058 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3059 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3060 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3061 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003062 /* Enable SW_EV to inherit in char driver - assume harmless here */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003063 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003064 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003065 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003066 /* Squash TX of packets of 16 bytes or less */
Ben Hutchings55668612008-05-16 21:16:10 +01003067 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003068 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003069 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003070
3071 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3072 * descriptors (which is bad).
3073 */
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003074 efx_reado(efx, &temp, FR_AZ_TX_CFG);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003075 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003076 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003077
Ben Hutchings56241ce2009-10-23 08:30:06 +00003078 falcon_init_rx_cfg(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003079
3080 /* Set destination of both TX and RX Flush events */
Ben Hutchings55668612008-05-16 21:16:10 +01003081 if (falcon_rev(efx) >= FALCON_REV_B0) {
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003082 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003083 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003084 }
3085
3086 return 0;
3087}
3088
3089void falcon_remove_nic(struct efx_nic *efx)
3090{
3091 struct falcon_nic_data *nic_data = efx->nic_data;
Ben Hutchingse775fb92009-11-23 16:06:02 +00003092 struct falcon_board *board = falcon_board(efx);
Ben Hutchings37b5a602008-05-30 22:27:04 +01003093 int rc;
3094
Ben Hutchings44838a42009-11-25 16:09:41 +00003095 board->type->fini(efx);
Ben Hutchings278c0622009-11-23 16:05:12 +00003096
Ben Hutchings8c870372009-03-04 09:53:02 +00003097 /* Remove I2C adapter and clear it in preparation for a retry */
Ben Hutchingse775fb92009-11-23 16:06:02 +00003098 rc = i2c_del_adapter(&board->i2c_adap);
Ben Hutchings37b5a602008-05-30 22:27:04 +01003099 BUG_ON(rc);
Ben Hutchingse775fb92009-11-23 16:06:02 +00003100 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
Ben Hutchings8ceee662008-04-27 12:55:59 +01003101
Ben Hutchings4a5b5042008-09-01 12:47:16 +01003102 falcon_remove_spi_devices(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003103 falcon_free_buffer(efx, &efx->irq_status);
3104
Ben Hutchings91ad7572008-05-16 21:14:27 +01003105 falcon_reset_hw(efx, RESET_TYPE_ALL);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003106
3107 /* Release the second function after the reset */
3108 if (nic_data->pci_dev2) {
3109 pci_dev_put(nic_data->pci_dev2);
3110 nic_data->pci_dev2 = NULL;
3111 }
3112
3113 /* Tear down the private nic state */
3114 kfree(efx->nic_data);
3115 efx->nic_data = NULL;
3116}
3117
3118void falcon_update_nic_stats(struct efx_nic *efx)
3119{
3120 efx_oword_t cnt;
3121
Ben Hutchings12d00ca2009-10-23 08:30:46 +00003122 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003123 efx->n_rx_nodesc_drop_cnt +=
3124 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
Ben Hutchings8ceee662008-04-27 12:55:59 +01003125}
3126
3127/**************************************************************************
3128 *
3129 * Revision-dependent attributes used by efx.c
3130 *
3131 **************************************************************************
3132 */
3133
3134struct efx_nic_type falcon_a_nic_type = {
Ben Hutchings8ceee662008-04-27 12:55:59 +01003135 .mem_map_size = 0x20000,
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003136 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3137 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3138 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3139 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3140 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
Ben Hutchings6d51d302009-10-23 08:31:07 +00003141 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
Ben Hutchings8ceee662008-04-27 12:55:59 +01003142 .rx_buffer_padding = 0x24,
3143 .max_interrupt_mode = EFX_INT_MODE_MSI,
3144 .phys_addr_channels = 4,
3145};
3146
3147struct efx_nic_type falcon_b_nic_type = {
Ben Hutchings8ceee662008-04-27 12:55:59 +01003148 /* Map everything up to and including the RSS indirection
3149 * table. Don't map MSI-X table, MSI-X PBA since Linux
3150 * requires that they not be mapped. */
Ben Hutchings3e6c4532009-10-23 08:30:36 +00003151 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3152 FR_BZ_RX_INDIRECTION_TBL_STEP *
3153 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3154 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3155 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3156 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3157 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3158 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
Ben Hutchings6d51d302009-10-23 08:31:07 +00003159 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
Ben Hutchings8ceee662008-04-27 12:55:59 +01003160 .rx_buffer_padding = 0,
3161 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3162 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3163 * interrupt handler only supports 32
3164 * channels */
3165};
3166