blob: 60e730a6f1ddebc4f6093db2c90223e7f702a798 [file] [log] [blame]
Michael Buesch424047e2008-01-09 16:13:56 +01001/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
John W. Linville819d7722008-01-17 16:57:10 -050025#include <linux/delay.h>
26#include <linux/types.h>
27
Michael Buesch424047e2008-01-09 16:13:56 +010028#include "b43.h"
Michael Buesch3d0da752008-08-30 02:27:19 +020029#include "phy_n.h"
Michael Buesch53a6e232008-01-13 21:23:44 +010030#include "tables_nphy.h"
Rafał Miłeckibbec3982010-01-15 14:31:39 +010031#include "main.h"
Michael Buesch424047e2008-01-09 16:13:56 +010032
Rafał Miłeckif8187b52010-01-15 12:34:21 +010033struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
Michael Buesch424047e2008-01-09 16:13:56 +010057
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +010058enum b43_nphy_rf_sequence {
59 B43_RFSEQ_RX2TX,
60 B43_RFSEQ_TX2RX,
61 B43_RFSEQ_RESET2RX,
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
65};
66
67static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
68 enum b43_nphy_rf_sequence seq);
69
Michael Buesch53a6e232008-01-13 21:23:44 +010070void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
71{//TODO
72}
73
Michael Buesch18c8ade2008-08-28 19:33:40 +020074static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
Michael Buesch53a6e232008-01-13 21:23:44 +010075{//TODO
76}
77
Michael Buesch18c8ade2008-08-28 19:33:40 +020078static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
79 bool ignore_tssi)
80{//TODO
81 return B43_TXPWR_RES_DONE;
82}
83
Michael Bueschd1591312008-01-14 00:05:57 +010084static void b43_chantab_radio_upload(struct b43_wldev *dev,
85 const struct b43_nphy_channeltab_entry *e)
86{
87 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
88 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
89 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
90 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
91 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
92 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
93 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
94 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
95 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
96 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
97 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
98 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
99 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
100 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
101 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
102 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
103 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
104 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
105 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
106 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
107 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
108 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
109}
110
111static void b43_chantab_phy_upload(struct b43_wldev *dev,
112 const struct b43_nphy_channeltab_entry *e)
113{
114 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
115 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
116 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
117 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
118 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
119 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
120}
121
122static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
123{
124 //TODO
125}
126
Michael Bueschef1a6282008-08-27 18:53:02 +0200127/* Tune the hardware to a new channel. */
128static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
Michael Buesch53a6e232008-01-13 21:23:44 +0100129{
Michael Bueschd1591312008-01-14 00:05:57 +0100130 const struct b43_nphy_channeltab_entry *tabent;
Michael Buesch53a6e232008-01-13 21:23:44 +0100131
Michael Bueschd1591312008-01-14 00:05:57 +0100132 tabent = b43_nphy_get_chantabent(dev, channel);
133 if (!tabent)
134 return -ESRCH;
135
136 //FIXME enable/disable band select upper20 in RXCTL
137 if (0 /*FIXME 5Ghz*/)
138 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
139 else
140 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
141 b43_chantab_radio_upload(dev, tabent);
142 udelay(50);
143 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
144 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
145 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
146 udelay(300);
147 if (0 /*FIXME 5Ghz*/)
148 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
149 else
150 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
151 b43_chantab_phy_upload(dev, tabent);
152 b43_nphy_tx_power_fix(dev);
153
154 return 0;
Michael Buesch53a6e232008-01-13 21:23:44 +0100155}
156
157static void b43_radio_init2055_pre(struct b43_wldev *dev)
158{
159 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
160 ~B43_NPHY_RFCTL_CMD_PORFORCE);
161 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
162 B43_NPHY_RFCTL_CMD_CHIP0PU |
163 B43_NPHY_RFCTL_CMD_OEPORFORCE);
164 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
165 B43_NPHY_RFCTL_CMD_PORFORCE);
166}
167
168static void b43_radio_init2055_post(struct b43_wldev *dev)
169{
170 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
171 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
172 int i;
173 u16 val;
174
175 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
176 msleep(1);
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200177 if ((sprom->revision != 4) ||
178 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
Michael Buesch53a6e232008-01-13 21:23:44 +0100179 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
180 (binfo->type != 0x46D) ||
181 (binfo->rev < 0x41)) {
182 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
183 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
184 msleep(1);
185 }
186 }
187 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
188 msleep(1);
189 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
190 msleep(1);
191 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
192 msleep(1);
193 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
194 msleep(1);
195 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
196 msleep(1);
197 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
198 msleep(1);
199 for (i = 0; i < 100; i++) {
200 val = b43_radio_read16(dev, B2055_CAL_COUT2);
201 if (val & 0x80)
202 break;
203 udelay(10);
204 }
205 msleep(1);
206 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
207 msleep(1);
Michael Bueschef1a6282008-08-27 18:53:02 +0200208 nphy_channel_switch(dev, dev->phy.channel);
Michael Buesch53a6e232008-01-13 21:23:44 +0100209 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
210 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
211 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
212 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
213}
214
215/* Initialize a Broadcom 2055 N-radio */
216static void b43_radio_init2055(struct b43_wldev *dev)
217{
218 b43_radio_init2055_pre(dev);
219 if (b43_status(dev) < B43_STAT_INITIALIZED)
220 b2055_upload_inittab(dev, 0, 1);
221 else
222 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
223 b43_radio_init2055_post(dev);
224}
225
226void b43_nphy_radio_turn_on(struct b43_wldev *dev)
227{
228 b43_radio_init2055(dev);
229}
230
231void b43_nphy_radio_turn_off(struct b43_wldev *dev)
232{
233 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
234 ~B43_NPHY_RFCTL_CMD_EN);
235}
236
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100237/*
238 * Upload the N-PHY tables.
239 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
240 */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100241static void b43_nphy_tables_init(struct b43_wldev *dev)
242{
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100243 if (dev->phy.rev < 3)
244 b43_nphy_rev0_1_2_tables_init(dev);
245 else
246 b43_nphy_rev3plus_tables_init(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100247}
248
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +0100249/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
250static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
251{
252 struct b43_phy_n *nphy = dev->phy.n;
253 enum ieee80211_band band;
254 u16 tmp;
255
256 if (!enable) {
257 nphy->rfctrl_intc1_save = b43_phy_read(dev,
258 B43_NPHY_RFCTL_INTC1);
259 nphy->rfctrl_intc2_save = b43_phy_read(dev,
260 B43_NPHY_RFCTL_INTC2);
261 band = b43_current_band(dev->wl);
262 if (dev->phy.rev >= 3) {
263 if (band == IEEE80211_BAND_5GHZ)
264 tmp = 0x600;
265 else
266 tmp = 0x480;
267 } else {
268 if (band == IEEE80211_BAND_5GHZ)
269 tmp = 0x180;
270 else
271 tmp = 0x120;
272 }
273 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
274 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
275 } else {
276 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
277 nphy->rfctrl_intc1_save);
278 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
279 nphy->rfctrl_intc2_save);
280 }
281}
282
Rafał Miłeckife3e46e2010-01-15 15:51:55 +0100283/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
284static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
285{
286 struct b43_phy_n *nphy = dev->phy.n;
287 u16 tmp;
288 enum ieee80211_band band = b43_current_band(dev->wl);
289 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
290 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
291
292 if (dev->phy.rev >= 3) {
293 if (ipa) {
294 tmp = 4;
295 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
296 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
297 }
298
299 tmp = 1;
300 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
301 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
302 }
303}
304
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100305/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
306static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
307{
308 u32 tmslow;
309
310 if (dev->phy.type != B43_PHYTYPE_N)
311 return;
312
313 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
314 if (force)
315 tmslow |= SSB_TMSLOW_FGC;
316 else
317 tmslow &= ~SSB_TMSLOW_FGC;
318 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
319}
320
321/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100322static void b43_nphy_reset_cca(struct b43_wldev *dev)
323{
324 u16 bbcfg;
325
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100326 b43_nphy_bmac_clock_fgc(dev, 1);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100327 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100328 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
329 udelay(1);
330 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
331 b43_nphy_bmac_clock_fgc(dev, 0);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100332 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100333}
334
Rafał Miłeckiad9716e2010-01-17 13:03:40 +0100335/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
336static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
337{
338 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
339
340 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
341 if (preamble == 1)
342 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
343 else
344 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
345
346 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
347}
348
Rafał Miłecki4f4ab6c2010-01-17 13:03:55 +0100349/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
350static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
351{
352 struct b43_phy_n *nphy = dev->phy.n;
353
354 bool override = false;
355 u16 chain = 0x33;
356
357 if (nphy->txrx_chain == 0) {
358 chain = 0x11;
359 override = true;
360 } else if (nphy->txrx_chain == 1) {
361 chain = 0x22;
362 override = true;
363 }
364
365 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
366 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
367 chain);
368
369 if (override)
370 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
371 B43_NPHY_RFSEQMODE_CAOVER);
372 else
373 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
374 ~B43_NPHY_RFSEQMODE_CAOVER);
375}
376
Rafał Miłecki2faa6b82010-01-15 15:26:12 +0100377/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
378static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
379 u16 samps, u8 time, bool wait)
380{
381 int i;
382 u16 tmp;
383
384 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
385 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
386 if (wait)
387 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
388 else
389 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
390
391 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
392
393 for (i = 1000; i; i--) {
394 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
395 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
396 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
397 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
398 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
399 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
400 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
401 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
402
403 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
404 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
405 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
406 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
407 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
408 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
409 return;
410 }
411 udelay(10);
412 }
413 memset(est, 0, sizeof(*est));
414}
415
Rafał Miłeckia67162a2010-01-15 15:16:25 +0100416/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
417static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
418 struct b43_phy_n_iq_comp *pcomp)
419{
420 if (write) {
421 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
422 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
423 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
424 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
425 } else {
426 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
427 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
428 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
429 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
430 }
431}
432
Rafał Miłecki026816f2010-01-17 13:03:28 +0100433/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
434static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
435{
436 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
437
438 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
439 if (core == 0) {
440 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
441 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
442 } else {
443 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
444 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
445 }
446 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
447 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
448 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
449 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
450 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
451 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
452 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
453 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
454}
455
456/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
457static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
458{
459 u8 rxval, txval;
460 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
461
462 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
463 if (core == 0) {
464 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
465 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
466 } else {
467 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
468 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
469 }
470 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
471 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
472 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
473 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
474 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
475 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
476 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
477 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
478
479 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
480 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
481
482 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
483 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
484 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
485 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
486 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
487 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
488 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
489 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
490
491 if (core == 0) {
492 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
493 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
494 } else {
495 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
496 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
497 }
498
499 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
500 /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100501 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
Rafał Miłecki026816f2010-01-17 13:03:28 +0100502
503 if (core == 0) {
504 rxval = 1;
505 txval = 8;
506 } else {
507 rxval = 4;
508 txval = 2;
509 }
510
511 /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
512 /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
513}
514
Rafał Miłecki34a56f22010-01-15 15:29:05 +0100515/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
516static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
517{
518 int i;
519 s32 iq;
520 u32 ii;
521 u32 qq;
522 int iq_nbits, qq_nbits;
523 int arsh, brsh;
524 u16 tmp, a, b;
525
526 struct nphy_iq_est est;
527 struct b43_phy_n_iq_comp old;
528 struct b43_phy_n_iq_comp new = { };
529 bool error = false;
530
531 if (mask == 0)
532 return;
533
534 b43_nphy_rx_iq_coeffs(dev, false, &old);
535 b43_nphy_rx_iq_coeffs(dev, true, &new);
536 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
537 new = old;
538
539 for (i = 0; i < 2; i++) {
540 if (i == 0 && (mask & 1)) {
541 iq = est.iq0_prod;
542 ii = est.i0_pwr;
543 qq = est.q0_pwr;
544 } else if (i == 1 && (mask & 2)) {
545 iq = est.iq1_prod;
546 ii = est.i1_pwr;
547 qq = est.q1_pwr;
548 } else {
549 B43_WARN_ON(1);
550 continue;
551 }
552
553 if (ii + qq < 2) {
554 error = true;
555 break;
556 }
557
558 iq_nbits = fls(abs(iq));
559 qq_nbits = fls(qq);
560
561 arsh = iq_nbits - 20;
562 if (arsh >= 0) {
563 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
564 tmp = ii >> arsh;
565 } else {
566 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
567 tmp = ii << -arsh;
568 }
569 if (tmp == 0) {
570 error = true;
571 break;
572 }
573 a /= tmp;
574
575 brsh = qq_nbits - 11;
576 if (brsh >= 0) {
577 b = (qq << (31 - qq_nbits));
578 tmp = ii >> brsh;
579 } else {
580 b = (qq << (31 - qq_nbits));
581 tmp = ii << -brsh;
582 }
583 if (tmp == 0) {
584 error = true;
585 break;
586 }
587 b = int_sqrt(b / tmp - a * a) - (1 << 10);
588
589 if (i == 0 && (mask & 0x1)) {
590 if (dev->phy.rev >= 3) {
591 new.a0 = a & 0x3FF;
592 new.b0 = b & 0x3FF;
593 } else {
594 new.a0 = b & 0x3FF;
595 new.b0 = a & 0x3FF;
596 }
597 } else if (i == 1 && (mask & 0x2)) {
598 if (dev->phy.rev >= 3) {
599 new.a1 = a & 0x3FF;
600 new.b1 = b & 0x3FF;
601 } else {
602 new.a1 = b & 0x3FF;
603 new.b1 = a & 0x3FF;
604 }
605 }
606 }
607
608 if (error)
609 new = old;
610
611 b43_nphy_rx_iq_coeffs(dev, true, &new);
612}
613
Rafał Miłecki09146402010-01-15 15:17:10 +0100614/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
615static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
616{
617 u16 array[4];
618 int i;
619
620 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
621 for (i = 0; i < 4; i++)
622 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
623
624 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
625 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
626 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
627 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
628}
629
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100630/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
631static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
632{
633 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
634 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
635}
636
637/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
638static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
639{
640 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
641 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
642}
643
644/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
645static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
646{
647 u16 tmp;
648
649 if (dev->dev->id.revision == 16)
650 b43_mac_suspend(dev);
651
652 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
653 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
654 B43_NPHY_CLASSCTL_WAITEDEN);
655 tmp &= ~mask;
656 tmp |= (val & mask);
657 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
658
659 if (dev->dev->id.revision == 16)
660 b43_mac_enable(dev);
661
662 return tmp;
663}
664
Rafał Miłecki5c1a1402010-01-15 15:10:54 +0100665/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
666static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
667{
668 struct b43_phy *phy = &dev->phy;
669 struct b43_phy_n *nphy = phy->n;
670
671 if (enable) {
672 u16 clip[] = { 0xFFFF, 0xFFFF };
673 if (nphy->deaf_count++ == 0) {
674 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
675 b43_nphy_classifier(dev, 0x7, 0);
676 b43_nphy_read_clip_detection(dev, nphy->clip_state);
677 b43_nphy_write_clip_detection(dev, clip);
678 }
679 b43_nphy_reset_cca(dev);
680 } else {
681 if (--nphy->deaf_count == 0) {
682 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
683 b43_nphy_write_clip_detection(dev, nphy->clip_state);
684 }
685 }
686}
687
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100688/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
689static void b43_nphy_stop_playback(struct b43_wldev *dev)
690{
691 struct b43_phy_n *nphy = dev->phy.n;
692 u16 tmp;
693
694 if (nphy->hang_avoid)
695 b43_nphy_stay_in_carrier_search(dev, 1);
696
697 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
698 if (tmp & 0x1)
699 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
700 else if (tmp & 0x2)
701 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
702
703 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
704
705 if (nphy->bb_mult_save & 0x80000000) {
706 tmp = nphy->bb_mult_save & 0xFFFF;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100707 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100708 nphy->bb_mult_save = 0;
709 }
710
711 if (nphy->hang_avoid)
712 b43_nphy_stay_in_carrier_search(dev, 0);
713}
714
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100715/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
716static void b43_nphy_workarounds(struct b43_wldev *dev)
717{
718 struct ssb_bus *bus = dev->dev->bus;
719 struct b43_phy *phy = &dev->phy;
720 struct b43_phy_n *nphy = phy->n;
721
722 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
723 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
724
725 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
726 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
727
728 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
729 b43_nphy_classifier(dev, 1, 0);
730 else
731 b43_nphy_classifier(dev, 1, 1);
732
733 if (nphy->hang_avoid)
734 b43_nphy_stay_in_carrier_search(dev, 1);
735
736 b43_phy_set(dev, B43_NPHY_IQFLIP,
737 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
738
739 if (dev->phy.rev >= 3) {
740 /* TODO */
741 } else {
742 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
743 nphy->band5g_pwrgain) {
744 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
745 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
746 } else {
747 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
748 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
749 }
750
751 /* TODO: convert to b43_ntab_write? */
752 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
753 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
754 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
755 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
756 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
757 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
758 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
759 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
760
761 if (dev->phy.rev < 2) {
762 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
763 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
764 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
765 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
766 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
767 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
768 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
769 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
770 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
771 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
772 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
773 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
774 }
775
776 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
777 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
778 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
779 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
780
781 if (bus->sprom.boardflags2_lo & 0x100 &&
782 bus->boardinfo.type == 0x8B) {
783 delays1[0] = 0x1;
784 delays1[5] = 0x14;
785 }
786 /*TODO:b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);*/
787 /*TODO:b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);*/
788
789 /*TODO:b43_nphy_gain_crtl_workarounds(dev);*/
790
791 if (dev->phy.rev < 2) {
792 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
793 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
794 } else if (dev->phy.rev == 2) {
795 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
796 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
797 }
798
799 if (dev->phy.rev < 2)
800 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
801 ~B43_NPHY_SCRAM_SIGCTL_SCM);
802
803 /* Set phase track alpha and beta */
804 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
805 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
806 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
807 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
808 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
809 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
810
811 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
812 (u16)~B43_NPHY_PIL_DW_64QAM);
813 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
814 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
815 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
816
817 if (dev->phy.rev == 2)
818 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
819 B43_NPHY_FINERX2_CGC_DECGC);
820 }
821
822 if (nphy->hang_avoid)
823 b43_nphy_stay_in_carrier_search(dev, 0);
824}
825
Rafał Miłecki59af0992010-01-22 01:53:16 +0100826/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
827static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
828 bool test)
829{
830 int i;
Rafał Miłeckif2982182010-01-25 19:00:01 +0100831 u16 bw, len, rot, angle;
Larry Fingerda860472010-01-26 16:42:02 -0600832 struct b43_c32 *samples;
Rafał Miłeckif2982182010-01-25 19:00:01 +0100833
Rafał Miłecki59af0992010-01-22 01:53:16 +0100834
835 bw = (dev->phy.is_40mhz) ? 40 : 20;
836 len = bw << 3;
837
838 if (test) {
839 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
840 bw = 82;
841 else
842 bw = 80;
843
844 if (dev->phy.is_40mhz)
845 bw <<= 1;
846
847 len = bw << 1;
848 }
849
Larry Fingerda860472010-01-26 16:42:02 -0600850 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
Rafał Miłecki59af0992010-01-22 01:53:16 +0100851 rot = (((freq * 36) / bw) << 16) / 100;
852 angle = 0;
853
Rafał Miłeckif2982182010-01-25 19:00:01 +0100854 for (i = 0; i < len; i++) {
855 samples[i] = b43_cordic(angle);
856 angle += rot;
857 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
858 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
Rafał Miłecki59af0992010-01-22 01:53:16 +0100859 }
860
Rafał Miłeckif2982182010-01-25 19:00:01 +0100861 /* TODO: Call N PHY Load Sample Table with buffer, len as arguments */
862 kfree(samples);
863 return len;
Rafał Miłecki59af0992010-01-22 01:53:16 +0100864}
865
Rafał Miłecki10a79872010-01-22 01:53:14 +0100866/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
867static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
868 u16 wait, bool iqmode, bool dac_test)
869{
870 struct b43_phy_n *nphy = dev->phy.n;
871 int i;
872 u16 seq_mode;
873 u32 tmp;
874
875 if (nphy->hang_avoid)
876 b43_nphy_stay_in_carrier_search(dev, true);
877
878 if ((nphy->bb_mult_save & 0x80000000) == 0) {
879 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
880 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
881 }
882
883 if (!dev->phy.is_40mhz)
884 tmp = 0x6464;
885 else
886 tmp = 0x4747;
887 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
888
889 if (nphy->hang_avoid)
890 b43_nphy_stay_in_carrier_search(dev, false);
891
892 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
893
894 if (loops != 0xFFFF)
895 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
896 else
897 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
898
899 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
900
901 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
902
903 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
904 if (iqmode) {
905 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
906 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
907 } else {
908 if (dac_test)
909 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
910 else
911 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
912 }
913 for (i = 0; i < 100; i++) {
914 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
915 i = 0;
916 break;
917 }
918 udelay(10);
919 }
920 if (i)
921 b43err(dev->wl, "run samples timeout\n");
922
923 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
924}
925
Rafał Miłecki59af0992010-01-22 01:53:16 +0100926/*
927 * Transmits a known value for LO calibration
928 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
929 */
930static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
931 bool iqmode, bool dac_test)
932{
933 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
934 if (samp == 0)
935 return -1;
936 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
937 return 0;
938}
939
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100940/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
941static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
942{
943 struct b43_phy_n *nphy = dev->phy.n;
944 int i, j;
945 u32 tmp;
946 u32 cur_real, cur_imag, real_part, imag_part;
947
948 u16 buffer[7];
949
950 if (nphy->hang_avoid)
951 b43_nphy_stay_in_carrier_search(dev, true);
952
Rafał Miłecki91458342010-01-18 00:21:35 +0100953 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100954
955 for (i = 0; i < 2; i++) {
956 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
957 (buffer[i * 2 + 1] & 0x3FF);
958 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
959 (((i + 26) << 10) | 320));
960 for (j = 0; j < 128; j++) {
961 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
962 ((tmp >> 16) & 0xFFFF));
963 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
964 (tmp & 0xFFFF));
965 }
966 }
967
968 for (i = 0; i < 2; i++) {
969 tmp = buffer[5 + i];
970 real_part = (tmp >> 8) & 0xFF;
971 imag_part = (tmp & 0xFF);
972 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
973 (((i + 26) << 10) | 448));
974
975 if (dev->phy.rev >= 3) {
976 cur_real = real_part;
977 cur_imag = imag_part;
978 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
979 }
980
981 for (j = 0; j < 128; j++) {
982 if (dev->phy.rev < 3) {
983 cur_real = (real_part * loscale[j] + 128) >> 8;
984 cur_imag = (imag_part * loscale[j] + 128) >> 8;
985 tmp = ((cur_real & 0xFF) << 8) |
986 (cur_imag & 0xFF);
987 }
988 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
989 ((tmp >> 16) & 0xFFFF));
990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
991 (tmp & 0xFFFF));
992 }
993 }
994
995 if (dev->phy.rev >= 3) {
996 b43_shm_write16(dev, B43_SHM_SHARED,
997 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
998 b43_shm_write16(dev, B43_SHM_SHARED,
999 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1000 }
1001
1002 if (nphy->hang_avoid)
1003 b43_nphy_stay_in_carrier_search(dev, false);
1004}
1005
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +01001006/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
Michael Buesch95b66ba2008-01-18 01:09:25 +01001007static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1008 enum b43_nphy_rf_sequence seq)
1009{
1010 static const u16 trigger[] = {
1011 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1012 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1013 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1014 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1015 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1016 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1017 };
1018 int i;
Rafał Miłeckic57199b2010-01-17 13:04:08 +01001019 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
Michael Buesch95b66ba2008-01-18 01:09:25 +01001020
1021 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1022
1023 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1024 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1025 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1026 for (i = 0; i < 200; i++) {
1027 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1028 goto ok;
1029 msleep(1);
1030 }
1031 b43err(dev->wl, "RF sequence status timeout\n");
1032ok:
Rafał Miłeckic57199b2010-01-17 13:04:08 +01001033 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
Michael Buesch95b66ba2008-01-18 01:09:25 +01001034}
1035
Rafał Miłecki75377b22010-01-22 01:53:13 +01001036/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1037static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1038 u16 value, u8 core, bool off)
1039{
1040 int i;
1041 u8 index = fls(field);
1042 u8 addr, en_addr, val_addr;
1043 /* we expect only one bit set */
Rafał Miłecki3ed0fac2010-01-25 18:59:58 +01001044 B43_WARN_ON(field & (~(1 << (index - 1))));
Rafał Miłecki75377b22010-01-22 01:53:13 +01001045
1046 if (dev->phy.rev >= 3) {
1047 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1048 for (i = 0; i < 2; i++) {
1049 if (index == 0 || index == 16) {
1050 b43err(dev->wl,
1051 "Unsupported RF Ctrl Override call\n");
1052 return;
1053 }
1054
1055 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1056 en_addr = B43_PHY_N((i == 0) ?
1057 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1058 val_addr = B43_PHY_N((i == 0) ?
1059 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1060
1061 if (off) {
1062 b43_phy_mask(dev, en_addr, ~(field));
1063 b43_phy_mask(dev, val_addr,
1064 ~(rf_ctrl->val_mask));
1065 } else {
1066 if (core == 0 || ((1 << core) & i) != 0) {
1067 b43_phy_set(dev, en_addr, field);
1068 b43_phy_maskset(dev, val_addr,
1069 ~(rf_ctrl->val_mask),
1070 (value << rf_ctrl->val_shift));
1071 }
1072 }
1073 }
1074 } else {
1075 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1076 if (off) {
1077 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1078 value = 0;
1079 } else {
1080 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1081 }
1082
1083 for (i = 0; i < 2; i++) {
1084 if (index <= 1 || index == 16) {
1085 b43err(dev->wl,
1086 "Unsupported RF Ctrl Override call\n");
1087 return;
1088 }
1089
1090 if (index == 2 || index == 10 ||
1091 (index >= 13 && index <= 15)) {
1092 core = 1;
1093 }
1094
1095 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1096 addr = B43_PHY_N((i == 0) ?
1097 rf_ctrl->addr0 : rf_ctrl->addr1);
1098
1099 if ((core & (1 << i)) != 0)
1100 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1101 (value << rf_ctrl->shift));
1102
1103 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1104 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1105 B43_NPHY_RFCTL_CMD_START);
1106 udelay(1);
1107 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1108 }
1109 }
1110}
1111
Michael Buesch95b66ba2008-01-18 01:09:25 +01001112static void b43_nphy_bphy_init(struct b43_wldev *dev)
1113{
1114 unsigned int i;
1115 u16 val;
1116
1117 val = 0x1E1F;
1118 for (i = 0; i < 14; i++) {
1119 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1120 val -= 0x202;
1121 }
1122 val = 0x3E3F;
1123 for (i = 0; i < 16; i++) {
1124 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1125 val -= 0x202;
1126 }
1127 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1128}
1129
Rafał Miłecki3c956272010-01-15 14:38:32 +01001130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1131static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1132 s8 offset, u8 core, u8 rail, u8 type)
1133{
1134 u16 tmp;
1135 bool core1or5 = (core == 1) || (core == 5);
1136 bool core2or5 = (core == 2) || (core == 5);
1137
1138 offset = clamp_val(offset, -32, 31);
1139 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1140
1141 if (core1or5 && (rail == 0) && (type == 2))
1142 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1143 if (core1or5 && (rail == 1) && (type == 2))
1144 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1145 if (core2or5 && (rail == 0) && (type == 2))
1146 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1147 if (core2or5 && (rail == 1) && (type == 2))
1148 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1149 if (core1or5 && (rail == 0) && (type == 0))
1150 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1151 if (core1or5 && (rail == 1) && (type == 0))
1152 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1153 if (core2or5 && (rail == 0) && (type == 0))
1154 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1155 if (core2or5 && (rail == 1) && (type == 0))
1156 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1157 if (core1or5 && (rail == 0) && (type == 1))
1158 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1159 if (core1or5 && (rail == 1) && (type == 1))
1160 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1161 if (core2or5 && (rail == 0) && (type == 1))
1162 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1163 if (core2or5 && (rail == 1) && (type == 1))
1164 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1165 if (core1or5 && (rail == 0) && (type == 6))
1166 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1167 if (core1or5 && (rail == 1) && (type == 6))
1168 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1169 if (core2or5 && (rail == 0) && (type == 6))
1170 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1171 if (core2or5 && (rail == 1) && (type == 6))
1172 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1173 if (core1or5 && (rail == 0) && (type == 3))
1174 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1175 if (core1or5 && (rail == 1) && (type == 3))
1176 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1177 if (core2or5 && (rail == 0) && (type == 3))
1178 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1179 if (core2or5 && (rail == 1) && (type == 3))
1180 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1181 if (core1or5 && (type == 4))
1182 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1183 if (core2or5 && (type == 4))
1184 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1185 if (core1or5 && (type == 5))
1186 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1187 if (core2or5 && (type == 5))
1188 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1189}
1190
1191/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1192static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1193{
1194 u16 val;
1195
1196 if (dev->phy.rev >= 3) {
1197 /* TODO */
1198 } else {
1199 if (type < 3)
1200 val = 0;
1201 else if (type == 6)
1202 val = 1;
1203 else if (type == 3)
1204 val = 2;
1205 else
1206 val = 3;
1207
1208 val = (val << 12) | (val << 14);
1209 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1210 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1211
1212 if (type < 3) {
1213 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1214 (type + 1) << 4);
1215 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1216 (type + 1) << 4);
1217 }
1218
1219 /* TODO use some definitions */
1220 if (code == 0) {
1221 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1222 if (type < 3) {
1223 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1224 0xFEC7, 0);
1225 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1226 0xEFDC, 0);
1227 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1228 0xFFFE, 0);
1229 udelay(20);
1230 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1231 0xFFFE, 0);
1232 }
1233 } else {
1234 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1235 0x3000);
1236 if (type < 3) {
1237 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1238 0xFEC7, 0x0180);
1239 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1240 0xEFDC, (code << 1 | 0x1021));
1241 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1242 0xFFFE, 0x0001);
1243 udelay(20);
1244 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1245 0xFFFE, 0);
1246 }
1247 }
1248 }
1249}
1250
Rafał Miłeckidfb4aa52010-01-15 14:45:13 +01001251/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1252static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1253{
1254 int i;
1255 for (i = 0; i < 2; i++) {
1256 if (type == 2) {
1257 if (i == 0) {
1258 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1259 0xFC, buf[0]);
1260 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1261 0xFC, buf[1]);
1262 } else {
1263 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1264 0xFC, buf[2 * i]);
1265 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1266 0xFC, buf[2 * i + 1]);
1267 }
1268 } else {
1269 if (i == 0)
1270 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1271 0xF3, buf[0] << 2);
1272 else
1273 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1274 0xF3, buf[2 * i + 1] << 2);
1275 }
1276 }
1277}
1278
1279/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1280static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1281 u8 nsamp)
1282{
1283 int i;
1284 int out;
1285 u16 save_regs_phy[9];
1286 u16 s[2];
1287
1288 if (dev->phy.rev >= 3) {
1289 save_regs_phy[0] = b43_phy_read(dev,
1290 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1291 save_regs_phy[1] = b43_phy_read(dev,
1292 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1293 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1294 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1295 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1296 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1297 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1298 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1299 }
1300
1301 b43_nphy_rssi_select(dev, 5, type);
1302
1303 if (dev->phy.rev < 2) {
1304 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1305 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1306 }
1307
1308 for (i = 0; i < 4; i++)
1309 buf[i] = 0;
1310
1311 for (i = 0; i < nsamp; i++) {
1312 if (dev->phy.rev < 2) {
1313 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1314 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1315 } else {
1316 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1317 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1318 }
1319
1320 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1321 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1322 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1323 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1324 }
1325 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1326 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1327
1328 if (dev->phy.rev < 2)
1329 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1330
1331 if (dev->phy.rev >= 3) {
1332 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1333 save_regs_phy[0]);
1334 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1335 save_regs_phy[1]);
1336 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1337 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1338 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1339 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1340 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1341 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1342 }
1343
1344 return out;
1345}
1346
Rafał Miłecki4cb99772010-01-15 13:40:58 +01001347/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1348static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
Michael Buesch95b66ba2008-01-18 01:09:25 +01001349{
Rafał Miłecki90b97382010-01-15 14:48:21 +01001350 int i, j;
1351 u8 state[4];
1352 u8 code, val;
1353 u16 class, override;
1354 u8 regs_save_radio[2];
1355 u16 regs_save_phy[2];
1356 s8 offset[4];
1357
1358 u16 clip_state[2];
1359 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1360 s32 results_min[4] = { };
1361 u8 vcm_final[4] = { };
1362 s32 results[4][4] = { };
1363 s32 miniq[4][2] = { };
1364
1365 if (type == 2) {
1366 code = 0;
1367 val = 6;
1368 } else if (type < 2) {
1369 code = 25;
1370 val = 4;
1371 } else {
1372 B43_WARN_ON(1);
1373 return;
1374 }
1375
1376 class = b43_nphy_classifier(dev, 0, 0);
1377 b43_nphy_classifier(dev, 7, 4);
1378 b43_nphy_read_clip_detection(dev, clip_state);
1379 b43_nphy_write_clip_detection(dev, clip_off);
1380
1381 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1382 override = 0x140;
1383 else
1384 override = 0x110;
1385
1386 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1387 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1388 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1389 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1390
1391 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1392 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1393 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1394 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1395
1396 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1397 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1398 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1399 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1400 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1401 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1402
1403 b43_nphy_rssi_select(dev, 5, type);
1404 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1405 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1406
1407 for (i = 0; i < 4; i++) {
1408 u8 tmp[4];
1409 for (j = 0; j < 4; j++)
1410 tmp[j] = i;
1411 if (type != 1)
1412 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1413 b43_nphy_poll_rssi(dev, type, results[i], 8);
1414 if (type < 2)
1415 for (j = 0; j < 2; j++)
1416 miniq[i][j] = min(results[i][2 * j],
1417 results[i][2 * j + 1]);
1418 }
1419
1420 for (i = 0; i < 4; i++) {
1421 s32 mind = 40;
1422 u8 minvcm = 0;
1423 s32 minpoll = 249;
1424 s32 curr;
1425 for (j = 0; j < 4; j++) {
1426 if (type == 2)
1427 curr = abs(results[j][i]);
1428 else
1429 curr = abs(miniq[j][i / 2] - code * 8);
1430
1431 if (curr < mind) {
1432 mind = curr;
1433 minvcm = j;
1434 }
1435
1436 if (results[j][i] < minpoll)
1437 minpoll = results[j][i];
1438 }
1439 results_min[i] = minpoll;
1440 vcm_final[i] = minvcm;
1441 }
1442
1443 if (type != 1)
1444 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1445
1446 for (i = 0; i < 4; i++) {
1447 offset[i] = (code * 8) - results[vcm_final[i]][i];
1448
1449 if (offset[i] < 0)
1450 offset[i] = -((abs(offset[i]) + 4) / 8);
1451 else
1452 offset[i] = (offset[i] + 4) / 8;
1453
1454 if (results_min[i] == 248)
1455 offset[i] = code - 32;
1456
1457 if (i % 2 == 0)
1458 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1459 type);
1460 else
1461 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1462 type);
1463 }
1464
1465 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1466 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1467
1468 switch (state[2]) {
1469 case 1:
1470 b43_nphy_rssi_select(dev, 1, 2);
1471 break;
1472 case 4:
1473 b43_nphy_rssi_select(dev, 1, 0);
1474 break;
1475 case 2:
1476 b43_nphy_rssi_select(dev, 1, 1);
1477 break;
1478 default:
1479 b43_nphy_rssi_select(dev, 1, 1);
1480 break;
1481 }
1482
1483 switch (state[3]) {
1484 case 1:
1485 b43_nphy_rssi_select(dev, 2, 2);
1486 break;
1487 case 4:
1488 b43_nphy_rssi_select(dev, 2, 0);
1489 break;
1490 default:
1491 b43_nphy_rssi_select(dev, 2, 1);
1492 break;
1493 }
1494
1495 b43_nphy_rssi_select(dev, 0, type);
1496
1497 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1498 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1499 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1500 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1501
1502 b43_nphy_classifier(dev, 7, class);
1503 b43_nphy_write_clip_detection(dev, clip_state);
Rafał Miłecki4cb99772010-01-15 13:40:58 +01001504}
1505
1506/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1507static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1508{
1509 /* TODO */
1510}
1511
1512/*
1513 * RSSI Calibration
1514 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1515 */
1516static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1517{
1518 if (dev->phy.rev >= 3) {
1519 b43_nphy_rev3_rssi_cal(dev);
1520 } else {
1521 b43_nphy_rev2_rssi_cal(dev, 2);
1522 b43_nphy_rev2_rssi_cal(dev, 0);
1523 b43_nphy_rev2_rssi_cal(dev, 1);
1524 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01001525}
1526
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01001527/*
Rafał Miłecki42e15472010-01-15 15:06:47 +01001528 * Restore RSSI Calibration
1529 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1530 */
1531static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1532{
1533 struct b43_phy_n *nphy = dev->phy.n;
1534
1535 u16 *rssical_radio_regs = NULL;
1536 u16 *rssical_phy_regs = NULL;
1537
1538 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1539 if (!nphy->rssical_chanspec_2G)
1540 return;
1541 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1542 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1543 } else {
1544 if (!nphy->rssical_chanspec_5G)
1545 return;
1546 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1547 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1548 }
1549
1550 /* TODO use some definitions */
1551 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1552 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1553
1554 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1555 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1556 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1557 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1558
1559 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1560 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1561 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1562 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1563
1564 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1565 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1566 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1567 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1568}
1569
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001570/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1571static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1572{
1573 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1574 if (dev->phy.rev >= 6) {
1575 /* TODO If the chip is 47162
1576 return txpwrctrl_tx_gain_ipa_rev5 */
1577 return txpwrctrl_tx_gain_ipa_rev6;
1578 } else if (dev->phy.rev >= 5) {
1579 return txpwrctrl_tx_gain_ipa_rev5;
1580 } else {
1581 return txpwrctrl_tx_gain_ipa;
1582 }
1583 } else {
1584 return txpwrctrl_tx_gain_ipa_5g;
1585 }
1586}
1587
Rafał Miłeckic4a92002010-01-15 15:55:18 +01001588/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1589static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1590{
1591 struct b43_phy_n *nphy = dev->phy.n;
1592 u16 *save = nphy->tx_rx_cal_radio_saveregs;
1593
1594 if (dev->phy.rev >= 3) {
1595 /* TODO */
1596 } else {
1597 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1598 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1599
1600 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1601 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1602
1603 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1604 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1605
1606 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1607 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1608
1609 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1610 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1611
1612 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1613 B43_NPHY_BANDCTL_5GHZ)) {
1614 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1615 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1616 } else {
1617 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1618 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1619 }
1620
1621 if (dev->phy.rev < 2) {
1622 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1623 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1624 } else {
1625 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1626 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1627 }
1628 }
1629}
1630
Rafał Miłeckie9762492010-01-15 16:08:25 +01001631/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1632static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1633 struct nphy_txgains target,
1634 struct nphy_iqcal_params *params)
1635{
1636 int i, j, indx;
1637 u16 gain;
1638
1639 if (dev->phy.rev >= 3) {
1640 params->txgm = target.txgm[core];
1641 params->pga = target.pga[core];
1642 params->pad = target.pad[core];
1643 params->ipa = target.ipa[core];
1644 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1645 (params->pad << 4) | (params->ipa);
1646 for (j = 0; j < 5; j++)
1647 params->ncorr[j] = 0x79;
1648 } else {
1649 gain = (target.pad[core]) | (target.pga[core] << 4) |
1650 (target.txgm[core] << 8);
1651
1652 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1653 1 : 0;
1654 for (i = 0; i < 9; i++)
1655 if (tbl_iqcal_gainparams[indx][i][0] == gain)
1656 break;
1657 i = min(i, 8);
1658
1659 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1660 params->pga = tbl_iqcal_gainparams[indx][i][2];
1661 params->pad = tbl_iqcal_gainparams[indx][i][3];
1662 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1663 (params->pad << 2);
1664 for (j = 0; j < 4; j++)
1665 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1666 }
1667}
1668
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +01001669/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1670static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1671{
1672 struct b43_phy_n *nphy = dev->phy.n;
1673 int i;
1674 u16 scale, entry;
1675
1676 u16 tmp = nphy->txcal_bbmult;
1677 if (core == 0)
1678 tmp >>= 8;
1679 tmp &= 0xff;
1680
1681 for (i = 0; i < 18; i++) {
1682 scale = (ladder_lo[i].percent * tmp) / 100;
1683 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001684 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +01001685
1686 scale = (ladder_iq[i].percent * tmp) / 100;
1687 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001688 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +01001689 }
1690}
1691
Rafał Miłecki45ca6972010-01-22 01:53:15 +01001692/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
1693static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
1694{
1695 int i;
1696 for (i = 0; i < 15; i++)
1697 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
1698 tbl_tx_filter_coef_rev4[2][i]);
1699}
1700
1701/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
1702static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
1703{
1704 int i, j;
1705 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
1706 u16 offset[] = { 0x186, 0x195, 0x2C5 };
1707
1708 for (i = 0; i < 3; i++)
1709 for (j = 0; j < 15; j++)
1710 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
1711 tbl_tx_filter_coef_rev4[i][j]);
1712
1713 if (dev->phy.is_40mhz) {
1714 for (j = 0; j < 15; j++)
1715 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
1716 tbl_tx_filter_coef_rev4[3][j]);
1717 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1718 for (j = 0; j < 15; j++)
1719 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
1720 tbl_tx_filter_coef_rev4[5][j]);
1721 }
1722
1723 if (dev->phy.channel == 14)
1724 for (j = 0; j < 15; j++)
1725 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
1726 tbl_tx_filter_coef_rev4[6][j]);
1727}
1728
Rafał Miłeckib0022e12010-01-15 15:40:50 +01001729/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1730static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1731{
1732 struct b43_phy_n *nphy = dev->phy.n;
1733
1734 u16 curr_gain[2];
1735 struct nphy_txgains target;
1736 const u32 *table = NULL;
1737
1738 if (nphy->txpwrctrl == 0) {
1739 int i;
1740
1741 if (nphy->hang_avoid)
1742 b43_nphy_stay_in_carrier_search(dev, true);
Rafał Miłecki91458342010-01-18 00:21:35 +01001743 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
Rafał Miłeckib0022e12010-01-15 15:40:50 +01001744 if (nphy->hang_avoid)
1745 b43_nphy_stay_in_carrier_search(dev, false);
1746
1747 for (i = 0; i < 2; ++i) {
1748 if (dev->phy.rev >= 3) {
1749 target.ipa[i] = curr_gain[i] & 0x000F;
1750 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1751 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1752 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1753 } else {
1754 target.ipa[i] = curr_gain[i] & 0x0003;
1755 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1756 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1757 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1758 }
1759 }
1760 } else {
1761 int i;
1762 u16 index[2];
1763 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1764 B43_NPHY_TXPCTL_STAT_BIDX) >>
1765 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1766 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1767 B43_NPHY_TXPCTL_STAT_BIDX) >>
1768 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1769
1770 for (i = 0; i < 2; ++i) {
1771 if (dev->phy.rev >= 3) {
1772 enum ieee80211_band band =
1773 b43_current_band(dev->wl);
1774
1775 if ((nphy->ipa2g_on &&
1776 band == IEEE80211_BAND_2GHZ) ||
1777 (nphy->ipa5g_on &&
1778 band == IEEE80211_BAND_5GHZ)) {
1779 table = b43_nphy_get_ipa_gain_table(dev);
1780 } else {
1781 if (band == IEEE80211_BAND_5GHZ) {
1782 if (dev->phy.rev == 3)
1783 table = b43_ntab_tx_gain_rev3_5ghz;
1784 else if (dev->phy.rev == 4)
1785 table = b43_ntab_tx_gain_rev4_5ghz;
1786 else
1787 table = b43_ntab_tx_gain_rev5plus_5ghz;
1788 } else {
1789 table = b43_ntab_tx_gain_rev3plus_2ghz;
1790 }
1791 }
1792
1793 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1794 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1795 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1796 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1797 } else {
1798 table = b43_ntab_tx_gain_rev0_1_2;
1799
1800 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1801 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1802 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1803 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1804 }
1805 }
1806 }
1807
1808 return target;
1809}
1810
Rafał Miłeckie53de672010-01-17 13:03:32 +01001811/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1812static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1813{
1814 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1815
1816 if (dev->phy.rev >= 3) {
1817 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1818 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1819 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1820 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1821 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001822 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
1823 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001824 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1825 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1826 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1827 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1828 b43_nphy_reset_cca(dev);
1829 } else {
1830 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1831 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1832 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001833 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
1834 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001835 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1836 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1837 }
1838}
1839
1840/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1841static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1842{
1843 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1844 u16 tmp;
1845
1846 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1847 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1848 if (dev->phy.rev >= 3) {
1849 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1850 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1851
1852 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1853 regs[2] = tmp;
1854 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1855
1856 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1857 regs[3] = tmp;
1858 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1859
1860 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
Rafał Miłeckide9a47f2010-01-18 00:21:49 +01001861 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001862
Rafał Miłeckic643a662010-01-18 00:21:27 +01001863 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001864 regs[5] = tmp;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001865 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
Rafał Miłeckic643a662010-01-18 00:21:27 +01001866
1867 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001868 regs[6] = tmp;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001869 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001870 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1871 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1872
1873 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1874 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1875 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1876
1877 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1878 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1879 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1880 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1881 } else {
1882 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1883 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1884 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1885 regs[2] = tmp;
1886 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
Rafał Miłeckic643a662010-01-18 00:21:27 +01001887 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001888 regs[3] = tmp;
1889 tmp |= 0x2000;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001890 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
Rafał Miłeckic643a662010-01-18 00:21:27 +01001891 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001892 regs[4] = tmp;
1893 tmp |= 0x2000;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001894 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001895 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1896 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1897 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1898 tmp = 0x0180;
1899 else
1900 tmp = 0x0120;
1901 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1902 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1903 }
1904}
1905
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001906/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1907static void b43_nphy_restore_cal(struct b43_wldev *dev)
1908{
1909 struct b43_phy_n *nphy = dev->phy.n;
1910
1911 u16 coef[4];
1912 u16 *loft = NULL;
1913 u16 *table = NULL;
1914
1915 int i;
1916 u16 *txcal_radio_regs = NULL;
1917 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1918
1919 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1920 if (nphy->iqcal_chanspec_2G == 0)
1921 return;
1922 table = nphy->cal_cache.txcal_coeffs_2G;
1923 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1924 } else {
1925 if (nphy->iqcal_chanspec_5G == 0)
1926 return;
1927 table = nphy->cal_cache.txcal_coeffs_5G;
1928 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1929 }
1930
Rafał Miłecki2581b142010-01-18 00:21:21 +01001931 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001932
1933 for (i = 0; i < 4; i++) {
1934 if (dev->phy.rev >= 3)
1935 table[i] = coef[i];
1936 else
1937 coef[i] = 0;
1938 }
1939
Rafał Miłecki2581b142010-01-18 00:21:21 +01001940 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
1941 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
1942 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001943
1944 if (dev->phy.rev < 2)
1945 b43_nphy_tx_iq_workaround(dev);
1946
1947 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1948 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1949 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1950 } else {
1951 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1952 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1953 }
1954
1955 /* TODO use some definitions */
1956 if (dev->phy.rev >= 3) {
1957 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1958 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1959 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1960 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1961 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1962 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1963 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1964 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1965 } else {
1966 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1967 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1968 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1969 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1970 }
1971 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1972}
1973
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001974/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1975static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1976 struct nphy_txgains target,
1977 bool full, bool mphase)
1978{
1979 struct b43_phy_n *nphy = dev->phy.n;
1980 int i;
1981 int error = 0;
1982 int freq;
1983 bool avoid = false;
1984 u8 length;
1985 u16 tmp, core, type, count, max, numb, last, cmd;
1986 const u16 *table;
1987 bool phy6or5x;
1988
1989 u16 buffer[11];
1990 u16 diq_start = 0;
1991 u16 save[2];
1992 u16 gain[2];
1993 struct nphy_iqcal_params params[2];
1994 bool updated[2] = { };
1995
1996 b43_nphy_stay_in_carrier_search(dev, true);
1997
1998 if (dev->phy.rev >= 4) {
1999 avoid = nphy->hang_avoid;
2000 nphy->hang_avoid = 0;
2001 }
2002
Rafał Miłecki91458342010-01-18 00:21:35 +01002003 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002004
2005 for (i = 0; i < 2; i++) {
2006 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2007 gain[i] = params[i].cal_gain;
2008 }
Rafał Miłecki2581b142010-01-18 00:21:21 +01002009
2010 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002011
2012 b43_nphy_tx_cal_radio_setup(dev);
Rafał Miłeckie53de672010-01-17 13:03:32 +01002013 b43_nphy_tx_cal_phy_setup(dev);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002014
2015 phy6or5x = dev->phy.rev >= 6 ||
2016 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2017 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2018 if (phy6or5x) {
2019 /* TODO */
2020 }
2021
2022 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2023
Rafał Miłeckiaa4c7b22010-01-22 01:53:12 +01002024 if (!dev->phy.is_40mhz)
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002025 freq = 2500;
2026 else
2027 freq = 5000;
2028
2029 if (nphy->mphase_cal_phase_id > 2)
Rafał Miłecki10a79872010-01-22 01:53:14 +01002030 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2031 0xFFFF, 0, true, false);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002032 else
Rafał Miłecki59af0992010-01-22 01:53:16 +01002033 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002034
2035 if (error == 0) {
2036 if (nphy->mphase_cal_phase_id > 2) {
2037 table = nphy->mphase_txcal_bestcoeffs;
2038 length = 11;
2039 if (dev->phy.rev < 3)
2040 length -= 2;
2041 } else {
2042 if (!full && nphy->txiqlocal_coeffsvalid) {
2043 table = nphy->txiqlocal_bestc;
2044 length = 11;
2045 if (dev->phy.rev < 3)
2046 length -= 2;
2047 } else {
2048 full = true;
2049 if (dev->phy.rev >= 3) {
2050 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2051 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2052 } else {
2053 table = tbl_tx_iqlo_cal_startcoefs;
2054 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2055 }
2056 }
2057 }
2058
Rafał Miłecki2581b142010-01-18 00:21:21 +01002059 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002060
2061 if (full) {
2062 if (dev->phy.rev >= 3)
2063 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2064 else
2065 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2066 } else {
2067 if (dev->phy.rev >= 3)
2068 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2069 else
2070 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2071 }
2072
2073 if (mphase) {
2074 count = nphy->mphase_txcal_cmdidx;
2075 numb = min(max,
2076 (u16)(count + nphy->mphase_txcal_numcmds));
2077 } else {
2078 count = 0;
2079 numb = max;
2080 }
2081
2082 for (; count < numb; count++) {
2083 if (full) {
2084 if (dev->phy.rev >= 3)
2085 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2086 else
2087 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2088 } else {
2089 if (dev->phy.rev >= 3)
2090 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2091 else
2092 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2093 }
2094
2095 core = (cmd & 0x3000) >> 12;
2096 type = (cmd & 0x0F00) >> 8;
2097
2098 if (phy6or5x && updated[core] == 0) {
2099 b43_nphy_update_tx_cal_ladder(dev, core);
2100 updated[core] = 1;
2101 }
2102
2103 tmp = (params[core].ncorr[type] << 8) | 0x66;
2104 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2105
2106 if (type == 1 || type == 3 || type == 4) {
Rafał Miłeckic643a662010-01-18 00:21:27 +01002107 buffer[0] = b43_ntab_read(dev,
2108 B43_NTAB16(15, 69 + core));
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002109 diq_start = buffer[0];
2110 buffer[0] = 0;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01002111 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2112 0);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002113 }
2114
2115 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2116 for (i = 0; i < 2000; i++) {
2117 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2118 if (tmp & 0xC000)
2119 break;
2120 udelay(10);
2121 }
2122
Rafał Miłecki91458342010-01-18 00:21:35 +01002123 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2124 buffer);
Rafał Miłecki2581b142010-01-18 00:21:21 +01002125 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2126 buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002127
2128 if (type == 1 || type == 3 || type == 4)
2129 buffer[0] = diq_start;
2130 }
2131
2132 if (mphase)
2133 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2134
2135 last = (dev->phy.rev < 3) ? 6 : 7;
2136
2137 if (!mphase || nphy->mphase_cal_phase_id == last) {
Rafał Miłecki2581b142010-01-18 00:21:21 +01002138 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
Rafał Miłecki91458342010-01-18 00:21:35 +01002139 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002140 if (dev->phy.rev < 3) {
2141 buffer[0] = 0;
2142 buffer[1] = 0;
2143 buffer[2] = 0;
2144 buffer[3] = 0;
2145 }
Rafał Miłecki2581b142010-01-18 00:21:21 +01002146 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2147 buffer);
2148 b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2149 buffer);
2150 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2151 buffer);
2152 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2153 buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002154 length = 11;
2155 if (dev->phy.rev < 3)
2156 length -= 2;
Rafał Miłecki91458342010-01-18 00:21:35 +01002157 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2158 nphy->txiqlocal_bestc);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002159 nphy->txiqlocal_coeffsvalid = true;
2160 /* TODO: Set nphy->txiqlocal_chanspec to
2161 the current channel */
2162 } else {
2163 length = 11;
2164 if (dev->phy.rev < 3)
2165 length -= 2;
Rafał Miłecki91458342010-01-18 00:21:35 +01002166 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2167 nphy->mphase_txcal_bestcoeffs);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002168 }
2169
Rafał Miłecki53ae8e82010-01-17 13:03:48 +01002170 b43_nphy_stop_playback(dev);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002171 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2172 }
2173
Rafał Miłeckie53de672010-01-17 13:03:32 +01002174 b43_nphy_tx_cal_phy_cleanup(dev);
Rafał Miłecki2581b142010-01-18 00:21:21 +01002175 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002176
2177 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2178 b43_nphy_tx_iq_workaround(dev);
2179
2180 if (dev->phy.rev >= 4)
2181 nphy->hang_avoid = avoid;
2182
2183 b43_nphy_stay_in_carrier_search(dev, false);
2184
2185 return error;
2186}
2187
Rafał Miłecki15931e32010-01-15 16:20:56 +01002188/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2189static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2190 struct nphy_txgains target, u8 type, bool debug)
2191{
2192 struct b43_phy_n *nphy = dev->phy.n;
2193 int i, j, index;
2194 u8 rfctl[2];
2195 u8 afectl_core;
2196 u16 tmp[6];
2197 u16 cur_hpf1, cur_hpf2, cur_lna;
2198 u32 real, imag;
2199 enum ieee80211_band band;
2200
2201 u8 use;
2202 u16 cur_hpf;
2203 u16 lna[3] = { 3, 3, 1 };
2204 u16 hpf1[3] = { 7, 2, 0 };
2205 u16 hpf2[3] = { 2, 0, 0 };
Rafał Miłeckide9a47f2010-01-18 00:21:49 +01002206 u32 power[3] = { };
Rafał Miłecki15931e32010-01-15 16:20:56 +01002207 u16 gain_save[2];
2208 u16 cal_gain[2];
2209 struct nphy_iqcal_params cal_params[2];
2210 struct nphy_iq_est est;
2211 int ret = 0;
2212 bool playtone = true;
2213 int desired = 13;
2214
2215 b43_nphy_stay_in_carrier_search(dev, 1);
2216
2217 if (dev->phy.rev < 2)
2218 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
Rafał Miłecki91458342010-01-18 00:21:35 +01002219 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002220 for (i = 0; i < 2; i++) {
2221 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2222 cal_gain[i] = cal_params[i].cal_gain;
2223 }
Rafał Miłecki2581b142010-01-18 00:21:21 +01002224 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002225
2226 for (i = 0; i < 2; i++) {
2227 if (i == 0) {
2228 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2229 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2230 afectl_core = B43_NPHY_AFECTL_C1;
2231 } else {
2232 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2233 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2234 afectl_core = B43_NPHY_AFECTL_C2;
2235 }
2236
2237 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2238 tmp[2] = b43_phy_read(dev, afectl_core);
2239 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2240 tmp[4] = b43_phy_read(dev, rfctl[0]);
2241 tmp[5] = b43_phy_read(dev, rfctl[1]);
2242
2243 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2244 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2245 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2246 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2247 (1 - i));
2248 b43_phy_set(dev, afectl_core, 0x0006);
2249 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2250
2251 band = b43_current_band(dev->wl);
2252
2253 if (nphy->rxcalparams & 0xFF000000) {
2254 if (band == IEEE80211_BAND_5GHZ)
2255 b43_phy_write(dev, rfctl[0], 0x140);
2256 else
2257 b43_phy_write(dev, rfctl[0], 0x110);
2258 } else {
2259 if (band == IEEE80211_BAND_5GHZ)
2260 b43_phy_write(dev, rfctl[0], 0x180);
2261 else
2262 b43_phy_write(dev, rfctl[0], 0x120);
2263 }
2264
2265 if (band == IEEE80211_BAND_5GHZ)
2266 b43_phy_write(dev, rfctl[1], 0x148);
2267 else
2268 b43_phy_write(dev, rfctl[1], 0x114);
2269
2270 if (nphy->rxcalparams & 0x10000) {
2271 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2272 (i + 1));
2273 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2274 (2 - i));
2275 }
2276
2277 for (j = 0; i < 4; j++) {
2278 if (j < 3) {
2279 cur_lna = lna[j];
2280 cur_hpf1 = hpf1[j];
2281 cur_hpf2 = hpf2[j];
2282 } else {
2283 if (power[1] > 10000) {
2284 use = 1;
2285 cur_hpf = cur_hpf1;
2286 index = 2;
2287 } else {
2288 if (power[0] > 10000) {
2289 use = 1;
2290 cur_hpf = cur_hpf1;
2291 index = 1;
2292 } else {
2293 index = 0;
2294 use = 2;
2295 cur_hpf = cur_hpf2;
2296 }
2297 }
2298 cur_lna = lna[index];
2299 cur_hpf1 = hpf1[index];
2300 cur_hpf2 = hpf2[index];
2301 cur_hpf += desired - hweight32(power[index]);
2302 cur_hpf = clamp_val(cur_hpf, 0, 10);
2303 if (use == 1)
2304 cur_hpf1 = cur_hpf;
2305 else
2306 cur_hpf2 = cur_hpf;
2307 }
2308
2309 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2310 (cur_lna << 2));
Rafał Miłecki75377b22010-01-22 01:53:13 +01002311 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2312 false);
Rafał Miłeckide9a47f2010-01-18 00:21:49 +01002313 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +01002314 b43_nphy_stop_playback(dev);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002315
2316 if (playtone) {
Rafał Miłecki59af0992010-01-22 01:53:16 +01002317 ret = b43_nphy_tx_tone(dev, 4000,
2318 (nphy->rxcalparams & 0xFFFF),
2319 false, false);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002320 playtone = false;
2321 } else {
Rafał Miłecki10a79872010-01-22 01:53:14 +01002322 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2323 false, false);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002324 }
2325
2326 if (ret == 0) {
2327 if (j < 3) {
2328 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2329 false);
2330 if (i == 0) {
2331 real = est.i0_pwr;
2332 imag = est.q0_pwr;
2333 } else {
2334 real = est.i1_pwr;
2335 imag = est.q1_pwr;
2336 }
2337 power[i] = ((real + imag) / 1024) + 1;
2338 } else {
2339 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2340 }
Rafał Miłecki53ae8e82010-01-17 13:03:48 +01002341 b43_nphy_stop_playback(dev);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002342 }
2343
2344 if (ret != 0)
2345 break;
2346 }
2347
2348 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2349 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2350 b43_phy_write(dev, rfctl[1], tmp[5]);
2351 b43_phy_write(dev, rfctl[0], tmp[4]);
2352 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2353 b43_phy_write(dev, afectl_core, tmp[2]);
2354 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2355
2356 if (ret != 0)
2357 break;
2358 }
2359
Rafał Miłecki75377b22010-01-22 01:53:13 +01002360 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +01002361 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłecki2581b142010-01-18 00:21:21 +01002362 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002363
2364 b43_nphy_stay_in_carrier_search(dev, 0);
2365
2366 return ret;
2367}
2368
2369static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2370 struct nphy_txgains target, u8 type, bool debug)
2371{
2372 return -1;
2373}
2374
2375/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2376static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2377 struct nphy_txgains target, u8 type, bool debug)
2378{
2379 if (dev->phy.rev >= 3)
2380 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2381 else
2382 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2383}
2384
Rafał Miłecki42e15472010-01-15 15:06:47 +01002385/*
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002386 * Init N-PHY
2387 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2388 */
Michael Buesch424047e2008-01-09 16:13:56 +01002389int b43_phy_initn(struct b43_wldev *dev)
2390{
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002391 struct ssb_bus *bus = dev->dev->bus;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002392 struct b43_phy *phy = &dev->phy;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002393 struct b43_phy_n *nphy = phy->n;
2394 u8 tx_pwr_state;
2395 struct nphy_txgains target;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002396 u16 tmp;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002397 enum ieee80211_band tmp2;
2398 bool do_rssi_cal;
Michael Buesch424047e2008-01-09 16:13:56 +01002399
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002400 u16 clip[2];
2401 bool do_cal = false;
2402
2403 if ((dev->phy.rev >= 3) &&
2404 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2405 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2406 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2407 }
2408 nphy->deaf_count = 0;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002409 b43_nphy_tables_init(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002410 nphy->crsminpwr_adjusted = false;
2411 nphy->noisevars_adjusted = false;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002412
2413 /* Clear all overrides */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002414 if (dev->phy.rev >= 3) {
2415 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2416 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2417 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2418 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2419 } else {
2420 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2421 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002422 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2423 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002424 if (dev->phy.rev < 6) {
2425 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2426 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2427 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002428 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2429 ~(B43_NPHY_RFSEQMODE_CAOVER |
2430 B43_NPHY_RFSEQMODE_TROVER));
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002431 if (dev->phy.rev >= 3)
2432 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002433 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2434
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002435 if (dev->phy.rev <= 2) {
2436 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2437 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2438 ~B43_NPHY_BPHY_CTL3_SCALE,
2439 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2440 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002441 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2442 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2443
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002444 if (bus->sprom.boardflags2_lo & 0x100 ||
2445 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2446 bus->boardinfo.type == 0x8B))
2447 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2448 else
2449 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2450 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2451 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2452 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002453
Rafał Miłeckiad9716e2010-01-17 13:03:40 +01002454 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
Rafał Miłecki4f4ab6c2010-01-17 13:03:55 +01002455 b43_nphy_update_txrx_chain(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002456
2457 if (phy->rev < 2) {
2458 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2459 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2460 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002461
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002462 tmp2 = b43_current_band(dev->wl);
2463 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2464 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2465 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2466 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2467 nphy->papd_epsilon_offset[0] << 7);
2468 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2469 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2470 nphy->papd_epsilon_offset[1] << 7);
Rafał Miłecki45ca6972010-01-22 01:53:15 +01002471 b43_nphy_int_pa_set_tx_dig_filters(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002472 } else if (phy->rev >= 5) {
Rafał Miłecki45ca6972010-01-22 01:53:15 +01002473 b43_nphy_ext_pa_set_tx_dig_filters(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002474 }
2475
2476 b43_nphy_workarounds(dev);
2477
2478 /* Reset CCA, in init code it differs a little from standard way */
Rafał Miłecki730dd702010-01-15 16:38:07 +01002479 b43_nphy_bmac_clock_fgc(dev, 1);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002480 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2481 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2482 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
Rafał Miłecki730dd702010-01-15 16:38:07 +01002483 b43_nphy_bmac_clock_fgc(dev, 0);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002484
2485 /* TODO N PHY MAC PHY Clock Set with argument 1 */
2486
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +01002487 b43_nphy_pa_override(dev, false);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002488 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2489 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +01002490 b43_nphy_pa_override(dev, true);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002491
Rafał Miłeckibbec3982010-01-15 14:31:39 +01002492 b43_nphy_classifier(dev, 0, 0);
2493 b43_nphy_read_clip_detection(dev, clip);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002494 tx_pwr_state = nphy->txpwrctrl;
2495 /* TODO N PHY TX power control with argument 0
2496 (turning off power control) */
2497 /* TODO Fix the TX Power Settings */
2498 /* TODO N PHY TX Power Control Idle TSSI */
2499 /* TODO N PHY TX Power Control Setup */
Michael Buesch95b66ba2008-01-18 01:09:25 +01002500
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002501 if (phy->rev >= 3) {
2502 /* TODO */
2503 } else {
Rafał Miłecki2581b142010-01-18 00:21:21 +01002504 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
2505 b43_ntab_tx_gain_rev0_1_2);
2506 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
2507 b43_ntab_tx_gain_rev0_1_2);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002508 }
2509
2510 if (nphy->phyrxchain != 3)
2511 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2512 if (nphy->mphase_cal_phase_id > 0)
2513 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2514
2515 do_rssi_cal = false;
2516 if (phy->rev >= 3) {
2517 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2518 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2519 else
2520 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2521
2522 if (do_rssi_cal)
Rafał Miłecki4cb99772010-01-15 13:40:58 +01002523 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002524 else
Rafał Miłecki42e15472010-01-15 15:06:47 +01002525 b43_nphy_restore_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002526 } else {
Rafał Miłecki4cb99772010-01-15 13:40:58 +01002527 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002528 }
2529
2530 if (!((nphy->measure_hold & 0x6) != 0)) {
2531 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2532 do_cal = (nphy->iqcal_chanspec_2G == 0);
2533 else
2534 do_cal = (nphy->iqcal_chanspec_5G == 0);
2535
2536 if (nphy->mute)
2537 do_cal = false;
2538
2539 if (do_cal) {
Rafał Miłeckib0022e12010-01-15 15:40:50 +01002540 target = b43_nphy_get_tx_gains(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002541
2542 if (nphy->antsel_type == 2)
2543 ;/*TODO NPHY Superswitch Init with argument 1*/
2544 if (nphy->perical != 2) {
Rafał Miłecki90b97382010-01-15 14:48:21 +01002545 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002546 if (phy->rev >= 3) {
2547 nphy->cal_orig_pwr_idx[0] =
2548 nphy->txpwrindex[0].index_internal;
2549 nphy->cal_orig_pwr_idx[1] =
2550 nphy->txpwrindex[1].index_internal;
2551 /* TODO N PHY Pre Calibrate TX Gain */
Rafał Miłeckib0022e12010-01-15 15:40:50 +01002552 target = b43_nphy_get_tx_gains(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002553 }
2554 }
2555 }
2556 }
2557
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002558 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2559 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
Rafał Miłecki15931e32010-01-15 16:20:56 +01002560 ;/* Call N PHY Save Cal */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002561 else if (nphy->mphase_cal_phase_id == 0)
Rafał Miłecki15931e32010-01-15 16:20:56 +01002562 ;/* N PHY Periodic Calibration with argument 3 */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002563 } else {
2564 b43_nphy_restore_cal(dev);
2565 }
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002566
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +01002567 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002568 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2569 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2570 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2571 if (phy->rev >= 3 && phy->rev <= 6)
2572 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
Rafał Miłeckife3e46e2010-01-15 15:51:55 +01002573 b43_nphy_tx_lp_fbw(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002574 /* TODO N PHY Spur Workaround */
Michael Buesch95b66ba2008-01-18 01:09:25 +01002575
2576 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
Michael Buesch53a6e232008-01-13 21:23:44 +01002577 return 0;
Michael Buesch424047e2008-01-09 16:13:56 +01002578}
Michael Bueschef1a6282008-08-27 18:53:02 +02002579
2580static int b43_nphy_op_allocate(struct b43_wldev *dev)
2581{
2582 struct b43_phy_n *nphy;
2583
2584 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2585 if (!nphy)
2586 return -ENOMEM;
2587 dev->phy.n = nphy;
2588
Michael Bueschef1a6282008-08-27 18:53:02 +02002589 return 0;
2590}
2591
Michael Bueschfb111372008-09-02 13:00:34 +02002592static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
2593{
2594 struct b43_phy *phy = &dev->phy;
2595 struct b43_phy_n *nphy = phy->n;
2596
2597 memset(nphy, 0, sizeof(*nphy));
2598
2599 //TODO init struct b43_phy_n
2600}
2601
2602static void b43_nphy_op_free(struct b43_wldev *dev)
2603{
2604 struct b43_phy *phy = &dev->phy;
2605 struct b43_phy_n *nphy = phy->n;
2606
2607 kfree(nphy);
2608 phy->n = NULL;
2609}
2610
Michael Bueschef1a6282008-08-27 18:53:02 +02002611static int b43_nphy_op_init(struct b43_wldev *dev)
2612{
Michael Bueschfb111372008-09-02 13:00:34 +02002613 return b43_phy_initn(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +02002614}
2615
2616static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2617{
2618#if B43_DEBUG
2619 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2620 /* OFDM registers are onnly available on A/G-PHYs */
2621 b43err(dev->wl, "Invalid OFDM PHY access at "
2622 "0x%04X on N-PHY\n", offset);
2623 dump_stack();
2624 }
2625 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2626 /* Ext-G registers are only available on G-PHYs */
2627 b43err(dev->wl, "Invalid EXT-G PHY access at "
2628 "0x%04X on N-PHY\n", offset);
2629 dump_stack();
2630 }
2631#endif /* B43_DEBUG */
2632}
2633
2634static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2635{
2636 check_phyreg(dev, reg);
2637 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2638 return b43_read16(dev, B43_MMIO_PHY_DATA);
2639}
2640
2641static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2642{
2643 check_phyreg(dev, reg);
2644 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2645 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2646}
2647
2648static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2649{
2650 /* Register 1 is a 32-bit register. */
2651 B43_WARN_ON(reg == 1);
2652 /* N-PHY needs 0x100 for read access */
2653 reg |= 0x100;
2654
2655 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2656 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2657}
2658
2659static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2660{
2661 /* Register 1 is a 32-bit register. */
2662 B43_WARN_ON(reg == 1);
2663
2664 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2665 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2666}
2667
2668static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
Johannes Berg19d337d2009-06-02 13:01:37 +02002669 bool blocked)
Michael Bueschef1a6282008-08-27 18:53:02 +02002670{//TODO
2671}
2672
Michael Bueschcb24f572008-09-03 12:12:20 +02002673static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2674{
2675 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2676 on ? 0 : 0x7FFF);
2677}
2678
Michael Bueschef1a6282008-08-27 18:53:02 +02002679static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2680 unsigned int new_channel)
2681{
2682 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2683 if ((new_channel < 1) || (new_channel > 14))
2684 return -EINVAL;
2685 } else {
2686 if (new_channel > 200)
2687 return -EINVAL;
2688 }
2689
2690 return nphy_channel_switch(dev, new_channel);
2691}
2692
2693static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2694{
2695 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2696 return 1;
2697 return 36;
2698}
2699
Michael Bueschef1a6282008-08-27 18:53:02 +02002700const struct b43_phy_operations b43_phyops_n = {
2701 .allocate = b43_nphy_op_allocate,
Michael Bueschfb111372008-09-02 13:00:34 +02002702 .free = b43_nphy_op_free,
2703 .prepare_structs = b43_nphy_op_prepare_structs,
Michael Bueschef1a6282008-08-27 18:53:02 +02002704 .init = b43_nphy_op_init,
Michael Bueschef1a6282008-08-27 18:53:02 +02002705 .phy_read = b43_nphy_op_read,
2706 .phy_write = b43_nphy_op_write,
2707 .radio_read = b43_nphy_op_radio_read,
2708 .radio_write = b43_nphy_op_radio_write,
2709 .software_rfkill = b43_nphy_op_software_rfkill,
Michael Bueschcb24f572008-09-03 12:12:20 +02002710 .switch_analog = b43_nphy_op_switch_analog,
Michael Bueschef1a6282008-08-27 18:53:02 +02002711 .switch_channel = b43_nphy_op_switch_channel,
2712 .get_default_chan = b43_nphy_op_get_default_chan,
Michael Buesch18c8ade2008-08-28 19:33:40 +02002713 .recalc_txpower = b43_nphy_op_recalc_txpower,
2714 .adjust_txpower = b43_nphy_op_adjust_txpower,
Michael Bueschef1a6282008-08-27 18:53:02 +02002715};