Mauro Carvalho Chehab | 52707f9 | 2010-05-18 20:43:52 -0300 | [diff] [blame] | 1 | /* Intel i7 core/Nehalem Memory Controller kernel module |
| 2 | * |
| 3 | * This driver supports yhe memory controllers found on the Intel |
| 4 | * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx, |
| 5 | * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield |
| 6 | * and Westmere-EP. |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 7 | * |
| 8 | * This file may be distributed under the terms of the |
| 9 | * GNU General Public License version 2 only. |
| 10 | * |
Mauro Carvalho Chehab | 52707f9 | 2010-05-18 20:43:52 -0300 | [diff] [blame] | 11 | * Copyright (c) 2009-2010 by: |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 12 | * Mauro Carvalho Chehab <mchehab@redhat.com> |
| 13 | * |
| 14 | * Red Hat Inc. http://www.redhat.com |
| 15 | * |
| 16 | * Forked and adapted from the i5400_edac driver |
| 17 | * |
| 18 | * Based on the following public Intel datasheets: |
| 19 | * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor |
| 20 | * Datasheet, Volume 2: |
| 21 | * http://download.intel.com/design/processor/datashts/320835.pdf |
| 22 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 |
| 23 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf |
| 24 | * also available at: |
| 25 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
| 26 | */ |
| 27 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/pci_ids.h> |
| 32 | #include <linux/slab.h> |
Randy Dunlap | 3b918c1 | 2009-11-08 01:36:40 -0200 | [diff] [blame] | 33 | #include <linux/delay.h> |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 34 | #include <linux/edac.h> |
| 35 | #include <linux/mmzone.h> |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 36 | #include <linux/edac_mce.h> |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 37 | #include <linux/smp.h> |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 38 | #include <asm/processor.h> |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 39 | |
| 40 | #include "edac_core.h" |
| 41 | |
Mauro Carvalho Chehab | 18c2900 | 2010-08-10 18:33:27 -0300 | [diff] [blame] | 42 | /* Static vars */ |
| 43 | static LIST_HEAD(i7core_edac_list); |
| 44 | static DEFINE_MUTEX(i7core_edac_lock); |
| 45 | static int probed; |
| 46 | |
Mauro Carvalho Chehab | 54a08ab | 2010-08-19 15:51:00 -0300 | [diff] [blame] | 47 | static int use_pci_fixup; |
| 48 | module_param(use_pci_fixup, int, 0444); |
| 49 | MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices"); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 50 | /* |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 51 | * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core |
| 52 | * registers start at bus 255, and are not reported by BIOS. |
| 53 | * We currently find devices with only 2 sockets. In order to support more QPI |
| 54 | * Quick Path Interconnect, just increment this number. |
| 55 | */ |
| 56 | #define MAX_SOCKET_BUSES 2 |
| 57 | |
| 58 | |
| 59 | /* |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 60 | * Alter this version for the module when modifications are made |
| 61 | */ |
| 62 | #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__ |
| 63 | #define EDAC_MOD_STR "i7core_edac" |
| 64 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 65 | /* |
| 66 | * Debug macros |
| 67 | */ |
| 68 | #define i7core_printk(level, fmt, arg...) \ |
| 69 | edac_printk(level, "i7core", fmt, ##arg) |
| 70 | |
| 71 | #define i7core_mc_printk(mci, level, fmt, arg...) \ |
| 72 | edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg) |
| 73 | |
| 74 | /* |
| 75 | * i7core Memory Controller Registers |
| 76 | */ |
| 77 | |
Mauro Carvalho Chehab | e9bd2e7 | 2009-07-09 22:14:35 -0300 | [diff] [blame] | 78 | /* OFFSETS for Device 0 Function 0 */ |
| 79 | |
| 80 | #define MC_CFG_CONTROL 0x90 |
| 81 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 82 | /* OFFSETS for Device 3 Function 0 */ |
| 83 | |
| 84 | #define MC_CONTROL 0x48 |
| 85 | #define MC_STATUS 0x4c |
| 86 | #define MC_MAX_DOD 0x64 |
| 87 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 88 | /* |
| 89 | * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet: |
| 90 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
| 91 | */ |
| 92 | |
| 93 | #define MC_TEST_ERR_RCV1 0x60 |
| 94 | #define DIMM2_COR_ERR(r) ((r) & 0x7fff) |
| 95 | |
| 96 | #define MC_TEST_ERR_RCV0 0x64 |
| 97 | #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) |
| 98 | #define DIMM0_COR_ERR(r) ((r) & 0x7fff) |
| 99 | |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 100 | /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */ |
| 101 | #define MC_COR_ECC_CNT_0 0x80 |
| 102 | #define MC_COR_ECC_CNT_1 0x84 |
| 103 | #define MC_COR_ECC_CNT_2 0x88 |
| 104 | #define MC_COR_ECC_CNT_3 0x8c |
| 105 | #define MC_COR_ECC_CNT_4 0x90 |
| 106 | #define MC_COR_ECC_CNT_5 0x94 |
| 107 | |
| 108 | #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff) |
| 109 | #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff) |
| 110 | |
| 111 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 112 | /* OFFSETS for Devices 4,5 and 6 Function 0 */ |
| 113 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 114 | #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58 |
| 115 | #define THREE_DIMMS_PRESENT (1 << 24) |
| 116 | #define SINGLE_QUAD_RANK_PRESENT (1 << 23) |
| 117 | #define QUAD_RANK_PRESENT (1 << 22) |
| 118 | #define REGISTERED_DIMM (1 << 15) |
| 119 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 120 | #define MC_CHANNEL_MAPPER 0x60 |
| 121 | #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) |
| 122 | #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) |
| 123 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 124 | #define MC_CHANNEL_RANK_PRESENT 0x7c |
| 125 | #define RANK_PRESENT_MASK 0xffff |
| 126 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 127 | #define MC_CHANNEL_ADDR_MATCH 0xf0 |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 128 | #define MC_CHANNEL_ERROR_MASK 0xf8 |
| 129 | #define MC_CHANNEL_ERROR_INJECT 0xfc |
| 130 | #define INJECT_ADDR_PARITY 0x10 |
| 131 | #define INJECT_ECC 0x08 |
| 132 | #define MASK_CACHELINE 0x06 |
| 133 | #define MASK_FULL_CACHELINE 0x06 |
| 134 | #define MASK_MSB32_CACHELINE 0x04 |
| 135 | #define MASK_LSB32_CACHELINE 0x02 |
| 136 | #define NO_MASK_CACHELINE 0x00 |
| 137 | #define REPEAT_EN 0x01 |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 138 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 139 | /* OFFSETS for Devices 4,5 and 6 Function 1 */ |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 140 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 141 | #define MC_DOD_CH_DIMM0 0x48 |
| 142 | #define MC_DOD_CH_DIMM1 0x4c |
| 143 | #define MC_DOD_CH_DIMM2 0x50 |
| 144 | #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10)) |
| 145 | #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10) |
| 146 | #define DIMM_PRESENT_MASK (1 << 9) |
| 147 | #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9) |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 148 | #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7)) |
| 149 | #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) |
| 150 | #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) |
| 151 | #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 152 | #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2)) |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 153 | #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2) |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 154 | #define MC_DOD_NUMCOL_MASK 3 |
| 155 | #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 156 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 157 | #define MC_RANK_PRESENT 0x7c |
| 158 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 159 | #define MC_SAG_CH_0 0x80 |
| 160 | #define MC_SAG_CH_1 0x84 |
| 161 | #define MC_SAG_CH_2 0x88 |
| 162 | #define MC_SAG_CH_3 0x8c |
| 163 | #define MC_SAG_CH_4 0x90 |
| 164 | #define MC_SAG_CH_5 0x94 |
| 165 | #define MC_SAG_CH_6 0x98 |
| 166 | #define MC_SAG_CH_7 0x9c |
| 167 | |
| 168 | #define MC_RIR_LIMIT_CH_0 0x40 |
| 169 | #define MC_RIR_LIMIT_CH_1 0x44 |
| 170 | #define MC_RIR_LIMIT_CH_2 0x48 |
| 171 | #define MC_RIR_LIMIT_CH_3 0x4C |
| 172 | #define MC_RIR_LIMIT_CH_4 0x50 |
| 173 | #define MC_RIR_LIMIT_CH_5 0x54 |
| 174 | #define MC_RIR_LIMIT_CH_6 0x58 |
| 175 | #define MC_RIR_LIMIT_CH_7 0x5C |
| 176 | #define MC_RIR_LIMIT_MASK ((1 << 10) - 1) |
| 177 | |
| 178 | #define MC_RIR_WAY_CH 0x80 |
| 179 | #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7) |
| 180 | #define MC_RIR_WAY_RANK_MASK 0x7 |
| 181 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 182 | /* |
| 183 | * i7core structs |
| 184 | */ |
| 185 | |
| 186 | #define NUM_CHANS 3 |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 187 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
| 188 | #define MAX_MCR_FUNC 4 |
| 189 | #define MAX_CHAN_FUNC 3 |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 190 | |
| 191 | struct i7core_info { |
| 192 | u32 mc_control; |
| 193 | u32 mc_status; |
| 194 | u32 max_dod; |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 195 | u32 ch_map; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 196 | }; |
| 197 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 198 | |
| 199 | struct i7core_inject { |
| 200 | int enable; |
| 201 | |
| 202 | u32 section; |
| 203 | u32 type; |
| 204 | u32 eccmask; |
| 205 | |
| 206 | /* Error address mask */ |
| 207 | int channel, dimm, rank, bank, page, col; |
| 208 | }; |
| 209 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 210 | struct i7core_channel { |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 211 | u32 ranks; |
| 212 | u32 dimms; |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 213 | }; |
| 214 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 215 | struct pci_id_descr { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 216 | int dev; |
| 217 | int func; |
| 218 | int dev_id; |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 219 | int optional; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 220 | }; |
| 221 | |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 222 | struct pci_id_table { |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 223 | const struct pci_id_descr *descr; |
| 224 | int n_devs; |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 225 | }; |
| 226 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 227 | struct i7core_dev { |
| 228 | struct list_head list; |
| 229 | u8 socket; |
| 230 | struct pci_dev **pdev; |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 231 | int n_devs; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 232 | struct mem_ctl_info *mci; |
| 233 | }; |
| 234 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 235 | struct i7core_pvt { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 236 | struct pci_dev *pci_noncore; |
| 237 | struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1]; |
| 238 | struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1]; |
| 239 | |
| 240 | struct i7core_dev *i7core_dev; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 241 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 242 | struct i7core_info info; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 243 | struct i7core_inject inject; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 244 | struct i7core_channel channel[NUM_CHANS]; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 245 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 246 | int channels; /* Number of active channels */ |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 247 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 248 | int ce_count_available; |
| 249 | int csrow_map[NUM_CHANS][MAX_DIMMS]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 250 | |
| 251 | /* ECC corrected errors counts per udimm */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 252 | unsigned long udimm_ce_count[MAX_DIMMS]; |
| 253 | int udimm_last_ce_count[MAX_DIMMS]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 254 | /* ECC corrected errors counts per rdimm */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 255 | unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS]; |
| 256 | int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS]; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 257 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 258 | unsigned int is_registered; |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 259 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 260 | /* mcelog glue */ |
| 261 | struct edac_mce edac_mce; |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 262 | |
| 263 | /* Fifo double buffers */ |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 264 | struct mce mce_entry[MCE_LOG_LEN]; |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 265 | struct mce mce_outentry[MCE_LOG_LEN]; |
| 266 | |
| 267 | /* Fifo in/out counters */ |
| 268 | unsigned mce_in, mce_out; |
| 269 | |
| 270 | /* Count indicator to show errors not got */ |
| 271 | unsigned mce_overrun; |
Mauro Carvalho Chehab | 939747bd | 2010-08-10 11:22:01 -0300 | [diff] [blame] | 272 | |
| 273 | /* Struct to control EDAC polling */ |
| 274 | struct edac_pci_ctl_info *i7core_pci; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 275 | }; |
| 276 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 277 | #define PCI_DESCR(device, function, device_id) \ |
| 278 | .dev = (device), \ |
| 279 | .func = (function), \ |
| 280 | .dev_id = (device_id) |
| 281 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 282 | static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = { |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 283 | /* Memory controller */ |
| 284 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, |
| 285 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 286 | /* Exists only for RDIMM */ |
| 287 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 }, |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 288 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, |
| 289 | |
| 290 | /* Channel 0 */ |
| 291 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, |
| 292 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, |
| 293 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) }, |
| 294 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) }, |
| 295 | |
| 296 | /* Channel 1 */ |
| 297 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) }, |
| 298 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) }, |
| 299 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) }, |
| 300 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) }, |
| 301 | |
| 302 | /* Channel 2 */ |
| 303 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) }, |
| 304 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) }, |
| 305 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) }, |
| 306 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) }, |
Mauro Carvalho Chehab | 310cbb7 | 2009-07-17 00:09:10 -0300 | [diff] [blame] | 307 | |
| 308 | /* Generic Non-core registers */ |
| 309 | /* |
| 310 | * This is the PCI device on i7core and on Xeon 35xx (8086:2c41) |
| 311 | * On Xeon 55xx, however, it has a different id (8086:2c40). So, |
| 312 | * the probing code needs to test for the other address in case of |
| 313 | * failure of this one |
| 314 | */ |
Mauro Carvalho Chehab | fd38265 | 2009-10-14 06:07:07 -0300 | [diff] [blame] | 315 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) }, |
Mauro Carvalho Chehab | 310cbb7 | 2009-07-17 00:09:10 -0300 | [diff] [blame] | 316 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 317 | }; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 318 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 319 | static const struct pci_id_descr pci_dev_descr_lynnfield[] = { |
Mauro Carvalho Chehab | 52a2e4fc | 2009-10-14 11:21:58 -0300 | [diff] [blame] | 320 | { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) }, |
| 321 | { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) }, |
| 322 | { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) }, |
| 323 | |
| 324 | { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) }, |
| 325 | { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) }, |
| 326 | { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) }, |
| 327 | { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) }, |
| 328 | |
Mauro Carvalho Chehab | 508fa17 | 2009-10-14 13:44:37 -0300 | [diff] [blame] | 329 | { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) }, |
| 330 | { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) }, |
| 331 | { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) }, |
| 332 | { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) }, |
Mauro Carvalho Chehab | 52a2e4fc | 2009-10-14 11:21:58 -0300 | [diff] [blame] | 333 | |
Mauro Carvalho Chehab | f05da2f | 2009-10-14 13:31:06 -0300 | [diff] [blame] | 334 | /* |
| 335 | * This is the PCI device has an alternate address on some |
| 336 | * processors like Core i7 860 |
| 337 | */ |
Mauro Carvalho Chehab | 52a2e4fc | 2009-10-14 11:21:58 -0300 | [diff] [blame] | 338 | { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) }, |
| 339 | }; |
| 340 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 341 | static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = { |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 342 | /* Memory controller */ |
| 343 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) }, |
| 344 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) }, |
| 345 | /* Exists only for RDIMM */ |
| 346 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 }, |
| 347 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) }, |
| 348 | |
| 349 | /* Channel 0 */ |
| 350 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) }, |
| 351 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) }, |
| 352 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) }, |
| 353 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) }, |
| 354 | |
| 355 | /* Channel 1 */ |
| 356 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) }, |
| 357 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) }, |
| 358 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) }, |
| 359 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) }, |
| 360 | |
| 361 | /* Channel 2 */ |
| 362 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) }, |
| 363 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) }, |
| 364 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) }, |
| 365 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) }, |
| 366 | |
| 367 | /* Generic Non-core registers */ |
| 368 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) }, |
| 369 | |
| 370 | }; |
| 371 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 372 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } |
| 373 | static const struct pci_id_table pci_dev_table[] = { |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 374 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem), |
| 375 | PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield), |
| 376 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere), |
| 377 | }; |
| 378 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 379 | /* |
| 380 | * pci_device_id table for which devices we are looking for |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 381 | */ |
| 382 | static const struct pci_device_id i7core_pci_tbl[] __devinitdata = { |
Mauro Carvalho Chehab | d1fd4fb | 2009-07-10 18:39:53 -0300 | [diff] [blame] | 383 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)}, |
Mauro Carvalho Chehab | f05da2f | 2009-10-14 13:31:06 -0300 | [diff] [blame] | 384 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)}, |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 385 | {0,} /* 0 terminated list. */ |
| 386 | }; |
| 387 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 388 | /**************************************************************************** |
| 389 | Anciliary status routines |
| 390 | ****************************************************************************/ |
| 391 | |
| 392 | /* MC_CONTROL bits */ |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 393 | #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) |
| 394 | #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 395 | |
| 396 | /* MC_STATUS bits */ |
Keith Mannthey | 61053fd | 2009-09-02 23:46:59 -0300 | [diff] [blame] | 397 | #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 398 | #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 399 | |
| 400 | /* MC_MAX_DOD read functions */ |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 401 | static inline int numdimms(u32 dimms) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 402 | { |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 403 | return (dimms & 0x3) + 1; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 404 | } |
| 405 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 406 | static inline int numrank(u32 rank) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 407 | { |
| 408 | static int ranks[4] = { 1, 2, 4, -EINVAL }; |
| 409 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 410 | return ranks[rank & 0x3]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 411 | } |
| 412 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 413 | static inline int numbank(u32 bank) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 414 | { |
| 415 | static int banks[4] = { 4, 8, 16, -EINVAL }; |
| 416 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 417 | return banks[bank & 0x3]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 418 | } |
| 419 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 420 | static inline int numrow(u32 row) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 421 | { |
| 422 | static int rows[8] = { |
| 423 | 1 << 12, 1 << 13, 1 << 14, 1 << 15, |
| 424 | 1 << 16, -EINVAL, -EINVAL, -EINVAL, |
| 425 | }; |
| 426 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 427 | return rows[row & 0x7]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 428 | } |
| 429 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 430 | static inline int numcol(u32 col) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 431 | { |
| 432 | static int cols[8] = { |
| 433 | 1 << 10, 1 << 11, 1 << 12, -EINVAL, |
| 434 | }; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 435 | return cols[col & 0x3]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 436 | } |
| 437 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 438 | static struct i7core_dev *get_i7core_dev(u8 socket) |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 439 | { |
| 440 | struct i7core_dev *i7core_dev; |
| 441 | |
| 442 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { |
| 443 | if (i7core_dev->socket == socket) |
| 444 | return i7core_dev; |
| 445 | } |
| 446 | |
| 447 | return NULL; |
| 448 | } |
| 449 | |
Hidetoshi Seto | 848b2f7 | 2010-08-20 04:24:44 -0300 | [diff] [blame] | 450 | static struct i7core_dev *alloc_i7core_dev(u8 socket, |
| 451 | const struct pci_id_table *table) |
| 452 | { |
| 453 | struct i7core_dev *i7core_dev; |
| 454 | |
| 455 | i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL); |
| 456 | if (!i7core_dev) |
| 457 | return NULL; |
| 458 | |
| 459 | i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs, |
| 460 | GFP_KERNEL); |
| 461 | if (!i7core_dev->pdev) { |
| 462 | kfree(i7core_dev); |
| 463 | return NULL; |
| 464 | } |
| 465 | |
| 466 | i7core_dev->socket = socket; |
| 467 | i7core_dev->n_devs = table->n_devs; |
| 468 | list_add_tail(&i7core_dev->list, &i7core_edac_list); |
| 469 | |
| 470 | return i7core_dev; |
| 471 | } |
| 472 | |
Hidetoshi Seto | 2aa9be4 | 2010-08-20 04:25:00 -0300 | [diff] [blame] | 473 | static void free_i7core_dev(struct i7core_dev *i7core_dev) |
| 474 | { |
| 475 | list_del(&i7core_dev->list); |
| 476 | kfree(i7core_dev->pdev); |
| 477 | kfree(i7core_dev); |
| 478 | } |
| 479 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 480 | /**************************************************************************** |
| 481 | Memory check routines |
| 482 | ****************************************************************************/ |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 483 | static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot, |
| 484 | unsigned func) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 485 | { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 486 | struct i7core_dev *i7core_dev = get_i7core_dev(socket); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 487 | int i; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 488 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 489 | if (!i7core_dev) |
| 490 | return NULL; |
| 491 | |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 492 | for (i = 0; i < i7core_dev->n_devs; i++) { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 493 | if (!i7core_dev->pdev[i]) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 494 | continue; |
| 495 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 496 | if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot && |
| 497 | PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) { |
| 498 | return i7core_dev->pdev[i]; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 499 | } |
| 500 | } |
| 501 | |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 502 | return NULL; |
| 503 | } |
| 504 | |
Mauro Carvalho Chehab | ec6df24 | 2009-07-18 10:44:30 -0300 | [diff] [blame] | 505 | /** |
| 506 | * i7core_get_active_channels() - gets the number of channels and csrows |
| 507 | * @socket: Quick Path Interconnect socket |
| 508 | * @channels: Number of channels that will be returned |
| 509 | * @csrows: Number of csrows found |
| 510 | * |
| 511 | * Since EDAC core needs to know in advance the number of available channels |
| 512 | * and csrows, in order to allocate memory for csrows/channels, it is needed |
| 513 | * to run two similar steps. At the first step, implemented on this function, |
| 514 | * it checks the number of csrows/channels present at one socket. |
| 515 | * this is used in order to properly allocate the size of mci components. |
| 516 | * |
| 517 | * It should be noticed that none of the current available datasheets explain |
| 518 | * or even mention how csrows are seen by the memory controller. So, we need |
| 519 | * to add a fake description for csrows. |
| 520 | * So, this driver is attributing one DIMM memory for one csrow. |
| 521 | */ |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 522 | static int i7core_get_active_channels(const u8 socket, unsigned *channels, |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 523 | unsigned *csrows) |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 524 | { |
| 525 | struct pci_dev *pdev = NULL; |
| 526 | int i, j; |
| 527 | u32 status, control; |
| 528 | |
| 529 | *channels = 0; |
| 530 | *csrows = 0; |
| 531 | |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 532 | pdev = get_pdev_slot_func(socket, 3, 0); |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 533 | if (!pdev) { |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 534 | i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n", |
| 535 | socket); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 536 | return -ENODEV; |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 537 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 538 | |
| 539 | /* Device 3 function 0 reads */ |
| 540 | pci_read_config_dword(pdev, MC_STATUS, &status); |
| 541 | pci_read_config_dword(pdev, MC_CONTROL, &control); |
| 542 | |
| 543 | for (i = 0; i < NUM_CHANS; i++) { |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 544 | u32 dimm_dod[3]; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 545 | /* Check if the channel is active */ |
| 546 | if (!(control & (1 << (8 + i)))) |
| 547 | continue; |
| 548 | |
| 549 | /* Check if the channel is disabled */ |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 550 | if (status & (1 << i)) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 551 | continue; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 552 | |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 553 | pdev = get_pdev_slot_func(socket, i + 4, 1); |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 554 | if (!pdev) { |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 555 | i7core_printk(KERN_ERR, "Couldn't find socket %d " |
| 556 | "fn %d.%d!!!\n", |
| 557 | socket, i + 4, 1); |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 558 | return -ENODEV; |
| 559 | } |
| 560 | /* Devices 4-6 function 1 */ |
| 561 | pci_read_config_dword(pdev, |
| 562 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
| 563 | pci_read_config_dword(pdev, |
| 564 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
| 565 | pci_read_config_dword(pdev, |
| 566 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
| 567 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 568 | (*channels)++; |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 569 | |
| 570 | for (j = 0; j < 3; j++) { |
| 571 | if (!DIMM_PRESENT(dimm_dod[j])) |
| 572 | continue; |
| 573 | (*csrows)++; |
| 574 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 575 | } |
| 576 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 577 | debugf0("Number of active channels on socket %d: %d\n", |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 578 | socket, *channels); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 579 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 580 | return 0; |
| 581 | } |
| 582 | |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 583 | static int get_dimm_config(const struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 584 | { |
| 585 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 586 | struct csrow_info *csr; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 587 | struct pci_dev *pdev; |
Mauro Carvalho Chehab | ba6c5c6 | 2009-07-15 09:02:32 -0300 | [diff] [blame] | 588 | int i, j; |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 589 | int csrow = 0; |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 590 | unsigned long last_page = 0; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 591 | enum edac_type mode; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 592 | enum mem_type mtype; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 593 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 594 | /* Get data from the MC register, function 0 */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 595 | pdev = pvt->pci_mcr[0]; |
Mauro Carvalho Chehab | 7dd6953 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 596 | if (!pdev) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 597 | return -ENODEV; |
| 598 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 599 | /* Device 3 function 0 reads */ |
Mauro Carvalho Chehab | 7dd6953 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 600 | pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); |
| 601 | pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); |
| 602 | pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); |
| 603 | pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 604 | |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 605 | debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", |
Mauro Carvalho Chehab | 4af9188 | 2009-09-24 09:58:26 -0300 | [diff] [blame] | 606 | pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status, |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 607 | pvt->info.max_dod, pvt->info.ch_map); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 608 | |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 609 | if (ECC_ENABLED(pvt)) { |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 610 | debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 611 | if (ECCx8(pvt)) |
| 612 | mode = EDAC_S8ECD8ED; |
| 613 | else |
| 614 | mode = EDAC_S4ECD4ED; |
| 615 | } else { |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 616 | debugf0("ECC disabled\n"); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 617 | mode = EDAC_NONE; |
| 618 | } |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 619 | |
| 620 | /* FIXME: need to handle the error codes */ |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 621 | debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked " |
| 622 | "x%x x 0x%x\n", |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 623 | numdimms(pvt->info.max_dod), |
| 624 | numrank(pvt->info.max_dod >> 2), |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 625 | numbank(pvt->info.max_dod >> 4), |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 626 | numrow(pvt->info.max_dod >> 6), |
| 627 | numcol(pvt->info.max_dod >> 9)); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 628 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 629 | for (i = 0; i < NUM_CHANS; i++) { |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 630 | u32 data, dimm_dod[3], value[8]; |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 631 | |
Mauro Carvalho Chehab | 52a2e4fc | 2009-10-14 11:21:58 -0300 | [diff] [blame] | 632 | if (!pvt->pci_ch[i][0]) |
| 633 | continue; |
| 634 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 635 | if (!CH_ACTIVE(pvt, i)) { |
| 636 | debugf0("Channel %i is not active\n", i); |
| 637 | continue; |
| 638 | } |
| 639 | if (CH_DISABLED(pvt, i)) { |
| 640 | debugf0("Channel %i is disabled\n", i); |
| 641 | continue; |
| 642 | } |
| 643 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 644 | /* Devices 4-6 function 0 */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 645 | pci_read_config_dword(pvt->pci_ch[i][0], |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 646 | MC_CHANNEL_DIMM_INIT_PARAMS, &data); |
| 647 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 648 | pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ? |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 649 | 4 : 2; |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 650 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 651 | if (data & REGISTERED_DIMM) |
| 652 | mtype = MEM_RDDR3; |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 653 | else |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 654 | mtype = MEM_DDR3; |
| 655 | #if 0 |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 656 | if (data & THREE_DIMMS_PRESENT) |
| 657 | pvt->channel[i].dimms = 3; |
| 658 | else if (data & SINGLE_QUAD_RANK_PRESENT) |
| 659 | pvt->channel[i].dimms = 1; |
| 660 | else |
| 661 | pvt->channel[i].dimms = 2; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 662 | #endif |
| 663 | |
| 664 | /* Devices 4-6 function 1 */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 665 | pci_read_config_dword(pvt->pci_ch[i][1], |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 666 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 667 | pci_read_config_dword(pvt->pci_ch[i][1], |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 668 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 669 | pci_read_config_dword(pvt->pci_ch[i][1], |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 670 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 671 | |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 672 | debugf0("Ch%d phy rd%d, wr%d (0x%08x): " |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 673 | "%d ranks, %cDIMMs\n", |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 674 | i, |
| 675 | RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), |
| 676 | data, |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 677 | pvt->channel[i].ranks, |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 678 | (data & REGISTERED_DIMM) ? 'R' : 'U'); |
Mauro Carvalho Chehab | 7dd6953 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 679 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 680 | for (j = 0; j < 3; j++) { |
| 681 | u32 banks, ranks, rows, cols; |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 682 | u32 size, npages; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 683 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 684 | if (!DIMM_PRESENT(dimm_dod[j])) |
| 685 | continue; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 686 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 687 | banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); |
| 688 | ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); |
| 689 | rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); |
| 690 | cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 691 | |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 692 | /* DDR3 has 8 I/O banks */ |
| 693 | size = (rows * cols * banks * ranks) >> (20 - 3); |
| 694 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 695 | pvt->channel[i].dimms++; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 696 | |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 697 | debugf0("\tdimm %d %d Mb offset: %x, " |
| 698 | "bank: %d, rank: %d, row: %#x, col: %#x\n", |
| 699 | j, size, |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 700 | RANKOFFSET(dimm_dod[j]), |
| 701 | banks, ranks, rows, cols); |
| 702 | |
Mauro Carvalho Chehab | e914460 | 2010-08-10 20:26:35 -0300 | [diff] [blame] | 703 | npages = MiB_TO_PAGES(size); |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 704 | |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 705 | csr = &mci->csrows[csrow]; |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 706 | csr->first_page = last_page + 1; |
| 707 | last_page += npages; |
| 708 | csr->last_page = last_page; |
| 709 | csr->nr_pages = npages; |
| 710 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 711 | csr->page_mask = 0; |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 712 | csr->grain = 8; |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 713 | csr->csrow_idx = csrow; |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 714 | csr->nr_channels = 1; |
| 715 | |
| 716 | csr->channels[0].chan_idx = i; |
| 717 | csr->channels[0].ce_count = 0; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 718 | |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 719 | pvt->csrow_map[i][j] = csrow; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 720 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 721 | switch (banks) { |
| 722 | case 4: |
| 723 | csr->dtype = DEV_X4; |
| 724 | break; |
| 725 | case 8: |
| 726 | csr->dtype = DEV_X8; |
| 727 | break; |
| 728 | case 16: |
| 729 | csr->dtype = DEV_X16; |
| 730 | break; |
| 731 | default: |
| 732 | csr->dtype = DEV_UNKNOWN; |
| 733 | } |
| 734 | |
| 735 | csr->edac_mode = mode; |
| 736 | csr->mtype = mtype; |
| 737 | |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 738 | csrow++; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 739 | } |
| 740 | |
| 741 | pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]); |
| 742 | pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]); |
| 743 | pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]); |
| 744 | pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]); |
| 745 | pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]); |
| 746 | pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); |
| 747 | pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); |
| 748 | pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 749 | debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 750 | for (j = 0; j < 8; j++) |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 751 | debugf1("\t\t%#x\t%#x\t%#x\n", |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 752 | (value[j] >> 27) & 0x1, |
| 753 | (value[j] >> 24) & 0x7, |
| 754 | (value[j] && ((1 << 24) - 1))); |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 755 | } |
| 756 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 757 | return 0; |
| 758 | } |
| 759 | |
| 760 | /**************************************************************************** |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 761 | Error insertion routines |
| 762 | ****************************************************************************/ |
| 763 | |
| 764 | /* The i7core has independent error injection features per channel. |
| 765 | However, to have a simpler code, we don't allow enabling error injection |
| 766 | on more than one channel. |
| 767 | Also, since a change at an inject parameter will be applied only at enable, |
| 768 | we're disabling error injection on all write calls to the sysfs nodes that |
| 769 | controls the error code injection. |
| 770 | */ |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 771 | static int disable_inject(const struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 772 | { |
| 773 | struct i7core_pvt *pvt = mci->pvt_info; |
| 774 | |
| 775 | pvt->inject.enable = 0; |
| 776 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 777 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 778 | return -ENODEV; |
| 779 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 780 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 781 | MC_CHANNEL_ERROR_INJECT, 0); |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 782 | |
| 783 | return 0; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 784 | } |
| 785 | |
| 786 | /* |
| 787 | * i7core inject inject.section |
| 788 | * |
| 789 | * accept and store error injection inject.section value |
| 790 | * bit 0 - refers to the lower 32-byte half cacheline |
| 791 | * bit 1 - refers to the upper 32-byte half cacheline |
| 792 | */ |
| 793 | static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci, |
| 794 | const char *data, size_t count) |
| 795 | { |
| 796 | struct i7core_pvt *pvt = mci->pvt_info; |
| 797 | unsigned long value; |
| 798 | int rc; |
| 799 | |
| 800 | if (pvt->inject.enable) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 801 | disable_inject(mci); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 802 | |
| 803 | rc = strict_strtoul(data, 10, &value); |
| 804 | if ((rc < 0) || (value > 3)) |
Mauro Carvalho Chehab | 2068def | 2009-08-05 19:28:27 -0300 | [diff] [blame] | 805 | return -EIO; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 806 | |
| 807 | pvt->inject.section = (u32) value; |
| 808 | return count; |
| 809 | } |
| 810 | |
| 811 | static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci, |
| 812 | char *data) |
| 813 | { |
| 814 | struct i7core_pvt *pvt = mci->pvt_info; |
| 815 | return sprintf(data, "0x%08x\n", pvt->inject.section); |
| 816 | } |
| 817 | |
| 818 | /* |
| 819 | * i7core inject.type |
| 820 | * |
| 821 | * accept and store error injection inject.section value |
| 822 | * bit 0 - repeat enable - Enable error repetition |
| 823 | * bit 1 - inject ECC error |
| 824 | * bit 2 - inject parity error |
| 825 | */ |
| 826 | static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci, |
| 827 | const char *data, size_t count) |
| 828 | { |
| 829 | struct i7core_pvt *pvt = mci->pvt_info; |
| 830 | unsigned long value; |
| 831 | int rc; |
| 832 | |
| 833 | if (pvt->inject.enable) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 834 | disable_inject(mci); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 835 | |
| 836 | rc = strict_strtoul(data, 10, &value); |
| 837 | if ((rc < 0) || (value > 7)) |
Mauro Carvalho Chehab | 2068def | 2009-08-05 19:28:27 -0300 | [diff] [blame] | 838 | return -EIO; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 839 | |
| 840 | pvt->inject.type = (u32) value; |
| 841 | return count; |
| 842 | } |
| 843 | |
| 844 | static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci, |
| 845 | char *data) |
| 846 | { |
| 847 | struct i7core_pvt *pvt = mci->pvt_info; |
| 848 | return sprintf(data, "0x%08x\n", pvt->inject.type); |
| 849 | } |
| 850 | |
| 851 | /* |
| 852 | * i7core_inject_inject.eccmask_store |
| 853 | * |
| 854 | * The type of error (UE/CE) will depend on the inject.eccmask value: |
| 855 | * Any bits set to a 1 will flip the corresponding ECC bit |
| 856 | * Correctable errors can be injected by flipping 1 bit or the bits within |
| 857 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or |
| 858 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an |
| 859 | * uncorrectable error to be injected. |
| 860 | */ |
| 861 | static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci, |
| 862 | const char *data, size_t count) |
| 863 | { |
| 864 | struct i7core_pvt *pvt = mci->pvt_info; |
| 865 | unsigned long value; |
| 866 | int rc; |
| 867 | |
| 868 | if (pvt->inject.enable) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 869 | disable_inject(mci); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 870 | |
| 871 | rc = strict_strtoul(data, 10, &value); |
| 872 | if (rc < 0) |
Mauro Carvalho Chehab | 2068def | 2009-08-05 19:28:27 -0300 | [diff] [blame] | 873 | return -EIO; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 874 | |
| 875 | pvt->inject.eccmask = (u32) value; |
| 876 | return count; |
| 877 | } |
| 878 | |
| 879 | static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci, |
| 880 | char *data) |
| 881 | { |
| 882 | struct i7core_pvt *pvt = mci->pvt_info; |
| 883 | return sprintf(data, "0x%08x\n", pvt->inject.eccmask); |
| 884 | } |
| 885 | |
| 886 | /* |
| 887 | * i7core_addrmatch |
| 888 | * |
| 889 | * The type of error (UE/CE) will depend on the inject.eccmask value: |
| 890 | * Any bits set to a 1 will flip the corresponding ECC bit |
| 891 | * Correctable errors can be injected by flipping 1 bit or the bits within |
| 892 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or |
| 893 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an |
| 894 | * uncorrectable error to be injected. |
| 895 | */ |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 896 | |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 897 | #define DECLARE_ADDR_MATCH(param, limit) \ |
| 898 | static ssize_t i7core_inject_store_##param( \ |
| 899 | struct mem_ctl_info *mci, \ |
| 900 | const char *data, size_t count) \ |
| 901 | { \ |
Mauro Carvalho Chehab | cc301b3 | 2009-09-24 16:23:42 -0300 | [diff] [blame] | 902 | struct i7core_pvt *pvt; \ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 903 | long value; \ |
| 904 | int rc; \ |
| 905 | \ |
Mauro Carvalho Chehab | cc301b3 | 2009-09-24 16:23:42 -0300 | [diff] [blame] | 906 | debugf1("%s()\n", __func__); \ |
| 907 | pvt = mci->pvt_info; \ |
| 908 | \ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 909 | if (pvt->inject.enable) \ |
| 910 | disable_inject(mci); \ |
| 911 | \ |
Mauro Carvalho Chehab | 4f87fad | 2009-10-04 11:54:56 -0300 | [diff] [blame] | 912 | if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 913 | value = -1; \ |
| 914 | else { \ |
| 915 | rc = strict_strtoul(data, 10, &value); \ |
| 916 | if ((rc < 0) || (value >= limit)) \ |
| 917 | return -EIO; \ |
| 918 | } \ |
| 919 | \ |
| 920 | pvt->inject.param = value; \ |
| 921 | \ |
| 922 | return count; \ |
| 923 | } \ |
| 924 | \ |
| 925 | static ssize_t i7core_inject_show_##param( \ |
| 926 | struct mem_ctl_info *mci, \ |
| 927 | char *data) \ |
| 928 | { \ |
Mauro Carvalho Chehab | cc301b3 | 2009-09-24 16:23:42 -0300 | [diff] [blame] | 929 | struct i7core_pvt *pvt; \ |
| 930 | \ |
| 931 | pvt = mci->pvt_info; \ |
| 932 | debugf1("%s() pvt=%p\n", __func__, pvt); \ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 933 | if (pvt->inject.param < 0) \ |
| 934 | return sprintf(data, "any\n"); \ |
| 935 | else \ |
| 936 | return sprintf(data, "%d\n", pvt->inject.param);\ |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 937 | } |
| 938 | |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 939 | #define ATTR_ADDR_MATCH(param) \ |
| 940 | { \ |
| 941 | .attr = { \ |
| 942 | .name = #param, \ |
| 943 | .mode = (S_IRUGO | S_IWUSR) \ |
| 944 | }, \ |
| 945 | .show = i7core_inject_show_##param, \ |
| 946 | .store = i7core_inject_store_##param, \ |
| 947 | } |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 948 | |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 949 | DECLARE_ADDR_MATCH(channel, 3); |
| 950 | DECLARE_ADDR_MATCH(dimm, 3); |
| 951 | DECLARE_ADDR_MATCH(rank, 4); |
| 952 | DECLARE_ADDR_MATCH(bank, 32); |
| 953 | DECLARE_ADDR_MATCH(page, 0x10000); |
| 954 | DECLARE_ADDR_MATCH(col, 0x4000); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 955 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 956 | static int write_and_test(struct pci_dev *dev, const int where, const u32 val) |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 957 | { |
| 958 | u32 read; |
| 959 | int count; |
| 960 | |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 961 | debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n", |
| 962 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 963 | where, val); |
| 964 | |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 965 | for (count = 0; count < 10; count++) { |
| 966 | if (count) |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 967 | msleep(100); |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 968 | pci_write_config_dword(dev, where, val); |
| 969 | pci_read_config_dword(dev, where, &read); |
| 970 | |
| 971 | if (read == val) |
| 972 | return 0; |
| 973 | } |
| 974 | |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 975 | i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x " |
| 976 | "write=%08x. Read=%08x\n", |
| 977 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 978 | where, val, read); |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 979 | |
| 980 | return -EINVAL; |
| 981 | } |
| 982 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 983 | /* |
| 984 | * This routine prepares the Memory Controller for error injection. |
| 985 | * The error will be injected when some process tries to write to the |
| 986 | * memory that matches the given criteria. |
| 987 | * The criteria can be set in terms of a mask where dimm, rank, bank, page |
| 988 | * and col can be specified. |
| 989 | * A -1 value for any of the mask items will make the MCU to ignore |
| 990 | * that matching criteria for error injection. |
| 991 | * |
| 992 | * It should be noticed that the error will only happen after a write operation |
| 993 | * on a memory that matches the condition. if REPEAT_EN is not enabled at |
| 994 | * inject mask, then it will produce just one error. Otherwise, it will repeat |
| 995 | * until the injectmask would be cleaned. |
| 996 | * |
| 997 | * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD |
| 998 | * is reliable enough to check if the MC is using the |
| 999 | * three channels. However, this is not clear at the datasheet. |
| 1000 | */ |
| 1001 | static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci, |
| 1002 | const char *data, size_t count) |
| 1003 | { |
| 1004 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1005 | u32 injectmask; |
| 1006 | u64 mask = 0; |
| 1007 | int rc; |
| 1008 | long enable; |
| 1009 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1010 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1011 | return 0; |
| 1012 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1013 | rc = strict_strtoul(data, 10, &enable); |
| 1014 | if ((rc < 0)) |
| 1015 | return 0; |
| 1016 | |
| 1017 | if (enable) { |
| 1018 | pvt->inject.enable = 1; |
| 1019 | } else { |
| 1020 | disable_inject(mci); |
| 1021 | return count; |
| 1022 | } |
| 1023 | |
| 1024 | /* Sets pvt->inject.dimm mask */ |
| 1025 | if (pvt->inject.dimm < 0) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1026 | mask |= 1LL << 41; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1027 | else { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1028 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1029 | mask |= (pvt->inject.dimm & 0x3LL) << 35; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1030 | else |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1031 | mask |= (pvt->inject.dimm & 0x1LL) << 36; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1032 | } |
| 1033 | |
| 1034 | /* Sets pvt->inject.rank mask */ |
| 1035 | if (pvt->inject.rank < 0) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1036 | mask |= 1LL << 40; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1037 | else { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1038 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1039 | mask |= (pvt->inject.rank & 0x1LL) << 34; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1040 | else |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1041 | mask |= (pvt->inject.rank & 0x3LL) << 34; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1042 | } |
| 1043 | |
| 1044 | /* Sets pvt->inject.bank mask */ |
| 1045 | if (pvt->inject.bank < 0) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1046 | mask |= 1LL << 39; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1047 | else |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1048 | mask |= (pvt->inject.bank & 0x15LL) << 30; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1049 | |
| 1050 | /* Sets pvt->inject.page mask */ |
| 1051 | if (pvt->inject.page < 0) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1052 | mask |= 1LL << 38; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1053 | else |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1054 | mask |= (pvt->inject.page & 0xffff) << 14; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1055 | |
| 1056 | /* Sets pvt->inject.column mask */ |
| 1057 | if (pvt->inject.col < 0) |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1058 | mask |= 1LL << 37; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1059 | else |
Alan Cox | 486dd09 | 2009-11-08 01:34:27 -0200 | [diff] [blame] | 1060 | mask |= (pvt->inject.col & 0x3fff); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1061 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1062 | /* |
| 1063 | * bit 0: REPEAT_EN |
| 1064 | * bits 1-2: MASK_HALF_CACHELINE |
| 1065 | * bit 3: INJECT_ECC |
| 1066 | * bit 4: INJECT_ADDR_PARITY |
| 1067 | */ |
| 1068 | |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1069 | injectmask = (pvt->inject.type & 1) | |
| 1070 | (pvt->inject.section & 0x3) << 1 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1071 | (pvt->inject.type & 0x6) << (3 - 1); |
| 1072 | |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1073 | /* Unlock writes to registers - this register is write only */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1074 | pci_write_config_dword(pvt->pci_noncore, |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1075 | MC_CFG_CONTROL, 0x2); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1076 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1077 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1078 | MC_CHANNEL_ADDR_MATCH, mask); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1079 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1080 | MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); |
| 1081 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1082 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1083 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); |
| 1084 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1085 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 1086 | MC_CHANNEL_ERROR_INJECT, injectmask); |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1087 | |
| 1088 | /* |
| 1089 | * This is something undocumented, based on my tests |
| 1090 | * Without writing 8 to this register, errors aren't injected. Not sure |
| 1091 | * why. |
| 1092 | */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1093 | pci_write_config_dword(pvt->pci_noncore, |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 1094 | MC_CFG_CONTROL, 8); |
| 1095 | |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 1096 | debugf0("Error inject addr match 0x%016llx, ecc 0x%08x," |
| 1097 | " inject 0x%08x\n", |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1098 | mask, pvt->inject.eccmask, injectmask); |
| 1099 | |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1100 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1101 | return count; |
| 1102 | } |
| 1103 | |
| 1104 | static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci, |
| 1105 | char *data) |
| 1106 | { |
| 1107 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1108 | u32 injectmask; |
| 1109 | |
Mauro Carvalho Chehab | 52a2e4fc | 2009-10-14 11:21:58 -0300 | [diff] [blame] | 1110 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
| 1111 | return 0; |
| 1112 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1113 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 1114 | MC_CHANNEL_ERROR_INJECT, &injectmask); |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1115 | |
| 1116 | debugf0("Inject error read: 0x%018x\n", injectmask); |
| 1117 | |
| 1118 | if (injectmask & 0x0c) |
| 1119 | pvt->inject.enable = 1; |
| 1120 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1121 | return sprintf(data, "%d\n", pvt->inject.enable); |
| 1122 | } |
| 1123 | |
Mauro Carvalho Chehab | f338d73 | 2009-09-24 17:25:43 -0300 | [diff] [blame] | 1124 | #define DECLARE_COUNTER(param) \ |
| 1125 | static ssize_t i7core_show_counter_##param( \ |
| 1126 | struct mem_ctl_info *mci, \ |
| 1127 | char *data) \ |
| 1128 | { \ |
| 1129 | struct i7core_pvt *pvt = mci->pvt_info; \ |
| 1130 | \ |
| 1131 | debugf1("%s() \n", __func__); \ |
| 1132 | if (!pvt->ce_count_available || (pvt->is_registered)) \ |
| 1133 | return sprintf(data, "data unavailable\n"); \ |
| 1134 | return sprintf(data, "%lu\n", \ |
| 1135 | pvt->udimm_ce_count[param]); \ |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1136 | } |
| 1137 | |
Mauro Carvalho Chehab | f338d73 | 2009-09-24 17:25:43 -0300 | [diff] [blame] | 1138 | #define ATTR_COUNTER(param) \ |
| 1139 | { \ |
| 1140 | .attr = { \ |
| 1141 | .name = __stringify(udimm##param), \ |
| 1142 | .mode = (S_IRUGO | S_IWUSR) \ |
| 1143 | }, \ |
| 1144 | .show = i7core_show_counter_##param \ |
| 1145 | } |
| 1146 | |
| 1147 | DECLARE_COUNTER(0); |
| 1148 | DECLARE_COUNTER(1); |
| 1149 | DECLARE_COUNTER(2); |
| 1150 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1151 | /* |
| 1152 | * Sysfs struct |
| 1153 | */ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 1154 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1155 | static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = { |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 1156 | ATTR_ADDR_MATCH(channel), |
| 1157 | ATTR_ADDR_MATCH(dimm), |
| 1158 | ATTR_ADDR_MATCH(rank), |
| 1159 | ATTR_ADDR_MATCH(bank), |
| 1160 | ATTR_ADDR_MATCH(page), |
| 1161 | ATTR_ADDR_MATCH(col), |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1162 | { } /* End of list */ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 1163 | }; |
| 1164 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1165 | static const struct mcidev_sysfs_group i7core_inject_addrmatch = { |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 1166 | .name = "inject_addrmatch", |
| 1167 | .mcidev_attr = i7core_addrmatch_attrs, |
| 1168 | }; |
| 1169 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1170 | static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = { |
Mauro Carvalho Chehab | f338d73 | 2009-09-24 17:25:43 -0300 | [diff] [blame] | 1171 | ATTR_COUNTER(0), |
| 1172 | ATTR_COUNTER(1), |
| 1173 | ATTR_COUNTER(2), |
Marcin Slusarz | 64aab72 | 2010-09-30 15:15:30 -0700 | [diff] [blame] | 1174 | { .attr = { .name = NULL } } |
Mauro Carvalho Chehab | f338d73 | 2009-09-24 17:25:43 -0300 | [diff] [blame] | 1175 | }; |
| 1176 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1177 | static const struct mcidev_sysfs_group i7core_udimm_counters = { |
Mauro Carvalho Chehab | f338d73 | 2009-09-24 17:25:43 -0300 | [diff] [blame] | 1178 | .name = "all_channel_counts", |
| 1179 | .mcidev_attr = i7core_udimm_counters_attrs, |
| 1180 | }; |
| 1181 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1182 | static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = { |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1183 | { |
| 1184 | .attr = { |
| 1185 | .name = "inject_section", |
| 1186 | .mode = (S_IRUGO | S_IWUSR) |
| 1187 | }, |
| 1188 | .show = i7core_inject_section_show, |
| 1189 | .store = i7core_inject_section_store, |
| 1190 | }, { |
| 1191 | .attr = { |
| 1192 | .name = "inject_type", |
| 1193 | .mode = (S_IRUGO | S_IWUSR) |
| 1194 | }, |
| 1195 | .show = i7core_inject_type_show, |
| 1196 | .store = i7core_inject_type_store, |
| 1197 | }, { |
| 1198 | .attr = { |
| 1199 | .name = "inject_eccmask", |
| 1200 | .mode = (S_IRUGO | S_IWUSR) |
| 1201 | }, |
| 1202 | .show = i7core_inject_eccmask_show, |
| 1203 | .store = i7core_inject_eccmask_store, |
| 1204 | }, { |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame] | 1205 | .grp = &i7core_inject_addrmatch, |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1206 | }, { |
| 1207 | .attr = { |
| 1208 | .name = "inject_enable", |
| 1209 | .mode = (S_IRUGO | S_IWUSR) |
| 1210 | }, |
| 1211 | .show = i7core_inject_enable_show, |
| 1212 | .store = i7core_inject_enable_store, |
| 1213 | }, |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1214 | { } /* End of list */ |
| 1215 | }; |
| 1216 | |
| 1217 | static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = { |
| 1218 | { |
| 1219 | .attr = { |
| 1220 | .name = "inject_section", |
| 1221 | .mode = (S_IRUGO | S_IWUSR) |
| 1222 | }, |
| 1223 | .show = i7core_inject_section_show, |
| 1224 | .store = i7core_inject_section_store, |
| 1225 | }, { |
| 1226 | .attr = { |
| 1227 | .name = "inject_type", |
| 1228 | .mode = (S_IRUGO | S_IWUSR) |
| 1229 | }, |
| 1230 | .show = i7core_inject_type_show, |
| 1231 | .store = i7core_inject_type_store, |
| 1232 | }, { |
| 1233 | .attr = { |
| 1234 | .name = "inject_eccmask", |
| 1235 | .mode = (S_IRUGO | S_IWUSR) |
| 1236 | }, |
| 1237 | .show = i7core_inject_eccmask_show, |
| 1238 | .store = i7core_inject_eccmask_store, |
| 1239 | }, { |
| 1240 | .grp = &i7core_inject_addrmatch, |
| 1241 | }, { |
| 1242 | .attr = { |
| 1243 | .name = "inject_enable", |
| 1244 | .mode = (S_IRUGO | S_IWUSR) |
| 1245 | }, |
| 1246 | .show = i7core_inject_enable_show, |
| 1247 | .store = i7core_inject_enable_store, |
| 1248 | }, { |
| 1249 | .grp = &i7core_udimm_counters, |
| 1250 | }, |
| 1251 | { } /* End of list */ |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1252 | }; |
| 1253 | |
| 1254 | /**************************************************************************** |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1255 | Device initialization routines: put/get, init/exit |
| 1256 | ****************************************************************************/ |
| 1257 | |
| 1258 | /* |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 1259 | * i7core_put_all_devices 'put' all the devices that we have |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1260 | * reserved via 'get' |
| 1261 | */ |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1262 | static void i7core_put_devices(struct i7core_dev *i7core_dev) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1263 | { |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1264 | int i; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1265 | |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1266 | debugf0(__FILE__ ": %s()\n", __func__); |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1267 | for (i = 0; i < i7core_dev->n_devs; i++) { |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1268 | struct pci_dev *pdev = i7core_dev->pdev[i]; |
| 1269 | if (!pdev) |
| 1270 | continue; |
| 1271 | debugf0("Removing dev %02x:%02x.%d\n", |
| 1272 | pdev->bus->number, |
| 1273 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
| 1274 | pci_dev_put(pdev); |
| 1275 | } |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1276 | } |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1277 | |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1278 | static void i7core_put_all_devices(void) |
| 1279 | { |
Mauro Carvalho Chehab | 4253868 | 2009-09-24 09:59:13 -0300 | [diff] [blame] | 1280 | struct i7core_dev *i7core_dev, *tmp; |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1281 | |
Mauro Carvalho Chehab | 39300e7 | 2010-08-11 23:40:15 -0300 | [diff] [blame] | 1282 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) { |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1283 | i7core_put_devices(i7core_dev); |
Hidetoshi Seto | 2aa9be4 | 2010-08-20 04:25:00 -0300 | [diff] [blame] | 1284 | free_i7core_dev(i7core_dev); |
Mauro Carvalho Chehab | 39300e7 | 2010-08-11 23:40:15 -0300 | [diff] [blame] | 1285 | } |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1286 | } |
| 1287 | |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1288 | static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table) |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1289 | { |
| 1290 | struct pci_dev *pdev = NULL; |
| 1291 | int i; |
Mauro Carvalho Chehab | 54a08ab | 2010-08-19 15:51:00 -0300 | [diff] [blame] | 1292 | |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1293 | /* |
| 1294 | * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses |
| 1295 | * aren't announced by acpi. So, we need to use a legacy scan probing |
| 1296 | * to detect them |
| 1297 | */ |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 1298 | while (table && table->descr) { |
| 1299 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL); |
| 1300 | if (unlikely(!pdev)) { |
| 1301 | for (i = 0; i < MAX_SOCKET_BUSES; i++) |
| 1302 | pcibios_scan_specific_bus(255-i); |
| 1303 | } |
Mauro Carvalho Chehab | bda1428 | 2010-06-30 01:41:35 -0300 | [diff] [blame] | 1304 | pci_dev_put(pdev); |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 1305 | table++; |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1306 | } |
| 1307 | } |
| 1308 | |
Mauro Carvalho Chehab | bda1428 | 2010-06-30 01:41:35 -0300 | [diff] [blame] | 1309 | static unsigned i7core_pci_lastbus(void) |
| 1310 | { |
| 1311 | int last_bus = 0, bus; |
| 1312 | struct pci_bus *b = NULL; |
| 1313 | |
| 1314 | while ((b = pci_find_next_bus(b)) != NULL) { |
| 1315 | bus = b->number; |
| 1316 | debugf0("Found bus %d\n", bus); |
| 1317 | if (bus > last_bus) |
| 1318 | last_bus = bus; |
| 1319 | } |
| 1320 | |
| 1321 | debugf0("Last bus %d\n", last_bus); |
| 1322 | |
| 1323 | return last_bus; |
| 1324 | } |
| 1325 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1326 | /* |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 1327 | * i7core_get_all_devices Find and perform 'get' operation on the MCH's |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1328 | * device/functions we want to reference for this driver |
| 1329 | * |
| 1330 | * Need to 'get' device 16 func 1 and func 2 |
| 1331 | */ |
Hidetoshi Seto | b197cba | 2010-08-20 04:24:31 -0300 | [diff] [blame] | 1332 | static int i7core_get_onedevice(struct pci_dev **prev, |
| 1333 | const struct pci_id_table *table, |
| 1334 | const unsigned devno, |
| 1335 | const unsigned last_bus) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1336 | { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1337 | struct i7core_dev *i7core_dev; |
Hidetoshi Seto | b197cba | 2010-08-20 04:24:31 -0300 | [diff] [blame] | 1338 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1339 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1340 | struct pci_dev *pdev = NULL; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 1341 | u8 bus = 0; |
| 1342 | u8 socket = 0; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1343 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1344 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1345 | dev_descr->dev_id, *prev); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1346 | |
| 1347 | /* |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1348 | * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs |
| 1349 | * is at addr 8086:2c40, instead of 8086:2c41. So, we need |
| 1350 | * to probe for the alternate address in case of failure |
| 1351 | */ |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1352 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1353 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
Mauro Carvalho Chehab | fd38265 | 2009-10-14 06:07:07 -0300 | [diff] [blame] | 1354 | PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev); |
Mauro Carvalho Chehab | d1fd4fb | 2009-07-10 18:39:53 -0300 | [diff] [blame] | 1355 | |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 1356 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev) |
Mauro Carvalho Chehab | f05da2f | 2009-10-14 13:31:06 -0300 | [diff] [blame] | 1357 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1358 | PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT, |
| 1359 | *prev); |
| 1360 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1361 | if (!pdev) { |
| 1362 | if (*prev) { |
| 1363 | *prev = pdev; |
| 1364 | return 0; |
Mauro Carvalho Chehab | d1fd4fb | 2009-07-10 18:39:53 -0300 | [diff] [blame] | 1365 | } |
| 1366 | |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1367 | if (dev_descr->optional) |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1368 | return 0; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1369 | |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 1370 | if (devno == 0) |
| 1371 | return -ENODEV; |
| 1372 | |
Daniel J Blueman | ab08937 | 2010-07-23 23:16:52 +0100 | [diff] [blame] | 1373 | i7core_printk(KERN_INFO, |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1374 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1375 | dev_descr->dev, dev_descr->func, |
| 1376 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1377 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1378 | /* End of list, leave */ |
| 1379 | return -ENODEV; |
| 1380 | } |
| 1381 | bus = pdev->bus->number; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1382 | |
Mauro Carvalho Chehab | bda1428 | 2010-06-30 01:41:35 -0300 | [diff] [blame] | 1383 | socket = last_bus - bus; |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1384 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1385 | i7core_dev = get_i7core_dev(socket); |
| 1386 | if (!i7core_dev) { |
Hidetoshi Seto | 848b2f7 | 2010-08-20 04:24:44 -0300 | [diff] [blame] | 1387 | i7core_dev = alloc_i7core_dev(socket, table); |
Hidetoshi Seto | 2896637 | 2010-08-20 04:28:51 -0300 | [diff] [blame] | 1388 | if (!i7core_dev) { |
| 1389 | pci_dev_put(pdev); |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1390 | return -ENOMEM; |
Hidetoshi Seto | 2896637 | 2010-08-20 04:28:51 -0300 | [diff] [blame] | 1391 | } |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1392 | } |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1393 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1394 | if (i7core_dev->pdev[devno]) { |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1395 | i7core_printk(KERN_ERR, |
| 1396 | "Duplicated device for " |
| 1397 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1398 | bus, dev_descr->dev, dev_descr->func, |
| 1399 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1400 | pci_dev_put(pdev); |
| 1401 | return -ENODEV; |
| 1402 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1403 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1404 | i7core_dev->pdev[devno] = pdev; |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1405 | |
| 1406 | /* Sanity check */ |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1407 | if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || |
| 1408 | PCI_FUNC(pdev->devfn) != dev_descr->func)) { |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1409 | i7core_printk(KERN_ERR, |
| 1410 | "Device PCI ID %04x:%04x " |
| 1411 | "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n", |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1412 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id, |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1413 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1414 | bus, dev_descr->dev, dev_descr->func); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1415 | return -ENODEV; |
| 1416 | } |
| 1417 | |
| 1418 | /* Be sure that the device is enabled */ |
| 1419 | if (unlikely(pci_enable_device(pdev) < 0)) { |
| 1420 | i7core_printk(KERN_ERR, |
| 1421 | "Couldn't enable " |
| 1422 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1423 | bus, dev_descr->dev, dev_descr->func, |
| 1424 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1425 | return -ENODEV; |
| 1426 | } |
| 1427 | |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 1428 | debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1429 | socket, bus, dev_descr->dev, |
| 1430 | dev_descr->func, |
| 1431 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1432 | |
| 1433 | *prev = pdev; |
| 1434 | |
| 1435 | return 0; |
| 1436 | } |
| 1437 | |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 1438 | static int i7core_get_all_devices(void) |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1439 | { |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 1440 | int i, j, rc, last_bus; |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1441 | struct pci_dev *pdev = NULL; |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 1442 | const struct pci_id_table *table; |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1443 | |
Mauro Carvalho Chehab | bda1428 | 2010-06-30 01:41:35 -0300 | [diff] [blame] | 1444 | last_bus = i7core_pci_lastbus(); |
| 1445 | |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 1446 | for (j = 0; j < ARRAY_SIZE(pci_dev_table); j++) { |
| 1447 | table = &pci_dev_table[j]; |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 1448 | for (i = 0; i < table->n_devs; i++) { |
| 1449 | pdev = NULL; |
| 1450 | do { |
Hidetoshi Seto | b197cba | 2010-08-20 04:24:31 -0300 | [diff] [blame] | 1451 | rc = i7core_get_onedevice(&pdev, table, i, |
Mauro Carvalho Chehab | bda1428 | 2010-06-30 01:41:35 -0300 | [diff] [blame] | 1452 | last_bus); |
Vernon Mauery | bd9e19c | 2010-05-18 19:02:50 -0300 | [diff] [blame] | 1453 | if (rc < 0) { |
| 1454 | if (i == 0) { |
| 1455 | i = table->n_devs; |
| 1456 | break; |
| 1457 | } |
| 1458 | i7core_put_all_devices(); |
| 1459 | return -ENODEV; |
| 1460 | } |
| 1461 | } while (pdev); |
| 1462 | } |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1463 | } |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1464 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1465 | return 0; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1466 | } |
| 1467 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1468 | static int mci_bind_devs(struct mem_ctl_info *mci, |
| 1469 | struct i7core_dev *i7core_dev) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1470 | { |
| 1471 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1472 | struct pci_dev *pdev; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1473 | int i, func, slot; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1474 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1475 | pvt->is_registered = 0; |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 1476 | for (i = 0; i < i7core_dev->n_devs; i++) { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1477 | pdev = i7core_dev->pdev[i]; |
| 1478 | if (!pdev) |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1479 | continue; |
| 1480 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1481 | func = PCI_FUNC(pdev->devfn); |
| 1482 | slot = PCI_SLOT(pdev->devfn); |
| 1483 | if (slot == 3) { |
| 1484 | if (unlikely(func > MAX_MCR_FUNC)) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1485 | goto error; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1486 | pvt->pci_mcr[func] = pdev; |
| 1487 | } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) { |
| 1488 | if (unlikely(func > MAX_CHAN_FUNC)) |
| 1489 | goto error; |
| 1490 | pvt->pci_ch[slot - 4][func] = pdev; |
| 1491 | } else if (!slot && !func) |
| 1492 | pvt->pci_noncore = pdev; |
| 1493 | else |
| 1494 | goto error; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1495 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1496 | debugf0("Associated fn %d.%d, dev = %p, socket %d\n", |
| 1497 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1498 | pdev, i7core_dev->socket); |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 1499 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1500 | if (PCI_SLOT(pdev->devfn) == 3 && |
| 1501 | PCI_FUNC(pdev->devfn) == 2) |
| 1502 | pvt->is_registered = 1; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1503 | } |
Mauro Carvalho Chehab | e9bd2e7 | 2009-07-09 22:14:35 -0300 | [diff] [blame] | 1504 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1505 | return 0; |
| 1506 | |
| 1507 | error: |
| 1508 | i7core_printk(KERN_ERR, "Device %d, function %d " |
| 1509 | "is out of the expected range\n", |
| 1510 | slot, func); |
| 1511 | return -EINVAL; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1512 | } |
| 1513 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1514 | /**************************************************************************** |
| 1515 | Error check routines |
| 1516 | ****************************************************************************/ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1517 | static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci, |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1518 | const int chan, |
| 1519 | const int dimm, |
| 1520 | const int add) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1521 | { |
| 1522 | char *msg; |
| 1523 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1524 | int row = pvt->csrow_map[chan][dimm], i; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1525 | |
| 1526 | for (i = 0; i < add; i++) { |
| 1527 | msg = kasprintf(GFP_KERNEL, "Corrected error " |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1528 | "(Socket=%d channel=%d dimm=%d)", |
| 1529 | pvt->i7core_dev->socket, chan, dimm); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1530 | |
| 1531 | edac_mc_handle_fbd_ce(mci, row, 0, msg); |
| 1532 | kfree (msg); |
| 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci, |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1537 | const int chan, |
| 1538 | const int new0, |
| 1539 | const int new1, |
| 1540 | const int new2) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1541 | { |
| 1542 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1543 | int add0 = 0, add1 = 0, add2 = 0; |
| 1544 | /* Updates CE counters if it is not the first time here */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1545 | if (pvt->ce_count_available) { |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1546 | /* Updates CE counters */ |
| 1547 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1548 | add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; |
| 1549 | add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; |
| 1550 | add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1551 | |
| 1552 | if (add2 < 0) |
| 1553 | add2 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1554 | pvt->rdimm_ce_count[chan][2] += add2; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1555 | |
| 1556 | if (add1 < 0) |
| 1557 | add1 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1558 | pvt->rdimm_ce_count[chan][1] += add1; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1559 | |
| 1560 | if (add0 < 0) |
| 1561 | add0 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1562 | pvt->rdimm_ce_count[chan][0] += add0; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1563 | } else |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1564 | pvt->ce_count_available = 1; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1565 | |
| 1566 | /* Store the new values */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1567 | pvt->rdimm_last_ce_count[chan][2] = new2; |
| 1568 | pvt->rdimm_last_ce_count[chan][1] = new1; |
| 1569 | pvt->rdimm_last_ce_count[chan][0] = new0; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1570 | |
| 1571 | /*updated the edac core */ |
| 1572 | if (add0 != 0) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1573 | i7core_rdimm_update_csrow(mci, chan, 0, add0); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1574 | if (add1 != 0) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1575 | i7core_rdimm_update_csrow(mci, chan, 1, add1); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1576 | if (add2 != 0) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1577 | i7core_rdimm_update_csrow(mci, chan, 2, add2); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1578 | |
| 1579 | } |
| 1580 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1581 | static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1582 | { |
| 1583 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1584 | u32 rcv[3][2]; |
| 1585 | int i, new0, new1, new2; |
| 1586 | |
| 1587 | /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1588 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1589 | &rcv[0][0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1590 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1591 | &rcv[0][1]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1592 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1593 | &rcv[1][0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1594 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1595 | &rcv[1][1]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1596 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1597 | &rcv[2][0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1598 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1599 | &rcv[2][1]); |
| 1600 | for (i = 0 ; i < 3; i++) { |
| 1601 | debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", |
| 1602 | (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); |
| 1603 | /*if the channel has 3 dimms*/ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1604 | if (pvt->channel[i].dimms > 2) { |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1605 | new0 = DIMM_BOT_COR_ERR(rcv[i][0]); |
| 1606 | new1 = DIMM_TOP_COR_ERR(rcv[i][0]); |
| 1607 | new2 = DIMM_BOT_COR_ERR(rcv[i][1]); |
| 1608 | } else { |
| 1609 | new0 = DIMM_TOP_COR_ERR(rcv[i][0]) + |
| 1610 | DIMM_BOT_COR_ERR(rcv[i][0]); |
| 1611 | new1 = DIMM_TOP_COR_ERR(rcv[i][1]) + |
| 1612 | DIMM_BOT_COR_ERR(rcv[i][1]); |
| 1613 | new2 = 0; |
| 1614 | } |
| 1615 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1616 | i7core_rdimm_update_ce_count(mci, i, new0, new1, new2); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1617 | } |
| 1618 | } |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1619 | |
| 1620 | /* This function is based on the device 3 function 4 registers as described on: |
| 1621 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 |
| 1622 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf |
| 1623 | * also available at: |
| 1624 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
| 1625 | */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1626 | static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1627 | { |
| 1628 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1629 | u32 rcv1, rcv0; |
| 1630 | int new0, new1, new2; |
| 1631 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1632 | if (!pvt->pci_mcr[4]) { |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 1633 | debugf0("%s MCR registers not found\n", __func__); |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1634 | return; |
| 1635 | } |
| 1636 | |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1637 | /* Corrected test errors */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1638 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); |
| 1639 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1640 | |
| 1641 | /* Store the new values */ |
| 1642 | new2 = DIMM2_COR_ERR(rcv1); |
| 1643 | new1 = DIMM1_COR_ERR(rcv0); |
| 1644 | new0 = DIMM0_COR_ERR(rcv0); |
| 1645 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1646 | /* Updates CE counters if it is not the first time here */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1647 | if (pvt->ce_count_available) { |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1648 | /* Updates CE counters */ |
| 1649 | int add0, add1, add2; |
| 1650 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1651 | add2 = new2 - pvt->udimm_last_ce_count[2]; |
| 1652 | add1 = new1 - pvt->udimm_last_ce_count[1]; |
| 1653 | add0 = new0 - pvt->udimm_last_ce_count[0]; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1654 | |
| 1655 | if (add2 < 0) |
| 1656 | add2 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1657 | pvt->udimm_ce_count[2] += add2; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1658 | |
| 1659 | if (add1 < 0) |
| 1660 | add1 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1661 | pvt->udimm_ce_count[1] += add1; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1662 | |
| 1663 | if (add0 < 0) |
| 1664 | add0 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1665 | pvt->udimm_ce_count[0] += add0; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1666 | |
| 1667 | if (add0 | add1 | add2) |
| 1668 | i7core_printk(KERN_ERR, "New Corrected error(s): " |
| 1669 | "dimm0: +%d, dimm1: +%d, dimm2 +%d\n", |
| 1670 | add0, add1, add2); |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1671 | } else |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1672 | pvt->ce_count_available = 1; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1673 | |
| 1674 | /* Store the new values */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1675 | pvt->udimm_last_ce_count[2] = new2; |
| 1676 | pvt->udimm_last_ce_count[1] = new1; |
| 1677 | pvt->udimm_last_ce_count[0] = new0; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1678 | } |
| 1679 | |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1680 | /* |
| 1681 | * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 |
| 1682 | * Architectures Software Developer’s Manual Volume 3B. |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1683 | * Nehalem are defined as family 0x06, model 0x1a |
| 1684 | * |
| 1685 | * The MCA registers used here are the following ones: |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1686 | * struct mce field MCA Register |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1687 | * m->status MSR_IA32_MC8_STATUS |
| 1688 | * m->addr MSR_IA32_MC8_ADDR |
| 1689 | * m->misc MSR_IA32_MC8_MISC |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1690 | * In the case of Nehalem, the error information is masked at .status and .misc |
| 1691 | * fields |
| 1692 | */ |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1693 | static void i7core_mce_output_error(struct mem_ctl_info *mci, |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1694 | const struct mce *m) |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1695 | { |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1696 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1697 | char *type, *optype, *err, *msg; |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1698 | unsigned long error = m->status & 0x1ff0000l; |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1699 | u32 optypenum = (m->status >> 4) & 0x07; |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1700 | u32 core_err_cnt = (m->status >> 38) && 0x7fff; |
| 1701 | u32 dimm = (m->misc >> 16) & 0x3; |
| 1702 | u32 channel = (m->misc >> 18) & 0x3; |
| 1703 | u32 syndrome = m->misc >> 32; |
| 1704 | u32 errnum = find_first_bit(&error, 32); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1705 | int csrow; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1706 | |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1707 | if (m->mcgstatus & 1) |
| 1708 | type = "FATAL"; |
| 1709 | else |
| 1710 | type = "NON_FATAL"; |
| 1711 | |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1712 | switch (optypenum) { |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 1713 | case 0: |
| 1714 | optype = "generic undef request"; |
| 1715 | break; |
| 1716 | case 1: |
| 1717 | optype = "read error"; |
| 1718 | break; |
| 1719 | case 2: |
| 1720 | optype = "write error"; |
| 1721 | break; |
| 1722 | case 3: |
| 1723 | optype = "addr/cmd error"; |
| 1724 | break; |
| 1725 | case 4: |
| 1726 | optype = "scrubbing error"; |
| 1727 | break; |
| 1728 | default: |
| 1729 | optype = "reserved"; |
| 1730 | break; |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1731 | } |
| 1732 | |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1733 | switch (errnum) { |
| 1734 | case 16: |
| 1735 | err = "read ECC error"; |
| 1736 | break; |
| 1737 | case 17: |
| 1738 | err = "RAS ECC error"; |
| 1739 | break; |
| 1740 | case 18: |
| 1741 | err = "write parity error"; |
| 1742 | break; |
| 1743 | case 19: |
| 1744 | err = "redundacy loss"; |
| 1745 | break; |
| 1746 | case 20: |
| 1747 | err = "reserved"; |
| 1748 | break; |
| 1749 | case 21: |
| 1750 | err = "memory range error"; |
| 1751 | break; |
| 1752 | case 22: |
| 1753 | err = "RTID out of range"; |
| 1754 | break; |
| 1755 | case 23: |
| 1756 | err = "address parity error"; |
| 1757 | break; |
| 1758 | case 24: |
| 1759 | err = "byte enable parity error"; |
| 1760 | break; |
| 1761 | default: |
| 1762 | err = "unknown"; |
| 1763 | } |
| 1764 | |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1765 | /* FIXME: should convert addr into bank and rank information */ |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1766 | msg = kasprintf(GFP_ATOMIC, |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1767 | "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, " |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1768 | "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n", |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1769 | type, (long long) m->addr, m->cpu, dimm, channel, |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1770 | syndrome, core_err_cnt, (long long)m->status, |
| 1771 | (long long)m->misc, optype, err); |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1772 | |
| 1773 | debugf0("%s", msg); |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1774 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1775 | csrow = pvt->csrow_map[channel][dimm]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1776 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1777 | /* Call the helper to output message */ |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1778 | if (m->mcgstatus & 1) |
| 1779 | edac_mc_handle_fbd_ue(mci, csrow, 0, |
| 1780 | 0 /* FIXME: should be channel here */, msg); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1781 | else if (!pvt->is_registered) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1782 | edac_mc_handle_fbd_ce(mci, csrow, |
| 1783 | 0 /* FIXME: should be channel here */, msg); |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1784 | |
| 1785 | kfree(msg); |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1786 | } |
| 1787 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1788 | /* |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1789 | * i7core_check_error Retrieve and process errors reported by the |
| 1790 | * hardware. Called by the Core module. |
| 1791 | */ |
| 1792 | static void i7core_check_error(struct mem_ctl_info *mci) |
| 1793 | { |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1794 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1795 | int i; |
| 1796 | unsigned count = 0; |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1797 | struct mce *m; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1798 | |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1799 | /* |
| 1800 | * MCE first step: Copy all mce errors into a temporary buffer |
| 1801 | * We use a double buffering here, to reduce the risk of |
| 1802 | * loosing an error. |
| 1803 | */ |
| 1804 | smp_rmb(); |
Mauro Carvalho Chehab | 321ece4 | 2009-10-08 13:11:08 -0300 | [diff] [blame] | 1805 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) |
| 1806 | % MCE_LOG_LEN; |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1807 | if (!count) |
Vernon Mauery | 8a311e1 | 2010-04-16 19:40:19 -0300 | [diff] [blame] | 1808 | goto check_ce_error; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1809 | |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1810 | m = pvt->mce_outentry; |
Mauro Carvalho Chehab | 321ece4 | 2009-10-08 13:11:08 -0300 | [diff] [blame] | 1811 | if (pvt->mce_in + count > MCE_LOG_LEN) { |
| 1812 | unsigned l = MCE_LOG_LEN - pvt->mce_in; |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1813 | |
| 1814 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); |
| 1815 | smp_wmb(); |
| 1816 | pvt->mce_in = 0; |
| 1817 | count -= l; |
| 1818 | m += l; |
| 1819 | } |
| 1820 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); |
| 1821 | smp_wmb(); |
| 1822 | pvt->mce_in += count; |
| 1823 | |
| 1824 | smp_rmb(); |
| 1825 | if (pvt->mce_overrun) { |
| 1826 | i7core_printk(KERN_ERR, "Lost %d memory errors\n", |
| 1827 | pvt->mce_overrun); |
| 1828 | smp_wmb(); |
| 1829 | pvt->mce_overrun = 0; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1830 | } |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1831 | |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1832 | /* |
| 1833 | * MCE second step: parse errors and display |
| 1834 | */ |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1835 | for (i = 0; i < count; i++) |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1836 | i7core_mce_output_error(mci, &pvt->mce_outentry[i]); |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1837 | |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1838 | /* |
| 1839 | * Now, let's increment CE error counts |
| 1840 | */ |
Vernon Mauery | 8a311e1 | 2010-04-16 19:40:19 -0300 | [diff] [blame] | 1841 | check_ce_error: |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1842 | if (!pvt->is_registered) |
| 1843 | i7core_udimm_check_mc_ecc_err(mci); |
| 1844 | else |
| 1845 | i7core_rdimm_check_mc_ecc_err(mci); |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1846 | } |
| 1847 | |
| 1848 | /* |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1849 | * i7core_mce_check_error Replicates mcelog routine to get errors |
| 1850 | * This routine simply queues mcelog errors, and |
| 1851 | * return. The error itself should be handled later |
| 1852 | * by i7core_check_error. |
Mauro Carvalho Chehab | 6e103be | 2009-10-05 09:40:09 -0300 | [diff] [blame] | 1853 | * WARNING: As this routine should be called at NMI time, extra care should |
| 1854 | * be taken to avoid deadlocks, and to be as fast as possible. |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1855 | */ |
| 1856 | static int i7core_mce_check_error(void *priv, struct mce *mce) |
| 1857 | { |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1858 | struct mem_ctl_info *mci = priv; |
| 1859 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1860 | |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1861 | /* |
| 1862 | * Just let mcelog handle it if the error is |
| 1863 | * outside the memory controller |
| 1864 | */ |
| 1865 | if (((mce->status & 0xffff) >> 7) != 1) |
| 1866 | return 0; |
| 1867 | |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1868 | /* Bank 8 registers are the only ones that we know how to handle */ |
| 1869 | if (mce->bank != 8) |
| 1870 | return 0; |
| 1871 | |
Randy Dunlap | 3b918c1 | 2009-11-08 01:36:40 -0200 | [diff] [blame] | 1872 | #ifdef CONFIG_SMP |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1873 | /* Only handle if it is the right mc controller */ |
Mauro Carvalho Chehab | 6e103be | 2009-10-05 09:40:09 -0300 | [diff] [blame] | 1874 | if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1875 | return 0; |
Randy Dunlap | 3b918c1 | 2009-11-08 01:36:40 -0200 | [diff] [blame] | 1876 | #endif |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1877 | |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1878 | smp_rmb(); |
Mauro Carvalho Chehab | 321ece4 | 2009-10-08 13:11:08 -0300 | [diff] [blame] | 1879 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1880 | smp_wmb(); |
| 1881 | pvt->mce_overrun++; |
| 1882 | return 0; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1883 | } |
Mauro Carvalho Chehab | 6e103be | 2009-10-05 09:40:09 -0300 | [diff] [blame] | 1884 | |
| 1885 | /* Copy memory error at the ringbuffer */ |
| 1886 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); |
Mauro Carvalho Chehab | ca9c90b | 2009-10-04 10:15:40 -0300 | [diff] [blame] | 1887 | smp_wmb(); |
Mauro Carvalho Chehab | 321ece4 | 2009-10-08 13:11:08 -0300 | [diff] [blame] | 1888 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1889 | |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1890 | /* Handle fatal errors immediately */ |
| 1891 | if (mce->mcgstatus & 1) |
| 1892 | i7core_check_error(mci); |
| 1893 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1894 | /* Advice mcelog that the error were handled */ |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1895 | return 1; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1896 | } |
| 1897 | |
Hidetoshi Seto | a3aa0a4 | 2010-08-20 04:25:18 -0300 | [diff] [blame] | 1898 | static void i7core_pci_ctl_create(struct i7core_pvt *pvt) |
| 1899 | { |
| 1900 | pvt->i7core_pci = edac_pci_create_generic_ctl( |
| 1901 | &pvt->i7core_dev->pdev[0]->dev, |
| 1902 | EDAC_MOD_STR); |
| 1903 | if (unlikely(!pvt->i7core_pci)) |
| 1904 | pr_warn("Unable to setup PCI error report via EDAC\n"); |
| 1905 | } |
| 1906 | |
| 1907 | static void i7core_pci_ctl_release(struct i7core_pvt *pvt) |
| 1908 | { |
| 1909 | if (likely(pvt->i7core_pci)) |
| 1910 | edac_pci_release_generic_ctl(pvt->i7core_pci); |
| 1911 | else |
| 1912 | i7core_printk(KERN_ERR, |
| 1913 | "Couldn't find mem_ctl_info for socket %d\n", |
| 1914 | pvt->i7core_dev->socket); |
| 1915 | pvt->i7core_pci = NULL; |
| 1916 | } |
| 1917 | |
Hidetoshi Seto | 1c6edbb | 2010-08-20 04:32:33 -0300 | [diff] [blame] | 1918 | static void i7core_unregister_mci(struct i7core_dev *i7core_dev) |
| 1919 | { |
| 1920 | struct mem_ctl_info *mci = i7core_dev->mci; |
| 1921 | struct i7core_pvt *pvt; |
| 1922 | |
| 1923 | if (unlikely(!mci || !mci->pvt_info)) { |
| 1924 | debugf0("MC: " __FILE__ ": %s(): dev = %p\n", |
| 1925 | __func__, &i7core_dev->pdev[0]->dev); |
| 1926 | |
| 1927 | i7core_printk(KERN_ERR, "Couldn't find mci handler\n"); |
| 1928 | return; |
| 1929 | } |
| 1930 | |
| 1931 | pvt = mci->pvt_info; |
| 1932 | |
| 1933 | debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n", |
| 1934 | __func__, mci, &i7core_dev->pdev[0]->dev); |
| 1935 | |
| 1936 | /* Disable MCE NMI handler */ |
| 1937 | edac_mce_unregister(&pvt->edac_mce); |
| 1938 | |
| 1939 | /* Disable EDAC polling */ |
| 1940 | i7core_pci_ctl_release(pvt); |
| 1941 | |
| 1942 | /* Remove MC sysfs nodes */ |
| 1943 | edac_mc_del_mc(mci->dev); |
| 1944 | |
| 1945 | debugf1("%s: free mci struct\n", mci->ctl_name); |
| 1946 | kfree(mci->ctl_name); |
| 1947 | edac_mc_free(mci); |
| 1948 | i7core_dev->mci = NULL; |
| 1949 | } |
| 1950 | |
Hidetoshi Seto | aace428 | 2010-08-20 04:32:45 -0300 | [diff] [blame] | 1951 | static int i7core_register_mci(struct i7core_dev *i7core_dev) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1952 | { |
| 1953 | struct mem_ctl_info *mci; |
| 1954 | struct i7core_pvt *pvt; |
Hidetoshi Seto | aace428 | 2010-08-20 04:32:45 -0300 | [diff] [blame] | 1955 | int rc, channels, csrows; |
| 1956 | |
| 1957 | /* Check the number of active and not disabled channels */ |
| 1958 | rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows); |
| 1959 | if (unlikely(rc < 0)) |
| 1960 | return rc; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1961 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1962 | /* allocate a new MC control structure */ |
Hidetoshi Seto | aace428 | 2010-08-20 04:32:45 -0300 | [diff] [blame] | 1963 | mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1964 | if (unlikely(!mci)) |
| 1965 | return -ENOMEM; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1966 | |
Mauro Carvalho Chehab | 3cfd014 | 2010-08-10 23:23:46 -0300 | [diff] [blame] | 1967 | debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n", |
| 1968 | __func__, mci, &i7core_dev->pdev[0]->dev); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1969 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1970 | pvt = mci->pvt_info; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1971 | memset(pvt, 0, sizeof(*pvt)); |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 1972 | |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 1973 | /* |
| 1974 | * FIXME: how to handle RDDR3 at MCI level? It is possible to have |
| 1975 | * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different |
| 1976 | * memory channels |
| 1977 | */ |
| 1978 | mci->mtype_cap = MEM_FLAG_DDR3; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1979 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
| 1980 | mci->edac_cap = EDAC_FLAG_NONE; |
| 1981 | mci->mod_name = "i7core_edac.c"; |
| 1982 | mci->mod_ver = I7CORE_REVISION; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1983 | mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", |
| 1984 | i7core_dev->socket); |
| 1985 | mci->dev_name = pci_name(i7core_dev->pdev[0]); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1986 | mci->ctl_page_to_phys = NULL; |
Mauro Carvalho Chehab | 1288c18 | 2010-08-10 18:57:01 -0300 | [diff] [blame] | 1987 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1988 | /* Store pci devices at mci for faster access */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1989 | rc = mci_bind_devs(mci, i7core_dev); |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 1990 | if (unlikely(rc < 0)) |
Hidetoshi Seto | 628c5dd | 2010-08-20 04:28:40 -0300 | [diff] [blame] | 1991 | goto fail0; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1992 | |
Hidetoshi Seto | 5939813 | 2010-08-20 04:28:25 -0300 | [diff] [blame] | 1993 | if (pvt->is_registered) |
| 1994 | mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs; |
| 1995 | else |
| 1996 | mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs; |
| 1997 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1998 | /* Get dimm basic config */ |
Hidetoshi Seto | 2e5185f | 2010-08-20 04:32:56 -0300 | [diff] [blame^] | 1999 | get_dimm_config(mci); |
Hidetoshi Seto | 5939813 | 2010-08-20 04:28:25 -0300 | [diff] [blame] | 2000 | /* record ptr to the generic device */ |
| 2001 | mci->dev = &i7core_dev->pdev[0]->dev; |
| 2002 | /* Set the function pointer to an actual operation function */ |
| 2003 | mci->edac_check = i7core_check_error; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 2004 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2005 | /* add this new MC control structure to EDAC's list of MCs */ |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 2006 | if (unlikely(edac_mc_add_mc(mci))) { |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2007 | debugf0("MC: " __FILE__ |
| 2008 | ": %s(): failed edac_mc_add_mc()\n", __func__); |
| 2009 | /* FIXME: perhaps some code should go here that disables error |
| 2010 | * reporting if we just enabled it |
| 2011 | */ |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 2012 | |
| 2013 | rc = -EINVAL; |
Hidetoshi Seto | 628c5dd | 2010-08-20 04:28:40 -0300 | [diff] [blame] | 2014 | goto fail0; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2015 | } |
| 2016 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 2017 | /* Default error mask is any memory */ |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 2018 | pvt->inject.channel = 0; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 2019 | pvt->inject.dimm = -1; |
| 2020 | pvt->inject.rank = -1; |
| 2021 | pvt->inject.bank = -1; |
| 2022 | pvt->inject.page = -1; |
| 2023 | pvt->inject.col = -1; |
| 2024 | |
Hidetoshi Seto | a3aa0a4 | 2010-08-20 04:25:18 -0300 | [diff] [blame] | 2025 | /* allocating generic PCI control info */ |
| 2026 | i7core_pci_ctl_create(pvt); |
| 2027 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 2028 | /* Registers on edac_mce in order to receive memory errors */ |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 2029 | pvt->edac_mce.priv = mci; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 2030 | pvt->edac_mce.check_error = i7core_mce_check_error; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 2031 | rc = edac_mce_register(&pvt->edac_mce); |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 2032 | if (unlikely(rc < 0)) { |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 2033 | debugf0("MC: " __FILE__ |
| 2034 | ": %s(): failed edac_mce_register()\n", __func__); |
Hidetoshi Seto | 628c5dd | 2010-08-20 04:28:40 -0300 | [diff] [blame] | 2035 | goto fail1; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2036 | } |
| 2037 | |
Hidetoshi Seto | 1c6edbb | 2010-08-20 04:32:33 -0300 | [diff] [blame] | 2038 | /* Associates i7core_dev and mci for future usage */ |
| 2039 | pvt->i7core_dev = i7core_dev; |
| 2040 | i7core_dev->mci = mci; |
| 2041 | |
Hidetoshi Seto | 628c5dd | 2010-08-20 04:28:40 -0300 | [diff] [blame] | 2042 | return 0; |
| 2043 | |
| 2044 | fail1: |
| 2045 | i7core_pci_ctl_release(pvt); |
| 2046 | edac_mc_del_mc(mci->dev); |
| 2047 | fail0: |
| 2048 | kfree(mci->ctl_name); |
| 2049 | edac_mc_free(mci); |
Hidetoshi Seto | 1c6edbb | 2010-08-20 04:32:33 -0300 | [diff] [blame] | 2050 | i7core_dev->mci = NULL; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2051 | return rc; |
| 2052 | } |
| 2053 | |
| 2054 | /* |
| 2055 | * i7core_probe Probe for ONE instance of device to see if it is |
| 2056 | * present. |
| 2057 | * return: |
| 2058 | * 0 for FOUND a device |
| 2059 | * < 0 for error code |
| 2060 | */ |
Mauro Carvalho Chehab | 2d95d81 | 2010-06-30 01:42:21 -0300 | [diff] [blame] | 2061 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2062 | static int __devinit i7core_probe(struct pci_dev *pdev, |
| 2063 | const struct pci_device_id *id) |
| 2064 | { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2065 | int rc; |
| 2066 | struct i7core_dev *i7core_dev; |
| 2067 | |
Mauro Carvalho Chehab | 2d95d81 | 2010-06-30 01:42:21 -0300 | [diff] [blame] | 2068 | /* get the pci devices we want to reserve for our use */ |
| 2069 | mutex_lock(&i7core_edac_lock); |
| 2070 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2071 | /* |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 2072 | * All memory controllers are allocated at the first pass. |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2073 | */ |
Mauro Carvalho Chehab | 2d95d81 | 2010-06-30 01:42:21 -0300 | [diff] [blame] | 2074 | if (unlikely(probed >= 1)) { |
| 2075 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2076 | return -EINVAL; |
Mauro Carvalho Chehab | 2d95d81 | 2010-06-30 01:42:21 -0300 | [diff] [blame] | 2077 | } |
| 2078 | probed++; |
Mauro Carvalho Chehab | de06eee | 2009-10-14 08:02:40 -0300 | [diff] [blame] | 2079 | |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 2080 | rc = i7core_get_all_devices(); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 2081 | if (unlikely(rc < 0)) |
| 2082 | goto fail0; |
| 2083 | |
| 2084 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { |
Hidetoshi Seto | aace428 | 2010-08-20 04:32:45 -0300 | [diff] [blame] | 2085 | rc = i7core_register_mci(i7core_dev); |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 2086 | if (unlikely(rc < 0)) |
| 2087 | goto fail1; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 2088 | } |
| 2089 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 2090 | i7core_printk(KERN_INFO, "Driver loaded.\n"); |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 2091 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 2092 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2093 | return 0; |
| 2094 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 2095 | fail1: |
Hidetoshi Seto | 1c6edbb | 2010-08-20 04:32:33 -0300 | [diff] [blame] | 2096 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { |
| 2097 | if (i7core_dev->mci) |
| 2098 | i7core_unregister_mci(i7core_dev); |
| 2099 | } |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 2100 | i7core_put_all_devices(); |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 2101 | fail0: |
| 2102 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 2103 | return rc; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2104 | } |
| 2105 | |
| 2106 | /* |
| 2107 | * i7core_remove destructor for one instance of device |
| 2108 | * |
| 2109 | */ |
| 2110 | static void __devexit i7core_remove(struct pci_dev *pdev) |
| 2111 | { |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 2112 | struct i7core_dev *i7core_dev; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2113 | |
| 2114 | debugf0(__FILE__ ": %s()\n", __func__); |
| 2115 | |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 2116 | /* |
| 2117 | * we have a trouble here: pdev value for removal will be wrong, since |
| 2118 | * it will point to the X58 register used to detect that the machine |
| 2119 | * is a Nehalem or upper design. However, due to the way several PCI |
| 2120 | * devices are grouped together to provide MC functionality, we need |
| 2121 | * to use a different method for releasing the devices |
| 2122 | */ |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 2123 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 2124 | mutex_lock(&i7core_edac_lock); |
Hidetoshi Seto | 71fe017 | 2010-08-20 04:29:47 -0300 | [diff] [blame] | 2125 | |
| 2126 | if (unlikely(!probed)) { |
| 2127 | mutex_unlock(&i7core_edac_lock); |
| 2128 | return; |
| 2129 | } |
| 2130 | |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 2131 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { |
Hidetoshi Seto | 1c6edbb | 2010-08-20 04:32:33 -0300 | [diff] [blame] | 2132 | if (i7core_dev->mci) |
| 2133 | i7core_unregister_mci(i7core_dev); |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 2134 | } |
Hidetoshi Seto | 64c10f6 | 2010-08-20 04:28:14 -0300 | [diff] [blame] | 2135 | |
| 2136 | /* Release PCI resources */ |
| 2137 | i7core_put_all_devices(); |
| 2138 | |
Mauro Carvalho Chehab | 2d95d81 | 2010-06-30 01:42:21 -0300 | [diff] [blame] | 2139 | probed--; |
| 2140 | |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 2141 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2142 | } |
| 2143 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2144 | MODULE_DEVICE_TABLE(pci, i7core_pci_tbl); |
| 2145 | |
| 2146 | /* |
| 2147 | * i7core_driver pci_driver structure for this module |
| 2148 | * |
| 2149 | */ |
| 2150 | static struct pci_driver i7core_driver = { |
| 2151 | .name = "i7core_edac", |
| 2152 | .probe = i7core_probe, |
| 2153 | .remove = __devexit_p(i7core_remove), |
| 2154 | .id_table = i7core_pci_tbl, |
| 2155 | }; |
| 2156 | |
| 2157 | /* |
| 2158 | * i7core_init Module entry function |
| 2159 | * Try to initialize this module for its devices |
| 2160 | */ |
| 2161 | static int __init i7core_init(void) |
| 2162 | { |
| 2163 | int pci_rc; |
| 2164 | |
| 2165 | debugf2("MC: " __FILE__ ": %s()\n", __func__); |
| 2166 | |
| 2167 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 2168 | opstate_init(); |
| 2169 | |
Mauro Carvalho Chehab | 54a08ab | 2010-08-19 15:51:00 -0300 | [diff] [blame] | 2170 | if (use_pci_fixup) |
| 2171 | i7core_xeon_pci_fixup(pci_dev_table); |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 2172 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2173 | pci_rc = pci_register_driver(&i7core_driver); |
| 2174 | |
Mauro Carvalho Chehab | 3ef288a | 2009-09-02 23:43:33 -0300 | [diff] [blame] | 2175 | if (pci_rc >= 0) |
| 2176 | return 0; |
| 2177 | |
| 2178 | i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", |
| 2179 | pci_rc); |
| 2180 | |
| 2181 | return pci_rc; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 2182 | } |
| 2183 | |
| 2184 | /* |
| 2185 | * i7core_exit() Module exit function |
| 2186 | * Unregister the driver |
| 2187 | */ |
| 2188 | static void __exit i7core_exit(void) |
| 2189 | { |
| 2190 | debugf2("MC: " __FILE__ ": %s()\n", __func__); |
| 2191 | pci_unregister_driver(&i7core_driver); |
| 2192 | } |
| 2193 | |
| 2194 | module_init(i7core_init); |
| 2195 | module_exit(i7core_exit); |
| 2196 | |
| 2197 | MODULE_LICENSE("GPL"); |
| 2198 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); |
| 2199 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
| 2200 | MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " |
| 2201 | I7CORE_REVISION); |
| 2202 | |
| 2203 | module_param(edac_op_state, int, 0444); |
| 2204 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |