Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 1 | /* |
Eric Miao | 38f539a | 2009-01-20 12:09:06 +0800 | [diff] [blame] | 2 | * linux/arch/arm/plat-pxa/gpio.c |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 3 | * |
| 4 | * Generic PXA GPIO handling |
| 5 | * |
| 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 |
| 8 | * Copyright: MontaVista Software Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
Russell King | 2f8163b | 2011-07-26 10:53:52 +0100 | [diff] [blame^] | 14 | #include <linux/gpio.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 15 | #include <linux/init.h> |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 16 | #include <linux/irq.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 17 | #include <linux/io.h> |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 18 | #include <linux/syscore_ops.h> |
Daniel Mack | 4aa7826 | 2009-06-19 22:56:09 +0200 | [diff] [blame] | 19 | #include <linux/slab.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 20 | |
Eric Miao | 3b8e285 | 2009-01-07 11:30:49 +0800 | [diff] [blame] | 21 | int pxa_last_gpio; |
| 22 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 23 | struct pxa_gpio_chip { |
| 24 | struct gpio_chip chip; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 25 | void __iomem *regbase; |
| 26 | char label[10]; |
| 27 | |
| 28 | unsigned long irq_mask; |
| 29 | unsigned long irq_edge_rise; |
| 30 | unsigned long irq_edge_fall; |
| 31 | |
| 32 | #ifdef CONFIG_PM |
| 33 | unsigned long saved_gplr; |
| 34 | unsigned long saved_gpdr; |
| 35 | unsigned long saved_grer; |
| 36 | unsigned long saved_gfer; |
| 37 | #endif |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 38 | }; |
| 39 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 40 | static DEFINE_SPINLOCK(gpio_lock); |
| 41 | static struct pxa_gpio_chip *pxa_gpio_chips; |
| 42 | |
| 43 | #define for_each_gpio_chip(i, c) \ |
| 44 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) |
| 45 | |
| 46 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) |
| 47 | { |
| 48 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; |
| 49 | } |
| 50 | |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 51 | static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 52 | { |
| 53 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; |
| 54 | } |
| 55 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 56 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 57 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 58 | void __iomem *base = gpio_chip_base(chip); |
| 59 | uint32_t value, mask = 1 << offset; |
| 60 | unsigned long flags; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 61 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 62 | spin_lock_irqsave(&gpio_lock, flags); |
| 63 | |
| 64 | value = __raw_readl(base + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 65 | if (__gpio_is_inverted(chip->base + offset)) |
| 66 | value |= mask; |
| 67 | else |
| 68 | value &= ~mask; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 69 | __raw_writel(value, base + GPDR_OFFSET); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 70 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 71 | spin_unlock_irqrestore(&gpio_lock, flags); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static int pxa_gpio_direction_output(struct gpio_chip *chip, |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 76 | unsigned offset, int value) |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 77 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 78 | void __iomem *base = gpio_chip_base(chip); |
| 79 | uint32_t tmp, mask = 1 << offset; |
| 80 | unsigned long flags; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 81 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 82 | __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
| 83 | |
| 84 | spin_lock_irqsave(&gpio_lock, flags); |
| 85 | |
| 86 | tmp = __raw_readl(base + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 87 | if (__gpio_is_inverted(chip->base + offset)) |
| 88 | tmp &= ~mask; |
| 89 | else |
| 90 | tmp |= mask; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 91 | __raw_writel(tmp, base + GPDR_OFFSET); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 92 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 93 | spin_unlock_irqrestore(&gpio_lock, flags); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 94 | return 0; |
| 95 | } |
| 96 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 97 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 98 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 99 | return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 100 | } |
| 101 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 102 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 103 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 104 | __raw_writel(1 << offset, gpio_chip_base(chip) + |
| 105 | (value ? GPSR_OFFSET : GPCR_OFFSET)); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 106 | } |
| 107 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 108 | static int __init pxa_init_gpio_chip(int gpio_end) |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 109 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 110 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; |
| 111 | struct pxa_gpio_chip *chips; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 112 | |
Daniel Mack | 4aa7826 | 2009-06-19 22:56:09 +0200 | [diff] [blame] | 113 | chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 114 | if (chips == NULL) { |
| 115 | pr_err("%s: failed to allocate GPIO chips\n", __func__); |
| 116 | return -ENOMEM; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 117 | } |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 118 | |
| 119 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
| 120 | struct gpio_chip *c = &chips[i].chip; |
| 121 | |
| 122 | sprintf(chips[i].label, "gpio-%d", i); |
| 123 | chips[i].regbase = (void __iomem *)GPIO_BANK(i); |
| 124 | |
| 125 | c->base = gpio; |
| 126 | c->label = chips[i].label; |
| 127 | |
| 128 | c->direction_input = pxa_gpio_direction_input; |
| 129 | c->direction_output = pxa_gpio_direction_output; |
| 130 | c->get = pxa_gpio_get; |
| 131 | c->set = pxa_gpio_set; |
| 132 | |
| 133 | /* number of GPIOs on last bank may be less than 32 */ |
| 134 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; |
| 135 | gpiochip_add(c); |
| 136 | } |
| 137 | pxa_gpio_chips = chips; |
| 138 | return 0; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 139 | } |
| 140 | |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 141 | /* Update only those GRERx and GFERx edge detection register bits if those |
| 142 | * bits are set in c->irq_mask |
| 143 | */ |
| 144 | static inline void update_edge_detect(struct pxa_gpio_chip *c) |
| 145 | { |
| 146 | uint32_t grer, gfer; |
| 147 | |
| 148 | grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
| 149 | gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask; |
| 150 | grer |= c->irq_edge_rise & c->irq_mask; |
| 151 | gfer |= c->irq_edge_fall & c->irq_mask; |
| 152 | __raw_writel(grer, c->regbase + GRER_OFFSET); |
| 153 | __raw_writel(gfer, c->regbase + GFER_OFFSET); |
| 154 | } |
| 155 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 156 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 157 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 158 | struct pxa_gpio_chip *c; |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 159 | int gpio = irq_to_gpio(d->irq); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 160 | unsigned long gpdr, mask = GPIO_bit(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 161 | |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 162 | c = gpio_to_pxachip(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 163 | |
| 164 | if (type == IRQ_TYPE_PROBE) { |
| 165 | /* Don't mess with enabled GPIOs using preconfigured edges or |
| 166 | * GPIOs set to alternate function or to output during probe |
| 167 | */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 168 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 169 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 170 | |
| 171 | if (__gpio_is_occupied(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 172 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 173 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 174 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 175 | } |
| 176 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 177 | gpdr = __raw_readl(c->regbase + GPDR_OFFSET); |
| 178 | |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 179 | if (__gpio_is_inverted(gpio)) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 180 | __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 181 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 182 | __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 183 | |
| 184 | if (type & IRQ_TYPE_EDGE_RISING) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 185 | c->irq_edge_rise |= mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 186 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 187 | c->irq_edge_rise &= ~mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 188 | |
| 189 | if (type & IRQ_TYPE_EDGE_FALLING) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 190 | c->irq_edge_fall |= mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 191 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 192 | c->irq_edge_fall &= ~mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 193 | |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 194 | update_edge_detect(c); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 195 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 196 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 197 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
| 198 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); |
| 199 | return 0; |
| 200 | } |
| 201 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 202 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
| 203 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 204 | struct pxa_gpio_chip *c; |
| 205 | int loop, gpio, gpio_base, n; |
| 206 | unsigned long gedr; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 207 | |
| 208 | do { |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 209 | loop = 0; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 210 | for_each_gpio_chip(gpio, c) { |
| 211 | gpio_base = c->chip.base; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 212 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 213 | gedr = __raw_readl(c->regbase + GEDR_OFFSET); |
| 214 | gedr = gedr & c->irq_mask; |
| 215 | __raw_writel(gedr, c->regbase + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 216 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 217 | n = find_first_bit(&gedr, BITS_PER_LONG); |
| 218 | while (n < BITS_PER_LONG) { |
| 219 | loop = 1; |
| 220 | |
| 221 | generic_handle_irq(gpio_to_irq(gpio_base + n)); |
| 222 | n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); |
| 223 | } |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 224 | } |
| 225 | } while (loop); |
| 226 | } |
| 227 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 228 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 229 | { |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 230 | int gpio = irq_to_gpio(d->irq); |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 231 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 232 | |
| 233 | __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 234 | } |
| 235 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 236 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 237 | { |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 238 | int gpio = irq_to_gpio(d->irq); |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 239 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 240 | uint32_t grer, gfer; |
| 241 | |
| 242 | c->irq_mask &= ~GPIO_bit(gpio); |
| 243 | |
| 244 | grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); |
| 245 | gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); |
| 246 | __raw_writel(grer, c->regbase + GRER_OFFSET); |
| 247 | __raw_writel(gfer, c->regbase + GFER_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 248 | } |
| 249 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 250 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 251 | { |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 252 | int gpio = irq_to_gpio(d->irq); |
Linus Walleij | a065685 | 2011-06-13 10:42:19 +0200 | [diff] [blame] | 253 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 254 | |
| 255 | c->irq_mask |= GPIO_bit(gpio); |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 256 | update_edge_detect(c); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | static struct irq_chip pxa_muxed_gpio_chip = { |
| 260 | .name = "GPIO", |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 261 | .irq_ack = pxa_ack_muxed_gpio, |
| 262 | .irq_mask = pxa_mask_muxed_gpio, |
| 263 | .irq_unmask = pxa_unmask_muxed_gpio, |
| 264 | .irq_set_type = pxa_gpio_irq_type, |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 265 | }; |
| 266 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 267 | void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 268 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 269 | struct pxa_gpio_chip *c; |
| 270 | int gpio, irq; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 271 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 272 | pxa_last_gpio = end; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 273 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 274 | /* Initialize GPIO chips */ |
| 275 | pxa_init_gpio_chip(end); |
| 276 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 277 | /* clear all GPIO edge detects */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 278 | for_each_gpio_chip(gpio, c) { |
| 279 | __raw_writel(0, c->regbase + GFER_OFFSET); |
| 280 | __raw_writel(0, c->regbase + GRER_OFFSET); |
| 281 | __raw_writel(~0,c->regbase + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 282 | } |
| 283 | |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 284 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 285 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
| 286 | handle_edge_irq); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 287 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 288 | } |
| 289 | |
| 290 | /* Install handler for GPIO>=2 edge detect interrupts */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 291 | irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler); |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 292 | pxa_muxed_gpio_chip.irq_set_wake = fn; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 293 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 294 | |
| 295 | #ifdef CONFIG_PM |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 296 | static int pxa_gpio_suspend(void) |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 297 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 298 | struct pxa_gpio_chip *c; |
| 299 | int gpio; |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 300 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 301 | for_each_gpio_chip(gpio, c) { |
| 302 | c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET); |
| 303 | c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET); |
| 304 | c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET); |
| 305 | c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 306 | |
| 307 | /* Clear GPIO transition detect bits */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 308 | __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 309 | } |
| 310 | return 0; |
| 311 | } |
| 312 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 313 | static void pxa_gpio_resume(void) |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 314 | { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 315 | struct pxa_gpio_chip *c; |
| 316 | int gpio; |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 317 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 318 | for_each_gpio_chip(gpio, c) { |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 319 | /* restore level with set/clear */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 320 | __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET); |
| 321 | __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 322 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 323 | __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET); |
| 324 | __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); |
| 325 | __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 326 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 327 | } |
| 328 | #else |
| 329 | #define pxa_gpio_suspend NULL |
| 330 | #define pxa_gpio_resume NULL |
| 331 | #endif |
| 332 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 333 | struct syscore_ops pxa_gpio_syscore_ops = { |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 334 | .suspend = pxa_gpio_suspend, |
| 335 | .resume = pxa_gpio_resume, |
| 336 | }; |