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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
Alexander Beregalov1737ef72009-01-29 02:30:56 +030047#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "sata_sil"
Robert Hancockc7e324f2008-12-24 19:06:06 -060050#define DRV_VERSION "2.4"
51
52#define SIL_DMA_BOUNDARY 0x7fffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090055 SIL_MMIO_BAR = 5,
56
Tejun Heoe653a1e2006-03-05 16:03:52 +090057 /*
58 * host flags
59 */
Tejun Heo201ce852006-06-26 21:23:52 +090060 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
Tejun Heoe4e10e32006-02-25 13:52:30 +090061 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
Tejun Heoe4deec62005-08-23 07:27:25 +090062 SIL_FLAG_MOD15WRITE = (1 << 30),
Tejun Heo20888d82006-05-31 18:27:53 +090063
Jeff Garzikcca39742006-08-24 03:19:22 -040064 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo0c887582007-08-06 18:36:23 +090065 ATA_FLAG_MMIO,
Tejun Heoe4deec62005-08-23 07:27:25 +090066
Tejun Heoe653a1e2006-03-05 16:03:52 +090067 /*
68 * Controller IDs
69 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070070 sil_3112 = 0,
Tejun Heo201ce852006-06-26 21:23:52 +090071 sil_3112_no_sata_irq = 1,
72 sil_3512 = 2,
73 sil_3114 = 3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
Tejun Heoe653a1e2006-03-05 16:03:52 +090075 /*
76 * Register offsets
77 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 SIL_SYSCFG = 0x48,
Tejun Heoe653a1e2006-03-05 16:03:52 +090079
80 /*
81 * Register bits
82 */
83 /* SYSCFG */
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 SIL_MASK_IDE0_INT = (1 << 22),
85 SIL_MASK_IDE1_INT = (1 << 23),
86 SIL_MASK_IDE2_INT = (1 << 24),
87 SIL_MASK_IDE3_INT = (1 << 25),
88 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
89 SIL_MASK_4PORT = SIL_MASK_2PORT |
90 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
91
Tejun Heoe653a1e2006-03-05 16:03:52 +090092 /* BMDMA/BMDMA2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 SIL_INTR_STEERING = (1 << 1),
Tejun Heoe653a1e2006-03-05 16:03:52 +090094
Tejun Heo20888d82006-05-31 18:27:53 +090095 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
96 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
97 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
98 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
99 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
100 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
101 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
102 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
103 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
104 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
105
106 /* SIEN */
107 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
108
Tejun Heoe653a1e2006-03-05 16:03:52 +0900109 /*
110 * Others
111 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 SIL_QUIRK_MOD15WRITE = (1 << 0),
113 SIL_QUIRK_UDMA5MAX = (1 << 1),
114};
115
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400116static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700117#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900118static int sil_pci_device_resume(struct pci_dev *pdev);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700119#endif
Alancd0d3bb2007-03-02 00:56:15 +0000120static void sil_dev_config(struct ata_device *dev);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900121static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
122static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Tejun Heo02607312007-08-06 18:36:23 +0900123static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
Robert Hancockc7e324f2008-12-24 19:06:06 -0600124static void sil_qc_prep(struct ata_queued_cmd *qc);
125static void sil_bmdma_setup(struct ata_queued_cmd *qc);
126static void sil_bmdma_start(struct ata_queued_cmd *qc);
127static void sil_bmdma_stop(struct ata_queued_cmd *qc);
Tejun Heof6aae272006-05-15 20:58:27 +0900128static void sil_freeze(struct ata_port *ap);
129static void sil_thaw(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
Jeff Garzik374b1872005-08-30 05:42:52 -0400131
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500132static const struct pci_device_id sil_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400133 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
134 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
135 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
136 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
137 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
138 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
139 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 { } /* terminate list */
142};
143
144
145/* TODO firmware versions should be added - eric */
146static const struct sil_drivelist {
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400147 const char *product;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 unsigned int quirk;
149} sil_blacklist [] = {
150 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
151 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
152 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
153 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
155 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
157 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
158 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
159 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
160 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
161 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
162 { }
163};
164
165static struct pci_driver sil_pci_driver = {
166 .name = DRV_NAME,
167 .id_table = sil_pci_tbl,
168 .probe = sil_init_one,
169 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700170#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900171 .suspend = ata_pci_device_suspend,
172 .resume = sil_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700173#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174};
175
Jeff Garzik193515d2005-11-07 00:59:37 -0500176static struct scsi_host_template sil_sht = {
Robert Hancockc7e324f2008-12-24 19:06:06 -0600177 ATA_BASE_SHT(DRV_NAME),
178 /** These controllers support Large Block Transfer which allows
179 transfer chunks up to 2GB and which cross 64KB boundaries,
180 therefore the DMA limits are more relaxed than standard ATA SFF. */
181 .dma_boundary = SIL_DMA_BOUNDARY,
182 .sg_tablesize = ATA_MAX_PRD
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183};
184
Tejun Heo029cfd62008-03-25 12:22:49 +0900185static struct ata_port_operations sil_ops = {
Robert Hancock31f80112009-04-13 22:57:28 -0600186 .inherits = &ata_bmdma32_port_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 .dev_config = sil_dev_config,
Alan Cox9d2c7c72007-03-08 23:09:12 +0000188 .set_mode = sil_set_mode,
Robert Hancockc7e324f2008-12-24 19:06:06 -0600189 .bmdma_setup = sil_bmdma_setup,
190 .bmdma_start = sil_bmdma_start,
191 .bmdma_stop = sil_bmdma_stop,
192 .qc_prep = sil_qc_prep,
Tejun Heof6aae272006-05-15 20:58:27 +0900193 .freeze = sil_freeze,
194 .thaw = sil_thaw,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 .scr_read = sil_scr_read,
196 .scr_write = sil_scr_write,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197};
198
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100199static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 /* sil_3112 */
201 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400202 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100203 .pio_mask = ATA_PIO4,
204 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400205 .udma_mask = ATA_UDMA5,
Tejun Heoe4deec62005-08-23 07:27:25 +0900206 .port_ops = &sil_ops,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900207 },
Tejun Heo201ce852006-06-26 21:23:52 +0900208 /* sil_3112_no_sata_irq */
209 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400210 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
Tejun Heo201ce852006-06-26 21:23:52 +0900211 SIL_FLAG_NO_SATA_IRQ,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100212 .pio_mask = ATA_PIO4,
213 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400214 .udma_mask = ATA_UDMA5,
Tejun Heo201ce852006-06-26 21:23:52 +0900215 .port_ops = &sil_ops,
216 },
Tejun Heo0ee304d2006-02-25 13:52:30 +0900217 /* sil_3512 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400219 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100220 .pio_mask = ATA_PIO4,
221 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400222 .udma_mask = ATA_UDMA5,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900223 .port_ops = &sil_ops,
224 },
225 /* sil_3114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400227 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100228 .pio_mask = ATA_PIO4,
229 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400230 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 .port_ops = &sil_ops,
232 },
233};
234
235/* per-port register offsets */
236/* TODO: we can probably calculate rather than use a table */
237static const struct {
238 unsigned long tf; /* ATA taskfile register block */
239 unsigned long ctl; /* ATA control/altstatus register block */
240 unsigned long bmdma; /* DMA register block */
Tejun Heo20888d82006-05-31 18:27:53 +0900241 unsigned long bmdma2; /* DMA register block #2 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900242 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 unsigned long scr; /* SATA control register block */
244 unsigned long sien; /* SATA Interrupt Enable register */
245 unsigned long xfer_mode;/* data transfer mode register */
Tejun Heoe4e10e32006-02-25 13:52:30 +0900246 unsigned long sfis_cfg; /* SATA FIS reception config register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247} sil_port[] = {
248 /* port 0 ... */
Jeff Garzik5bcd7a002007-05-26 16:35:42 -0400249 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
250 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
251 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
Tejun Heo20888d82006-05-31 18:27:53 +0900252 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
253 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 /* ... port 3 */
255};
256
257MODULE_AUTHOR("Jeff Garzik");
258MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
259MODULE_LICENSE("GPL");
260MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
261MODULE_VERSION(DRV_VERSION);
262
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400263static int slow_down;
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500264module_param(slow_down, int, 0444);
265MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
266
Jeff Garzik374b1872005-08-30 05:42:52 -0400267
Robert Hancockc7e324f2008-12-24 19:06:06 -0600268static void sil_bmdma_stop(struct ata_queued_cmd *qc)
269{
270 struct ata_port *ap = qc->ap;
271 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
272 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
273
274 /* clear start/stop bit - can safely always write 0 */
275 iowrite8(0, bmdma2);
276
277 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
278 ata_sff_dma_pause(ap);
279}
280
281static void sil_bmdma_setup(struct ata_queued_cmd *qc)
282{
283 struct ata_port *ap = qc->ap;
284 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
285
286 /* load PRD table addr. */
287 iowrite32(ap->prd_dma, bmdma + ATA_DMA_TABLE_OFS);
288
289 /* issue r/w command */
290 ap->ops->sff_exec_command(ap, &qc->tf);
291}
292
293static void sil_bmdma_start(struct ata_queued_cmd *qc)
294{
295 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
296 struct ata_port *ap = qc->ap;
297 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
298 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
299 u8 dmactl = ATA_DMA_START;
300
301 /* set transfer direction, start host DMA transaction
302 Note: For Large Block Transfer to work, the DMA must be started
303 using the bmdma2 register. */
304 if (!rw)
305 dmactl |= ATA_DMA_WR;
306 iowrite8(dmactl, bmdma2);
307}
308
309/* The way God intended PCI IDE scatter/gather lists to look and behave... */
310static void sil_fill_sg(struct ata_queued_cmd *qc)
311{
312 struct scatterlist *sg;
313 struct ata_port *ap = qc->ap;
314 struct ata_prd *prd, *last_prd = NULL;
315 unsigned int si;
316
317 prd = &ap->prd[0];
318 for_each_sg(qc->sg, sg, qc->n_elem, si) {
319 /* Note h/w doesn't support 64-bit, so we unconditionally
320 * truncate dma_addr_t to u32.
321 */
322 u32 addr = (u32) sg_dma_address(sg);
323 u32 sg_len = sg_dma_len(sg);
324
325 prd->addr = cpu_to_le32(addr);
326 prd->flags_len = cpu_to_le32(sg_len);
Pasi Kärkkäinen41137aa2009-02-02 21:47:14 +0200327 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
Robert Hancockc7e324f2008-12-24 19:06:06 -0600328
329 last_prd = prd;
330 prd++;
331 }
332
333 if (likely(last_prd))
334 last_prd->flags_len |= cpu_to_le32(ATA_PRD_EOT);
335}
336
337static void sil_qc_prep(struct ata_queued_cmd *qc)
338{
339 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
340 return;
341
342 sil_fill_sg(qc);
343}
344
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
346{
347 u8 cache_line = 0;
348 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
349 return cache_line;
350}
351
Alan Cox9d2c7c72007-03-08 23:09:12 +0000352/**
353 * sil_set_mode - wrap set_mode functions
Tejun Heo02607312007-08-06 18:36:23 +0900354 * @link: link to set up
Alan Cox9d2c7c72007-03-08 23:09:12 +0000355 * @r_failed: returned device when we fail
356 *
357 * Wrap the libata method for device setup as after the setup we need
358 * to inspect the results and do some configuration work
359 */
360
Tejun Heo02607312007-08-06 18:36:23 +0900361static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362{
Tejun Heo02607312007-08-06 18:36:23 +0900363 struct ata_port *ap = link->ap;
364 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heo0d5ff562007-02-01 15:06:36 +0900365 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
Tejun Heo02607312007-08-06 18:36:23 +0900366 struct ata_device *dev;
Tejun Heof58229f2007-08-06 18:36:23 +0900367 u32 tmp, dev_mode[2] = { };
Alan Cox9d2c7c72007-03-08 23:09:12 +0000368 int rc;
Jeff Garzika617c092007-05-21 20:14:23 -0400369
Tejun Heo02607312007-08-06 18:36:23 +0900370 rc = ata_do_set_mode(link, r_failed);
Alan Cox9d2c7c72007-03-08 23:09:12 +0000371 if (rc)
372 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
Tejun Heo1eca4362008-11-03 20:03:17 +0900374 ata_for_each_dev(dev, link, ALL) {
Tejun Heoe1211e32006-04-01 01:38:18 +0900375 if (!ata_dev_enabled(dev))
Tejun Heof58229f2007-08-06 18:36:23 +0900376 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 else if (dev->flags & ATA_DFLAG_PIO)
Tejun Heof58229f2007-08-06 18:36:23 +0900378 dev_mode[dev->devno] = 1; /* PIO3/4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 else
Tejun Heof58229f2007-08-06 18:36:23 +0900380 dev_mode[dev->devno] = 3; /* UDMA */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 /* value 2 indicates MDMA */
382 }
383
384 tmp = readl(addr);
385 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
386 tmp |= dev_mode[0];
387 tmp |= (dev_mode[1] << 4);
388 writel(tmp, addr);
389 readl(addr); /* flush */
Alan Cox9d2c7c72007-03-08 23:09:12 +0000390 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391}
392
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400393static inline void __iomem *sil_scr_addr(struct ata_port *ap,
394 unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900396 void __iomem *offset = ap->ioaddr.scr_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397
398 switch (sc_reg) {
399 case SCR_STATUS:
400 return offset + 4;
401 case SCR_ERROR:
402 return offset + 8;
403 case SCR_CONTROL:
404 return offset;
405 default:
406 /* do nothing */
407 break;
408 }
409
Randy Dunlap8d9db2d2007-02-16 01:40:06 -0800410 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411}
412
Tejun Heo82ef04f2008-07-31 17:02:40 +0900413static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900415 void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900416
417 if (mmio) {
418 *val = readl(mmio);
419 return 0;
420 }
421 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422}
423
Tejun Heo82ef04f2008-07-31 17:02:40 +0900424static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900426 void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900427
428 if (mmio) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 writel(val, mmio);
Tejun Heoda3dbb12007-07-16 14:29:40 +0900430 return 0;
431 }
432 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433}
434
Tejun Heocbe88fb2006-05-31 18:27:55 +0900435static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
436{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900437 struct ata_eh_info *ehi = &ap->link.eh_info;
438 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900439 u8 status;
440
Tejun Heoe5738902006-05-31 18:28:16 +0900441 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900442 u32 serror;
443
444 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
445 * controllers continue to assert IRQ as long as
446 * SError bits are pending. Clear SError immediately.
447 */
Tejun Heo82ef04f2008-07-31 17:02:40 +0900448 sil_scr_read(&ap->link, SCR_ERROR, &serror);
449 sil_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heod4c85322006-06-12 18:45:55 +0900450
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900451 /* Sometimes spurious interrupts occur, double check
452 * it's PHYRDY CHG.
Tejun Heod4c85322006-06-12 18:45:55 +0900453 */
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900454 if (serror & SERR_PHYRDY_CHG) {
Tejun Heof7fe7ad42007-12-08 08:47:01 +0900455 ap->link.eh_info.serror |= serror;
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900456 goto freeze;
Tejun Heod4c85322006-06-12 18:45:55 +0900457 }
458
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900459 if (!(bmdma2 & SIL_DMA_COMPLETE))
460 return;
Tejun Heoe5738902006-05-31 18:28:16 +0900461 }
462
Tejun Heo8cf32ac2007-12-08 08:45:27 +0900463 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900464 /* this sometimes happens, just clear IRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900465 ap->ops->sff_check_status(ap);
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900466 return;
467 }
468
Tejun Heocbe88fb2006-05-31 18:27:55 +0900469 /* Check whether we are expecting interrupt in this state */
470 switch (ap->hsm_task_state) {
471 case HSM_ST_FIRST:
472 /* Some pre-ATAPI-4 devices assert INTRQ
473 * at this state when ready to receive CDB.
474 */
475
476 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
Tejun Heo405e66b2007-11-27 19:28:53 +0900477 * The flag was turned on only for atapi devices. No
478 * need to check ata_is_atapi(qc->tf.protocol) again.
Tejun Heocbe88fb2006-05-31 18:27:55 +0900479 */
480 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
481 goto err_hsm;
482 break;
483 case HSM_ST_LAST:
Tejun Heo405e66b2007-11-27 19:28:53 +0900484 if (ata_is_dma(qc->tf.protocol)) {
Tejun Heocbe88fb2006-05-31 18:27:55 +0900485 /* clear DMA-Start bit */
486 ap->ops->bmdma_stop(qc);
487
488 if (bmdma2 & SIL_DMA_ERROR) {
489 qc->err_mask |= AC_ERR_HOST_BUS;
490 ap->hsm_task_state = HSM_ST_ERR;
491 }
492 }
493 break;
494 case HSM_ST:
495 break;
496 default:
497 goto err_hsm;
498 }
499
500 /* check main status, clearing INTRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900501 status = ap->ops->sff_check_status(ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900502 if (unlikely(status & ATA_BUSY))
503 goto err_hsm;
504
505 /* ack bmdma irq events */
Tejun Heo9363c382008-04-07 22:47:16 +0900506 ata_sff_irq_clear(ap);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900507
508 /* kick HSM in the ass */
Tejun Heo9363c382008-04-07 22:47:16 +0900509 ata_sff_hsm_move(ap, qc, status, 0);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900510
Tejun Heo405e66b2007-11-27 19:28:53 +0900511 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
Tejun Heoea547632006-11-17 12:06:21 +0900512 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
513
Tejun Heocbe88fb2006-05-31 18:27:55 +0900514 return;
515
516 err_hsm:
517 qc->err_mask |= AC_ERR_HSM;
518 freeze:
519 ata_port_freeze(ap);
520}
521
David Howells7d12e782006-10-05 14:55:46 +0100522static irqreturn_t sil_interrupt(int irq, void *dev_instance)
Tejun Heocbe88fb2006-05-31 18:27:55 +0900523{
Jeff Garzikcca39742006-08-24 03:19:22 -0400524 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900525 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900526 int handled = 0;
527 int i;
528
Jeff Garzikcca39742006-08-24 03:19:22 -0400529 spin_lock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900530
Jeff Garzikcca39742006-08-24 03:19:22 -0400531 for (i = 0; i < host->n_ports; i++) {
532 struct ata_port *ap = host->ports[i];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900533 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
534
Bartlomiej Zolnierkiewiczc9abde12009-07-26 16:05:13 +0200535 if (unlikely(ap->flags & ATA_FLAG_DISABLED))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900536 continue;
537
Tejun Heo201ce852006-06-26 21:23:52 +0900538 /* turn off SATA_IRQ if not supported */
539 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
540 bmdma2 &= ~SIL_DMA_SATA_IRQ;
541
Tejun Heo23fa9612006-06-12 14:18:51 +0900542 if (bmdma2 == 0xffffffff ||
543 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900544 continue;
545
546 sil_host_intr(ap, bmdma2);
547 handled = 1;
548 }
549
Jeff Garzikcca39742006-08-24 03:19:22 -0400550 spin_unlock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900551
552 return IRQ_RETVAL(handled);
553}
554
Tejun Heof6aae272006-05-15 20:58:27 +0900555static void sil_freeze(struct ata_port *ap)
556{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900557 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900558 u32 tmp;
559
Tejun Heoe5738902006-05-31 18:28:16 +0900560 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
561 writel(0, mmio_base + sil_port[ap->port_no].sien);
562
Tejun Heof6aae272006-05-15 20:58:27 +0900563 /* plug IRQ */
564 tmp = readl(mmio_base + SIL_SYSCFG);
565 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
566 writel(tmp, mmio_base + SIL_SYSCFG);
567 readl(mmio_base + SIL_SYSCFG); /* flush */
Jeff Garzik2fc37ad2009-04-07 19:18:32 -0400568
569 /* Ensure DMA_ENABLE is off.
570 *
571 * This is because the controller will not give us access to the
572 * taskfile registers while a DMA is in progress
573 */
574 iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
575 ap->ioaddr.bmdma_addr);
576
577 /* According to ata_bmdma_stop, an HDMA transition requires
578 * on PIO cycle. But we can't read a taskfile register.
579 */
580 ioread8(ap->ioaddr.bmdma_addr);
Tejun Heof6aae272006-05-15 20:58:27 +0900581}
582
583static void sil_thaw(struct ata_port *ap)
584{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900585 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900586 u32 tmp;
587
588 /* clear IRQ */
Tejun Heo5682ed32008-04-07 22:47:16 +0900589 ap->ops->sff_check_status(ap);
Tejun Heo9363c382008-04-07 22:47:16 +0900590 ata_sff_irq_clear(ap);
Tejun Heof6aae272006-05-15 20:58:27 +0900591
Tejun Heo201ce852006-06-26 21:23:52 +0900592 /* turn on SATA IRQ if supported */
593 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
594 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
Tejun Heoe5738902006-05-31 18:28:16 +0900595
Tejun Heof6aae272006-05-15 20:58:27 +0900596 /* turn on IRQ */
597 tmp = readl(mmio_base + SIL_SYSCFG);
598 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
599 writel(tmp, mmio_base + SIL_SYSCFG);
600}
601
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602/**
603 * sil_dev_config - Apply device/host-specific errata fixups
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 * @dev: Device to be examined
605 *
606 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
607 * device is known to be present, this function is called.
608 * We apply two errata fixups which are specific to Silicon Image,
609 * a Seagate and a Maxtor fixup.
610 *
611 * For certain Seagate devices, we must limit the maximum sectors
612 * to under 8K.
613 *
614 * For certain Maxtor devices, we must not program the drive
615 * beyond udma5.
616 *
617 * Both fixups are unfairly pessimistic. As soon as I get more
618 * information on these errata, I will create a more exhaustive
619 * list, and apply the fixups to only the specific
620 * devices/hosts/firmwares that need it.
621 *
622 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
623 * The Maxtor quirk is in the blacklist, but I'm keeping the original
624 * pessimistic fix for the following reasons...
625 * - There seems to be less info on it, only one device gleaned off the
626 * Windows driver, maybe only one is affected. More info would be greatly
627 * appreciated.
628 * - But then again UDMA5 is hardly anything to complain about
629 */
Alancd0d3bb2007-03-02 00:56:15 +0000630static void sil_dev_config(struct ata_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900632 struct ata_port *ap = dev->link->ap;
633 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 unsigned int n, quirks = 0;
Tejun Heoa0cf7332007-01-02 20:18:49 +0900635 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
Tejun Heoa0cf7332007-01-02 20:18:49 +0900637 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638
Jeff Garzik8a60a072005-07-31 13:13:24 -0400639 for (n = 0; sil_blacklist[n].product; n++)
Tejun Heo2e026712006-02-12 22:47:04 +0900640 if (!strcmp(sil_blacklist[n].product, model_num)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 quirks = sil_blacklist[n].quirk;
642 break;
643 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400644
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500646 if (slow_down ||
647 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
648 (quirks & SIL_QUIRK_MOD15WRITE))) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900649 if (print_info)
650 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
651 "errata fix (mod15write workaround)\n");
Tejun Heob00eec12006-02-12 23:32:59 +0900652 dev->max_sectors = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 return;
654 }
655
656 /* limit to udma5 */
657 if (quirks & SIL_QUIRK_UDMA5MAX) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900658 if (print_info)
659 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
660 "errata fix %s\n", model_num);
Tejun Heo5a529132006-03-24 14:07:50 +0900661 dev->udma_mask &= ATA_UDMA5;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 return;
663 }
664}
665
Tejun Heo4447d352007-04-17 23:44:08 +0900666static void sil_init_controller(struct ata_host *host)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900667{
Tejun Heo4447d352007-04-17 23:44:08 +0900668 struct pci_dev *pdev = to_pci_dev(host->dev);
669 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heo3d8ec912006-07-03 16:07:27 +0900670 u8 cls;
671 u32 tmp;
672 int i;
673
674 /* Initialize FIFO PCI bus arbitration */
675 cls = sil_get_device_cache_line(pdev);
676 if (cls) {
677 cls >>= 3;
678 cls++; /* cls = (line_size/8)+1 */
Tejun Heo4447d352007-04-17 23:44:08 +0900679 for (i = 0; i < host->n_ports; i++)
Tejun Heo3d8ec912006-07-03 16:07:27 +0900680 writew(cls << 8 | cls,
681 mmio_base + sil_port[i].fifo_cfg);
682 } else
683 dev_printk(KERN_WARNING, &pdev->dev,
684 "cache line size not set. Driver may not function\n");
685
686 /* Apply R_ERR on DMA activate FIS errata workaround */
Tejun Heo4447d352007-04-17 23:44:08 +0900687 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900688 int cnt;
689
Tejun Heo4447d352007-04-17 23:44:08 +0900690 for (i = 0, cnt = 0; i < host->n_ports; i++) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900691 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
692 if ((tmp & 0x3) != 0x01)
693 continue;
694 if (!cnt)
695 dev_printk(KERN_INFO, &pdev->dev,
696 "Applying R_ERR on DMA activate "
697 "FIS errata fix\n");
698 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
699 cnt++;
700 }
701 }
702
Tejun Heo4447d352007-04-17 23:44:08 +0900703 if (host->n_ports == 4) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900704 /* flip the magic "make 4 ports work" bit */
705 tmp = readl(mmio_base + sil_port[2].bmdma);
706 if ((tmp & SIL_INTR_STEERING) == 0)
707 writel(tmp | SIL_INTR_STEERING,
708 mmio_base + sil_port[2].bmdma);
709 }
710}
711
Rafael J. Wysockie57db7b2009-01-19 20:58:29 +0100712static bool sil_broken_system_poweroff(struct pci_dev *pdev)
713{
714 static const struct dmi_system_id broken_systems[] = {
715 {
716 .ident = "HP Compaq nx6325",
717 .matches = {
718 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
719 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
720 },
721 /* PCI slot number of the controller */
722 .driver_data = (void *)0x12UL,
723 },
724
725 { } /* terminate list */
726 };
727 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
728
729 if (dmi) {
730 unsigned long slot = (unsigned long)dmi->driver_data;
731 /* apply the quirk only to on-board controllers */
732 return slot == PCI_SLOT(pdev->devfn);
733 }
734
735 return false;
736}
737
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400738static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739{
740 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +0900741 int board_id = ent->driver_data;
Rafael J. Wysockie57db7b2009-01-19 20:58:29 +0100742 struct ata_port_info pi = sil_port_info[board_id];
743 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo4447d352007-04-17 23:44:08 +0900744 struct ata_host *host;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400745 void __iomem *mmio_base;
Tejun Heo4447d352007-04-17 23:44:08 +0900746 int n_ports, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748
749 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500750 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
Tejun Heo4447d352007-04-17 23:44:08 +0900752 /* allocate host */
753 n_ports = 2;
754 if (board_id == sil_3114)
755 n_ports = 4;
756
Rafael J. Wysockie57db7b2009-01-19 20:58:29 +0100757 if (sil_broken_system_poweroff(pdev)) {
758 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN |
759 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
760 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
761 "on poweroff and hibernation\n");
762 }
763
Tejun Heo4447d352007-04-17 23:44:08 +0900764 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
765 if (!host)
766 return -ENOMEM;
767
768 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900769 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 if (rc)
771 return rc;
772
Tejun Heo0d5ff562007-02-01 15:06:36 +0900773 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
774 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900775 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900776 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900777 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +0900778 host->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779
780 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
781 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900782 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
784 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900785 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
Tejun Heo4447d352007-04-17 23:44:08 +0900787 mmio_base = host->iomap[SIL_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788
Tejun Heo4447d352007-04-17 23:44:08 +0900789 for (i = 0; i < host->n_ports; i++) {
Tejun Heocbcdd872007-08-18 13:14:55 +0900790 struct ata_port *ap = host->ports[i];
791 struct ata_ioports *ioaddr = &ap->ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792
Tejun Heo4447d352007-04-17 23:44:08 +0900793 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
794 ioaddr->altstatus_addr =
795 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
796 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
797 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
Tejun Heo9363c382008-04-07 22:47:16 +0900798 ata_sff_std_ports(ioaddr);
Tejun Heocbcdd872007-08-18 13:14:55 +0900799
800 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
801 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 }
803
Tejun Heo4447d352007-04-17 23:44:08 +0900804 /* initialize and activate */
805 sil_init_controller(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 pci_set_master(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +0900808 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
809 &sil_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810}
811
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700812#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900813static int sil_pci_device_resume(struct pci_dev *pdev)
814{
Jeff Garzikcca39742006-08-24 03:19:22 -0400815 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo553c4aa2006-12-26 19:39:50 +0900816 int rc;
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900817
Tejun Heo553c4aa2006-12-26 19:39:50 +0900818 rc = ata_pci_device_do_resume(pdev);
819 if (rc)
820 return rc;
821
Tejun Heo4447d352007-04-17 23:44:08 +0900822 sil_init_controller(host);
Jeff Garzikcca39742006-08-24 03:19:22 -0400823 ata_host_resume(host);
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900824
825 return 0;
826}
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700827#endif
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829static int __init sil_init(void)
830{
Pavel Roskinb7887192006-08-10 18:13:18 +0900831 return pci_register_driver(&sil_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832}
833
834static void __exit sil_exit(void)
835{
836 pci_unregister_driver(&sil_pci_driver);
837}
838
839
840module_init(sil_init);
841module_exit(sil_exit);