Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1 | /* |
Kiran Gunda | 2d5f01d | 2018-01-02 16:14:44 +0530 | [diff] [blame] | 2 | * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 13 | #include <linux/bitmap.h> |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 14 | #include <linux/delay.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/io.h> |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 18 | #include <linux/irqchip/chained_irq.h> |
| 19 | #include <linux/irqdomain.h> |
| 20 | #include <linux/irq.h> |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/spmi.h> |
| 27 | |
| 28 | /* PMIC Arbiter configuration registers */ |
| 29 | #define PMIC_ARB_VERSION 0x0000 |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 30 | #define PMIC_ARB_VERSION_V2_MIN 0x20010000 |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 31 | #define PMIC_ARB_VERSION_V3_MIN 0x30000000 |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 32 | #define PMIC_ARB_VERSION_V5_MIN 0x50000000 |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 33 | #define PMIC_ARB_INT_EN 0x0004 |
| 34 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 35 | /* PMIC Arbiter channel registers offsets */ |
| 36 | #define PMIC_ARB_CMD 0x00 |
| 37 | #define PMIC_ARB_CONFIG 0x04 |
| 38 | #define PMIC_ARB_STATUS 0x08 |
| 39 | #define PMIC_ARB_WDATA0 0x10 |
| 40 | #define PMIC_ARB_WDATA1 0x14 |
| 41 | #define PMIC_ARB_RDATA0 0x18 |
| 42 | #define PMIC_ARB_RDATA1 0x1C |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 43 | |
| 44 | /* Mapping Table */ |
| 45 | #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) |
| 46 | #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF) |
| 47 | #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1) |
| 48 | #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF) |
| 49 | #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) |
| 50 | #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) |
| 51 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 52 | #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 53 | #define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */ |
| 54 | #define PMIC_ARB_CHAN_VALID BIT(15) |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 55 | #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24)) |
| 56 | #define INVALID_EE (-1) |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 57 | |
| 58 | /* Ownership Table */ |
| 59 | #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N))) |
| 60 | #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7) |
| 61 | |
David Collins | ee176e2 | 2017-06-20 16:33:04 -0700 | [diff] [blame] | 62 | #define SPMI_PROTOCOL_IRQ_STATUS 0x6000 |
| 63 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 64 | /* Channel Status fields */ |
| 65 | enum pmic_arb_chnl_status { |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 66 | PMIC_ARB_STATUS_DONE = BIT(0), |
| 67 | PMIC_ARB_STATUS_FAILURE = BIT(1), |
| 68 | PMIC_ARB_STATUS_DENIED = BIT(2), |
| 69 | PMIC_ARB_STATUS_DROPPED = BIT(3), |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | /* Command register fields */ |
| 73 | #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8 |
| 74 | |
| 75 | /* Command Opcodes */ |
| 76 | enum pmic_arb_cmd_op_code { |
| 77 | PMIC_ARB_OP_EXT_WRITEL = 0, |
| 78 | PMIC_ARB_OP_EXT_READL = 1, |
| 79 | PMIC_ARB_OP_EXT_WRITE = 2, |
| 80 | PMIC_ARB_OP_RESET = 3, |
| 81 | PMIC_ARB_OP_SLEEP = 4, |
| 82 | PMIC_ARB_OP_SHUTDOWN = 5, |
| 83 | PMIC_ARB_OP_WAKEUP = 6, |
| 84 | PMIC_ARB_OP_AUTHENTICATE = 7, |
| 85 | PMIC_ARB_OP_MSTR_READ = 8, |
| 86 | PMIC_ARB_OP_MSTR_WRITE = 9, |
| 87 | PMIC_ARB_OP_EXT_READ = 13, |
| 88 | PMIC_ARB_OP_WRITE = 14, |
| 89 | PMIC_ARB_OP_READ = 15, |
| 90 | PMIC_ARB_OP_ZERO_WRITE = 16, |
| 91 | }; |
| 92 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 93 | /* |
| 94 | * PMIC arbiter version 5 uses different register offsets for read/write vs |
| 95 | * observer channels. |
| 96 | */ |
| 97 | enum pmic_arb_channel { |
| 98 | PMIC_ARB_CHANNEL_RW, |
| 99 | PMIC_ARB_CHANNEL_OBS, |
| 100 | }; |
| 101 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 102 | /* Maximum number of support PMIC peripherals */ |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 103 | #define PMIC_ARB_MAX_PERIPHS 512 |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 104 | #define PMIC_ARB_TIMEOUT_US 100 |
| 105 | #define PMIC_ARB_MAX_TRANS_BYTES (8) |
| 106 | |
| 107 | #define PMIC_ARB_APID_MASK 0xFF |
| 108 | #define PMIC_ARB_PPID_MASK 0xFFF |
| 109 | |
| 110 | /* interrupt enable bit */ |
| 111 | #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) |
| 112 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 113 | #define HWIRQ(slave_id, periph_id, irq_id, apid) \ |
| 114 | ((((slave_id) & 0xF) << 28) | \ |
| 115 | (((periph_id) & 0xFF) << 20) | \ |
| 116 | (((irq_id) & 0x7) << 16) | \ |
| 117 | (((apid) & 0x1FF) << 0)) |
| 118 | |
| 119 | #define HWIRQ_SID(hwirq) (((hwirq) >> 28) & 0xF) |
| 120 | #define HWIRQ_PER(hwirq) (((hwirq) >> 20) & 0xFF) |
| 121 | #define HWIRQ_IRQ(hwirq) (((hwirq) >> 16) & 0x7) |
| 122 | #define HWIRQ_APID(hwirq) (((hwirq) >> 0) & 0x1FF) |
| 123 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 124 | struct pmic_arb_ver_ops; |
| 125 | |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 126 | struct apid_data { |
| 127 | u16 ppid; |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 128 | u8 write_owner; |
| 129 | u8 irq_owner; |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 130 | }; |
| 131 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 132 | /** |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 133 | * spmi_pmic_arb - SPMI PMIC Arbiter object |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 134 | * |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 135 | * @rd_base: on v1 "core", on v2 "observer" register base off DT. |
| 136 | * @wr_base: on v1 "core", on v2 "chnls" register base off DT. |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 137 | * @intr: address of the SPMI interrupt control registers. |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 138 | * @acc_status: address of SPMI ACC interrupt status registers. |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 139 | * @cnfg: address of the PMIC Arbiter configuration registers. |
| 140 | * @lock: lock to synchronize accesses. |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 141 | * @channel: execution environment channel to use for accesses. |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 142 | * @irq: PMIC ARB interrupt. |
| 143 | * @ee: the current Execution Environment |
| 144 | * @min_apid: minimum APID (used for bounding IRQ search) |
| 145 | * @max_apid: maximum APID |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 146 | * @max_periph: maximum number of PMIC peripherals supported by HW. |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 147 | * @mapping_table: in-memory copy of PPID -> APID mapping table. |
| 148 | * @domain: irq domain object for PMIC IRQ domain |
| 149 | * @spmic: SPMI controller object |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 150 | * @ver_ops: version dependent operations. |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 151 | * @ppid_to_apid in-memory copy of PPID -> channel (APID) mapping table. |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 152 | * v2 only. |
David Collins | ee176e2 | 2017-06-20 16:33:04 -0700 | [diff] [blame] | 153 | * @ahb_bus_wa: Use AHB bus workaround to avoid write transaction |
| 154 | * corruption on some PMIC arbiter v5 platforms. |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 155 | */ |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 156 | struct spmi_pmic_arb { |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 157 | void __iomem *rd_base; |
| 158 | void __iomem *wr_base; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 159 | void __iomem *intr; |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 160 | void __iomem *acc_status; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 161 | void __iomem *cnfg; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 162 | void __iomem *core; |
| 163 | resource_size_t core_size; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 164 | raw_spinlock_t lock; |
| 165 | u8 channel; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 166 | int irq; |
| 167 | u8 ee; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 168 | u16 min_apid; |
| 169 | u16 max_apid; |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 170 | u16 max_periph; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 171 | u32 *mapping_table; |
| 172 | DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 173 | struct irq_domain *domain; |
| 174 | struct spmi_controller *spmic; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 175 | const struct pmic_arb_ver_ops *ver_ops; |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 176 | u16 *ppid_to_apid; |
| 177 | u16 last_apid; |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 178 | struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS]; |
David Collins | ee176e2 | 2017-06-20 16:33:04 -0700 | [diff] [blame] | 179 | bool ahb_bus_wa; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 180 | }; |
| 181 | |
| 182 | /** |
| 183 | * pmic_arb_ver: version dependent functionality. |
| 184 | * |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 185 | * @ver_str: version string. |
| 186 | * @ppid_to_apid: finds the apid for a given ppid. |
| 187 | * @mode: access rights to specified pmic peripheral. |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 188 | * @non_data_cmd: on v1 issues an spmi non-data command. |
| 189 | * on v2 no HW support, returns -EOPNOTSUPP. |
| 190 | * @offset: on v1 offset of per-ee channel. |
| 191 | * on v2 offset of per-ee and per-ppid channel. |
| 192 | * @fmt_cmd: formats a GENI/SPMI command. |
| 193 | * @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn |
| 194 | * on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn. |
| 195 | * @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn |
| 196 | * on v2 offset of SPMI_PIC_ACC_ENABLEn. |
| 197 | * @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn |
| 198 | * on v2 offset of SPMI_PIC_IRQ_STATUSn. |
| 199 | * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn |
| 200 | * on v2 offset of SPMI_PIC_IRQ_CLEARn. |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 201 | * @channel_map_offset: offset of PMIC_ARB_REG_CHNLn |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 202 | */ |
| 203 | struct pmic_arb_ver_ops { |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 204 | const char *ver_str; |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 205 | int (*ppid_to_apid)(struct spmi_pmic_arb *pa, u8 sid, u16 addr, |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 206 | u16 *apid); |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 207 | int (*mode)(struct spmi_pmic_arb *dev, u8 sid, u16 addr, |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 208 | mode_t *mode); |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 209 | /* spmi commands (read_cmd, write_cmd, cmd) functionality */ |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 210 | int (*offset)(struct spmi_pmic_arb *dev, u8 sid, u16 addr, |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 211 | enum pmic_arb_channel ch_type, u32 *offset); |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 212 | u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); |
| 213 | int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); |
| 214 | /* Interrupts controller functionality (offset of PIC registers) */ |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 215 | u32 (*owner_acc_status)(u8 m, u16 n); |
| 216 | u32 (*acc_enable)(u16 n); |
| 217 | u32 (*irq_status)(u16 n); |
| 218 | u32 (*irq_clear)(u16 n); |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 219 | u32 (*channel_map_offset)(u16 n); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 220 | }; |
| 221 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 222 | static inline void pmic_arb_base_write(struct spmi_pmic_arb *pa, |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 223 | u32 offset, u32 val) |
| 224 | { |
David Collins | ee176e2 | 2017-06-20 16:33:04 -0700 | [diff] [blame] | 225 | if (pa->ahb_bus_wa) { |
| 226 | /* AHB bus register dummy read for workaround. */ |
| 227 | readl_relaxed(pa->cnfg + SPMI_PROTOCOL_IRQ_STATUS); |
| 228 | /* |
| 229 | * Ensure that the read completes before initiating the |
| 230 | * subsequent register write. |
| 231 | */ |
| 232 | mb(); |
| 233 | } |
| 234 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 235 | writel_relaxed(val, pa->wr_base + offset); |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 236 | } |
| 237 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 238 | static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pa, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 239 | u32 offset, u32 val) |
| 240 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 241 | writel_relaxed(val, pa->rd_base + offset); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | /** |
| 245 | * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf |
| 246 | * @bc: byte count -1. range: 0..3 |
| 247 | * @reg: register's address |
| 248 | * @buf: output parameter, length must be bc + 1 |
| 249 | */ |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 250 | static void pa_read_data(struct spmi_pmic_arb *pa, u8 *buf, u32 reg, u8 bc) |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 251 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 252 | u32 data = __raw_readl(pa->rd_base + reg); |
| 253 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 254 | memcpy(buf, &data, (bc & 3) + 1); |
| 255 | } |
| 256 | |
| 257 | /** |
| 258 | * pa_write_data: write 1..4 bytes from buf to pmic-arb's register |
| 259 | * @bc: byte-count -1. range: 0..3. |
| 260 | * @reg: register's address. |
| 261 | * @buf: buffer to write. length must be bc + 1. |
| 262 | */ |
| 263 | static void |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 264 | pa_write_data(struct spmi_pmic_arb *pa, const u8 *buf, u32 reg, u8 bc) |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 265 | { |
| 266 | u32 data = 0; |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 267 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 268 | memcpy(&data, buf, (bc & 3) + 1); |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 269 | pmic_arb_base_write(pa, reg, data); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 270 | } |
| 271 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 272 | static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 273 | void __iomem *base, u8 sid, u16 addr, |
| 274 | enum pmic_arb_channel ch_type) |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 275 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 276 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 277 | u32 status = 0; |
| 278 | u32 timeout = PMIC_ARB_TIMEOUT_US; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 279 | u32 offset; |
| 280 | int rc; |
| 281 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 282 | rc = pa->ver_ops->offset(pa, sid, addr, ch_type, &offset); |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 283 | if (rc) |
| 284 | return rc; |
| 285 | |
| 286 | offset += PMIC_ARB_STATUS; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 287 | |
| 288 | while (timeout--) { |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 289 | status = readl_relaxed(base + offset); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 290 | |
| 291 | if (status & PMIC_ARB_STATUS_DONE) { |
| 292 | if (status & PMIC_ARB_STATUS_DENIED) { |
| 293 | dev_err(&ctrl->dev, |
| 294 | "%s: transaction denied (0x%x)\n", |
| 295 | __func__, status); |
| 296 | return -EPERM; |
| 297 | } |
| 298 | |
| 299 | if (status & PMIC_ARB_STATUS_FAILURE) { |
| 300 | dev_err(&ctrl->dev, |
| 301 | "%s: transaction failed (0x%x)\n", |
| 302 | __func__, status); |
| 303 | return -EIO; |
| 304 | } |
| 305 | |
| 306 | if (status & PMIC_ARB_STATUS_DROPPED) { |
| 307 | dev_err(&ctrl->dev, |
| 308 | "%s: transaction dropped (0x%x)\n", |
| 309 | __func__, status); |
| 310 | return -EIO; |
| 311 | } |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | udelay(1); |
| 316 | } |
| 317 | |
| 318 | dev_err(&ctrl->dev, |
| 319 | "%s: timeout, status 0x%x\n", |
| 320 | __func__, status); |
| 321 | return -ETIMEDOUT; |
| 322 | } |
| 323 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 324 | static int |
| 325 | pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 326 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 327 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 328 | unsigned long flags; |
| 329 | u32 cmd; |
| 330 | int rc; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 331 | u32 offset; |
| 332 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 333 | rc = pa->ver_ops->offset(pa, sid, 0, PMIC_ARB_CHANNEL_RW, &offset); |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 334 | if (rc) |
| 335 | return rc; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 336 | |
| 337 | cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); |
| 338 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 339 | raw_spin_lock_irqsave(&pa->lock, flags); |
| 340 | pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd); |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 341 | rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, 0, |
| 342 | PMIC_ARB_CHANNEL_RW); |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 343 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 344 | |
| 345 | return rc; |
| 346 | } |
| 347 | |
| 348 | static int |
| 349 | pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) |
| 350 | { |
| 351 | return -EOPNOTSUPP; |
| 352 | } |
| 353 | |
| 354 | /* Non-data command */ |
| 355 | static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) |
| 356 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 357 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 358 | |
| 359 | dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 360 | |
| 361 | /* Check for valid non-data command */ |
| 362 | if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) |
| 363 | return -EINVAL; |
| 364 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 365 | return pa->ver_ops->non_data_cmd(ctrl, opc, sid); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| 369 | u16 addr, u8 *buf, size_t len) |
| 370 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 371 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 372 | unsigned long flags; |
| 373 | u8 bc = len - 1; |
| 374 | u32 cmd; |
| 375 | int rc; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 376 | u32 offset; |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 377 | mode_t mode; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 378 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 379 | rc = pa->ver_ops->offset(pa, sid, addr, PMIC_ARB_CHANNEL_OBS, &offset); |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 380 | if (rc) |
| 381 | return rc; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 382 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 383 | rc = pa->ver_ops->mode(pa, sid, addr, &mode); |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 384 | if (rc) |
| 385 | return rc; |
| 386 | |
| 387 | if (!(mode & 0400)) { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 388 | dev_err(&pa->spmic->dev, |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 389 | "error: impermissible read from peripheral sid:%d addr:0x%x\n", |
| 390 | sid, addr); |
| 391 | return -ENODEV; |
| 392 | } |
| 393 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 394 | if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { |
| 395 | dev_err(&ctrl->dev, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 396 | "pmic-arb supports 1..%d bytes per trans, but:%zu requested", |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 397 | PMIC_ARB_MAX_TRANS_BYTES, len); |
| 398 | return -EINVAL; |
| 399 | } |
| 400 | |
| 401 | /* Check the opcode */ |
| 402 | if (opc >= 0x60 && opc <= 0x7F) |
| 403 | opc = PMIC_ARB_OP_READ; |
| 404 | else if (opc >= 0x20 && opc <= 0x2F) |
| 405 | opc = PMIC_ARB_OP_EXT_READ; |
| 406 | else if (opc >= 0x38 && opc <= 0x3F) |
| 407 | opc = PMIC_ARB_OP_EXT_READL; |
| 408 | else |
| 409 | return -EINVAL; |
| 410 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 411 | cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 412 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 413 | raw_spin_lock_irqsave(&pa->lock, flags); |
| 414 | pmic_arb_set_rd_cmd(pa, offset + PMIC_ARB_CMD, cmd); |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 415 | rc = pmic_arb_wait_for_done(ctrl, pa->rd_base, sid, addr, |
| 416 | PMIC_ARB_CHANNEL_OBS); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 417 | if (rc) |
| 418 | goto done; |
| 419 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 420 | pa_read_data(pa, buf, offset + PMIC_ARB_RDATA0, |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 421 | min_t(u8, bc, 3)); |
| 422 | |
| 423 | if (bc > 3) |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 424 | pa_read_data(pa, buf + 4, offset + PMIC_ARB_RDATA1, bc - 4); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 425 | |
| 426 | done: |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 427 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 428 | return rc; |
| 429 | } |
| 430 | |
| 431 | static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
| 432 | u16 addr, const u8 *buf, size_t len) |
| 433 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 434 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 435 | unsigned long flags; |
| 436 | u8 bc = len - 1; |
| 437 | u32 cmd; |
| 438 | int rc; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 439 | u32 offset; |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 440 | mode_t mode; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 441 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 442 | rc = pa->ver_ops->offset(pa, sid, addr, PMIC_ARB_CHANNEL_RW, &offset); |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 443 | if (rc) |
| 444 | return rc; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 445 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 446 | rc = pa->ver_ops->mode(pa, sid, addr, &mode); |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 447 | if (rc) |
| 448 | return rc; |
| 449 | |
| 450 | if (!(mode & 0200)) { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 451 | dev_err(&pa->spmic->dev, |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 452 | "error: impermissible write to peripheral sid:%d addr:0x%x\n", |
| 453 | sid, addr); |
| 454 | return -ENODEV; |
| 455 | } |
| 456 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 457 | if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { |
| 458 | dev_err(&ctrl->dev, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 459 | "pmic-arb supports 1..%d bytes per trans, but:%zu requested", |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 460 | PMIC_ARB_MAX_TRANS_BYTES, len); |
| 461 | return -EINVAL; |
| 462 | } |
| 463 | |
| 464 | /* Check the opcode */ |
| 465 | if (opc >= 0x40 && opc <= 0x5F) |
| 466 | opc = PMIC_ARB_OP_WRITE; |
| 467 | else if (opc >= 0x00 && opc <= 0x0F) |
| 468 | opc = PMIC_ARB_OP_EXT_WRITE; |
| 469 | else if (opc >= 0x30 && opc <= 0x37) |
| 470 | opc = PMIC_ARB_OP_EXT_WRITEL; |
Stephen Boyd | 9b76968 | 2015-08-28 12:31:10 -0700 | [diff] [blame] | 471 | else if (opc >= 0x80) |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 472 | opc = PMIC_ARB_OP_ZERO_WRITE; |
| 473 | else |
| 474 | return -EINVAL; |
| 475 | |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 476 | cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 477 | |
| 478 | /* Write data to FIFOs */ |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 479 | raw_spin_lock_irqsave(&pa->lock, flags); |
| 480 | pa_write_data(pa, buf, offset + PMIC_ARB_WDATA0, min_t(u8, bc, 3)); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 481 | if (bc > 3) |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 482 | pa_write_data(pa, buf + 4, offset + PMIC_ARB_WDATA1, bc - 4); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 483 | |
| 484 | /* Start the transaction */ |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 485 | pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd); |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 486 | rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, addr, |
| 487 | PMIC_ARB_CHANNEL_RW); |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 488 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 489 | |
| 490 | return rc; |
| 491 | } |
| 492 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 493 | enum qpnpint_regs { |
| 494 | QPNPINT_REG_RT_STS = 0x10, |
| 495 | QPNPINT_REG_SET_TYPE = 0x11, |
| 496 | QPNPINT_REG_POLARITY_HIGH = 0x12, |
| 497 | QPNPINT_REG_POLARITY_LOW = 0x13, |
| 498 | QPNPINT_REG_LATCHED_CLR = 0x14, |
| 499 | QPNPINT_REG_EN_SET = 0x15, |
| 500 | QPNPINT_REG_EN_CLR = 0x16, |
| 501 | QPNPINT_REG_LATCHED_STS = 0x18, |
| 502 | }; |
| 503 | |
| 504 | struct spmi_pmic_arb_qpnpint_type { |
| 505 | u8 type; /* 1 -> edge */ |
| 506 | u8 polarity_high; |
| 507 | u8 polarity_low; |
| 508 | } __packed; |
| 509 | |
| 510 | /* Simplified accessor functions for irqchip callbacks */ |
| 511 | static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, |
| 512 | size_t len) |
| 513 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 514 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 515 | u8 sid = HWIRQ_SID(d->hwirq); |
| 516 | u8 per = HWIRQ_PER(d->hwirq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 517 | |
| 518 | if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, |
| 519 | (per << 8) + reg, buf, len)) |
| 520 | dev_err_ratelimited(&pa->spmic->dev, |
| 521 | "failed irqchip transaction on %x\n", |
| 522 | d->irq); |
| 523 | } |
| 524 | |
| 525 | static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) |
| 526 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 527 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 528 | u8 sid = HWIRQ_SID(d->hwirq); |
| 529 | u8 per = HWIRQ_PER(d->hwirq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 530 | |
| 531 | if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid, |
| 532 | (per << 8) + reg, buf, len)) |
| 533 | dev_err_ratelimited(&pa->spmic->dev, |
| 534 | "failed irqchip transaction on %x\n", |
| 535 | d->irq); |
| 536 | } |
| 537 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 538 | static void cleanup_irq(struct spmi_pmic_arb *pa, u16 apid, int id) |
Abhijeet Dharmapurikar | b9b8744 | 2016-01-08 10:50:19 -0800 | [diff] [blame] | 539 | { |
Abhijeet Dharmapurikar | b9b8744 | 2016-01-08 10:50:19 -0800 | [diff] [blame] | 540 | u16 ppid = pa->apid_data[apid].ppid; |
| 541 | u8 sid = ppid >> 8; |
| 542 | u8 per = ppid & 0xFF; |
Abhijeet Dharmapurikar | b9b8744 | 2016-01-08 10:50:19 -0800 | [diff] [blame] | 543 | u8 irq_mask = BIT(id); |
| 544 | |
Abhijeet Dharmapurikar | ed44ac1 | 2016-04-26 18:31:39 -0700 | [diff] [blame] | 545 | dev_err_ratelimited(&pa->spmic->dev, |
| 546 | "cleanup_irq apid=%d sid=0x%x per=0x%x irq=%d\n", |
| 547 | apid, sid, per, id); |
Abhijeet Dharmapurikar | b9b8744 | 2016-01-08 10:50:19 -0800 | [diff] [blame] | 548 | writel_relaxed(irq_mask, pa->intr + pa->ver_ops->irq_clear(apid)); |
Abhijeet Dharmapurikar | b9b8744 | 2016-01-08 10:50:19 -0800 | [diff] [blame] | 549 | } |
| 550 | |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 551 | static void periph_interrupt(struct spmi_pmic_arb *pa, u16 apid) |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 552 | { |
| 553 | unsigned int irq; |
Subbaraman Narayanamurthy | 9f39b0c | 2018-11-29 14:06:38 -0800 | [diff] [blame] | 554 | u32 status, id; |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 555 | u8 sid = (pa->apid_data[apid].ppid >> 8) & 0xF; |
| 556 | u8 per = pa->apid_data[apid].ppid & 0xFF; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 557 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 558 | status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 559 | while (status) { |
| 560 | id = ffs(status) - 1; |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 561 | status &= ~BIT(id); |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 562 | irq = irq_find_mapping(pa->domain, HWIRQ(sid, per, id, apid)); |
Abhijeet Dharmapurikar | b9b8744 | 2016-01-08 10:50:19 -0800 | [diff] [blame] | 563 | if (irq == 0) { |
| 564 | cleanup_irq(pa, apid, id); |
| 565 | continue; |
| 566 | } |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 567 | generic_handle_irq(irq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 568 | } |
| 569 | } |
| 570 | |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 571 | static void pmic_arb_chained_irq(struct irq_desc *desc) |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 572 | { |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 573 | struct spmi_pmic_arb *pa = irq_desc_get_handler_data(desc); |
| 574 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 575 | int first = pa->min_apid >> 5; |
| 576 | int last = pa->max_apid >> 5; |
Abhijeet Dharmapurikar | 5e5078b | 2016-04-27 20:39:46 -0700 | [diff] [blame] | 577 | u32 status, enable; |
| 578 | int i, id, apid; |
Ashay Jaiswal | 8fbf358 | 2017-02-27 12:33:17 +0530 | [diff] [blame] | 579 | /* status based dispatch */ |
| 580 | bool acc_valid = false; |
| 581 | u32 irq_status = 0; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 582 | |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 583 | chained_irq_enter(chip, desc); |
| 584 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 585 | for (i = first; i <= last; ++i) { |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 586 | status = readl_relaxed(pa->acc_status + |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 587 | pa->ver_ops->owner_acc_status(pa->ee, i)); |
Ashay Jaiswal | 8fbf358 | 2017-02-27 12:33:17 +0530 | [diff] [blame] | 588 | if (status) |
| 589 | acc_valid = true; |
| 590 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 591 | while (status) { |
| 592 | id = ffs(status) - 1; |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 593 | status &= ~BIT(id); |
Abhijeet Dharmapurikar | 5e5078b | 2016-04-27 20:39:46 -0700 | [diff] [blame] | 594 | apid = id + i * 32; |
David Collins | dc81798 | 2017-05-12 14:19:20 -0700 | [diff] [blame] | 595 | if (apid < pa->min_apid || apid > pa->max_apid) { |
| 596 | WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", |
| 597 | apid); |
| 598 | continue; |
| 599 | } |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 600 | enable = readl_relaxed(pa->intr + |
Abhijeet Dharmapurikar | 5e5078b | 2016-04-27 20:39:46 -0700 | [diff] [blame] | 601 | pa->ver_ops->acc_enable(apid)); |
| 602 | if (enable & SPMI_PIC_ACC_ENABLE_BIT) |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 603 | periph_interrupt(pa, apid); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 604 | } |
| 605 | } |
Ashay Jaiswal | 8fbf358 | 2017-02-27 12:33:17 +0530 | [diff] [blame] | 606 | |
| 607 | /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ |
| 608 | if (!acc_valid) { |
| 609 | for (i = pa->min_apid; i <= pa->max_apid; i++) { |
| 610 | /* skip if APPS is not irq owner */ |
| 611 | if (pa->apid_data[i].irq_owner != pa->ee) |
| 612 | continue; |
| 613 | |
| 614 | irq_status = readl_relaxed(pa->intr + |
| 615 | pa->ver_ops->irq_status(i)); |
| 616 | if (irq_status) { |
| 617 | enable = readl_relaxed(pa->intr + |
| 618 | pa->ver_ops->acc_enable(i)); |
| 619 | if (enable & SPMI_PIC_ACC_ENABLE_BIT) { |
| 620 | dev_dbg(&pa->spmic->dev, |
| 621 | "Dispatching IRQ for apid=%d status=%x\n", |
| 622 | i, irq_status); |
Stephen Boyd | 51257b7 | 2017-08-15 10:27:00 -0700 | [diff] [blame] | 623 | periph_interrupt(pa, i); |
Ashay Jaiswal | 8fbf358 | 2017-02-27 12:33:17 +0530 | [diff] [blame] | 624 | } |
| 625 | } |
| 626 | } |
| 627 | } |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 628 | |
| 629 | chained_irq_exit(chip, desc); |
| 630 | } |
| 631 | |
| 632 | static void qpnpint_irq_ack(struct irq_data *d) |
| 633 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 634 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 635 | u8 irq = HWIRQ_IRQ(d->hwirq); |
| 636 | u16 apid = HWIRQ_APID(d->hwirq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 637 | u8 data; |
| 638 | |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 639 | writel_relaxed(BIT(irq), pa->intr + pa->ver_ops->irq_clear(apid)); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 640 | |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 641 | data = BIT(irq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 642 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); |
| 643 | } |
| 644 | |
| 645 | static void qpnpint_irq_mask(struct irq_data *d) |
| 646 | { |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 647 | u8 irq = HWIRQ_IRQ(d->hwirq); |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 648 | u8 data = BIT(irq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 649 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 650 | qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); |
| 651 | } |
| 652 | |
| 653 | static void qpnpint_irq_unmask(struct irq_data *d) |
| 654 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 655 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 656 | u8 irq = HWIRQ_IRQ(d->hwirq); |
| 657 | u16 apid = HWIRQ_APID(d->hwirq); |
David Collins | a5a32ce | 2013-11-05 09:31:16 -0800 | [diff] [blame] | 658 | u8 buf[2]; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 659 | |
Abhijeet Dharmapurikar | c27d863 | 2016-02-23 15:56:23 -0800 | [diff] [blame] | 660 | writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, |
| 661 | pa->intr + pa->ver_ops->acc_enable(apid)); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 662 | |
David Collins | a5a32ce | 2013-11-05 09:31:16 -0800 | [diff] [blame] | 663 | qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); |
| 664 | if (!(buf[0] & BIT(irq))) { |
| 665 | /* |
| 666 | * Since the interrupt is currently disabled, write to both the |
| 667 | * LATCHED_CLR and EN_SET registers so that a spurious interrupt |
| 668 | * cannot be triggered when the interrupt is enabled |
| 669 | */ |
| 670 | buf[0] = BIT(irq); |
| 671 | buf[1] = BIT(irq); |
| 672 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); |
| 673 | } |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 674 | } |
| 675 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 676 | static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) |
| 677 | { |
| 678 | struct spmi_pmic_arb_qpnpint_type type; |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 679 | u8 irq = HWIRQ_IRQ(d->hwirq); |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 680 | u8 bit_mask_irq = BIT(irq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 681 | |
| 682 | qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); |
| 683 | |
| 684 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 685 | type.type |= bit_mask_irq; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 686 | if (flow_type & IRQF_TRIGGER_RISING) |
Yimin Peng | e96f27c | 2018-05-11 10:08:19 +0800 | [diff] [blame] | 687 | type.polarity_high |= bit_mask_irq; |
| 688 | else |
| 689 | type.polarity_high &= ~bit_mask_irq; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 690 | if (flow_type & IRQF_TRIGGER_FALLING) |
Yimin Peng | e96f27c | 2018-05-11 10:08:19 +0800 | [diff] [blame] | 691 | type.polarity_low |= bit_mask_irq; |
| 692 | else |
| 693 | type.polarity_low &= ~bit_mask_irq; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 694 | } else { |
| 695 | if ((flow_type & (IRQF_TRIGGER_HIGH)) && |
| 696 | (flow_type & (IRQF_TRIGGER_LOW))) |
| 697 | return -EINVAL; |
| 698 | |
Abhijeet Dharmapurikar | 469f2c3 | 2016-01-05 16:52:38 -0800 | [diff] [blame] | 699 | type.type &= ~bit_mask_irq; /* level trig */ |
Yimin Peng | e96f27c | 2018-05-11 10:08:19 +0800 | [diff] [blame] | 700 | if (flow_type & IRQF_TRIGGER_HIGH) { |
| 701 | type.polarity_high |= bit_mask_irq; |
| 702 | type.polarity_low &= ~bit_mask_irq; |
| 703 | } else { |
| 704 | type.polarity_low |= bit_mask_irq; |
| 705 | type.polarity_high &= ~bit_mask_irq; |
| 706 | } |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); |
Abhijeet Dharmapurikar | 2464e90 | 2016-04-19 20:06:46 -0700 | [diff] [blame] | 710 | |
| 711 | if (flow_type & IRQ_TYPE_EDGE_BOTH) |
| 712 | irq_set_handler_locked(d, handle_edge_irq); |
| 713 | else |
| 714 | irq_set_handler_locked(d, handle_level_irq); |
| 715 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 716 | return 0; |
| 717 | } |
| 718 | |
Courtney Cavin | 60be423 | 2015-07-30 10:53:54 -0700 | [diff] [blame] | 719 | static int qpnpint_get_irqchip_state(struct irq_data *d, |
| 720 | enum irqchip_irq_state which, |
| 721 | bool *state) |
| 722 | { |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 723 | u8 irq = HWIRQ_IRQ(d->hwirq); |
Courtney Cavin | 60be423 | 2015-07-30 10:53:54 -0700 | [diff] [blame] | 724 | u8 status = 0; |
| 725 | |
| 726 | if (which != IRQCHIP_STATE_LINE_LEVEL) |
| 727 | return -EINVAL; |
| 728 | |
| 729 | qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1); |
| 730 | *state = !!(status & BIT(irq)); |
| 731 | |
| 732 | return 0; |
| 733 | } |
| 734 | |
Kiran Gunda | 2d5f01d | 2018-01-02 16:14:44 +0530 | [diff] [blame] | 735 | static int qpnpint_irq_request_resources(struct irq_data *d) |
| 736 | { |
| 737 | struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d); |
| 738 | u16 periph = HWIRQ_PER(d->hwirq); |
| 739 | u16 apid = HWIRQ_APID(d->hwirq); |
| 740 | u16 sid = HWIRQ_SID(d->hwirq); |
| 741 | u16 irq = HWIRQ_IRQ(d->hwirq); |
| 742 | |
| 743 | if (pmic_arb->apid_data[apid].irq_owner != pmic_arb->ee) { |
| 744 | dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", |
| 745 | sid, periph, irq, pmic_arb->ee, |
| 746 | pmic_arb->apid_data[apid].irq_owner); |
| 747 | return -ENODEV; |
| 748 | } |
| 749 | |
| 750 | return 0; |
| 751 | } |
| 752 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 753 | static struct irq_chip pmic_arb_irqchip = { |
| 754 | .name = "pmic_arb", |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 755 | .irq_ack = qpnpint_irq_ack, |
| 756 | .irq_mask = qpnpint_irq_mask, |
| 757 | .irq_unmask = qpnpint_irq_unmask, |
| 758 | .irq_set_type = qpnpint_irq_set_type, |
Courtney Cavin | 60be423 | 2015-07-30 10:53:54 -0700 | [diff] [blame] | 759 | .irq_get_irqchip_state = qpnpint_get_irqchip_state, |
Kiran Gunda | 2d5f01d | 2018-01-02 16:14:44 +0530 | [diff] [blame] | 760 | .irq_request_resources = qpnpint_irq_request_resources, |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 761 | .flags = IRQCHIP_MASK_ON_SUSPEND |
| 762 | | IRQCHIP_SKIP_SET_WAKE, |
| 763 | }; |
| 764 | |
Subbaraman Narayanamurthy | f115a0e | 2017-01-30 15:26:24 -0800 | [diff] [blame] | 765 | static void qpnpint_irq_domain_activate(struct irq_domain *domain, |
| 766 | struct irq_data *d) |
| 767 | { |
| 768 | u8 irq = HWIRQ_IRQ(d->hwirq); |
| 769 | u8 buf; |
| 770 | |
| 771 | buf = BIT(irq); |
| 772 | qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); |
| 773 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); |
| 774 | } |
| 775 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 776 | static int qpnpint_irq_domain_dt_translate(struct irq_domain *d, |
| 777 | struct device_node *controller, |
| 778 | const u32 *intspec, |
| 779 | unsigned int intsize, |
| 780 | unsigned long *out_hwirq, |
| 781 | unsigned int *out_type) |
| 782 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 783 | struct spmi_pmic_arb *pa = d->host_data; |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 784 | int rc; |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 785 | u16 apid; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 786 | |
| 787 | dev_dbg(&pa->spmic->dev, |
| 788 | "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", |
| 789 | intspec[0], intspec[1], intspec[2]); |
| 790 | |
Marc Zyngier | 5d4c9bc | 2015-10-13 12:51:29 +0100 | [diff] [blame] | 791 | if (irq_domain_get_of_node(d) != controller) |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 792 | return -EINVAL; |
| 793 | if (intsize != 4) |
| 794 | return -EINVAL; |
| 795 | if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7) |
| 796 | return -EINVAL; |
| 797 | |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 798 | rc = pa->ver_ops->ppid_to_apid(pa, intspec[0], |
| 799 | (intspec[1] << 8), &apid); |
| 800 | if (rc < 0) { |
| 801 | dev_err(&pa->spmic->dev, |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 802 | "failed to xlate sid = 0x%x, periph = 0x%x, irq = %u rc = %d\n", |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 803 | intspec[0], intspec[1], intspec[2], rc); |
| 804 | return rc; |
| 805 | } |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 806 | |
| 807 | /* Keep track of {max,min}_apid for bounding search during interrupt */ |
| 808 | if (apid > pa->max_apid) |
| 809 | pa->max_apid = apid; |
| 810 | if (apid < pa->min_apid) |
| 811 | pa->min_apid = apid; |
| 812 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 813 | *out_hwirq = HWIRQ(intspec[0], intspec[1], intspec[2], apid); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 814 | *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; |
| 815 | |
| 816 | dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); |
| 817 | |
| 818 | return 0; |
| 819 | } |
| 820 | |
| 821 | static int qpnpint_irq_domain_map(struct irq_domain *d, |
| 822 | unsigned int virq, |
| 823 | irq_hw_number_t hwirq) |
| 824 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 825 | struct spmi_pmic_arb *pa = d->host_data; |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 826 | |
| 827 | dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq); |
| 828 | |
| 829 | irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq); |
| 830 | irq_set_chip_data(virq, d->host_data); |
| 831 | irq_set_noprobe(virq); |
| 832 | return 0; |
| 833 | } |
| 834 | |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 835 | static int |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 836 | pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid) |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 837 | { |
| 838 | u16 ppid = sid << 8 | ((addr >> 8) & 0xFF); |
| 839 | u32 *mapping_table = pa->mapping_table; |
| 840 | int index = 0, i; |
| 841 | u16 apid_valid; |
| 842 | u32 data; |
| 843 | |
| 844 | apid_valid = pa->ppid_to_apid[ppid]; |
| 845 | if (apid_valid & PMIC_ARB_CHAN_VALID) { |
| 846 | *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID); |
| 847 | return 0; |
| 848 | } |
| 849 | |
| 850 | for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { |
| 851 | if (!test_and_set_bit(index, pa->mapping_table_valid)) |
| 852 | mapping_table[index] = readl_relaxed(pa->cnfg + |
| 853 | SPMI_MAPPING_TABLE_REG(index)); |
| 854 | |
| 855 | data = mapping_table[index]; |
| 856 | |
| 857 | if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) { |
| 858 | if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { |
| 859 | index = SPMI_MAPPING_BIT_IS_1_RESULT(data); |
| 860 | } else { |
| 861 | *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); |
| 862 | pa->ppid_to_apid[ppid] |
| 863 | = *apid | PMIC_ARB_CHAN_VALID; |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 864 | pa->apid_data[*apid].ppid = ppid; |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 865 | return 0; |
| 866 | } |
| 867 | } else { |
| 868 | if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { |
| 869 | index = SPMI_MAPPING_BIT_IS_0_RESULT(data); |
| 870 | } else { |
| 871 | *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); |
| 872 | pa->ppid_to_apid[ppid] |
| 873 | = *apid | PMIC_ARB_CHAN_VALID; |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 874 | pa->apid_data[*apid].ppid = ppid; |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 875 | return 0; |
| 876 | } |
| 877 | } |
| 878 | } |
| 879 | |
| 880 | return -ENODEV; |
| 881 | } |
| 882 | |
| 883 | static int |
Abhijeet Dharmapurikar | 7888886 | 2016-07-05 17:54:47 -0700 | [diff] [blame] | 884 | pmic_arb_mode_v1_v3(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode) |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 885 | { |
| 886 | *mode = 0600; |
| 887 | return 0; |
| 888 | } |
| 889 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 890 | /* v1 offset per ee */ |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 891 | static int |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 892 | pmic_arb_offset_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, |
| 893 | enum pmic_arb_channel ch_type, u32 *offset) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 894 | { |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 895 | *offset = 0x800 + 0x80 * pa->channel; |
| 896 | return 0; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 897 | } |
| 898 | |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 899 | static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pa, u16 ppid) |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 900 | { |
| 901 | u32 regval, offset; |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 902 | u16 apid; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 903 | u16 id; |
| 904 | |
| 905 | /* |
| 906 | * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid. |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 907 | * ppid_to_apid is an in-memory invert of that table. |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 908 | */ |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 909 | for (apid = pa->last_apid; apid < pa->max_periph; apid++) { |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 910 | regval = readl_relaxed(pa->cnfg + |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 911 | SPMI_OWNERSHIP_TABLE_REG(apid)); |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 912 | pa->apid_data[apid].irq_owner |
| 913 | = SPMI_OWNERSHIP_PERIPH2OWNER(regval); |
| 914 | pa->apid_data[apid].write_owner = pa->apid_data[apid].irq_owner; |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 915 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 916 | offset = pa->ver_ops->channel_map_offset(apid); |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 917 | if (offset >= pa->core_size) |
| 918 | break; |
| 919 | |
| 920 | regval = readl_relaxed(pa->core + offset); |
| 921 | if (!regval) |
| 922 | continue; |
| 923 | |
| 924 | id = (regval >> 8) & PMIC_ARB_PPID_MASK; |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 925 | pa->ppid_to_apid[id] = apid | PMIC_ARB_CHAN_VALID; |
Abhijeet Dharmapurikar | 8f8ec81 | 2016-01-08 12:54:36 -0800 | [diff] [blame] | 926 | pa->apid_data[apid].ppid = id; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 927 | if (id == ppid) { |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 928 | apid |= PMIC_ARB_CHAN_VALID; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 929 | break; |
| 930 | } |
| 931 | } |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 932 | pa->last_apid = apid & ~PMIC_ARB_CHAN_VALID; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 933 | |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 934 | return apid; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 935 | } |
| 936 | |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 937 | static int |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 938 | pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid) |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 939 | { |
| 940 | u16 ppid = (sid << 8) | (addr >> 8); |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 941 | u16 apid_valid; |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 942 | |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 943 | apid_valid = pa->ppid_to_apid[ppid]; |
| 944 | if (!(apid_valid & PMIC_ARB_CHAN_VALID)) |
| 945 | apid_valid = pmic_arb_find_apid(pa, ppid); |
| 946 | if (!(apid_valid & PMIC_ARB_CHAN_VALID)) |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 947 | return -ENODEV; |
| 948 | |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 949 | *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID); |
| 950 | return 0; |
| 951 | } |
| 952 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 953 | static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pa) |
| 954 | { |
| 955 | u32 regval, offset; |
| 956 | u16 apid, prev_apid, ppid; |
| 957 | bool valid, is_irq_owner; |
| 958 | |
| 959 | /* |
| 960 | * PMIC_ARB_REG_CHNL is a table in HW mapping APID (channel) to PPID. |
| 961 | * ppid_to_apid is an in-memory invert of that table. In order to allow |
| 962 | * multiple EE's to write to a single PPID in arbiter version 5, there |
| 963 | * is more than one APID mapped to each PPID. The owner field for each |
| 964 | * of these mappings specifies the EE which is allowed to write to the |
David Collins | 084e216 | 2017-11-13 18:23:09 -0800 | [diff] [blame] | 965 | * APID. The owner of the last (highest) APID which has the IRQ owner |
| 966 | * bit set for a given PPID will receive interrupts from the PPID. |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 967 | */ |
| 968 | for (apid = 0; apid < pa->max_periph; apid++) { |
| 969 | offset = pa->ver_ops->channel_map_offset(apid); |
| 970 | if (offset >= pa->core_size) |
| 971 | break; |
| 972 | |
| 973 | regval = readl_relaxed(pa->core + offset); |
| 974 | if (!regval) |
| 975 | continue; |
| 976 | ppid = (regval >> 8) & PMIC_ARB_PPID_MASK; |
| 977 | is_irq_owner = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval); |
| 978 | |
| 979 | regval = readl_relaxed(pa->cnfg + |
| 980 | SPMI_OWNERSHIP_TABLE_REG(apid)); |
| 981 | pa->apid_data[apid].write_owner |
| 982 | = SPMI_OWNERSHIP_PERIPH2OWNER(regval); |
| 983 | |
| 984 | pa->apid_data[apid].irq_owner = is_irq_owner ? |
| 985 | pa->apid_data[apid].write_owner : INVALID_EE; |
| 986 | |
| 987 | valid = pa->ppid_to_apid[ppid] & PMIC_ARB_CHAN_VALID; |
| 988 | prev_apid = pa->ppid_to_apid[ppid] & ~PMIC_ARB_CHAN_VALID; |
| 989 | |
David Collins | 084e216 | 2017-11-13 18:23:09 -0800 | [diff] [blame] | 990 | if (!valid || pa->apid_data[apid].write_owner == pa->ee) { |
| 991 | /* First PPID mapping or one for this EE */ |
| 992 | pa->ppid_to_apid[ppid] = apid | PMIC_ARB_CHAN_VALID; |
| 993 | } else if (valid && is_irq_owner && |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 994 | pa->apid_data[prev_apid].write_owner == pa->ee) { |
| 995 | /* |
| 996 | * Duplicate PPID mapping after the one for this EE; |
| 997 | * override the irq owner |
| 998 | */ |
| 999 | pa->apid_data[prev_apid].irq_owner |
| 1000 | = pa->apid_data[apid].irq_owner; |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1001 | } |
| 1002 | |
| 1003 | pa->apid_data[apid].ppid = ppid; |
| 1004 | pa->last_apid = apid; |
| 1005 | } |
| 1006 | |
| 1007 | /* Dump the mapping table for debug purposes. */ |
| 1008 | dev_dbg(&pa->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); |
| 1009 | for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { |
| 1010 | valid = pa->ppid_to_apid[ppid] & PMIC_ARB_CHAN_VALID; |
| 1011 | apid = pa->ppid_to_apid[ppid] & ~PMIC_ARB_CHAN_VALID; |
| 1012 | |
| 1013 | if (valid) |
| 1014 | dev_dbg(&pa->spmic->dev, "0x%03X %3u %2u %2u\n", |
| 1015 | ppid, apid, pa->apid_data[apid].write_owner, |
| 1016 | pa->apid_data[apid].irq_owner); |
| 1017 | } |
| 1018 | |
| 1019 | return 0; |
| 1020 | } |
| 1021 | |
| 1022 | static int |
| 1023 | pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid) |
| 1024 | { |
| 1025 | u16 ppid = (sid << 8) | (addr >> 8); |
| 1026 | |
| 1027 | if (!(pa->ppid_to_apid[ppid] & PMIC_ARB_CHAN_VALID)) |
| 1028 | return -ENODEV; |
| 1029 | |
| 1030 | *apid = pa->ppid_to_apid[ppid] & ~PMIC_ARB_CHAN_VALID; |
| 1031 | |
| 1032 | return 0; |
| 1033 | } |
| 1034 | |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1035 | static int |
| 1036 | pmic_arb_mode_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode) |
| 1037 | { |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1038 | u16 apid; |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1039 | int rc; |
| 1040 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1041 | rc = pa->ver_ops->ppid_to_apid(pa, sid, addr, &apid); |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1042 | if (rc < 0) |
| 1043 | return rc; |
| 1044 | |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 1045 | *mode = 0; |
| 1046 | *mode |= 0400; |
| 1047 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1048 | if (pa->ee == pa->apid_data[apid].write_owner) |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 1049 | *mode |= 0200; |
| 1050 | return 0; |
| 1051 | } |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1052 | |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 1053 | /* v2 offset per ppid and per ee */ |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1054 | static int |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1055 | pmic_arb_offset_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, |
| 1056 | enum pmic_arb_channel ch_type, u32 *offset) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1057 | { |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1058 | u16 apid; |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1059 | int rc; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1060 | |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1061 | rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid); |
| 1062 | if (rc < 0) |
| 1063 | return rc; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1064 | |
Abhijeet Dharmapurikar | 39155b6 | 2016-01-06 19:55:21 -0800 | [diff] [blame] | 1065 | *offset = 0x1000 * pa->ee + 0x8000 * apid; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1066 | return 0; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1067 | } |
| 1068 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1069 | /* |
| 1070 | * v5 offset per ee and per apid for observer channels and per apid for |
| 1071 | * read/write channels. |
| 1072 | */ |
| 1073 | static int |
| 1074 | pmic_arb_offset_v5(struct spmi_pmic_arb *pa, u8 sid, u16 addr, |
| 1075 | enum pmic_arb_channel ch_type, u32 *offset) |
| 1076 | { |
| 1077 | u16 apid; |
| 1078 | int rc; |
| 1079 | |
| 1080 | rc = pmic_arb_ppid_to_apid_v5(pa, sid, addr, &apid); |
| 1081 | if (rc < 0) |
| 1082 | return rc; |
| 1083 | |
| 1084 | *offset = (ch_type == PMIC_ARB_CHANNEL_OBS) |
| 1085 | ? 0x10000 * pa->ee + 0x80 * apid |
| 1086 | : 0x10000 * apid; |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1090 | static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) |
| 1091 | { |
| 1092 | return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); |
| 1093 | } |
| 1094 | |
| 1095 | static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc) |
| 1096 | { |
| 1097 | return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); |
| 1098 | } |
| 1099 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1100 | static u32 pmic_arb_owner_acc_status_v1(u8 m, u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1101 | { |
| 1102 | return 0x20 * m + 0x4 * n; |
| 1103 | } |
| 1104 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1105 | static u32 pmic_arb_owner_acc_status_v2(u8 m, u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1106 | { |
| 1107 | return 0x100000 + 0x1000 * m + 0x4 * n; |
| 1108 | } |
| 1109 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1110 | static u32 pmic_arb_owner_acc_status_v3(u8 m, u16 n) |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1111 | { |
| 1112 | return 0x200000 + 0x1000 * m + 0x4 * n; |
| 1113 | } |
| 1114 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1115 | static u32 pmic_arb_owner_acc_status_v5(u8 m, u16 n) |
| 1116 | { |
| 1117 | return 0x10000 * m + 0x4 * n; |
| 1118 | } |
| 1119 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1120 | static u32 pmic_arb_acc_enable_v1(u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1121 | { |
| 1122 | return 0x200 + 0x4 * n; |
| 1123 | } |
| 1124 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1125 | static u32 pmic_arb_acc_enable_v2(u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1126 | { |
| 1127 | return 0x1000 * n; |
| 1128 | } |
| 1129 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1130 | static u32 pmic_arb_acc_enable_v5(u16 n) |
| 1131 | { |
| 1132 | return 0x100 + 0x10000 * n; |
| 1133 | } |
| 1134 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1135 | static u32 pmic_arb_irq_status_v1(u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1136 | { |
| 1137 | return 0x600 + 0x4 * n; |
| 1138 | } |
| 1139 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1140 | static u32 pmic_arb_irq_status_v2(u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1141 | { |
| 1142 | return 0x4 + 0x1000 * n; |
| 1143 | } |
| 1144 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1145 | static u32 pmic_arb_irq_status_v5(u16 n) |
| 1146 | { |
| 1147 | return 0x104 + 0x10000 * n; |
| 1148 | } |
| 1149 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1150 | static u32 pmic_arb_irq_clear_v1(u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1151 | { |
| 1152 | return 0xA00 + 0x4 * n; |
| 1153 | } |
| 1154 | |
David Collins | 370a4fa | 2016-07-21 16:58:29 -0700 | [diff] [blame] | 1155 | static u32 pmic_arb_irq_clear_v2(u16 n) |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1156 | { |
| 1157 | return 0x8 + 0x1000 * n; |
| 1158 | } |
| 1159 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1160 | static u32 pmic_arb_irq_clear_v5(u16 n) |
| 1161 | { |
| 1162 | return 0x108 + 0x10000 * n; |
| 1163 | } |
| 1164 | |
| 1165 | static u32 pmic_arb_channel_map_offset_v2(u16 n) |
| 1166 | { |
| 1167 | return 0x800 + 0x4 * n; |
| 1168 | } |
| 1169 | |
| 1170 | static u32 pmic_arb_channel_map_offset_v5(u16 n) |
| 1171 | { |
| 1172 | return 0x900 + 0x4 * n; |
| 1173 | } |
| 1174 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1175 | static const struct pmic_arb_ver_ops pmic_arb_v1 = { |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1176 | .ver_str = "v1", |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1177 | .ppid_to_apid = pmic_arb_ppid_to_apid_v1, |
Abhijeet Dharmapurikar | 7888886 | 2016-07-05 17:54:47 -0700 | [diff] [blame] | 1178 | .mode = pmic_arb_mode_v1_v3, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1179 | .non_data_cmd = pmic_arb_non_data_cmd_v1, |
| 1180 | .offset = pmic_arb_offset_v1, |
| 1181 | .fmt_cmd = pmic_arb_fmt_cmd_v1, |
| 1182 | .owner_acc_status = pmic_arb_owner_acc_status_v1, |
| 1183 | .acc_enable = pmic_arb_acc_enable_v1, |
| 1184 | .irq_status = pmic_arb_irq_status_v1, |
| 1185 | .irq_clear = pmic_arb_irq_clear_v1, |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1186 | .channel_map_offset = pmic_arb_channel_map_offset_v2, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1187 | }; |
| 1188 | |
| 1189 | static const struct pmic_arb_ver_ops pmic_arb_v2 = { |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1190 | .ver_str = "v2", |
Abhijeet Dharmapurikar | 6e9eb38 | 2016-01-08 12:50:24 -0800 | [diff] [blame] | 1191 | .ppid_to_apid = pmic_arb_ppid_to_apid_v2, |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 1192 | .mode = pmic_arb_mode_v2, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1193 | .non_data_cmd = pmic_arb_non_data_cmd_v2, |
| 1194 | .offset = pmic_arb_offset_v2, |
| 1195 | .fmt_cmd = pmic_arb_fmt_cmd_v2, |
| 1196 | .owner_acc_status = pmic_arb_owner_acc_status_v2, |
| 1197 | .acc_enable = pmic_arb_acc_enable_v2, |
| 1198 | .irq_status = pmic_arb_irq_status_v2, |
| 1199 | .irq_clear = pmic_arb_irq_clear_v2, |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1200 | .channel_map_offset = pmic_arb_channel_map_offset_v2, |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1201 | }; |
| 1202 | |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1203 | static const struct pmic_arb_ver_ops pmic_arb_v3 = { |
| 1204 | .ver_str = "v3", |
| 1205 | .ppid_to_apid = pmic_arb_ppid_to_apid_v2, |
Abhijeet Dharmapurikar | 7888886 | 2016-07-05 17:54:47 -0700 | [diff] [blame] | 1206 | .mode = pmic_arb_mode_v1_v3, |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1207 | .non_data_cmd = pmic_arb_non_data_cmd_v2, |
| 1208 | .offset = pmic_arb_offset_v2, |
| 1209 | .fmt_cmd = pmic_arb_fmt_cmd_v2, |
| 1210 | .owner_acc_status = pmic_arb_owner_acc_status_v3, |
| 1211 | .acc_enable = pmic_arb_acc_enable_v2, |
| 1212 | .irq_status = pmic_arb_irq_status_v2, |
| 1213 | .irq_clear = pmic_arb_irq_clear_v2, |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1214 | .channel_map_offset = pmic_arb_channel_map_offset_v2, |
| 1215 | }; |
| 1216 | |
| 1217 | static const struct pmic_arb_ver_ops pmic_arb_v5 = { |
| 1218 | .ver_str = "v5", |
| 1219 | .ppid_to_apid = pmic_arb_ppid_to_apid_v5, |
| 1220 | .mode = pmic_arb_mode_v2, |
| 1221 | .non_data_cmd = pmic_arb_non_data_cmd_v2, |
| 1222 | .offset = pmic_arb_offset_v5, |
| 1223 | .fmt_cmd = pmic_arb_fmt_cmd_v2, |
| 1224 | .owner_acc_status = pmic_arb_owner_acc_status_v5, |
| 1225 | .acc_enable = pmic_arb_acc_enable_v5, |
| 1226 | .irq_status = pmic_arb_irq_status_v5, |
| 1227 | .irq_clear = pmic_arb_irq_clear_v5, |
| 1228 | .channel_map_offset = pmic_arb_channel_map_offset_v5, |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1229 | }; |
| 1230 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1231 | static const struct irq_domain_ops pmic_arb_irq_domain_ops = { |
| 1232 | .map = qpnpint_irq_domain_map, |
| 1233 | .xlate = qpnpint_irq_domain_dt_translate, |
Subbaraman Narayanamurthy | f115a0e | 2017-01-30 15:26:24 -0800 | [diff] [blame] | 1234 | .activate = qpnpint_irq_domain_activate, |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1235 | }; |
| 1236 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1237 | static int spmi_pmic_arb_probe(struct platform_device *pdev) |
| 1238 | { |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 1239 | struct spmi_pmic_arb *pa; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1240 | struct spmi_controller *ctrl; |
| 1241 | struct resource *res; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1242 | void __iomem *core; |
| 1243 | u32 channel, ee, hw_ver; |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1244 | int err; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1245 | |
| 1246 | ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); |
| 1247 | if (!ctrl) |
| 1248 | return -ENOMEM; |
| 1249 | |
| 1250 | pa = spmi_controller_get_drvdata(ctrl); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1251 | pa->spmic = ctrl; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1252 | |
| 1253 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
Abhijeet Dharmapurikar | 57132f5 | 2016-09-13 11:10:48 -0700 | [diff] [blame] | 1254 | if (!res) { |
| 1255 | dev_err(&pdev->dev, "core resource not specified\n"); |
| 1256 | err = -EINVAL; |
| 1257 | goto err_put_ctrl; |
| 1258 | } |
| 1259 | |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1260 | pa->core_size = resource_size(res); |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 1261 | if (pa->core_size <= 0x800) { |
| 1262 | dev_err(&pdev->dev, "core_size is smaller than 0x800. Failing Probe\n"); |
| 1263 | err = -EINVAL; |
| 1264 | goto err_put_ctrl; |
| 1265 | } |
| 1266 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1267 | core = devm_ioremap_resource(&ctrl->dev, res); |
| 1268 | if (IS_ERR(core)) { |
| 1269 | err = PTR_ERR(core); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1270 | goto err_put_ctrl; |
| 1271 | } |
| 1272 | |
Kiran Gunda | c6e7a0c | 2018-01-03 14:53:52 +0530 | [diff] [blame] | 1273 | pa->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID, |
| 1274 | sizeof(*pa->ppid_to_apid), GFP_KERNEL); |
| 1275 | if (!pa->ppid_to_apid) { |
| 1276 | err = -ENOMEM; |
| 1277 | goto err_put_ctrl; |
| 1278 | } |
| 1279 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1280 | hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1281 | |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1282 | if (hw_ver < PMIC_ARB_VERSION_V2_MIN) { |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1283 | pa->ver_ops = &pmic_arb_v1; |
| 1284 | pa->wr_base = core; |
| 1285 | pa->rd_base = core; |
| 1286 | } else { |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1287 | pa->core = core; |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1288 | |
| 1289 | if (hw_ver < PMIC_ARB_VERSION_V3_MIN) |
| 1290 | pa->ver_ops = &pmic_arb_v2; |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1291 | else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1292 | pa->ver_ops = &pmic_arb_v3; |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1293 | else |
| 1294 | pa->ver_ops = &pmic_arb_v5; |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1295 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1296 | /* the apid to ppid table starts at PMIC_ARB_REG_CHNL0 */ |
| 1297 | pa->max_periph |
| 1298 | = (pa->core_size - pa->ver_ops->channel_map_offset(0)) / 4; |
Abhijeet Dharmapurikar | ea64f7f | 2016-01-18 22:00:33 -0800 | [diff] [blame] | 1299 | |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1300 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1301 | "obsrvr"); |
| 1302 | pa->rd_base = devm_ioremap_resource(&ctrl->dev, res); |
| 1303 | if (IS_ERR(pa->rd_base)) { |
| 1304 | err = PTR_ERR(pa->rd_base); |
| 1305 | goto err_put_ctrl; |
| 1306 | } |
| 1307 | |
| 1308 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1309 | "chnls"); |
| 1310 | pa->wr_base = devm_ioremap_resource(&ctrl->dev, res); |
| 1311 | if (IS_ERR(pa->wr_base)) { |
| 1312 | err = PTR_ERR(pa->wr_base); |
| 1313 | goto err_put_ctrl; |
| 1314 | } |
Gilad Avidov | d0c6ae4 | 2015-03-25 11:37:32 -0600 | [diff] [blame] | 1315 | } |
| 1316 | |
Nicholas Troast | 9c10f8f | 2016-03-28 10:16:31 -0700 | [diff] [blame] | 1317 | dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", |
| 1318 | pa->ver_ops->ver_str, hw_ver); |
| 1319 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1320 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); |
| 1321 | pa->intr = devm_ioremap_resource(&ctrl->dev, res); |
| 1322 | if (IS_ERR(pa->intr)) { |
| 1323 | err = PTR_ERR(pa->intr); |
| 1324 | goto err_put_ctrl; |
| 1325 | } |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1326 | pa->acc_status = pa->intr; |
| 1327 | |
| 1328 | /* |
| 1329 | * PMIC arbiter v5 groups the IRQ control registers in the same hardware |
| 1330 | * module as the read/write channels. |
| 1331 | */ |
| 1332 | if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) |
| 1333 | pa->intr = pa->wr_base; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1334 | |
| 1335 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); |
| 1336 | pa->cnfg = devm_ioremap_resource(&ctrl->dev, res); |
| 1337 | if (IS_ERR(pa->cnfg)) { |
| 1338 | err = PTR_ERR(pa->cnfg); |
| 1339 | goto err_put_ctrl; |
| 1340 | } |
| 1341 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1342 | pa->irq = platform_get_irq_byname(pdev, "periph_irq"); |
| 1343 | if (pa->irq < 0) { |
| 1344 | err = pa->irq; |
| 1345 | goto err_put_ctrl; |
| 1346 | } |
| 1347 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1348 | err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); |
| 1349 | if (err) { |
| 1350 | dev_err(&pdev->dev, "channel unspecified.\n"); |
| 1351 | goto err_put_ctrl; |
| 1352 | } |
| 1353 | |
| 1354 | if (channel > 5) { |
| 1355 | dev_err(&pdev->dev, "invalid channel (%u) specified.\n", |
| 1356 | channel); |
Christophe JAILLET | e98cc18 | 2016-09-26 22:24:46 +0200 | [diff] [blame] | 1357 | err = -EINVAL; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1358 | goto err_put_ctrl; |
| 1359 | } |
| 1360 | |
| 1361 | pa->channel = channel; |
| 1362 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1363 | err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee); |
| 1364 | if (err) { |
| 1365 | dev_err(&pdev->dev, "EE unspecified.\n"); |
| 1366 | goto err_put_ctrl; |
| 1367 | } |
| 1368 | |
| 1369 | if (ee > 5) { |
| 1370 | dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee); |
| 1371 | err = -EINVAL; |
| 1372 | goto err_put_ctrl; |
| 1373 | } |
| 1374 | |
| 1375 | pa->ee = ee; |
| 1376 | |
David Collins | ee176e2 | 2017-06-20 16:33:04 -0700 | [diff] [blame] | 1377 | pa->ahb_bus_wa = of_property_read_bool(pdev->dev.of_node, |
| 1378 | "qcom,enable-ahb-bus-workaround"); |
| 1379 | |
Stephen Boyd | 987a9f1 | 2015-11-17 16:13:55 -0800 | [diff] [blame] | 1380 | pa->mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS - 1, |
| 1381 | sizeof(*pa->mapping_table), GFP_KERNEL); |
| 1382 | if (!pa->mapping_table) { |
| 1383 | err = -ENOMEM; |
| 1384 | goto err_put_ctrl; |
| 1385 | } |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1386 | |
| 1387 | /* Initialize max_apid/min_apid to the opposite bounds, during |
| 1388 | * the irq domain translation, we are sure to update these */ |
| 1389 | pa->max_apid = 0; |
| 1390 | pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1; |
| 1391 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1392 | platform_set_drvdata(pdev, ctrl); |
| 1393 | raw_spin_lock_init(&pa->lock); |
| 1394 | |
| 1395 | ctrl->cmd = pmic_arb_cmd; |
| 1396 | ctrl->read_cmd = pmic_arb_read_cmd; |
| 1397 | ctrl->write_cmd = pmic_arb_write_cmd; |
| 1398 | |
David Collins | b2d9a40 | 2016-07-21 14:42:47 -0700 | [diff] [blame] | 1399 | if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) { |
| 1400 | err = pmic_arb_read_apid_map_v5(pa); |
| 1401 | if (err) { |
| 1402 | dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n", |
| 1403 | err); |
| 1404 | goto err_put_ctrl; |
| 1405 | } |
| 1406 | } |
| 1407 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1408 | dev_dbg(&pdev->dev, "adding irq domain\n"); |
| 1409 | pa->domain = irq_domain_add_tree(pdev->dev.of_node, |
| 1410 | &pmic_arb_irq_domain_ops, pa); |
| 1411 | if (!pa->domain) { |
| 1412 | dev_err(&pdev->dev, "unable to create irq_domain\n"); |
| 1413 | err = -ENOMEM; |
| 1414 | goto err_put_ctrl; |
| 1415 | } |
| 1416 | |
Thomas Gleixner | fb68ba6 | 2015-07-13 20:52:24 +0000 | [diff] [blame] | 1417 | irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa); |
Nicholas Troast | 237e914 | 2016-06-14 16:39:38 -0700 | [diff] [blame] | 1418 | enable_irq_wake(pa->irq); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1419 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1420 | err = spmi_controller_add(ctrl); |
| 1421 | if (err) |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1422 | goto err_domain_remove; |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1423 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1424 | return 0; |
| 1425 | |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1426 | err_domain_remove: |
Thomas Gleixner | fb68ba6 | 2015-07-13 20:52:24 +0000 | [diff] [blame] | 1427 | irq_set_chained_handler_and_data(pa->irq, NULL, NULL); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1428 | irq_domain_remove(pa->domain); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1429 | err_put_ctrl: |
| 1430 | spmi_controller_put(ctrl); |
| 1431 | return err; |
| 1432 | } |
| 1433 | |
| 1434 | static int spmi_pmic_arb_remove(struct platform_device *pdev) |
| 1435 | { |
| 1436 | struct spmi_controller *ctrl = platform_get_drvdata(pdev); |
Abhijeet Dharmapurikar | fbcfb7e | 2016-01-08 12:45:20 -0800 | [diff] [blame] | 1437 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
Abhijeet Dharmapurikar | 69dc3fc | 2016-11-07 15:51:24 -0800 | [diff] [blame] | 1438 | |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1439 | spmi_controller_remove(ctrl); |
Thomas Gleixner | fb68ba6 | 2015-07-13 20:52:24 +0000 | [diff] [blame] | 1440 | irq_set_chained_handler_and_data(pa->irq, NULL, NULL); |
Josh Cartwright | 67b563f | 2014-02-12 13:44:25 -0600 | [diff] [blame] | 1441 | irq_domain_remove(pa->domain); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1442 | spmi_controller_put(ctrl); |
| 1443 | return 0; |
| 1444 | } |
| 1445 | |
| 1446 | static const struct of_device_id spmi_pmic_arb_match_table[] = { |
| 1447 | { .compatible = "qcom,spmi-pmic-arb", }, |
| 1448 | {}, |
| 1449 | }; |
| 1450 | MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); |
| 1451 | |
| 1452 | static struct platform_driver spmi_pmic_arb_driver = { |
| 1453 | .probe = spmi_pmic_arb_probe, |
| 1454 | .remove = spmi_pmic_arb_remove, |
| 1455 | .driver = { |
| 1456 | .name = "spmi_pmic_arb", |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1457 | .of_match_table = spmi_pmic_arb_match_table, |
Patrick Daly | a118d1d | 2018-05-11 18:47:45 -0700 | [diff] [blame] | 1458 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1459 | }, |
| 1460 | }; |
Abhijeet Dharmapurikar | df9bf94 | 2015-09-23 11:36:23 -0700 | [diff] [blame] | 1461 | |
| 1462 | int __init spmi_pmic_arb_init(void) |
| 1463 | { |
| 1464 | return platform_driver_register(&spmi_pmic_arb_driver); |
| 1465 | } |
| 1466 | arch_initcall(spmi_pmic_arb_init); |
Kenneth Heitke | 39ae93e | 2014-02-12 13:44:24 -0600 | [diff] [blame] | 1467 | |
| 1468 | MODULE_LICENSE("GPL v2"); |
| 1469 | MODULE_ALIAS("platform:spmi_pmic_arb"); |