Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * Carsten Langgaard, carstenl@mips.com |
| 7 | * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. |
| 8 | * Copyright (C) 2001 Ralf Baechle |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 9 | * Copyright (C) 2013 Imagination Technologies Ltd. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | * Routines for generic manipulation of the interrupts found on the MIPS |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 12 | * Malta board. The interrupt controller is located in the South Bridge |
| 13 | * a PIIX4 device with two internal 82C95 interrupt controllers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | */ |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/irq.h> |
Paul Burton | 38ec82f | 2016-09-19 22:21:23 +0100 | [diff] [blame] | 17 | #include <linux/irqchip.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 19 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/interrupt.h> |
Dmitri Vorobiev | 54bf038 | 2008-01-24 19:52:49 +0300 | [diff] [blame] | 21 | #include <linux/io.h> |
Andrew Bresticker | 4060bbe | 2014-10-20 12:03:53 -0700 | [diff] [blame] | 22 | #include <linux/irqchip/mips-gic.h> |
Paul Burton | 38ec82f | 2016-09-19 22:21:23 +0100 | [diff] [blame] | 23 | #include <linux/of_irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <linux/kernel_stat.h> |
Ahmed S. Darwish | 25b8ac3 | 2007-02-05 04:42:11 +0200 | [diff] [blame] | 25 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #include <linux/random.h> |
| 27 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 28 | #include <asm/traps.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <asm/i8259.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 30 | #include <asm/irq_cpu.h> |
Ralf Baechle | ba38cdf | 2006-10-15 09:17:43 +0100 | [diff] [blame] | 31 | #include <asm/irq_regs.h> |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 32 | #include <asm/mips-cm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include <asm/mips-boards/malta.h> |
| 34 | #include <asm/mips-boards/maltaint.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/gt64120.h> |
| 36 | #include <asm/mips-boards/generic.h> |
| 37 | #include <asm/mips-boards/msc01_pci.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 38 | #include <asm/msc01_ic.h> |
David Howells | b81947c | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 39 | #include <asm/setup.h> |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 40 | #include <asm/rtlx.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 41 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | static inline int mips_pcibios_iack(void) |
| 43 | { |
| 44 | int irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * Determine highest priority pending interrupt by performing |
| 48 | * a PCI Interrupt Acknowledge cycle. |
| 49 | */ |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 50 | switch (mips_revision_sconid) { |
| 51 | case MIPS_REVISION_SCON_SOCIT: |
| 52 | case MIPS_REVISION_SCON_ROCIT: |
| 53 | case MIPS_REVISION_SCON_SOCITSC: |
| 54 | case MIPS_REVISION_SCON_SOCITSCP: |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 55 | MSC_READ(MSC01_PCI_IACK, irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | irq &= 0xff; |
| 57 | break; |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 58 | case MIPS_REVISION_SCON_GT64120: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | irq = GT_READ(GT_PCI0_IACK_OFS); |
| 60 | irq &= 0xff; |
| 61 | break; |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 62 | case MIPS_REVISION_SCON_BONITO: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | /* The following will generate a PCI IACK cycle on the |
| 64 | * Bonito controller. It's a little bit kludgy, but it |
| 65 | * was the easiest way to implement it in hardware at |
| 66 | * the given time. |
| 67 | */ |
| 68 | BONITO_PCIMAP_CFG = 0x20000; |
| 69 | |
| 70 | /* Flush Bonito register block */ |
Ralf Baechle | 6be63bb | 2011-03-29 11:48:22 +0200 | [diff] [blame] | 71 | (void) BONITO_PCIMAP_CFG; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 72 | iob(); /* sync */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | |
Chris Dearman | accfd35 | 2009-07-10 01:53:54 -0700 | [diff] [blame] | 74 | irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 75 | iob(); /* sync */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | irq &= 0xff; |
| 77 | BONITO_PCIMAP_CFG = 0; |
| 78 | break; |
| 79 | default: |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 80 | pr_emerg("Unknown system controller.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | return -1; |
| 82 | } |
| 83 | return irq; |
| 84 | } |
| 85 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 86 | static void corehi_irqdispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 88 | unsigned int intedge, intsteer, pcicmd, pcibadaddr; |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 89 | unsigned int pcimstat, intisr, inten, intpol; |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 90 | unsigned int intrcause, datalo, datahi; |
Ralf Baechle | ba38cdf | 2006-10-15 09:17:43 +0100 | [diff] [blame] | 91 | struct pt_regs *regs = get_irq_regs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 93 | pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n"); |
| 94 | pr_emerg("epc : %08lx\nStatus: %08lx\n" |
| 95 | "Cause : %08lx\nbadVaddr : %08lx\n", |
| 96 | regs->cp0_epc, regs->cp0_status, |
| 97 | regs->cp0_cause, regs->cp0_badvaddr); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 98 | |
| 99 | /* Read all the registers and then print them as there is a |
| 100 | problem with interspersed printk's upsetting the Bonito controller. |
| 101 | Do it for the others too. |
| 102 | */ |
| 103 | |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 104 | switch (mips_revision_sconid) { |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 105 | case MIPS_REVISION_SCON_SOCIT: |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 106 | case MIPS_REVISION_SCON_ROCIT: |
| 107 | case MIPS_REVISION_SCON_SOCITSC: |
| 108 | case MIPS_REVISION_SCON_SOCITSCP: |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 109 | ll_msc_irq(); |
| 110 | break; |
| 111 | case MIPS_REVISION_SCON_GT64120: |
| 112 | intrcause = GT_READ(GT_INTRCAUSE_OFS); |
| 113 | datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); |
| 114 | datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 115 | pr_emerg("GT_INTRCAUSE = %08x\n", intrcause); |
| 116 | pr_emerg("GT_CPUERR_ADDR = %02x%08x\n", |
Dmitri Vorobiev | 8216d34 | 2008-01-24 19:52:42 +0300 | [diff] [blame] | 117 | datahi, datalo); |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 118 | break; |
| 119 | case MIPS_REVISION_SCON_BONITO: |
| 120 | pcibadaddr = BONITO_PCIBADADDR; |
| 121 | pcimstat = BONITO_PCIMSTAT; |
| 122 | intisr = BONITO_INTISR; |
| 123 | inten = BONITO_INTEN; |
| 124 | intpol = BONITO_INTPOL; |
| 125 | intedge = BONITO_INTEDGE; |
| 126 | intsteer = BONITO_INTSTEER; |
| 127 | pcicmd = BONITO_PCICMD; |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 128 | pr_emerg("BONITO_INTISR = %08x\n", intisr); |
| 129 | pr_emerg("BONITO_INTEN = %08x\n", inten); |
| 130 | pr_emerg("BONITO_INTPOL = %08x\n", intpol); |
| 131 | pr_emerg("BONITO_INTEDGE = %08x\n", intedge); |
| 132 | pr_emerg("BONITO_INTSTEER = %08x\n", intsteer); |
| 133 | pr_emerg("BONITO_PCICMD = %08x\n", pcicmd); |
| 134 | pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr); |
| 135 | pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat); |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 136 | break; |
| 137 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 139 | die("CoreHi interrupt", regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | } |
| 141 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 142 | static irqreturn_t corehi_handler(int irq, void *dev_id) |
| 143 | { |
| 144 | corehi_irqdispatch(); |
| 145 | return IRQ_HANDLED; |
| 146 | } |
| 147 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 148 | #ifdef CONFIG_MIPS_MT_SMP |
| 149 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 150 | #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ |
| 151 | #define C_RESCHED C_SW0 |
| 152 | #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ |
| 153 | #define C_CALL C_SW1 |
| 154 | static int cpu_ipi_resched_irq, cpu_ipi_call_irq; |
| 155 | |
| 156 | static void ipi_resched_dispatch(void) |
| 157 | { |
| 158 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); |
| 159 | } |
| 160 | |
| 161 | static void ipi_call_dispatch(void) |
| 162 | { |
| 163 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); |
| 164 | } |
| 165 | |
| 166 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
| 167 | { |
Deng-Cheng Zhu | 9c1f6e0 | 2014-02-28 10:23:01 -0800 | [diff] [blame] | 168 | #ifdef CONFIG_MIPS_VPE_APSP_API_CMP |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 169 | if (aprp_hook) |
| 170 | aprp_hook(); |
| 171 | #endif |
| 172 | |
Peter Zijlstra | 184748c | 2011-04-05 17:23:39 +0200 | [diff] [blame] | 173 | scheduler_ipi(); |
| 174 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 175 | return IRQ_HANDLED; |
| 176 | } |
| 177 | |
| 178 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) |
| 179 | { |
Alex Smith | 4ace613 | 2015-07-24 16:57:49 +0100 | [diff] [blame] | 180 | generic_smp_call_function_interrupt(); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 181 | |
| 182 | return IRQ_HANDLED; |
| 183 | } |
| 184 | |
| 185 | static struct irqaction irq_resched = { |
| 186 | .handler = ipi_resched_interrupt, |
Yong Zhang | 8b5690f | 2011-11-22 14:38:03 +0000 | [diff] [blame] | 187 | .flags = IRQF_PERCPU, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 188 | .name = "IPI_resched" |
| 189 | }; |
| 190 | |
| 191 | static struct irqaction irq_call = { |
| 192 | .handler = ipi_call_interrupt, |
Yong Zhang | 8b5690f | 2011-11-22 14:38:03 +0000 | [diff] [blame] | 193 | .flags = IRQF_PERCPU, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 194 | .name = "IPI_call" |
| 195 | }; |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 196 | #endif /* CONFIG_MIPS_MT_SMP */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 197 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 198 | static struct irqaction corehi_irqaction = { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 199 | .handler = corehi_handler, |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 200 | .name = "CoreHi", |
| 201 | .flags = IRQF_NO_THREAD, |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 202 | }; |
| 203 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 204 | static msc_irqmap_t msc_irqmap[] __initdata = { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 205 | {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 206 | {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 207 | }; |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 208 | static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 209 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 210 | static msc_irqmap_t msc_eicirqmap[] __initdata = { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 211 | {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, |
| 212 | {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, |
| 213 | {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, |
| 214 | {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, |
| 215 | {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, |
| 216 | {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, |
| 217 | {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 218 | {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 219 | {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, |
| 220 | {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} |
| 221 | }; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 222 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 223 | static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 224 | |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 225 | void __init arch_init_ipiirq(int irq, struct irqaction *action) |
| 226 | { |
| 227 | setup_irq(irq, action); |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 228 | irq_set_handler(irq, handle_percpu_irq); |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 229 | } |
| 230 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | void __init arch_init_irq(void) |
| 232 | { |
Paul Burton | 38ec82f | 2016-09-19 22:21:23 +0100 | [diff] [blame] | 233 | int corehi_irq; |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 234 | |
Paul Burton | 38ec82f | 2016-09-19 22:21:23 +0100 | [diff] [blame] | 235 | i8259_set_poll(mips_pcibios_iack); |
| 236 | irqchip_init(); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 237 | |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 238 | switch (mips_revision_sconid) { |
| 239 | case MIPS_REVISION_SCON_SOCIT: |
| 240 | case MIPS_REVISION_SCON_ROCIT: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 241 | if (cpu_has_veic) |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 242 | init_msc_irqs(MIPS_MSC01_IC_REG_BASE, |
| 243 | MSC01E_INT_BASE, msc_eicirqmap, |
| 244 | msc_nr_eicirqs); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 245 | else |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 246 | init_msc_irqs(MIPS_MSC01_IC_REG_BASE, |
| 247 | MSC01C_INT_BASE, msc_irqmap, |
| 248 | msc_nr_irqs); |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 249 | break; |
| 250 | |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 251 | case MIPS_REVISION_SCON_SOCITSC: |
| 252 | case MIPS_REVISION_SCON_SOCITSCP: |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 253 | if (cpu_has_veic) |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 254 | init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, |
| 255 | MSC01E_INT_BASE, msc_eicirqmap, |
| 256 | msc_nr_eicirqs); |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 257 | else |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 258 | init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, |
| 259 | MSC01C_INT_BASE, msc_irqmap, |
| 260 | msc_nr_irqs); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 261 | } |
| 262 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 263 | if (gic_present) { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 264 | corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 265 | } else { |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 266 | #if defined(CONFIG_MIPS_MT_SMP) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 267 | /* set up ipi interrupts */ |
| 268 | if (cpu_has_veic) { |
| 269 | set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); |
| 270 | set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); |
| 271 | cpu_ipi_resched_irq = MSC01E_INT_SW0; |
| 272 | cpu_ipi_call_irq = MSC01E_INT_SW1; |
| 273 | } else { |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 274 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + |
| 275 | MIPS_CPU_IPI_RESCHED_IRQ; |
| 276 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + |
| 277 | MIPS_CPU_IPI_CALL_IRQ; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 278 | } |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 279 | arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); |
| 280 | arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 281 | #endif |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 282 | if (cpu_has_veic) { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 283 | set_vi_handler(MSC01E_INT_COREHI, |
| 284 | corehi_irqdispatch); |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 285 | corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; |
| 286 | } else { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 287 | corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; |
| 288 | } |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 289 | } |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 290 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 291 | setup_irq(corehi_irq, &corehi_irqaction); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 292 | } |