Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 28 | #include <linux/cpufreq.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "intel_drv.h" |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 31 | #include "../../../platform/x86/intel_ips.h" |
| 32 | #include <linux/module.h> |
Damien Lespiau | f4db932 | 2013-06-24 22:59:50 +0100 | [diff] [blame] | 33 | #include <drm/i915_powerwell.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 34 | |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 35 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
| 36 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
| 37 | * during in-memory transfers and, therefore, reduce the power packet. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 38 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 39 | * The benefits of FBC are mostly visible with solid backgrounds and |
| 40 | * variation-less patterns. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 41 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 42 | * FBC-related functionality can be enabled by the means of the |
| 43 | * i915.i915_enable_fbc parameter |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 44 | */ |
| 45 | |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 46 | static bool intel_crtc_active(struct drm_crtc *crtc) |
| 47 | { |
| 48 | /* Be paranoid as we can arrive here with only partial |
| 49 | * state retrieved from the hardware during setup. |
| 50 | */ |
| 51 | return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; |
| 52 | } |
| 53 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 54 | static void i8xx_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 55 | { |
| 56 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 57 | u32 fbc_ctl; |
| 58 | |
| 59 | /* Disable compression */ |
| 60 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 61 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 62 | return; |
| 63 | |
| 64 | fbc_ctl &= ~FBC_CTL_EN; |
| 65 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 66 | |
| 67 | /* Wait for compressing bit to clear */ |
| 68 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
| 69 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 70 | return; |
| 71 | } |
| 72 | |
| 73 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 74 | } |
| 75 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 76 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 77 | { |
| 78 | struct drm_device *dev = crtc->dev; |
| 79 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 80 | struct drm_framebuffer *fb = crtc->fb; |
| 81 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 82 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 83 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 84 | int cfb_pitch; |
| 85 | int plane, i; |
| 86 | u32 fbc_ctl, fbc_ctl2; |
| 87 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 88 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 89 | if (fb->pitches[0] < cfb_pitch) |
| 90 | cfb_pitch = fb->pitches[0]; |
| 91 | |
| 92 | /* FBC_CTL wants 64B units */ |
| 93 | cfb_pitch = (cfb_pitch / 64) - 1; |
| 94 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; |
| 95 | |
| 96 | /* Clear old tags */ |
| 97 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 98 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 99 | |
| 100 | /* Set it up... */ |
| 101 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
| 102 | fbc_ctl2 |= plane; |
| 103 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 104 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 105 | |
| 106 | /* enable it... */ |
| 107 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |
| 108 | if (IS_I945GM(dev)) |
| 109 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
| 110 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
| 111 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
| 112 | fbc_ctl |= obj->fence_reg; |
| 113 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 114 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 115 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ", |
| 116 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 117 | } |
| 118 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 119 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 120 | { |
| 121 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 122 | |
| 123 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 124 | } |
| 125 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 126 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 127 | { |
| 128 | struct drm_device *dev = crtc->dev; |
| 129 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 130 | struct drm_framebuffer *fb = crtc->fb; |
| 131 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 132 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 134 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
| 135 | unsigned long stall_watermark = 200; |
| 136 | u32 dpfc_ctl; |
| 137 | |
| 138 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
| 139 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
| 140 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 141 | |
| 142 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 143 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 144 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 145 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 146 | |
| 147 | /* enable it... */ |
| 148 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); |
| 149 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 150 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 151 | } |
| 152 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 153 | static void g4x_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 154 | { |
| 155 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 156 | u32 dpfc_ctl; |
| 157 | |
| 158 | /* Disable compression */ |
| 159 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 160 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 161 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 162 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 163 | |
| 164 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 165 | } |
| 166 | } |
| 167 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 168 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 169 | { |
| 170 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 171 | |
| 172 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 173 | } |
| 174 | |
| 175 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
| 176 | { |
| 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 178 | u32 blt_ecoskpd; |
| 179 | |
| 180 | /* Make sure blitter notifies FBC of writes */ |
| 181 | gen6_gt_force_wake_get(dev_priv); |
| 182 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
| 183 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
| 184 | GEN6_BLITTER_LOCK_SHIFT; |
| 185 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 186 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
| 187 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 188 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
| 189 | GEN6_BLITTER_LOCK_SHIFT); |
| 190 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 191 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
| 192 | gen6_gt_force_wake_put(dev_priv); |
| 193 | } |
| 194 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 195 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 196 | { |
| 197 | struct drm_device *dev = crtc->dev; |
| 198 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 199 | struct drm_framebuffer *fb = crtc->fb; |
| 200 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 201 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 203 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
| 204 | unsigned long stall_watermark = 200; |
| 205 | u32 dpfc_ctl; |
| 206 | |
| 207 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 208 | dpfc_ctl &= DPFC_RESERVED; |
| 209 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); |
| 210 | /* Set persistent mode for front-buffer rendering, ala X. */ |
| 211 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; |
| 212 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
| 213 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
| 214 | |
| 215 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
| 216 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | |
| 217 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); |
| 218 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 219 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 220 | /* enable it... */ |
| 221 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 222 | |
| 223 | if (IS_GEN6(dev)) { |
| 224 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 225 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 226 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 227 | sandybridge_blit_fbc_update(dev); |
| 228 | } |
| 229 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 230 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 231 | } |
| 232 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 233 | static void ironlake_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 234 | { |
| 235 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 236 | u32 dpfc_ctl; |
| 237 | |
| 238 | /* Disable compression */ |
| 239 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 240 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 241 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 242 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 243 | |
Rodrigo Vivi | b74ea10 | 2013-05-09 14:08:38 -0300 | [diff] [blame] | 244 | if (IS_IVYBRIDGE(dev)) |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 245 | /* WaFbcDisableDpfcClockGating:ivb */ |
Rodrigo Vivi | b74ea10 | 2013-05-09 14:08:38 -0300 | [diff] [blame] | 246 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 247 | I915_READ(ILK_DSPCLK_GATE_D) & |
| 248 | ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); |
| 249 | |
Rodrigo Vivi | d89f207 | 2013-05-09 14:20:50 -0300 | [diff] [blame] | 250 | if (IS_HASWELL(dev)) |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 251 | /* WaFbcDisableDpfcClockGating:hsw */ |
Rodrigo Vivi | d89f207 | 2013-05-09 14:20:50 -0300 | [diff] [blame] | 252 | I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, |
| 253 | I915_READ(HSW_CLKGATE_DISABLE_PART_1) & |
| 254 | ~HSW_DPFC_GATING_DISABLE); |
| 255 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 256 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 257 | } |
| 258 | } |
| 259 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 260 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 261 | { |
| 262 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 263 | |
| 264 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 265 | } |
| 266 | |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 267 | static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| 268 | { |
| 269 | struct drm_device *dev = crtc->dev; |
| 270 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 271 | struct drm_framebuffer *fb = crtc->fb; |
| 272 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 273 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 274 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 275 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 276 | I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj)); |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 277 | |
| 278 | I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | |
| 279 | IVB_DPFC_CTL_FENCE_EN | |
| 280 | intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); |
| 281 | |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 282 | if (IS_IVYBRIDGE(dev)) { |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 283 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 284 | I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 285 | /* WaFbcDisableDpfcClockGating:ivb */ |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 286 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 287 | I915_READ(ILK_DSPCLK_GATE_D) | |
| 288 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE); |
Rodrigo Vivi | 2855416 | 2013-05-06 19:37:37 -0300 | [diff] [blame] | 289 | } else { |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 290 | /* WaFbcAsynchFlipDisableFbcQueue:hsw */ |
Rodrigo Vivi | 2855416 | 2013-05-06 19:37:37 -0300 | [diff] [blame] | 291 | I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), |
| 292 | HSW_BYPASS_FBC_QUEUE); |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 293 | /* WaFbcDisableDpfcClockGating:hsw */ |
Rodrigo Vivi | d89f207 | 2013-05-09 14:20:50 -0300 | [diff] [blame] | 294 | I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, |
| 295 | I915_READ(HSW_CLKGATE_DISABLE_PART_1) | |
| 296 | HSW_DPFC_GATING_DISABLE); |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 297 | } |
Rodrigo Vivi | b74ea10 | 2013-05-09 14:08:38 -0300 | [diff] [blame] | 298 | |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 299 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 300 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 301 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 302 | |
| 303 | sandybridge_blit_fbc_update(dev); |
| 304 | |
| 305 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
| 306 | } |
| 307 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 308 | bool intel_fbc_enabled(struct drm_device *dev) |
| 309 | { |
| 310 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 311 | |
| 312 | if (!dev_priv->display.fbc_enabled) |
| 313 | return false; |
| 314 | |
| 315 | return dev_priv->display.fbc_enabled(dev); |
| 316 | } |
| 317 | |
| 318 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 319 | { |
| 320 | struct intel_fbc_work *work = |
| 321 | container_of(to_delayed_work(__work), |
| 322 | struct intel_fbc_work, work); |
| 323 | struct drm_device *dev = work->crtc->dev; |
| 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 325 | |
| 326 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 327 | if (work == dev_priv->fbc.fbc_work) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 328 | /* Double check that we haven't switched fb without cancelling |
| 329 | * the prior work. |
| 330 | */ |
| 331 | if (work->crtc->fb == work->fb) { |
| 332 | dev_priv->display.enable_fbc(work->crtc, |
| 333 | work->interval); |
| 334 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 335 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
| 336 | dev_priv->fbc.fb_id = work->crtc->fb->base.id; |
| 337 | dev_priv->fbc.y = work->crtc->y; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 338 | } |
| 339 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 340 | dev_priv->fbc.fbc_work = NULL; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 341 | } |
| 342 | mutex_unlock(&dev->struct_mutex); |
| 343 | |
| 344 | kfree(work); |
| 345 | } |
| 346 | |
| 347 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
| 348 | { |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 349 | if (dev_priv->fbc.fbc_work == NULL) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 350 | return; |
| 351 | |
| 352 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
| 353 | |
| 354 | /* Synchronisation is provided by struct_mutex and checking of |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 355 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 356 | * entirely asynchronously. |
| 357 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 358 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 359 | /* tasklet was killed before being run, clean up */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 360 | kfree(dev_priv->fbc.fbc_work); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 361 | |
| 362 | /* Mark the work as no longer wanted so that if it does |
| 363 | * wake-up (because the work was already running and waiting |
| 364 | * for our mutex), it will discover that is no longer |
| 365 | * necessary to run. |
| 366 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 367 | dev_priv->fbc.fbc_work = NULL; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 368 | } |
| 369 | |
Damien Lespiau | b63fb44 | 2013-06-24 16:22:01 +0100 | [diff] [blame] | 370 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 371 | { |
| 372 | struct intel_fbc_work *work; |
| 373 | struct drm_device *dev = crtc->dev; |
| 374 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 375 | |
| 376 | if (!dev_priv->display.enable_fbc) |
| 377 | return; |
| 378 | |
| 379 | intel_cancel_fbc_work(dev_priv); |
| 380 | |
| 381 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 382 | if (work == NULL) { |
Paulo Zanoni | 6cdcb5e | 2013-06-12 17:27:29 -0300 | [diff] [blame] | 383 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 384 | dev_priv->display.enable_fbc(crtc, interval); |
| 385 | return; |
| 386 | } |
| 387 | |
| 388 | work->crtc = crtc; |
| 389 | work->fb = crtc->fb; |
| 390 | work->interval = interval; |
| 391 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
| 392 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 393 | dev_priv->fbc.fbc_work = work; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 394 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 395 | /* Delay the actual enabling to let pageflipping cease and the |
| 396 | * display to settle before starting the compression. Note that |
| 397 | * this delay also serves a second purpose: it allows for a |
| 398 | * vblank to pass after disabling the FBC before we attempt |
| 399 | * to modify the control registers. |
| 400 | * |
| 401 | * A more complicated solution would involve tracking vblanks |
| 402 | * following the termination of the page-flipping sequence |
| 403 | * and indeed performing the enable as a co-routine and not |
| 404 | * waiting synchronously upon the vblank. |
Damien Lespiau | 7457d61 | 2013-06-07 17:41:07 +0100 | [diff] [blame] | 405 | * |
| 406 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 407 | */ |
| 408 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
| 409 | } |
| 410 | |
| 411 | void intel_disable_fbc(struct drm_device *dev) |
| 412 | { |
| 413 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 414 | |
| 415 | intel_cancel_fbc_work(dev_priv); |
| 416 | |
| 417 | if (!dev_priv->display.disable_fbc) |
| 418 | return; |
| 419 | |
| 420 | dev_priv->display.disable_fbc(dev); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 421 | dev_priv->fbc.plane = -1; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 422 | } |
| 423 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 424 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
| 425 | enum no_fbc_reason reason) |
| 426 | { |
| 427 | if (dev_priv->fbc.no_fbc_reason == reason) |
| 428 | return false; |
| 429 | |
| 430 | dev_priv->fbc.no_fbc_reason = reason; |
| 431 | return true; |
| 432 | } |
| 433 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 434 | /** |
| 435 | * intel_update_fbc - enable/disable FBC as needed |
| 436 | * @dev: the drm_device |
| 437 | * |
| 438 | * Set up the framebuffer compression hardware at mode set time. We |
| 439 | * enable it if possible: |
| 440 | * - plane A only (on pre-965) |
| 441 | * - no pixel mulitply/line duplication |
| 442 | * - no alpha buffer discard |
| 443 | * - no dual wide |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 444 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 445 | * |
| 446 | * We can't assume that any compression will take place (worst case), |
| 447 | * so the compressed buffer has to be the same size as the uncompressed |
| 448 | * one. It also must reside (along with the line length buffer) in |
| 449 | * stolen memory. |
| 450 | * |
| 451 | * We need to enable/disable FBC on a global basis. |
| 452 | */ |
| 453 | void intel_update_fbc(struct drm_device *dev) |
| 454 | { |
| 455 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 456 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
| 457 | struct intel_crtc *intel_crtc; |
| 458 | struct drm_framebuffer *fb; |
| 459 | struct intel_framebuffer *intel_fb; |
| 460 | struct drm_i915_gem_object *obj; |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 461 | unsigned int max_hdisplay, max_vdisplay; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 462 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 463 | if (!I915_HAS_FBC(dev)) { |
| 464 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 465 | return; |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 466 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 467 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 468 | if (!i915_powersave) { |
| 469 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
| 470 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 471 | return; |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 472 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 473 | |
| 474 | /* |
| 475 | * If FBC is already on, we just have to verify that we can |
| 476 | * keep it that way... |
| 477 | * Need to disable if: |
| 478 | * - more than one pipe is active |
| 479 | * - changing FBC params (stride, fence, mode) |
| 480 | * - new fb is too large to fit in compressed buffer |
| 481 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 482 | */ |
| 483 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 484 | if (intel_crtc_active(tmp_crtc) && |
| 485 | !to_intel_crtc(tmp_crtc)->primary_disabled) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 486 | if (crtc) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 487 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
| 488 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 489 | goto out_disable; |
| 490 | } |
| 491 | crtc = tmp_crtc; |
| 492 | } |
| 493 | } |
| 494 | |
| 495 | if (!crtc || crtc->fb == NULL) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 496 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
| 497 | DRM_DEBUG_KMS("no output, disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 498 | goto out_disable; |
| 499 | } |
| 500 | |
| 501 | intel_crtc = to_intel_crtc(crtc); |
| 502 | fb = crtc->fb; |
| 503 | intel_fb = to_intel_framebuffer(fb); |
| 504 | obj = intel_fb->obj; |
| 505 | |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 506 | if (i915_enable_fbc < 0 && |
| 507 | INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 508 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
| 509 | DRM_DEBUG_KMS("disabled per chip default\n"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 510 | goto out_disable; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 511 | } |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 512 | if (!i915_enable_fbc) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 513 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
| 514 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 515 | goto out_disable; |
| 516 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 517 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
| 518 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 519 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
| 520 | DRM_DEBUG_KMS("mode incompatible with compression, " |
| 521 | "disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 522 | goto out_disable; |
| 523 | } |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 524 | |
| 525 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
| 526 | max_hdisplay = 4096; |
| 527 | max_vdisplay = 2048; |
| 528 | } else { |
| 529 | max_hdisplay = 2048; |
| 530 | max_vdisplay = 1536; |
| 531 | } |
| 532 | if ((crtc->mode.hdisplay > max_hdisplay) || |
| 533 | (crtc->mode.vdisplay > max_vdisplay)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 534 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
| 535 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 536 | goto out_disable; |
| 537 | } |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 538 | if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) && |
| 539 | intel_crtc->plane != 0) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 540 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
| 541 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 542 | goto out_disable; |
| 543 | } |
| 544 | |
| 545 | /* The use of a CPU fence is mandatory in order to detect writes |
| 546 | * by the CPU to the scanout and trigger updates to the FBC. |
| 547 | */ |
| 548 | if (obj->tiling_mode != I915_TILING_X || |
| 549 | obj->fence_reg == I915_FENCE_REG_NONE) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 550 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
| 551 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 552 | goto out_disable; |
| 553 | } |
| 554 | |
| 555 | /* If the kernel debugger is active, always disable compression */ |
| 556 | if (in_dbg_master()) |
| 557 | goto out_disable; |
| 558 | |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 559 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 560 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
| 561 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 562 | goto out_disable; |
| 563 | } |
| 564 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 565 | /* If the scanout has not changed, don't modify the FBC settings. |
| 566 | * Note that we make the fundamental assumption that the fb->obj |
| 567 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 568 | * without first being decoupled from the scanout and FBC disabled. |
| 569 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 570 | if (dev_priv->fbc.plane == intel_crtc->plane && |
| 571 | dev_priv->fbc.fb_id == fb->base.id && |
| 572 | dev_priv->fbc.y == crtc->y) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 573 | return; |
| 574 | |
| 575 | if (intel_fbc_enabled(dev)) { |
| 576 | /* We update FBC along two paths, after changing fb/crtc |
| 577 | * configuration (modeswitching) and after page-flipping |
| 578 | * finishes. For the latter, we know that not only did |
| 579 | * we disable the FBC at the start of the page-flip |
| 580 | * sequence, but also more than one vblank has passed. |
| 581 | * |
| 582 | * For the former case of modeswitching, it is possible |
| 583 | * to switch between two FBC valid configurations |
| 584 | * instantaneously so we do need to disable the FBC |
| 585 | * before we can modify its control registers. We also |
| 586 | * have to wait for the next vblank for that to take |
| 587 | * effect. However, since we delay enabling FBC we can |
| 588 | * assume that a vblank has passed since disabling and |
| 589 | * that we can safely alter the registers in the deferred |
| 590 | * callback. |
| 591 | * |
| 592 | * In the scenario that we go from a valid to invalid |
| 593 | * and then back to valid FBC configuration we have |
| 594 | * no strict enforcement that a vblank occurred since |
| 595 | * disabling the FBC. However, along all current pipe |
| 596 | * disabling paths we do need to wait for a vblank at |
| 597 | * some point. And we wait before enabling FBC anyway. |
| 598 | */ |
| 599 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
| 600 | intel_disable_fbc(dev); |
| 601 | } |
| 602 | |
| 603 | intel_enable_fbc(crtc, 500); |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 604 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 605 | return; |
| 606 | |
| 607 | out_disable: |
| 608 | /* Multiple disables should be harmless */ |
| 609 | if (intel_fbc_enabled(dev)) { |
| 610 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
| 611 | intel_disable_fbc(dev); |
| 612 | } |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 613 | i915_gem_stolen_cleanup_compression(dev); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 614 | } |
| 615 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 616 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
| 617 | { |
| 618 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 619 | u32 tmp; |
| 620 | |
| 621 | tmp = I915_READ(CLKCFG); |
| 622 | |
| 623 | switch (tmp & CLKCFG_FSB_MASK) { |
| 624 | case CLKCFG_FSB_533: |
| 625 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 626 | break; |
| 627 | case CLKCFG_FSB_800: |
| 628 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 629 | break; |
| 630 | case CLKCFG_FSB_667: |
| 631 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 632 | break; |
| 633 | case CLKCFG_FSB_400: |
| 634 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 635 | break; |
| 636 | } |
| 637 | |
| 638 | switch (tmp & CLKCFG_MEM_MASK) { |
| 639 | case CLKCFG_MEM_533: |
| 640 | dev_priv->mem_freq = 533; |
| 641 | break; |
| 642 | case CLKCFG_MEM_667: |
| 643 | dev_priv->mem_freq = 667; |
| 644 | break; |
| 645 | case CLKCFG_MEM_800: |
| 646 | dev_priv->mem_freq = 800; |
| 647 | break; |
| 648 | } |
| 649 | |
| 650 | /* detect pineview DDR3 setting */ |
| 651 | tmp = I915_READ(CSHRDDR3CTL); |
| 652 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
| 653 | } |
| 654 | |
| 655 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 656 | { |
| 657 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 658 | u16 ddrpll, csipll; |
| 659 | |
| 660 | ddrpll = I915_READ16(DDRMPLL1); |
| 661 | csipll = I915_READ16(CSIPLL0); |
| 662 | |
| 663 | switch (ddrpll & 0xff) { |
| 664 | case 0xc: |
| 665 | dev_priv->mem_freq = 800; |
| 666 | break; |
| 667 | case 0x10: |
| 668 | dev_priv->mem_freq = 1066; |
| 669 | break; |
| 670 | case 0x14: |
| 671 | dev_priv->mem_freq = 1333; |
| 672 | break; |
| 673 | case 0x18: |
| 674 | dev_priv->mem_freq = 1600; |
| 675 | break; |
| 676 | default: |
| 677 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 678 | ddrpll & 0xff); |
| 679 | dev_priv->mem_freq = 0; |
| 680 | break; |
| 681 | } |
| 682 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 683 | dev_priv->ips.r_t = dev_priv->mem_freq; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 684 | |
| 685 | switch (csipll & 0x3ff) { |
| 686 | case 0x00c: |
| 687 | dev_priv->fsb_freq = 3200; |
| 688 | break; |
| 689 | case 0x00e: |
| 690 | dev_priv->fsb_freq = 3733; |
| 691 | break; |
| 692 | case 0x010: |
| 693 | dev_priv->fsb_freq = 4266; |
| 694 | break; |
| 695 | case 0x012: |
| 696 | dev_priv->fsb_freq = 4800; |
| 697 | break; |
| 698 | case 0x014: |
| 699 | dev_priv->fsb_freq = 5333; |
| 700 | break; |
| 701 | case 0x016: |
| 702 | dev_priv->fsb_freq = 5866; |
| 703 | break; |
| 704 | case 0x018: |
| 705 | dev_priv->fsb_freq = 6400; |
| 706 | break; |
| 707 | default: |
| 708 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 709 | csipll & 0x3ff); |
| 710 | dev_priv->fsb_freq = 0; |
| 711 | break; |
| 712 | } |
| 713 | |
| 714 | if (dev_priv->fsb_freq == 3200) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 715 | dev_priv->ips.c_m = 0; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 716 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 717 | dev_priv->ips.c_m = 1; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 718 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 719 | dev_priv->ips.c_m = 2; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 720 | } |
| 721 | } |
| 722 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 723 | static const struct cxsr_latency cxsr_latency_table[] = { |
| 724 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 725 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 726 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 727 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 728 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
| 729 | |
| 730 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 731 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 732 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 733 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 734 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
| 735 | |
| 736 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 737 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 738 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 739 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 740 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
| 741 | |
| 742 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 743 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 744 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 745 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 746 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
| 747 | |
| 748 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 749 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 750 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 751 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 752 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
| 753 | |
| 754 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 755 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 756 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 757 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 758 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
| 759 | }; |
| 760 | |
Daniel Vetter | 63c6227 | 2012-04-21 23:17:55 +0200 | [diff] [blame] | 761 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 762 | int is_ddr3, |
| 763 | int fsb, |
| 764 | int mem) |
| 765 | { |
| 766 | const struct cxsr_latency *latency; |
| 767 | int i; |
| 768 | |
| 769 | if (fsb == 0 || mem == 0) |
| 770 | return NULL; |
| 771 | |
| 772 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 773 | latency = &cxsr_latency_table[i]; |
| 774 | if (is_desktop == latency->is_desktop && |
| 775 | is_ddr3 == latency->is_ddr3 && |
| 776 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 777 | return latency; |
| 778 | } |
| 779 | |
| 780 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 781 | |
| 782 | return NULL; |
| 783 | } |
| 784 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 785 | static void pineview_disable_cxsr(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 786 | { |
| 787 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 788 | |
| 789 | /* deactivate cxsr */ |
| 790 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
| 791 | } |
| 792 | |
| 793 | /* |
| 794 | * Latency for FIFO fetches is dependent on several factors: |
| 795 | * - memory configuration (speed, channels) |
| 796 | * - chipset |
| 797 | * - current MCH state |
| 798 | * It can be fairly high in some situations, so here we assume a fairly |
| 799 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 800 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 801 | * and power consumption (set it too low to save power and we might see |
| 802 | * FIFO underruns and display "flicker"). |
| 803 | * |
| 804 | * A value of 5us seems to be a good balance; safe for very low end |
| 805 | * platforms but not overly aggressive on lower latency configs. |
| 806 | */ |
| 807 | static const int latency_ns = 5000; |
| 808 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 809 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 810 | { |
| 811 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 812 | uint32_t dsparb = I915_READ(DSPARB); |
| 813 | int size; |
| 814 | |
| 815 | size = dsparb & 0x7f; |
| 816 | if (plane) |
| 817 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
| 818 | |
| 819 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 820 | plane ? "B" : "A", size); |
| 821 | |
| 822 | return size; |
| 823 | } |
| 824 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 825 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 826 | { |
| 827 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 828 | uint32_t dsparb = I915_READ(DSPARB); |
| 829 | int size; |
| 830 | |
| 831 | size = dsparb & 0x1ff; |
| 832 | if (plane) |
| 833 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
| 834 | size >>= 1; /* Convert to cachelines */ |
| 835 | |
| 836 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 837 | plane ? "B" : "A", size); |
| 838 | |
| 839 | return size; |
| 840 | } |
| 841 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 842 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 843 | { |
| 844 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 845 | uint32_t dsparb = I915_READ(DSPARB); |
| 846 | int size; |
| 847 | |
| 848 | size = dsparb & 0x7f; |
| 849 | size >>= 2; /* Convert to cachelines */ |
| 850 | |
| 851 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 852 | plane ? "B" : "A", |
| 853 | size); |
| 854 | |
| 855 | return size; |
| 856 | } |
| 857 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 858 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 859 | { |
| 860 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 861 | uint32_t dsparb = I915_READ(DSPARB); |
| 862 | int size; |
| 863 | |
| 864 | size = dsparb & 0x7f; |
| 865 | size >>= 1; /* Convert to cachelines */ |
| 866 | |
| 867 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 868 | plane ? "B" : "A", size); |
| 869 | |
| 870 | return size; |
| 871 | } |
| 872 | |
| 873 | /* Pineview has different values for various configs */ |
| 874 | static const struct intel_watermark_params pineview_display_wm = { |
| 875 | PINEVIEW_DISPLAY_FIFO, |
| 876 | PINEVIEW_MAX_WM, |
| 877 | PINEVIEW_DFT_WM, |
| 878 | PINEVIEW_GUARD_WM, |
| 879 | PINEVIEW_FIFO_LINE_SIZE |
| 880 | }; |
| 881 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
| 882 | PINEVIEW_DISPLAY_FIFO, |
| 883 | PINEVIEW_MAX_WM, |
| 884 | PINEVIEW_DFT_HPLLOFF_WM, |
| 885 | PINEVIEW_GUARD_WM, |
| 886 | PINEVIEW_FIFO_LINE_SIZE |
| 887 | }; |
| 888 | static const struct intel_watermark_params pineview_cursor_wm = { |
| 889 | PINEVIEW_CURSOR_FIFO, |
| 890 | PINEVIEW_CURSOR_MAX_WM, |
| 891 | PINEVIEW_CURSOR_DFT_WM, |
| 892 | PINEVIEW_CURSOR_GUARD_WM, |
| 893 | PINEVIEW_FIFO_LINE_SIZE, |
| 894 | }; |
| 895 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
| 896 | PINEVIEW_CURSOR_FIFO, |
| 897 | PINEVIEW_CURSOR_MAX_WM, |
| 898 | PINEVIEW_CURSOR_DFT_WM, |
| 899 | PINEVIEW_CURSOR_GUARD_WM, |
| 900 | PINEVIEW_FIFO_LINE_SIZE |
| 901 | }; |
| 902 | static const struct intel_watermark_params g4x_wm_info = { |
| 903 | G4X_FIFO_SIZE, |
| 904 | G4X_MAX_WM, |
| 905 | G4X_MAX_WM, |
| 906 | 2, |
| 907 | G4X_FIFO_LINE_SIZE, |
| 908 | }; |
| 909 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
| 910 | I965_CURSOR_FIFO, |
| 911 | I965_CURSOR_MAX_WM, |
| 912 | I965_CURSOR_DFT_WM, |
| 913 | 2, |
| 914 | G4X_FIFO_LINE_SIZE, |
| 915 | }; |
| 916 | static const struct intel_watermark_params valleyview_wm_info = { |
| 917 | VALLEYVIEW_FIFO_SIZE, |
| 918 | VALLEYVIEW_MAX_WM, |
| 919 | VALLEYVIEW_MAX_WM, |
| 920 | 2, |
| 921 | G4X_FIFO_LINE_SIZE, |
| 922 | }; |
| 923 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
| 924 | I965_CURSOR_FIFO, |
| 925 | VALLEYVIEW_CURSOR_MAX_WM, |
| 926 | I965_CURSOR_DFT_WM, |
| 927 | 2, |
| 928 | G4X_FIFO_LINE_SIZE, |
| 929 | }; |
| 930 | static const struct intel_watermark_params i965_cursor_wm_info = { |
| 931 | I965_CURSOR_FIFO, |
| 932 | I965_CURSOR_MAX_WM, |
| 933 | I965_CURSOR_DFT_WM, |
| 934 | 2, |
| 935 | I915_FIFO_LINE_SIZE, |
| 936 | }; |
| 937 | static const struct intel_watermark_params i945_wm_info = { |
| 938 | I945_FIFO_SIZE, |
| 939 | I915_MAX_WM, |
| 940 | 1, |
| 941 | 2, |
| 942 | I915_FIFO_LINE_SIZE |
| 943 | }; |
| 944 | static const struct intel_watermark_params i915_wm_info = { |
| 945 | I915_FIFO_SIZE, |
| 946 | I915_MAX_WM, |
| 947 | 1, |
| 948 | 2, |
| 949 | I915_FIFO_LINE_SIZE |
| 950 | }; |
| 951 | static const struct intel_watermark_params i855_wm_info = { |
| 952 | I855GM_FIFO_SIZE, |
| 953 | I915_MAX_WM, |
| 954 | 1, |
| 955 | 2, |
| 956 | I830_FIFO_LINE_SIZE |
| 957 | }; |
| 958 | static const struct intel_watermark_params i830_wm_info = { |
| 959 | I830_FIFO_SIZE, |
| 960 | I915_MAX_WM, |
| 961 | 1, |
| 962 | 2, |
| 963 | I830_FIFO_LINE_SIZE |
| 964 | }; |
| 965 | |
| 966 | static const struct intel_watermark_params ironlake_display_wm_info = { |
| 967 | ILK_DISPLAY_FIFO, |
| 968 | ILK_DISPLAY_MAXWM, |
| 969 | ILK_DISPLAY_DFTWM, |
| 970 | 2, |
| 971 | ILK_FIFO_LINE_SIZE |
| 972 | }; |
| 973 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
| 974 | ILK_CURSOR_FIFO, |
| 975 | ILK_CURSOR_MAXWM, |
| 976 | ILK_CURSOR_DFTWM, |
| 977 | 2, |
| 978 | ILK_FIFO_LINE_SIZE |
| 979 | }; |
| 980 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
| 981 | ILK_DISPLAY_SR_FIFO, |
| 982 | ILK_DISPLAY_MAX_SRWM, |
| 983 | ILK_DISPLAY_DFT_SRWM, |
| 984 | 2, |
| 985 | ILK_FIFO_LINE_SIZE |
| 986 | }; |
| 987 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
| 988 | ILK_CURSOR_SR_FIFO, |
| 989 | ILK_CURSOR_MAX_SRWM, |
| 990 | ILK_CURSOR_DFT_SRWM, |
| 991 | 2, |
| 992 | ILK_FIFO_LINE_SIZE |
| 993 | }; |
| 994 | |
| 995 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
| 996 | SNB_DISPLAY_FIFO, |
| 997 | SNB_DISPLAY_MAXWM, |
| 998 | SNB_DISPLAY_DFTWM, |
| 999 | 2, |
| 1000 | SNB_FIFO_LINE_SIZE |
| 1001 | }; |
| 1002 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
| 1003 | SNB_CURSOR_FIFO, |
| 1004 | SNB_CURSOR_MAXWM, |
| 1005 | SNB_CURSOR_DFTWM, |
| 1006 | 2, |
| 1007 | SNB_FIFO_LINE_SIZE |
| 1008 | }; |
| 1009 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
| 1010 | SNB_DISPLAY_SR_FIFO, |
| 1011 | SNB_DISPLAY_MAX_SRWM, |
| 1012 | SNB_DISPLAY_DFT_SRWM, |
| 1013 | 2, |
| 1014 | SNB_FIFO_LINE_SIZE |
| 1015 | }; |
| 1016 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
| 1017 | SNB_CURSOR_SR_FIFO, |
| 1018 | SNB_CURSOR_MAX_SRWM, |
| 1019 | SNB_CURSOR_DFT_SRWM, |
| 1020 | 2, |
| 1021 | SNB_FIFO_LINE_SIZE |
| 1022 | }; |
| 1023 | |
| 1024 | |
| 1025 | /** |
| 1026 | * intel_calculate_wm - calculate watermark level |
| 1027 | * @clock_in_khz: pixel clock |
| 1028 | * @wm: chip FIFO params |
| 1029 | * @pixel_size: display pixel size |
| 1030 | * @latency_ns: memory latency for the platform |
| 1031 | * |
| 1032 | * Calculate the watermark level (the level at which the display plane will |
| 1033 | * start fetching from memory again). Each chip has a different display |
| 1034 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 1035 | * in the correct intel_watermark_params structure. |
| 1036 | * |
| 1037 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 1038 | * on the pixel size. When it reaches the watermark level, it'll start |
| 1039 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 1040 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 1041 | * will occur, and a display engine hang could result. |
| 1042 | */ |
| 1043 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 1044 | const struct intel_watermark_params *wm, |
| 1045 | int fifo_size, |
| 1046 | int pixel_size, |
| 1047 | unsigned long latency_ns) |
| 1048 | { |
| 1049 | long entries_required, wm_size; |
| 1050 | |
| 1051 | /* |
| 1052 | * Note: we need to make sure we don't overflow for various clock & |
| 1053 | * latency values. |
| 1054 | * clocks go from a few thousand to several hundred thousand. |
| 1055 | * latency is usually a few thousand |
| 1056 | */ |
| 1057 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 1058 | 1000; |
| 1059 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
| 1060 | |
| 1061 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
| 1062 | |
| 1063 | wm_size = fifo_size - (entries_required + wm->guard_size); |
| 1064 | |
| 1065 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
| 1066 | |
| 1067 | /* Don't promote wm_size to unsigned... */ |
| 1068 | if (wm_size > (long)wm->max_wm) |
| 1069 | wm_size = wm->max_wm; |
| 1070 | if (wm_size <= 0) |
| 1071 | wm_size = wm->default_wm; |
| 1072 | return wm_size; |
| 1073 | } |
| 1074 | |
| 1075 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 1076 | { |
| 1077 | struct drm_crtc *crtc, *enabled = NULL; |
| 1078 | |
| 1079 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1080 | if (intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1081 | if (enabled) |
| 1082 | return NULL; |
| 1083 | enabled = crtc; |
| 1084 | } |
| 1085 | } |
| 1086 | |
| 1087 | return enabled; |
| 1088 | } |
| 1089 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1090 | static void pineview_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1091 | { |
| 1092 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1093 | struct drm_crtc *crtc; |
| 1094 | const struct cxsr_latency *latency; |
| 1095 | u32 reg; |
| 1096 | unsigned long wm; |
| 1097 | |
| 1098 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 1099 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 1100 | if (!latency) { |
| 1101 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 1102 | pineview_disable_cxsr(dev); |
| 1103 | return; |
| 1104 | } |
| 1105 | |
| 1106 | crtc = single_enabled_crtc(dev); |
| 1107 | if (crtc) { |
| 1108 | int clock = crtc->mode.clock; |
| 1109 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1110 | |
| 1111 | /* Display SR */ |
| 1112 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 1113 | pineview_display_wm.fifo_size, |
| 1114 | pixel_size, latency->display_sr); |
| 1115 | reg = I915_READ(DSPFW1); |
| 1116 | reg &= ~DSPFW_SR_MASK; |
| 1117 | reg |= wm << DSPFW_SR_SHIFT; |
| 1118 | I915_WRITE(DSPFW1, reg); |
| 1119 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 1120 | |
| 1121 | /* cursor SR */ |
| 1122 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 1123 | pineview_display_wm.fifo_size, |
| 1124 | pixel_size, latency->cursor_sr); |
| 1125 | reg = I915_READ(DSPFW3); |
| 1126 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 1127 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 1128 | I915_WRITE(DSPFW3, reg); |
| 1129 | |
| 1130 | /* Display HPLL off SR */ |
| 1131 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 1132 | pineview_display_hplloff_wm.fifo_size, |
| 1133 | pixel_size, latency->display_hpll_disable); |
| 1134 | reg = I915_READ(DSPFW3); |
| 1135 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 1136 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 1137 | I915_WRITE(DSPFW3, reg); |
| 1138 | |
| 1139 | /* cursor HPLL off SR */ |
| 1140 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 1141 | pineview_display_hplloff_wm.fifo_size, |
| 1142 | pixel_size, latency->cursor_hpll_disable); |
| 1143 | reg = I915_READ(DSPFW3); |
| 1144 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 1145 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 1146 | I915_WRITE(DSPFW3, reg); |
| 1147 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 1148 | |
| 1149 | /* activate cxsr */ |
| 1150 | I915_WRITE(DSPFW3, |
| 1151 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
| 1152 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
| 1153 | } else { |
| 1154 | pineview_disable_cxsr(dev); |
| 1155 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
| 1156 | } |
| 1157 | } |
| 1158 | |
| 1159 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 1160 | int plane, |
| 1161 | const struct intel_watermark_params *display, |
| 1162 | int display_latency_ns, |
| 1163 | const struct intel_watermark_params *cursor, |
| 1164 | int cursor_latency_ns, |
| 1165 | int *plane_wm, |
| 1166 | int *cursor_wm) |
| 1167 | { |
| 1168 | struct drm_crtc *crtc; |
| 1169 | int htotal, hdisplay, clock, pixel_size; |
| 1170 | int line_time_us, line_count; |
| 1171 | int entries, tlb_miss; |
| 1172 | |
| 1173 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1174 | if (!intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1175 | *cursor_wm = cursor->guard_size; |
| 1176 | *plane_wm = display->guard_size; |
| 1177 | return false; |
| 1178 | } |
| 1179 | |
| 1180 | htotal = crtc->mode.htotal; |
| 1181 | hdisplay = crtc->mode.hdisplay; |
| 1182 | clock = crtc->mode.clock; |
| 1183 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1184 | |
| 1185 | /* Use the small buffer method to calculate plane watermark */ |
| 1186 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 1187 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 1188 | if (tlb_miss > 0) |
| 1189 | entries += tlb_miss; |
| 1190 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 1191 | *plane_wm = entries + display->guard_size; |
| 1192 | if (*plane_wm > (int)display->max_wm) |
| 1193 | *plane_wm = display->max_wm; |
| 1194 | |
| 1195 | /* Use the large buffer method to calculate cursor watermark */ |
| 1196 | line_time_us = ((htotal * 1000) / clock); |
| 1197 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
| 1198 | entries = line_count * 64 * pixel_size; |
| 1199 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 1200 | if (tlb_miss > 0) |
| 1201 | entries += tlb_miss; |
| 1202 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1203 | *cursor_wm = entries + cursor->guard_size; |
| 1204 | if (*cursor_wm > (int)cursor->max_wm) |
| 1205 | *cursor_wm = (int)cursor->max_wm; |
| 1206 | |
| 1207 | return true; |
| 1208 | } |
| 1209 | |
| 1210 | /* |
| 1211 | * Check the wm result. |
| 1212 | * |
| 1213 | * If any calculated watermark values is larger than the maximum value that |
| 1214 | * can be programmed into the associated watermark register, that watermark |
| 1215 | * must be disabled. |
| 1216 | */ |
| 1217 | static bool g4x_check_srwm(struct drm_device *dev, |
| 1218 | int display_wm, int cursor_wm, |
| 1219 | const struct intel_watermark_params *display, |
| 1220 | const struct intel_watermark_params *cursor) |
| 1221 | { |
| 1222 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 1223 | display_wm, cursor_wm); |
| 1224 | |
| 1225 | if (display_wm > display->max_wm) { |
| 1226 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
| 1227 | display_wm, display->max_wm); |
| 1228 | return false; |
| 1229 | } |
| 1230 | |
| 1231 | if (cursor_wm > cursor->max_wm) { |
| 1232 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
| 1233 | cursor_wm, cursor->max_wm); |
| 1234 | return false; |
| 1235 | } |
| 1236 | |
| 1237 | if (!(display_wm || cursor_wm)) { |
| 1238 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 1239 | return false; |
| 1240 | } |
| 1241 | |
| 1242 | return true; |
| 1243 | } |
| 1244 | |
| 1245 | static bool g4x_compute_srwm(struct drm_device *dev, |
| 1246 | int plane, |
| 1247 | int latency_ns, |
| 1248 | const struct intel_watermark_params *display, |
| 1249 | const struct intel_watermark_params *cursor, |
| 1250 | int *display_wm, int *cursor_wm) |
| 1251 | { |
| 1252 | struct drm_crtc *crtc; |
| 1253 | int hdisplay, htotal, pixel_size, clock; |
| 1254 | unsigned long line_time_us; |
| 1255 | int line_count, line_size; |
| 1256 | int small, large; |
| 1257 | int entries; |
| 1258 | |
| 1259 | if (!latency_ns) { |
| 1260 | *display_wm = *cursor_wm = 0; |
| 1261 | return false; |
| 1262 | } |
| 1263 | |
| 1264 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1265 | hdisplay = crtc->mode.hdisplay; |
| 1266 | htotal = crtc->mode.htotal; |
| 1267 | clock = crtc->mode.clock; |
| 1268 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1269 | |
| 1270 | line_time_us = (htotal * 1000) / clock; |
| 1271 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1272 | line_size = hdisplay * pixel_size; |
| 1273 | |
| 1274 | /* Use the minimum of the small and large buffer method for primary */ |
| 1275 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1276 | large = line_count * line_size; |
| 1277 | |
| 1278 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1279 | *display_wm = entries + display->guard_size; |
| 1280 | |
| 1281 | /* calculate the self-refresh watermark for display cursor */ |
| 1282 | entries = line_count * pixel_size * 64; |
| 1283 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1284 | *cursor_wm = entries + cursor->guard_size; |
| 1285 | |
| 1286 | return g4x_check_srwm(dev, |
| 1287 | *display_wm, *cursor_wm, |
| 1288 | display, cursor); |
| 1289 | } |
| 1290 | |
| 1291 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
| 1292 | int plane, |
| 1293 | int *plane_prec_mult, |
| 1294 | int *plane_dl, |
| 1295 | int *cursor_prec_mult, |
| 1296 | int *cursor_dl) |
| 1297 | { |
| 1298 | struct drm_crtc *crtc; |
| 1299 | int clock, pixel_size; |
| 1300 | int entries; |
| 1301 | |
| 1302 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1303 | if (!intel_crtc_active(crtc)) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1304 | return false; |
| 1305 | |
| 1306 | clock = crtc->mode.clock; /* VESA DOT Clock */ |
| 1307 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
| 1308 | |
| 1309 | entries = (clock / 1000) * pixel_size; |
| 1310 | *plane_prec_mult = (entries > 256) ? |
| 1311 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
| 1312 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
| 1313 | pixel_size); |
| 1314 | |
| 1315 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
| 1316 | *cursor_prec_mult = (entries > 256) ? |
| 1317 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
| 1318 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
| 1319 | |
| 1320 | return true; |
| 1321 | } |
| 1322 | |
| 1323 | /* |
| 1324 | * Update drain latency registers of memory arbiter |
| 1325 | * |
| 1326 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
| 1327 | * to be programmed. Each plane has a drain latency multiplier and a drain |
| 1328 | * latency value. |
| 1329 | */ |
| 1330 | |
| 1331 | static void vlv_update_drain_latency(struct drm_device *dev) |
| 1332 | { |
| 1333 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1334 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
| 1335 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
| 1336 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
| 1337 | either 16 or 32 */ |
| 1338 | |
| 1339 | /* For plane A, Cursor A */ |
| 1340 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
| 1341 | &cursor_prec_mult, &cursora_dl)) { |
| 1342 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1343 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
| 1344 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1345 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
| 1346 | |
| 1347 | I915_WRITE(VLV_DDL1, cursora_prec | |
| 1348 | (cursora_dl << DDL_CURSORA_SHIFT) | |
| 1349 | planea_prec | planea_dl); |
| 1350 | } |
| 1351 | |
| 1352 | /* For plane B, Cursor B */ |
| 1353 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
| 1354 | &cursor_prec_mult, &cursorb_dl)) { |
| 1355 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1356 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
| 1357 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1358 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
| 1359 | |
| 1360 | I915_WRITE(VLV_DDL2, cursorb_prec | |
| 1361 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
| 1362 | planeb_prec | planeb_dl); |
| 1363 | } |
| 1364 | } |
| 1365 | |
| 1366 | #define single_plane_enabled(mask) is_power_of_2(mask) |
| 1367 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1368 | static void valleyview_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1369 | { |
| 1370 | static const int sr_latency_ns = 12000; |
| 1371 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1372 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1373 | int plane_sr, cursor_sr; |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 1374 | int ignore_plane_sr, ignore_cursor_sr; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1375 | unsigned int enabled = 0; |
| 1376 | |
| 1377 | vlv_update_drain_latency(dev); |
| 1378 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1379 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1380 | &valleyview_wm_info, latency_ns, |
| 1381 | &valleyview_cursor_wm_info, latency_ns, |
| 1382 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1383 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1384 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1385 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1386 | &valleyview_wm_info, latency_ns, |
| 1387 | &valleyview_cursor_wm_info, latency_ns, |
| 1388 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1389 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1390 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1391 | if (single_plane_enabled(enabled) && |
| 1392 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1393 | sr_latency_ns, |
| 1394 | &valleyview_wm_info, |
| 1395 | &valleyview_cursor_wm_info, |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 1396 | &plane_sr, &ignore_cursor_sr) && |
| 1397 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1398 | 2*sr_latency_ns, |
| 1399 | &valleyview_wm_info, |
| 1400 | &valleyview_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1401 | &ignore_plane_sr, &cursor_sr)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1402 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1403 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1404 | I915_WRITE(FW_BLC_SELF_VLV, |
| 1405 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1406 | plane_sr = cursor_sr = 0; |
| 1407 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1408 | |
| 1409 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 1410 | planea_wm, cursora_wm, |
| 1411 | planeb_wm, cursorb_wm, |
| 1412 | plane_sr, cursor_sr); |
| 1413 | |
| 1414 | I915_WRITE(DSPFW1, |
| 1415 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1416 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1417 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1418 | planea_wm); |
| 1419 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1420 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1421 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1422 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1423 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
| 1424 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1425 | } |
| 1426 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1427 | static void g4x_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1428 | { |
| 1429 | static const int sr_latency_ns = 12000; |
| 1430 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1431 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1432 | int plane_sr, cursor_sr; |
| 1433 | unsigned int enabled = 0; |
| 1434 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1435 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1436 | &g4x_wm_info, latency_ns, |
| 1437 | &g4x_cursor_wm_info, latency_ns, |
| 1438 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1439 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1440 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1441 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1442 | &g4x_wm_info, latency_ns, |
| 1443 | &g4x_cursor_wm_info, latency_ns, |
| 1444 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1445 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1446 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1447 | if (single_plane_enabled(enabled) && |
| 1448 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1449 | sr_latency_ns, |
| 1450 | &g4x_wm_info, |
| 1451 | &g4x_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1452 | &plane_sr, &cursor_sr)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1453 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1454 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1455 | I915_WRITE(FW_BLC_SELF, |
| 1456 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1457 | plane_sr = cursor_sr = 0; |
| 1458 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1459 | |
| 1460 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 1461 | planea_wm, cursora_wm, |
| 1462 | planeb_wm, cursorb_wm, |
| 1463 | plane_sr, cursor_sr); |
| 1464 | |
| 1465 | I915_WRITE(DSPFW1, |
| 1466 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1467 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1468 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1469 | planea_wm); |
| 1470 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1471 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1472 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1473 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 1474 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1475 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1476 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1477 | } |
| 1478 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1479 | static void i965_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1480 | { |
| 1481 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1482 | struct drm_crtc *crtc; |
| 1483 | int srwm = 1; |
| 1484 | int cursor_sr = 16; |
| 1485 | |
| 1486 | /* Calc sr entries for one plane configs */ |
| 1487 | crtc = single_enabled_crtc(dev); |
| 1488 | if (crtc) { |
| 1489 | /* self-refresh has much higher latency */ |
| 1490 | static const int sr_latency_ns = 12000; |
| 1491 | int clock = crtc->mode.clock; |
| 1492 | int htotal = crtc->mode.htotal; |
| 1493 | int hdisplay = crtc->mode.hdisplay; |
| 1494 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1495 | unsigned long line_time_us; |
| 1496 | int entries; |
| 1497 | |
| 1498 | line_time_us = ((htotal * 1000) / clock); |
| 1499 | |
| 1500 | /* Use ns/us then divide to preserve precision */ |
| 1501 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1502 | pixel_size * hdisplay; |
| 1503 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
| 1504 | srwm = I965_FIFO_SIZE - entries; |
| 1505 | if (srwm < 0) |
| 1506 | srwm = 1; |
| 1507 | srwm &= 0x1ff; |
| 1508 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 1509 | entries, srwm); |
| 1510 | |
| 1511 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1512 | pixel_size * 64; |
| 1513 | entries = DIV_ROUND_UP(entries, |
| 1514 | i965_cursor_wm_info.cacheline_size); |
| 1515 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 1516 | (entries + i965_cursor_wm_info.guard_size); |
| 1517 | |
| 1518 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 1519 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 1520 | |
| 1521 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 1522 | "cursor %d\n", srwm, cursor_sr); |
| 1523 | |
| 1524 | if (IS_CRESTLINE(dev)) |
| 1525 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 1526 | } else { |
| 1527 | /* Turn off self refresh if both pipes are enabled */ |
| 1528 | if (IS_CRESTLINE(dev)) |
| 1529 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 1530 | & ~FW_BLC_SELF_EN); |
| 1531 | } |
| 1532 | |
| 1533 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 1534 | srwm); |
| 1535 | |
| 1536 | /* 965 has limitations... */ |
| 1537 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
| 1538 | (8 << 16) | (8 << 8) | (8 << 0)); |
| 1539 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
| 1540 | /* update cursor SR watermark */ |
| 1541 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1542 | } |
| 1543 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1544 | static void i9xx_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1545 | { |
| 1546 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1547 | const struct intel_watermark_params *wm_info; |
| 1548 | uint32_t fwater_lo; |
| 1549 | uint32_t fwater_hi; |
| 1550 | int cwm, srwm = 1; |
| 1551 | int fifo_size; |
| 1552 | int planea_wm, planeb_wm; |
| 1553 | struct drm_crtc *crtc, *enabled = NULL; |
| 1554 | |
| 1555 | if (IS_I945GM(dev)) |
| 1556 | wm_info = &i945_wm_info; |
| 1557 | else if (!IS_GEN2(dev)) |
| 1558 | wm_info = &i915_wm_info; |
| 1559 | else |
| 1560 | wm_info = &i855_wm_info; |
| 1561 | |
| 1562 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 1563 | crtc = intel_get_crtc_for_plane(dev, 0); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1564 | if (intel_crtc_active(crtc)) { |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1565 | int cpp = crtc->fb->bits_per_pixel / 8; |
| 1566 | if (IS_GEN2(dev)) |
| 1567 | cpp = 4; |
| 1568 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1569 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1570 | wm_info, fifo_size, cpp, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1571 | latency_ns); |
| 1572 | enabled = crtc; |
| 1573 | } else |
| 1574 | planea_wm = fifo_size - wm_info->guard_size; |
| 1575 | |
| 1576 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 1577 | crtc = intel_get_crtc_for_plane(dev, 1); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1578 | if (intel_crtc_active(crtc)) { |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1579 | int cpp = crtc->fb->bits_per_pixel / 8; |
| 1580 | if (IS_GEN2(dev)) |
| 1581 | cpp = 4; |
| 1582 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1583 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1584 | wm_info, fifo_size, cpp, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1585 | latency_ns); |
| 1586 | if (enabled == NULL) |
| 1587 | enabled = crtc; |
| 1588 | else |
| 1589 | enabled = NULL; |
| 1590 | } else |
| 1591 | planeb_wm = fifo_size - wm_info->guard_size; |
| 1592 | |
| 1593 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 1594 | |
| 1595 | /* |
| 1596 | * Overlay gets an aggressive default since video jitter is bad. |
| 1597 | */ |
| 1598 | cwm = 2; |
| 1599 | |
| 1600 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
| 1601 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1602 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
| 1603 | else if (IS_I915GM(dev)) |
| 1604 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); |
| 1605 | |
| 1606 | /* Calc sr entries for one plane configs */ |
| 1607 | if (HAS_FW_BLC(dev) && enabled) { |
| 1608 | /* self-refresh has much higher latency */ |
| 1609 | static const int sr_latency_ns = 6000; |
| 1610 | int clock = enabled->mode.clock; |
| 1611 | int htotal = enabled->mode.htotal; |
| 1612 | int hdisplay = enabled->mode.hdisplay; |
| 1613 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
| 1614 | unsigned long line_time_us; |
| 1615 | int entries; |
| 1616 | |
| 1617 | line_time_us = (htotal * 1000) / clock; |
| 1618 | |
| 1619 | /* Use ns/us then divide to preserve precision */ |
| 1620 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1621 | pixel_size * hdisplay; |
| 1622 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 1623 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 1624 | srwm = wm_info->fifo_size - entries; |
| 1625 | if (srwm < 0) |
| 1626 | srwm = 1; |
| 1627 | |
| 1628 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1629 | I915_WRITE(FW_BLC_SELF, |
| 1630 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 1631 | else if (IS_I915GM(dev)) |
| 1632 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 1633 | } |
| 1634 | |
| 1635 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
| 1636 | planea_wm, planeb_wm, cwm, srwm); |
| 1637 | |
| 1638 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 1639 | fwater_hi = (cwm & 0x1f); |
| 1640 | |
| 1641 | /* Set request length to 8 cachelines per fetch */ |
| 1642 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 1643 | fwater_hi = fwater_hi | (1 << 8); |
| 1644 | |
| 1645 | I915_WRITE(FW_BLC, fwater_lo); |
| 1646 | I915_WRITE(FW_BLC2, fwater_hi); |
| 1647 | |
| 1648 | if (HAS_FW_BLC(dev)) { |
| 1649 | if (enabled) { |
| 1650 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1651 | I915_WRITE(FW_BLC_SELF, |
| 1652 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
| 1653 | else if (IS_I915GM(dev)) |
| 1654 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); |
| 1655 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
| 1656 | } else |
| 1657 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
| 1658 | } |
| 1659 | } |
| 1660 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1661 | static void i830_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1662 | { |
| 1663 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1664 | struct drm_crtc *crtc; |
| 1665 | uint32_t fwater_lo; |
| 1666 | int planea_wm; |
| 1667 | |
| 1668 | crtc = single_enabled_crtc(dev); |
| 1669 | if (crtc == NULL) |
| 1670 | return; |
| 1671 | |
| 1672 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
| 1673 | dev_priv->display.get_fifo_size(dev, 0), |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1674 | 4, latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1675 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
| 1676 | fwater_lo |= (3<<8) | planea_wm; |
| 1677 | |
| 1678 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
| 1679 | |
| 1680 | I915_WRITE(FW_BLC, fwater_lo); |
| 1681 | } |
| 1682 | |
| 1683 | #define ILK_LP0_PLANE_LATENCY 700 |
| 1684 | #define ILK_LP0_CURSOR_LATENCY 1300 |
| 1685 | |
| 1686 | /* |
| 1687 | * Check the wm result. |
| 1688 | * |
| 1689 | * If any calculated watermark values is larger than the maximum value that |
| 1690 | * can be programmed into the associated watermark register, that watermark |
| 1691 | * must be disabled. |
| 1692 | */ |
| 1693 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
| 1694 | int fbc_wm, int display_wm, int cursor_wm, |
| 1695 | const struct intel_watermark_params *display, |
| 1696 | const struct intel_watermark_params *cursor) |
| 1697 | { |
| 1698 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1699 | |
| 1700 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," |
| 1701 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); |
| 1702 | |
| 1703 | if (fbc_wm > SNB_FBC_MAX_SRWM) { |
| 1704 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", |
| 1705 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
| 1706 | |
| 1707 | /* fbc has it's own way to disable FBC WM */ |
| 1708 | I915_WRITE(DISP_ARB_CTL, |
| 1709 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); |
| 1710 | return false; |
Ville Syrjälä | 615aaa5 | 2013-04-24 21:09:10 +0300 | [diff] [blame] | 1711 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 1712 | /* enable FBC WM (except on ILK, where it must remain off) */ |
| 1713 | I915_WRITE(DISP_ARB_CTL, |
| 1714 | I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1715 | } |
| 1716 | |
| 1717 | if (display_wm > display->max_wm) { |
| 1718 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
| 1719 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
| 1720 | return false; |
| 1721 | } |
| 1722 | |
| 1723 | if (cursor_wm > cursor->max_wm) { |
| 1724 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
| 1725 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
| 1726 | return false; |
| 1727 | } |
| 1728 | |
| 1729 | if (!(fbc_wm || display_wm || cursor_wm)) { |
| 1730 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); |
| 1731 | return false; |
| 1732 | } |
| 1733 | |
| 1734 | return true; |
| 1735 | } |
| 1736 | |
| 1737 | /* |
| 1738 | * Compute watermark values of WM[1-3], |
| 1739 | */ |
| 1740 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
| 1741 | int latency_ns, |
| 1742 | const struct intel_watermark_params *display, |
| 1743 | const struct intel_watermark_params *cursor, |
| 1744 | int *fbc_wm, int *display_wm, int *cursor_wm) |
| 1745 | { |
| 1746 | struct drm_crtc *crtc; |
| 1747 | unsigned long line_time_us; |
| 1748 | int hdisplay, htotal, pixel_size, clock; |
| 1749 | int line_count, line_size; |
| 1750 | int small, large; |
| 1751 | int entries; |
| 1752 | |
| 1753 | if (!latency_ns) { |
| 1754 | *fbc_wm = *display_wm = *cursor_wm = 0; |
| 1755 | return false; |
| 1756 | } |
| 1757 | |
| 1758 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 1759 | hdisplay = crtc->mode.hdisplay; |
| 1760 | htotal = crtc->mode.htotal; |
| 1761 | clock = crtc->mode.clock; |
| 1762 | pixel_size = crtc->fb->bits_per_pixel / 8; |
| 1763 | |
| 1764 | line_time_us = (htotal * 1000) / clock; |
| 1765 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1766 | line_size = hdisplay * pixel_size; |
| 1767 | |
| 1768 | /* Use the minimum of the small and large buffer method for primary */ |
| 1769 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1770 | large = line_count * line_size; |
| 1771 | |
| 1772 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1773 | *display_wm = entries + display->guard_size; |
| 1774 | |
| 1775 | /* |
| 1776 | * Spec says: |
| 1777 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
| 1778 | */ |
| 1779 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; |
| 1780 | |
| 1781 | /* calculate the self-refresh watermark for display cursor */ |
| 1782 | entries = line_count * pixel_size * 64; |
| 1783 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1784 | *cursor_wm = entries + cursor->guard_size; |
| 1785 | |
| 1786 | return ironlake_check_srwm(dev, level, |
| 1787 | *fbc_wm, *display_wm, *cursor_wm, |
| 1788 | display, cursor); |
| 1789 | } |
| 1790 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1791 | static void ironlake_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1792 | { |
| 1793 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1794 | int fbc_wm, plane_wm, cursor_wm; |
| 1795 | unsigned int enabled; |
| 1796 | |
| 1797 | enabled = 0; |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1798 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1799 | &ironlake_display_wm_info, |
| 1800 | ILK_LP0_PLANE_LATENCY, |
| 1801 | &ironlake_cursor_wm_info, |
| 1802 | ILK_LP0_CURSOR_LATENCY, |
| 1803 | &plane_wm, &cursor_wm)) { |
| 1804 | I915_WRITE(WM0_PIPEA_ILK, |
| 1805 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 1806 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 1807 | " plane %d, " "cursor: %d\n", |
| 1808 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1809 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1810 | } |
| 1811 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1812 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1813 | &ironlake_display_wm_info, |
| 1814 | ILK_LP0_PLANE_LATENCY, |
| 1815 | &ironlake_cursor_wm_info, |
| 1816 | ILK_LP0_CURSOR_LATENCY, |
| 1817 | &plane_wm, &cursor_wm)) { |
| 1818 | I915_WRITE(WM0_PIPEB_ILK, |
| 1819 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); |
| 1820 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 1821 | " plane %d, cursor: %d\n", |
| 1822 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1823 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1824 | } |
| 1825 | |
| 1826 | /* |
| 1827 | * Calculate and update the self-refresh watermark only when one |
| 1828 | * display plane is used. |
| 1829 | */ |
| 1830 | I915_WRITE(WM3_LP_ILK, 0); |
| 1831 | I915_WRITE(WM2_LP_ILK, 0); |
| 1832 | I915_WRITE(WM1_LP_ILK, 0); |
| 1833 | |
| 1834 | if (!single_plane_enabled(enabled)) |
| 1835 | return; |
| 1836 | enabled = ffs(enabled) - 1; |
| 1837 | |
| 1838 | /* WM1 */ |
| 1839 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 1840 | ILK_READ_WM1_LATENCY() * 500, |
| 1841 | &ironlake_display_srwm_info, |
| 1842 | &ironlake_cursor_srwm_info, |
| 1843 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1844 | return; |
| 1845 | |
| 1846 | I915_WRITE(WM1_LP_ILK, |
| 1847 | WM1_LP_SR_EN | |
| 1848 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1849 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1850 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1851 | cursor_wm); |
| 1852 | |
| 1853 | /* WM2 */ |
| 1854 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 1855 | ILK_READ_WM2_LATENCY() * 500, |
| 1856 | &ironlake_display_srwm_info, |
| 1857 | &ironlake_cursor_srwm_info, |
| 1858 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1859 | return; |
| 1860 | |
| 1861 | I915_WRITE(WM2_LP_ILK, |
| 1862 | WM2_LP_EN | |
| 1863 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1864 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1865 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1866 | cursor_wm); |
| 1867 | |
| 1868 | /* |
| 1869 | * WM3 is unsupported on ILK, probably because we don't have latency |
| 1870 | * data for that power state |
| 1871 | */ |
| 1872 | } |
| 1873 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 1874 | static void sandybridge_update_wm(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1875 | { |
| 1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1877 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
| 1878 | u32 val; |
| 1879 | int fbc_wm, plane_wm, cursor_wm; |
| 1880 | unsigned int enabled; |
| 1881 | |
| 1882 | enabled = 0; |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1883 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1884 | &sandybridge_display_wm_info, latency, |
| 1885 | &sandybridge_cursor_wm_info, latency, |
| 1886 | &plane_wm, &cursor_wm)) { |
| 1887 | val = I915_READ(WM0_PIPEA_ILK); |
| 1888 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 1889 | I915_WRITE(WM0_PIPEA_ILK, val | |
| 1890 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 1891 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 1892 | " plane %d, " "cursor: %d\n", |
| 1893 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1894 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1895 | } |
| 1896 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1897 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1898 | &sandybridge_display_wm_info, latency, |
| 1899 | &sandybridge_cursor_wm_info, latency, |
| 1900 | &plane_wm, &cursor_wm)) { |
| 1901 | val = I915_READ(WM0_PIPEB_ILK); |
| 1902 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 1903 | I915_WRITE(WM0_PIPEB_ILK, val | |
| 1904 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 1905 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 1906 | " plane %d, cursor: %d\n", |
| 1907 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1908 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1909 | } |
| 1910 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1911 | /* |
| 1912 | * Calculate and update the self-refresh watermark only when one |
| 1913 | * display plane is used. |
| 1914 | * |
| 1915 | * SNB support 3 levels of watermark. |
| 1916 | * |
| 1917 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
| 1918 | * and disabled in the descending order |
| 1919 | * |
| 1920 | */ |
| 1921 | I915_WRITE(WM3_LP_ILK, 0); |
| 1922 | I915_WRITE(WM2_LP_ILK, 0); |
| 1923 | I915_WRITE(WM1_LP_ILK, 0); |
| 1924 | |
| 1925 | if (!single_plane_enabled(enabled) || |
| 1926 | dev_priv->sprite_scaling_enabled) |
| 1927 | return; |
| 1928 | enabled = ffs(enabled) - 1; |
| 1929 | |
| 1930 | /* WM1 */ |
| 1931 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 1932 | SNB_READ_WM1_LATENCY() * 500, |
| 1933 | &sandybridge_display_srwm_info, |
| 1934 | &sandybridge_cursor_srwm_info, |
| 1935 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1936 | return; |
| 1937 | |
| 1938 | I915_WRITE(WM1_LP_ILK, |
| 1939 | WM1_LP_SR_EN | |
| 1940 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1941 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1942 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1943 | cursor_wm); |
| 1944 | |
| 1945 | /* WM2 */ |
| 1946 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 1947 | SNB_READ_WM2_LATENCY() * 500, |
| 1948 | &sandybridge_display_srwm_info, |
| 1949 | &sandybridge_cursor_srwm_info, |
| 1950 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1951 | return; |
| 1952 | |
| 1953 | I915_WRITE(WM2_LP_ILK, |
| 1954 | WM2_LP_EN | |
| 1955 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1956 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1957 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1958 | cursor_wm); |
| 1959 | |
| 1960 | /* WM3 */ |
| 1961 | if (!ironlake_compute_srwm(dev, 3, enabled, |
| 1962 | SNB_READ_WM3_LATENCY() * 500, |
| 1963 | &sandybridge_display_srwm_info, |
| 1964 | &sandybridge_cursor_srwm_info, |
| 1965 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 1966 | return; |
| 1967 | |
| 1968 | I915_WRITE(WM3_LP_ILK, |
| 1969 | WM3_LP_EN | |
| 1970 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 1971 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 1972 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 1973 | cursor_wm); |
| 1974 | } |
| 1975 | |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 1976 | static void ivybridge_update_wm(struct drm_device *dev) |
| 1977 | { |
| 1978 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1979 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
| 1980 | u32 val; |
| 1981 | int fbc_wm, plane_wm, cursor_wm; |
| 1982 | int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; |
| 1983 | unsigned int enabled; |
| 1984 | |
| 1985 | enabled = 0; |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1986 | if (g4x_compute_wm0(dev, PIPE_A, |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 1987 | &sandybridge_display_wm_info, latency, |
| 1988 | &sandybridge_cursor_wm_info, latency, |
| 1989 | &plane_wm, &cursor_wm)) { |
| 1990 | val = I915_READ(WM0_PIPEA_ILK); |
| 1991 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 1992 | I915_WRITE(WM0_PIPEA_ILK, val | |
| 1993 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 1994 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
| 1995 | " plane %d, " "cursor: %d\n", |
| 1996 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1997 | enabled |= 1 << PIPE_A; |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 1998 | } |
| 1999 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 2000 | if (g4x_compute_wm0(dev, PIPE_B, |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 2001 | &sandybridge_display_wm_info, latency, |
| 2002 | &sandybridge_cursor_wm_info, latency, |
| 2003 | &plane_wm, &cursor_wm)) { |
| 2004 | val = I915_READ(WM0_PIPEB_ILK); |
| 2005 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 2006 | I915_WRITE(WM0_PIPEB_ILK, val | |
| 2007 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 2008 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
| 2009 | " plane %d, cursor: %d\n", |
| 2010 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 2011 | enabled |= 1 << PIPE_B; |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 2012 | } |
| 2013 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 2014 | if (g4x_compute_wm0(dev, PIPE_C, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2015 | &sandybridge_display_wm_info, latency, |
| 2016 | &sandybridge_cursor_wm_info, latency, |
| 2017 | &plane_wm, &cursor_wm)) { |
| 2018 | val = I915_READ(WM0_PIPEC_IVB); |
| 2019 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
| 2020 | I915_WRITE(WM0_PIPEC_IVB, val | |
| 2021 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); |
| 2022 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
| 2023 | " plane %d, cursor: %d\n", |
| 2024 | plane_wm, cursor_wm); |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 2025 | enabled |= 1 << PIPE_C; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2026 | } |
| 2027 | |
| 2028 | /* |
| 2029 | * Calculate and update the self-refresh watermark only when one |
| 2030 | * display plane is used. |
| 2031 | * |
| 2032 | * SNB support 3 levels of watermark. |
| 2033 | * |
| 2034 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, |
| 2035 | * and disabled in the descending order |
| 2036 | * |
| 2037 | */ |
| 2038 | I915_WRITE(WM3_LP_ILK, 0); |
| 2039 | I915_WRITE(WM2_LP_ILK, 0); |
| 2040 | I915_WRITE(WM1_LP_ILK, 0); |
| 2041 | |
| 2042 | if (!single_plane_enabled(enabled) || |
| 2043 | dev_priv->sprite_scaling_enabled) |
| 2044 | return; |
| 2045 | enabled = ffs(enabled) - 1; |
| 2046 | |
| 2047 | /* WM1 */ |
| 2048 | if (!ironlake_compute_srwm(dev, 1, enabled, |
| 2049 | SNB_READ_WM1_LATENCY() * 500, |
| 2050 | &sandybridge_display_srwm_info, |
| 2051 | &sandybridge_cursor_srwm_info, |
| 2052 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 2053 | return; |
| 2054 | |
| 2055 | I915_WRITE(WM1_LP_ILK, |
| 2056 | WM1_LP_SR_EN | |
| 2057 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 2058 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 2059 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 2060 | cursor_wm); |
| 2061 | |
| 2062 | /* WM2 */ |
| 2063 | if (!ironlake_compute_srwm(dev, 2, enabled, |
| 2064 | SNB_READ_WM2_LATENCY() * 500, |
| 2065 | &sandybridge_display_srwm_info, |
| 2066 | &sandybridge_cursor_srwm_info, |
| 2067 | &fbc_wm, &plane_wm, &cursor_wm)) |
| 2068 | return; |
| 2069 | |
| 2070 | I915_WRITE(WM2_LP_ILK, |
| 2071 | WM2_LP_EN | |
| 2072 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 2073 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 2074 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 2075 | cursor_wm); |
| 2076 | |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 2077 | /* WM3, note we have to correct the cursor latency */ |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2078 | if (!ironlake_compute_srwm(dev, 3, enabled, |
| 2079 | SNB_READ_WM3_LATENCY() * 500, |
| 2080 | &sandybridge_display_srwm_info, |
| 2081 | &sandybridge_cursor_srwm_info, |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 2082 | &fbc_wm, &plane_wm, &ignore_cursor_wm) || |
| 2083 | !ironlake_compute_srwm(dev, 3, enabled, |
| 2084 | 2 * SNB_READ_WM3_LATENCY() * 500, |
| 2085 | &sandybridge_display_srwm_info, |
| 2086 | &sandybridge_cursor_srwm_info, |
| 2087 | &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2088 | return; |
| 2089 | |
| 2090 | I915_WRITE(WM3_LP_ILK, |
| 2091 | WM3_LP_EN | |
| 2092 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | |
| 2093 | (fbc_wm << WM1_LP_FBC_SHIFT) | |
| 2094 | (plane_wm << WM1_LP_SR_SHIFT) | |
| 2095 | cursor_wm); |
| 2096 | } |
| 2097 | |
Ville Syrjälä | 3658729 | 2013-07-05 11:57:16 +0300 | [diff] [blame^] | 2098 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
| 2099 | struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2100 | { |
| 2101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2102 | uint32_t pixel_rate, pfit_size; |
| 2103 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 2104 | pixel_rate = intel_crtc->config.adjusted_mode.clock; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2105 | |
| 2106 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
| 2107 | * adjust the pixel_rate here. */ |
| 2108 | |
| 2109 | pfit_size = intel_crtc->config.pch_pfit.size; |
| 2110 | if (pfit_size) { |
| 2111 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
| 2112 | |
| 2113 | pipe_w = intel_crtc->config.requested_mode.hdisplay; |
| 2114 | pipe_h = intel_crtc->config.requested_mode.vdisplay; |
| 2115 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
| 2116 | pfit_h = pfit_size & 0xFFFF; |
| 2117 | if (pipe_w < pfit_w) |
| 2118 | pipe_w = pfit_w; |
| 2119 | if (pipe_h < pfit_h) |
| 2120 | pipe_h = pfit_h; |
| 2121 | |
| 2122 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
| 2123 | pfit_w * pfit_h); |
| 2124 | } |
| 2125 | |
| 2126 | return pixel_rate; |
| 2127 | } |
| 2128 | |
| 2129 | static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
| 2130 | uint32_t latency) |
| 2131 | { |
| 2132 | uint64_t ret; |
| 2133 | |
| 2134 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
| 2135 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
| 2136 | |
| 2137 | return ret; |
| 2138 | } |
| 2139 | |
| 2140 | static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
| 2141 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
| 2142 | uint32_t latency) |
| 2143 | { |
| 2144 | uint32_t ret; |
| 2145 | |
| 2146 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
| 2147 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
| 2148 | ret = DIV_ROUND_UP(ret, 64) + 2; |
| 2149 | return ret; |
| 2150 | } |
| 2151 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2152 | static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
| 2153 | uint8_t bytes_per_pixel) |
| 2154 | { |
| 2155 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
| 2156 | } |
| 2157 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2158 | struct hsw_pipe_wm_parameters { |
| 2159 | bool active; |
| 2160 | bool sprite_enabled; |
| 2161 | uint8_t pri_bytes_per_pixel; |
| 2162 | uint8_t spr_bytes_per_pixel; |
| 2163 | uint8_t cur_bytes_per_pixel; |
| 2164 | uint32_t pri_horiz_pixels; |
| 2165 | uint32_t spr_horiz_pixels; |
| 2166 | uint32_t cur_horiz_pixels; |
| 2167 | uint32_t pipe_htotal; |
| 2168 | uint32_t pixel_rate; |
| 2169 | }; |
| 2170 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2171 | struct hsw_wm_maximums { |
| 2172 | uint16_t pri; |
| 2173 | uint16_t spr; |
| 2174 | uint16_t cur; |
| 2175 | uint16_t fbc; |
| 2176 | }; |
| 2177 | |
| 2178 | struct hsw_lp_wm_result { |
| 2179 | bool enable; |
| 2180 | bool fbc_enable; |
| 2181 | uint32_t pri_val; |
| 2182 | uint32_t spr_val; |
| 2183 | uint32_t cur_val; |
| 2184 | uint32_t fbc_val; |
| 2185 | }; |
| 2186 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2187 | struct hsw_wm_values { |
| 2188 | uint32_t wm_pipe[3]; |
| 2189 | uint32_t wm_lp[3]; |
| 2190 | uint32_t wm_lp_spr[3]; |
| 2191 | uint32_t wm_linetime[3]; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2192 | bool enable_fbc_wm; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2193 | }; |
| 2194 | |
| 2195 | enum hsw_data_buf_partitioning { |
| 2196 | HSW_DATA_BUF_PART_1_2, |
| 2197 | HSW_DATA_BUF_PART_5_6, |
| 2198 | }; |
| 2199 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2200 | /* For both WM_PIPE and WM_LP. */ |
| 2201 | static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params, |
| 2202 | uint32_t mem_value, |
| 2203 | bool is_lp) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2204 | { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2205 | uint32_t method1, method2; |
| 2206 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2207 | /* TODO: for now, assume the primary plane is always enabled. */ |
| 2208 | if (!params->active) |
| 2209 | return 0; |
| 2210 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2211 | method1 = hsw_wm_method1(params->pixel_rate, |
| 2212 | params->pri_bytes_per_pixel, |
| 2213 | mem_value); |
| 2214 | |
| 2215 | if (!is_lp) |
| 2216 | return method1; |
| 2217 | |
| 2218 | method2 = hsw_wm_method2(params->pixel_rate, |
| 2219 | params->pipe_htotal, |
| 2220 | params->pri_horiz_pixels, |
| 2221 | params->pri_bytes_per_pixel, |
| 2222 | mem_value); |
| 2223 | |
| 2224 | return min(method1, method2); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2225 | } |
| 2226 | |
| 2227 | /* For both WM_PIPE and WM_LP. */ |
| 2228 | static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params, |
| 2229 | uint32_t mem_value) |
| 2230 | { |
| 2231 | uint32_t method1, method2; |
| 2232 | |
| 2233 | if (!params->active || !params->sprite_enabled) |
| 2234 | return 0; |
| 2235 | |
| 2236 | method1 = hsw_wm_method1(params->pixel_rate, |
| 2237 | params->spr_bytes_per_pixel, |
| 2238 | mem_value); |
| 2239 | method2 = hsw_wm_method2(params->pixel_rate, |
| 2240 | params->pipe_htotal, |
| 2241 | params->spr_horiz_pixels, |
| 2242 | params->spr_bytes_per_pixel, |
| 2243 | mem_value); |
| 2244 | return min(method1, method2); |
| 2245 | } |
| 2246 | |
| 2247 | /* For both WM_PIPE and WM_LP. */ |
| 2248 | static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params, |
| 2249 | uint32_t mem_value) |
| 2250 | { |
| 2251 | if (!params->active) |
| 2252 | return 0; |
| 2253 | |
| 2254 | return hsw_wm_method2(params->pixel_rate, |
| 2255 | params->pipe_htotal, |
| 2256 | params->cur_horiz_pixels, |
| 2257 | params->cur_bytes_per_pixel, |
| 2258 | mem_value); |
| 2259 | } |
| 2260 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2261 | /* Only for WM_LP. */ |
| 2262 | static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params, |
| 2263 | uint32_t pri_val, |
| 2264 | uint32_t mem_value) |
| 2265 | { |
| 2266 | if (!params->active) |
| 2267 | return 0; |
| 2268 | |
| 2269 | return hsw_wm_fbc(pri_val, |
| 2270 | params->pri_horiz_pixels, |
| 2271 | params->pri_bytes_per_pixel); |
| 2272 | } |
| 2273 | |
| 2274 | static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max, |
| 2275 | struct hsw_pipe_wm_parameters *params, |
| 2276 | struct hsw_lp_wm_result *result) |
| 2277 | { |
| 2278 | enum pipe pipe; |
| 2279 | uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3]; |
| 2280 | |
| 2281 | for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) { |
| 2282 | struct hsw_pipe_wm_parameters *p = ¶ms[pipe]; |
| 2283 | |
| 2284 | pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true); |
| 2285 | spr_val[pipe] = hsw_compute_spr_wm(p, mem_value); |
| 2286 | cur_val[pipe] = hsw_compute_cur_wm(p, mem_value); |
| 2287 | fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value); |
| 2288 | } |
| 2289 | |
| 2290 | result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]); |
| 2291 | result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]); |
| 2292 | result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]); |
| 2293 | result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]); |
| 2294 | |
| 2295 | if (result->fbc_val > max->fbc) { |
| 2296 | result->fbc_enable = false; |
| 2297 | result->fbc_val = 0; |
| 2298 | } else { |
| 2299 | result->fbc_enable = true; |
| 2300 | } |
| 2301 | |
| 2302 | result->enable = result->pri_val <= max->pri && |
| 2303 | result->spr_val <= max->spr && |
| 2304 | result->cur_val <= max->cur; |
| 2305 | return result->enable; |
| 2306 | } |
| 2307 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2308 | static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv, |
| 2309 | uint32_t mem_value, enum pipe pipe, |
| 2310 | struct hsw_pipe_wm_parameters *params) |
| 2311 | { |
| 2312 | uint32_t pri_val, cur_val, spr_val; |
| 2313 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2314 | pri_val = hsw_compute_pri_wm(params, mem_value, false); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2315 | spr_val = hsw_compute_spr_wm(params, mem_value); |
| 2316 | cur_val = hsw_compute_cur_wm(params, mem_value); |
| 2317 | |
| 2318 | WARN(pri_val > 127, |
| 2319 | "Primary WM error, mode not supported for pipe %c\n", |
| 2320 | pipe_name(pipe)); |
| 2321 | WARN(spr_val > 127, |
| 2322 | "Sprite WM error, mode not supported for pipe %c\n", |
| 2323 | pipe_name(pipe)); |
| 2324 | WARN(cur_val > 63, |
| 2325 | "Cursor WM error, mode not supported for pipe %c\n", |
| 2326 | pipe_name(pipe)); |
| 2327 | |
| 2328 | return (pri_val << WM0_PIPE_PLANE_SHIFT) | |
| 2329 | (spr_val << WM0_PIPE_SPRITE_SHIFT) | |
| 2330 | cur_val; |
| 2331 | } |
| 2332 | |
| 2333 | static uint32_t |
| 2334 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2335 | { |
| 2336 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2338 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2339 | u32 linetime, ips_linetime; |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2340 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2341 | if (!intel_crtc_active(crtc)) |
| 2342 | return 0; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2343 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2344 | /* The WM are computed with base on how long it takes to fill a single |
| 2345 | * row at the given clock rate, multiplied by 8. |
| 2346 | * */ |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2347 | linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); |
| 2348 | ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, |
| 2349 | intel_ddi_get_cdclk_freq(dev_priv)); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2350 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2351 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
| 2352 | PIPE_WM_LINETIME_TIME(linetime); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2353 | } |
| 2354 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2355 | static void hsw_compute_wm_parameters(struct drm_device *dev, |
| 2356 | struct hsw_pipe_wm_parameters *params, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2357 | uint32_t *wm, |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2358 | struct hsw_wm_maximums *lp_max_1_2, |
| 2359 | struct hsw_wm_maximums *lp_max_5_6) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2360 | { |
| 2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2362 | struct drm_crtc *crtc; |
| 2363 | struct drm_plane *plane; |
| 2364 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
| 2365 | enum pipe pipe; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2366 | int pipes_active = 0, sprites_enabled = 0; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2367 | |
| 2368 | if ((sskpd >> 56) & 0xFF) |
| 2369 | wm[0] = (sskpd >> 56) & 0xFF; |
| 2370 | else |
| 2371 | wm[0] = sskpd & 0xF; |
| 2372 | wm[1] = ((sskpd >> 4) & 0xFF) * 5; |
| 2373 | wm[2] = ((sskpd >> 12) & 0xFF) * 5; |
| 2374 | wm[3] = ((sskpd >> 20) & 0x1FF) * 5; |
| 2375 | wm[4] = ((sskpd >> 32) & 0x1FF) * 5; |
| 2376 | |
| 2377 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 2378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2379 | struct hsw_pipe_wm_parameters *p; |
| 2380 | |
| 2381 | pipe = intel_crtc->pipe; |
| 2382 | p = ¶ms[pipe]; |
| 2383 | |
| 2384 | p->active = intel_crtc_active(crtc); |
| 2385 | if (!p->active) |
| 2386 | continue; |
| 2387 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2388 | pipes_active++; |
| 2389 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2390 | p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal; |
Ville Syrjälä | 3658729 | 2013-07-05 11:57:16 +0300 | [diff] [blame^] | 2391 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2392 | p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8; |
| 2393 | p->cur_bytes_per_pixel = 4; |
| 2394 | p->pri_horiz_pixels = |
| 2395 | intel_crtc->config.requested_mode.hdisplay; |
| 2396 | p->cur_horiz_pixels = 64; |
| 2397 | } |
| 2398 | |
| 2399 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
| 2400 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 2401 | struct hsw_pipe_wm_parameters *p; |
| 2402 | |
| 2403 | pipe = intel_plane->pipe; |
| 2404 | p = ¶ms[pipe]; |
| 2405 | |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2406 | p->sprite_enabled = intel_plane->wm.enabled; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2407 | p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel; |
| 2408 | p->spr_horiz_pixels = intel_plane->wm.horiz_pixels; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2409 | |
| 2410 | if (p->sprite_enabled) |
| 2411 | sprites_enabled++; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2412 | } |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2413 | |
| 2414 | if (pipes_active > 1) { |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2415 | lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256; |
| 2416 | lp_max_1_2->spr = lp_max_5_6->spr = 128; |
| 2417 | lp_max_1_2->cur = lp_max_5_6->cur = 64; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2418 | } else { |
| 2419 | lp_max_1_2->pri = sprites_enabled ? 384 : 768; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2420 | lp_max_5_6->pri = sprites_enabled ? 128 : 768; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2421 | lp_max_1_2->spr = 384; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2422 | lp_max_5_6->spr = 640; |
| 2423 | lp_max_1_2->cur = lp_max_5_6->cur = 255; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2424 | } |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2425 | lp_max_1_2->fbc = lp_max_5_6->fbc = 15; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2426 | } |
| 2427 | |
| 2428 | static void hsw_compute_wm_results(struct drm_device *dev, |
| 2429 | struct hsw_pipe_wm_parameters *params, |
| 2430 | uint32_t *wm, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2431 | struct hsw_wm_maximums *lp_maximums, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2432 | struct hsw_wm_values *results) |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2433 | { |
| 2434 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2435 | struct drm_crtc *crtc; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2436 | struct hsw_lp_wm_result lp_results[4] = {}; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2437 | enum pipe pipe; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2438 | int level, max_level, wm_lp; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2439 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2440 | for (level = 1; level <= 4; level++) |
| 2441 | if (!hsw_compute_lp_wm(wm[level], lp_maximums, params, |
| 2442 | &lp_results[level - 1])) |
| 2443 | break; |
| 2444 | max_level = level - 1; |
| 2445 | |
| 2446 | /* The spec says it is preferred to disable FBC WMs instead of disabling |
| 2447 | * a WM level. */ |
| 2448 | results->enable_fbc_wm = true; |
| 2449 | for (level = 1; level <= max_level; level++) { |
| 2450 | if (!lp_results[level - 1].fbc_enable) { |
| 2451 | results->enable_fbc_wm = false; |
| 2452 | break; |
| 2453 | } |
| 2454 | } |
| 2455 | |
| 2456 | memset(results, 0, sizeof(*results)); |
| 2457 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
| 2458 | const struct hsw_lp_wm_result *r; |
| 2459 | |
| 2460 | level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp; |
| 2461 | if (level > max_level) |
| 2462 | break; |
| 2463 | |
| 2464 | r = &lp_results[level - 1]; |
| 2465 | results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2, |
| 2466 | r->fbc_val, |
| 2467 | r->pri_val, |
| 2468 | r->cur_val); |
| 2469 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
| 2470 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2471 | |
| 2472 | for_each_pipe(pipe) |
| 2473 | results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0], |
| 2474 | pipe, |
| 2475 | ¶ms[pipe]); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2476 | |
| 2477 | for_each_pipe(pipe) { |
| 2478 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2479 | results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc); |
| 2480 | } |
| 2481 | } |
| 2482 | |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2483 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
| 2484 | * case both are at the same level. Prefer r1 in case they're the same. */ |
Damien Lespiau | f4db932 | 2013-06-24 22:59:50 +0100 | [diff] [blame] | 2485 | static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1, |
| 2486 | struct hsw_wm_values *r2) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2487 | { |
| 2488 | int i, val_r1 = 0, val_r2 = 0; |
| 2489 | |
| 2490 | for (i = 0; i < 3; i++) { |
| 2491 | if (r1->wm_lp[i] & WM3_LP_EN) |
| 2492 | val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK; |
| 2493 | if (r2->wm_lp[i] & WM3_LP_EN) |
| 2494 | val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK; |
| 2495 | } |
| 2496 | |
| 2497 | if (val_r1 == val_r2) { |
| 2498 | if (r2->enable_fbc_wm && !r1->enable_fbc_wm) |
| 2499 | return r2; |
| 2500 | else |
| 2501 | return r1; |
| 2502 | } else if (val_r1 > val_r2) { |
| 2503 | return r1; |
| 2504 | } else { |
| 2505 | return r2; |
| 2506 | } |
| 2507 | } |
| 2508 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2509 | /* |
| 2510 | * The spec says we shouldn't write when we don't need, because every write |
| 2511 | * causes WMs to be re-evaluated, expending some power. |
| 2512 | */ |
| 2513 | static void hsw_write_wm_values(struct drm_i915_private *dev_priv, |
| 2514 | struct hsw_wm_values *results, |
| 2515 | enum hsw_data_buf_partitioning partitioning) |
| 2516 | { |
| 2517 | struct hsw_wm_values previous; |
| 2518 | uint32_t val; |
| 2519 | enum hsw_data_buf_partitioning prev_partitioning; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2520 | bool prev_enable_fbc_wm; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2521 | |
| 2522 | previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK); |
| 2523 | previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK); |
| 2524 | previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB); |
| 2525 | previous.wm_lp[0] = I915_READ(WM1_LP_ILK); |
| 2526 | previous.wm_lp[1] = I915_READ(WM2_LP_ILK); |
| 2527 | previous.wm_lp[2] = I915_READ(WM3_LP_ILK); |
| 2528 | previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
| 2529 | previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
| 2530 | previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
| 2531 | previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A)); |
| 2532 | previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B)); |
| 2533 | previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C)); |
| 2534 | |
| 2535 | prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
| 2536 | HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2; |
| 2537 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2538 | prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
| 2539 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2540 | if (memcmp(results->wm_pipe, previous.wm_pipe, |
| 2541 | sizeof(results->wm_pipe)) == 0 && |
| 2542 | memcmp(results->wm_lp, previous.wm_lp, |
| 2543 | sizeof(results->wm_lp)) == 0 && |
| 2544 | memcmp(results->wm_lp_spr, previous.wm_lp_spr, |
| 2545 | sizeof(results->wm_lp_spr)) == 0 && |
| 2546 | memcmp(results->wm_linetime, previous.wm_linetime, |
| 2547 | sizeof(results->wm_linetime)) == 0 && |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2548 | partitioning == prev_partitioning && |
| 2549 | results->enable_fbc_wm == prev_enable_fbc_wm) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2550 | return; |
| 2551 | |
| 2552 | if (previous.wm_lp[2] != 0) |
| 2553 | I915_WRITE(WM3_LP_ILK, 0); |
| 2554 | if (previous.wm_lp[1] != 0) |
| 2555 | I915_WRITE(WM2_LP_ILK, 0); |
| 2556 | if (previous.wm_lp[0] != 0) |
| 2557 | I915_WRITE(WM1_LP_ILK, 0); |
| 2558 | |
| 2559 | if (previous.wm_pipe[0] != results->wm_pipe[0]) |
| 2560 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
| 2561 | if (previous.wm_pipe[1] != results->wm_pipe[1]) |
| 2562 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
| 2563 | if (previous.wm_pipe[2] != results->wm_pipe[2]) |
| 2564 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
| 2565 | |
| 2566 | if (previous.wm_linetime[0] != results->wm_linetime[0]) |
| 2567 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
| 2568 | if (previous.wm_linetime[1] != results->wm_linetime[1]) |
| 2569 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
| 2570 | if (previous.wm_linetime[2] != results->wm_linetime[2]) |
| 2571 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
| 2572 | |
| 2573 | if (prev_partitioning != partitioning) { |
| 2574 | val = I915_READ(WM_MISC); |
| 2575 | if (partitioning == HSW_DATA_BUF_PART_1_2) |
| 2576 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
| 2577 | else |
| 2578 | val |= WM_MISC_DATA_PARTITION_5_6; |
| 2579 | I915_WRITE(WM_MISC, val); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2580 | } |
| 2581 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2582 | if (prev_enable_fbc_wm != results->enable_fbc_wm) { |
| 2583 | val = I915_READ(DISP_ARB_CTL); |
| 2584 | if (results->enable_fbc_wm) |
| 2585 | val &= ~DISP_FBC_WM_DIS; |
| 2586 | else |
| 2587 | val |= DISP_FBC_WM_DIS; |
| 2588 | I915_WRITE(DISP_ARB_CTL, val); |
| 2589 | } |
| 2590 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2591 | if (previous.wm_lp_spr[0] != results->wm_lp_spr[0]) |
| 2592 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
| 2593 | if (previous.wm_lp_spr[1] != results->wm_lp_spr[1]) |
| 2594 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
| 2595 | if (previous.wm_lp_spr[2] != results->wm_lp_spr[2]) |
| 2596 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
| 2597 | |
| 2598 | if (results->wm_lp[0] != 0) |
| 2599 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
| 2600 | if (results->wm_lp[1] != 0) |
| 2601 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
| 2602 | if (results->wm_lp[2] != 0) |
| 2603 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
| 2604 | } |
| 2605 | |
| 2606 | static void haswell_update_wm(struct drm_device *dev) |
| 2607 | { |
| 2608 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2609 | struct hsw_wm_maximums lp_max_1_2, lp_max_5_6; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2610 | struct hsw_pipe_wm_parameters params[3]; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2611 | struct hsw_wm_values results_1_2, results_5_6, *best_results; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2612 | uint32_t wm[5]; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2613 | enum hsw_data_buf_partitioning partitioning; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2614 | |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2615 | hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6); |
| 2616 | |
| 2617 | hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2); |
| 2618 | if (lp_max_1_2.pri != lp_max_5_6.pri) { |
| 2619 | hsw_compute_wm_results(dev, params, wm, &lp_max_5_6, |
| 2620 | &results_5_6); |
| 2621 | best_results = hsw_find_best_result(&results_1_2, &results_5_6); |
| 2622 | } else { |
| 2623 | best_results = &results_1_2; |
| 2624 | } |
| 2625 | |
| 2626 | partitioning = (best_results == &results_1_2) ? |
| 2627 | HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6; |
| 2628 | |
| 2629 | hsw_write_wm_values(dev_priv, best_results, partitioning); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2630 | } |
| 2631 | |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2632 | static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, |
| 2633 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2634 | bool enabled, bool scaled) |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2635 | { |
| 2636 | struct drm_plane *plane; |
| 2637 | |
| 2638 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
| 2639 | struct intel_plane *intel_plane = to_intel_plane(plane); |
| 2640 | |
| 2641 | if (intel_plane->pipe == pipe) { |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2642 | intel_plane->wm.enabled = enabled; |
| 2643 | intel_plane->wm.scaled = scaled; |
Ville Syrjälä | 67ca28f | 2013-07-05 11:57:14 +0300 | [diff] [blame] | 2644 | intel_plane->wm.horiz_pixels = sprite_width; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2645 | intel_plane->wm.bytes_per_pixel = pixel_size; |
| 2646 | break; |
| 2647 | } |
| 2648 | } |
| 2649 | |
| 2650 | haswell_update_wm(dev); |
| 2651 | } |
| 2652 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2653 | static bool |
| 2654 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, |
| 2655 | uint32_t sprite_width, int pixel_size, |
| 2656 | const struct intel_watermark_params *display, |
| 2657 | int display_latency_ns, int *sprite_wm) |
| 2658 | { |
| 2659 | struct drm_crtc *crtc; |
| 2660 | int clock; |
| 2661 | int entries, tlb_miss; |
| 2662 | |
| 2663 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 2664 | if (!intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2665 | *sprite_wm = display->guard_size; |
| 2666 | return false; |
| 2667 | } |
| 2668 | |
| 2669 | clock = crtc->mode.clock; |
| 2670 | |
| 2671 | /* Use the small buffer method to calculate the sprite watermark */ |
| 2672 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 2673 | tlb_miss = display->fifo_size*display->cacheline_size - |
| 2674 | sprite_width * 8; |
| 2675 | if (tlb_miss > 0) |
| 2676 | entries += tlb_miss; |
| 2677 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 2678 | *sprite_wm = entries + display->guard_size; |
| 2679 | if (*sprite_wm > (int)display->max_wm) |
| 2680 | *sprite_wm = display->max_wm; |
| 2681 | |
| 2682 | return true; |
| 2683 | } |
| 2684 | |
| 2685 | static bool |
| 2686 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, |
| 2687 | uint32_t sprite_width, int pixel_size, |
| 2688 | const struct intel_watermark_params *display, |
| 2689 | int latency_ns, int *sprite_wm) |
| 2690 | { |
| 2691 | struct drm_crtc *crtc; |
| 2692 | unsigned long line_time_us; |
| 2693 | int clock; |
| 2694 | int line_count, line_size; |
| 2695 | int small, large; |
| 2696 | int entries; |
| 2697 | |
| 2698 | if (!latency_ns) { |
| 2699 | *sprite_wm = 0; |
| 2700 | return false; |
| 2701 | } |
| 2702 | |
| 2703 | crtc = intel_get_crtc_for_plane(dev, plane); |
| 2704 | clock = crtc->mode.clock; |
| 2705 | if (!clock) { |
| 2706 | *sprite_wm = 0; |
| 2707 | return false; |
| 2708 | } |
| 2709 | |
| 2710 | line_time_us = (sprite_width * 1000) / clock; |
| 2711 | if (!line_time_us) { |
| 2712 | *sprite_wm = 0; |
| 2713 | return false; |
| 2714 | } |
| 2715 | |
| 2716 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 2717 | line_size = sprite_width * pixel_size; |
| 2718 | |
| 2719 | /* Use the minimum of the small and large buffer method for primary */ |
| 2720 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 2721 | large = line_count * line_size; |
| 2722 | |
| 2723 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 2724 | *sprite_wm = entries + display->guard_size; |
| 2725 | |
| 2726 | return *sprite_wm > 0x3ff ? false : true; |
| 2727 | } |
| 2728 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 2729 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 2730 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2731 | bool enable, bool scaled) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2732 | { |
| 2733 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2734 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
| 2735 | u32 val; |
| 2736 | int sprite_wm, reg; |
| 2737 | int ret; |
| 2738 | |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 2739 | if (!enable) |
| 2740 | return; |
| 2741 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2742 | switch (pipe) { |
| 2743 | case 0: |
| 2744 | reg = WM0_PIPEA_ILK; |
| 2745 | break; |
| 2746 | case 1: |
| 2747 | reg = WM0_PIPEB_ILK; |
| 2748 | break; |
| 2749 | case 2: |
| 2750 | reg = WM0_PIPEC_IVB; |
| 2751 | break; |
| 2752 | default: |
| 2753 | return; /* bad pipe */ |
| 2754 | } |
| 2755 | |
| 2756 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, |
| 2757 | &sandybridge_display_wm_info, |
| 2758 | latency, &sprite_wm); |
| 2759 | if (!ret) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2760 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n", |
| 2761 | pipe_name(pipe)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2762 | return; |
| 2763 | } |
| 2764 | |
| 2765 | val = I915_READ(reg); |
| 2766 | val &= ~WM0_PIPE_SPRITE_MASK; |
| 2767 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2768 | DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2769 | |
| 2770 | |
| 2771 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 2772 | pixel_size, |
| 2773 | &sandybridge_display_srwm_info, |
| 2774 | SNB_READ_WM1_LATENCY() * 500, |
| 2775 | &sprite_wm); |
| 2776 | if (!ret) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2777 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n", |
| 2778 | pipe_name(pipe)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2779 | return; |
| 2780 | } |
| 2781 | I915_WRITE(WM1S_LP_ILK, sprite_wm); |
| 2782 | |
| 2783 | /* Only IVB has two more LP watermarks for sprite */ |
| 2784 | if (!IS_IVYBRIDGE(dev)) |
| 2785 | return; |
| 2786 | |
| 2787 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 2788 | pixel_size, |
| 2789 | &sandybridge_display_srwm_info, |
| 2790 | SNB_READ_WM2_LATENCY() * 500, |
| 2791 | &sprite_wm); |
| 2792 | if (!ret) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2793 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n", |
| 2794 | pipe_name(pipe)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2795 | return; |
| 2796 | } |
| 2797 | I915_WRITE(WM2S_LP_IVB, sprite_wm); |
| 2798 | |
| 2799 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, |
| 2800 | pixel_size, |
| 2801 | &sandybridge_display_srwm_info, |
| 2802 | SNB_READ_WM3_LATENCY() * 500, |
| 2803 | &sprite_wm); |
| 2804 | if (!ret) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2805 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n", |
| 2806 | pipe_name(pipe)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2807 | return; |
| 2808 | } |
| 2809 | I915_WRITE(WM3S_LP_IVB, sprite_wm); |
| 2810 | } |
| 2811 | |
| 2812 | /** |
| 2813 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 2814 | * |
| 2815 | * Calculate watermark values for the various WM regs based on current mode |
| 2816 | * and plane configuration. |
| 2817 | * |
| 2818 | * There are several cases to deal with here: |
| 2819 | * - normal (i.e. non-self-refresh) |
| 2820 | * - self-refresh (SR) mode |
| 2821 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 2822 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 2823 | * lines), so need to account for TLB latency |
| 2824 | * |
| 2825 | * The normal calculation is: |
| 2826 | * watermark = dotclock * bytes per pixel * latency |
| 2827 | * where latency is platform & configuration dependent (we assume pessimal |
| 2828 | * values here). |
| 2829 | * |
| 2830 | * The SR calculation is: |
| 2831 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 2832 | * bytes per pixel |
| 2833 | * where |
| 2834 | * line time = htotal / dotclock |
| 2835 | * surface width = hdisplay for normal plane and 64 for cursor |
| 2836 | * and latency is assumed to be high, as above. |
| 2837 | * |
| 2838 | * The final value programmed to the register should always be rounded up, |
| 2839 | * and include an extra 2 entries to account for clock crossings. |
| 2840 | * |
| 2841 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 2842 | * to set the non-SR watermarks to 8. |
| 2843 | */ |
| 2844 | void intel_update_watermarks(struct drm_device *dev) |
| 2845 | { |
| 2846 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2847 | |
| 2848 | if (dev_priv->display.update_wm) |
| 2849 | dev_priv->display.update_wm(dev); |
| 2850 | } |
| 2851 | |
| 2852 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 2853 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2854 | bool enable, bool scaled) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2855 | { |
| 2856 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2857 | |
| 2858 | if (dev_priv->display.update_sprite_wm) |
| 2859 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2860 | pixel_size, enable, scaled); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2861 | } |
| 2862 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2863 | static struct drm_i915_gem_object * |
| 2864 | intel_alloc_context_page(struct drm_device *dev) |
| 2865 | { |
| 2866 | struct drm_i915_gem_object *ctx; |
| 2867 | int ret; |
| 2868 | |
| 2869 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2870 | |
| 2871 | ctx = i915_gem_alloc_object(dev, 4096); |
| 2872 | if (!ctx) { |
| 2873 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 2874 | return NULL; |
| 2875 | } |
| 2876 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2877 | ret = i915_gem_object_pin(ctx, 4096, true, false); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2878 | if (ret) { |
| 2879 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 2880 | goto err_unref; |
| 2881 | } |
| 2882 | |
| 2883 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
| 2884 | if (ret) { |
| 2885 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 2886 | goto err_unpin; |
| 2887 | } |
| 2888 | |
| 2889 | return ctx; |
| 2890 | |
| 2891 | err_unpin: |
| 2892 | i915_gem_object_unpin(ctx); |
| 2893 | err_unref: |
| 2894 | drm_gem_object_unreference(&ctx->base); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2895 | return NULL; |
| 2896 | } |
| 2897 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2898 | /** |
| 2899 | * Lock protecting IPS related data structures |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2900 | */ |
| 2901 | DEFINE_SPINLOCK(mchdev_lock); |
| 2902 | |
| 2903 | /* Global for IPS driver to get at the current i915 device. Protected by |
| 2904 | * mchdev_lock. */ |
| 2905 | static struct drm_i915_private *i915_mch_dev; |
| 2906 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2907 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 2908 | { |
| 2909 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2910 | u16 rgvswctl; |
| 2911 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2912 | assert_spin_locked(&mchdev_lock); |
| 2913 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2914 | rgvswctl = I915_READ16(MEMSWCTL); |
| 2915 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 2916 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 2917 | return false; /* still busy with another command */ |
| 2918 | } |
| 2919 | |
| 2920 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 2921 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 2922 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 2923 | POSTING_READ16(MEMSWCTL); |
| 2924 | |
| 2925 | rgvswctl |= MEMCTL_CMD_STS; |
| 2926 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 2927 | |
| 2928 | return true; |
| 2929 | } |
| 2930 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2931 | static void ironlake_enable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2932 | { |
| 2933 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2934 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
| 2935 | u8 fmax, fmin, fstart, vstart; |
| 2936 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2937 | spin_lock_irq(&mchdev_lock); |
| 2938 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2939 | /* Enable temp reporting */ |
| 2940 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 2941 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 2942 | |
| 2943 | /* 100ms RC evaluation intervals */ |
| 2944 | I915_WRITE(RCUPEI, 100000); |
| 2945 | I915_WRITE(RCDNEI, 100000); |
| 2946 | |
| 2947 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 2948 | I915_WRITE(RCBMAXAVG, 90000); |
| 2949 | I915_WRITE(RCBMINAVG, 80000); |
| 2950 | |
| 2951 | I915_WRITE(MEMIHYST, 1); |
| 2952 | |
| 2953 | /* Set up min, max, and cur for interrupt handling */ |
| 2954 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 2955 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 2956 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 2957 | MEMMODE_FSTART_SHIFT; |
| 2958 | |
| 2959 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 2960 | PXVFREQ_PX_SHIFT; |
| 2961 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2962 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
| 2963 | dev_priv->ips.fstart = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2964 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2965 | dev_priv->ips.max_delay = fstart; |
| 2966 | dev_priv->ips.min_delay = fmin; |
| 2967 | dev_priv->ips.cur_delay = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2968 | |
| 2969 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 2970 | fmax, fmin, fstart); |
| 2971 | |
| 2972 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 2973 | |
| 2974 | /* |
| 2975 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 2976 | */ |
| 2977 | |
| 2978 | I915_WRITE(VIDSTART, vstart); |
| 2979 | POSTING_READ(VIDSTART); |
| 2980 | |
| 2981 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 2982 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 2983 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2984 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2985 | DRM_ERROR("stuck trying to change perf mode\n"); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2986 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2987 | |
| 2988 | ironlake_set_drps(dev, fstart); |
| 2989 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2990 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2991 | I915_READ(0x112e0); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2992 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
| 2993 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
| 2994 | getrawmonotonic(&dev_priv->ips.last_time2); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2995 | |
| 2996 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2997 | } |
| 2998 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2999 | static void ironlake_disable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3000 | { |
| 3001 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3002 | u16 rgvswctl; |
| 3003 | |
| 3004 | spin_lock_irq(&mchdev_lock); |
| 3005 | |
| 3006 | rgvswctl = I915_READ16(MEMSWCTL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3007 | |
| 3008 | /* Ack interrupts, disable EFC interrupt */ |
| 3009 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 3010 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 3011 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 3012 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 3013 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 3014 | |
| 3015 | /* Go back to the starting frequency */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3016 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3017 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3018 | rgvswctl |= MEMCTL_CMD_STS; |
| 3019 | I915_WRITE(MEMSWCTL, rgvswctl); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3020 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3021 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3022 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3023 | } |
| 3024 | |
Daniel Vetter | acbe947 | 2012-07-26 11:50:05 +0200 | [diff] [blame] | 3025 | /* There's a funny hw issue where the hw returns all 0 when reading from |
| 3026 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
| 3027 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
| 3028 | * all limits and the gpu stuck at whatever frequency it is at atm). |
| 3029 | */ |
Daniel Vetter | 65bccb5 | 2012-08-08 17:42:52 +0200 | [diff] [blame] | 3030 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3031 | { |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3032 | u32 limits; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3033 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3034 | limits = 0; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3035 | |
| 3036 | if (*val >= dev_priv->rps.max_delay) |
| 3037 | *val = dev_priv->rps.max_delay; |
| 3038 | limits |= dev_priv->rps.max_delay << 24; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3039 | |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3040 | /* Only set the down limit when we've reached the lowest level to avoid |
| 3041 | * getting more interrupts, otherwise leave this clear. This prevents a |
| 3042 | * race in the hw when coming out of rc6: There's a tiny window where |
| 3043 | * the hw runs at the minimal clock before selecting the desired |
| 3044 | * frequency, if the down threshold expires in that window we will not |
| 3045 | * receive a down interrupt. */ |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3046 | if (*val <= dev_priv->rps.min_delay) { |
| 3047 | *val = dev_priv->rps.min_delay; |
| 3048 | limits |= dev_priv->rps.min_delay << 16; |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3049 | } |
| 3050 | |
| 3051 | return limits; |
| 3052 | } |
| 3053 | |
| 3054 | void gen6_set_rps(struct drm_device *dev, u8 val) |
| 3055 | { |
| 3056 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 65bccb5 | 2012-08-08 17:42:52 +0200 | [diff] [blame] | 3057 | u32 limits = gen6_rps_limits(dev_priv, &val); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3058 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3059 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 3060 | WARN_ON(val > dev_priv->rps.max_delay); |
| 3061 | WARN_ON(val < dev_priv->rps.min_delay); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3062 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3063 | if (val == dev_priv->rps.cur_delay) |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3064 | return; |
| 3065 | |
Rodrigo Vivi | 92bd1bf | 2013-03-25 17:55:49 -0300 | [diff] [blame] | 3066 | if (IS_HASWELL(dev)) |
| 3067 | I915_WRITE(GEN6_RPNSWREQ, |
| 3068 | HSW_FREQUENCY(val)); |
| 3069 | else |
| 3070 | I915_WRITE(GEN6_RPNSWREQ, |
| 3071 | GEN6_FREQUENCY(val) | |
| 3072 | GEN6_OFFSET(0) | |
| 3073 | GEN6_AGGRESSIVE_TURBO); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3074 | |
| 3075 | /* Make sure we continue to get interrupts |
| 3076 | * until we hit the minimum or maximum frequencies. |
| 3077 | */ |
| 3078 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); |
| 3079 | |
Ben Widawsky | d5570a7 | 2012-09-07 19:43:41 -0700 | [diff] [blame] | 3080 | POSTING_READ(GEN6_RPNSWREQ); |
| 3081 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3082 | dev_priv->rps.cur_delay = val; |
Daniel Vetter | be2cde9 | 2012-08-30 13:26:48 +0200 | [diff] [blame] | 3083 | |
| 3084 | trace_intel_gpu_freq_change(val * 50); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3085 | } |
| 3086 | |
Ville Syrjälä | 80814ae | 2013-06-25 19:21:02 +0300 | [diff] [blame] | 3087 | /* |
| 3088 | * Wait until the previous freq change has completed, |
| 3089 | * or the timeout elapsed, and then update our notion |
| 3090 | * of the current GPU frequency. |
| 3091 | */ |
| 3092 | static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv) |
| 3093 | { |
Ville Syrjälä | 80814ae | 2013-06-25 19:21:02 +0300 | [diff] [blame] | 3094 | u32 pval; |
| 3095 | |
| 3096 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 3097 | |
Ville Syrjälä | e847440 | 2013-06-26 17:43:24 +0300 | [diff] [blame] | 3098 | if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10)) |
| 3099 | DRM_DEBUG_DRIVER("timed out waiting for Punit\n"); |
Ville Syrjälä | 80814ae | 2013-06-25 19:21:02 +0300 | [diff] [blame] | 3100 | |
| 3101 | pval >>= 8; |
| 3102 | |
| 3103 | if (pval != dev_priv->rps.cur_delay) |
| 3104 | DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n", |
| 3105 | vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay), |
| 3106 | dev_priv->rps.cur_delay, |
| 3107 | vlv_gpu_freq(dev_priv->mem_freq, pval), pval); |
| 3108 | |
| 3109 | dev_priv->rps.cur_delay = pval; |
| 3110 | } |
| 3111 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3112 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
| 3113 | { |
| 3114 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 7a67092 | 2013-06-25 19:21:06 +0300 | [diff] [blame] | 3115 | |
| 3116 | gen6_rps_limits(dev_priv, &val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3117 | |
| 3118 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 3119 | WARN_ON(val > dev_priv->rps.max_delay); |
| 3120 | WARN_ON(val < dev_priv->rps.min_delay); |
| 3121 | |
Ville Syrjälä | 80814ae | 2013-06-25 19:21:02 +0300 | [diff] [blame] | 3122 | vlv_update_rps_cur_delay(dev_priv); |
| 3123 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3124 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3125 | vlv_gpu_freq(dev_priv->mem_freq, |
| 3126 | dev_priv->rps.cur_delay), |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3127 | dev_priv->rps.cur_delay, |
| 3128 | vlv_gpu_freq(dev_priv->mem_freq, val), val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3129 | |
| 3130 | if (val == dev_priv->rps.cur_delay) |
| 3131 | return; |
| 3132 | |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 3133 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3134 | |
Ville Syrjälä | 80814ae | 2013-06-25 19:21:02 +0300 | [diff] [blame] | 3135 | dev_priv->rps.cur_delay = val; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3136 | |
| 3137 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 3138 | } |
| 3139 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3140 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3141 | { |
| 3142 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3143 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3144 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 3145 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3146 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 3147 | * item again unmasking PM interrupts because that is using a different |
| 3148 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
| 3149 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
| 3150 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 3151 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3152 | dev_priv->rps.pm_iir = 0; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 3153 | spin_unlock_irq(&dev_priv->irq_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3154 | |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 3155 | I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3156 | } |
| 3157 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3158 | static void gen6_disable_rps(struct drm_device *dev) |
| 3159 | { |
| 3160 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3161 | |
| 3162 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3163 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
| 3164 | |
| 3165 | gen6_disable_rps_interrupts(dev); |
| 3166 | } |
| 3167 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3168 | static void valleyview_disable_rps(struct drm_device *dev) |
| 3169 | { |
| 3170 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3171 | |
| 3172 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3173 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3174 | gen6_disable_rps_interrupts(dev); |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3175 | |
| 3176 | if (dev_priv->vlv_pctx) { |
| 3177 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
| 3178 | dev_priv->vlv_pctx = NULL; |
| 3179 | } |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3180 | } |
| 3181 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3182 | int intel_enable_rc6(const struct drm_device *dev) |
| 3183 | { |
Damien Lespiau | eb4926e | 2013-06-07 17:41:14 +0100 | [diff] [blame] | 3184 | /* No RC6 before Ironlake */ |
| 3185 | if (INTEL_INFO(dev)->gen < 5) |
| 3186 | return 0; |
| 3187 | |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 3188 | /* Respect the kernel parameter if it is set */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3189 | if (i915_enable_rc6 >= 0) |
| 3190 | return i915_enable_rc6; |
| 3191 | |
Chris Wilson | 6567d74 | 2012-11-10 10:00:06 +0000 | [diff] [blame] | 3192 | /* Disable RC6 on Ironlake */ |
| 3193 | if (INTEL_INFO(dev)->gen == 5) |
| 3194 | return 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3195 | |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 3196 | if (IS_HASWELL(dev)) { |
| 3197 | DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); |
| 3198 | return INTEL_RC6_ENABLE; |
| 3199 | } |
| 3200 | |
| 3201 | /* snb/ivb have more than one rc6 state. */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3202 | if (INTEL_INFO(dev)->gen == 6) { |
| 3203 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
| 3204 | return INTEL_RC6_ENABLE; |
| 3205 | } |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 3206 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3207 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
| 3208 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
| 3209 | } |
| 3210 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3211 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
| 3212 | { |
| 3213 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3214 | |
| 3215 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | a0b3335 | 2013-07-04 23:35:34 +0200 | [diff] [blame] | 3216 | WARN_ON(dev_priv->rps.pm_iir); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3217 | I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); |
| 3218 | I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); |
| 3219 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3220 | /* unmask all PM interrupts */ |
| 3221 | I915_WRITE(GEN6_PMINTRMSK, 0); |
| 3222 | } |
| 3223 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3224 | static void gen6_enable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3225 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3226 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3227 | struct intel_ring_buffer *ring; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3228 | u32 rp_state_cap; |
| 3229 | u32 gt_perf_status; |
Ben Widawsky | 31643d5 | 2012-09-26 10:34:01 -0700 | [diff] [blame] | 3230 | u32 rc6vids, pcu_mbox, rc6_mask = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3231 | u32 gtfifodbg; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3232 | int rc6_mode; |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3233 | int i, ret; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3234 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3235 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3236 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3237 | /* Here begins a magic sequence of register writes to enable |
| 3238 | * auto-downclocking. |
| 3239 | * |
| 3240 | * Perhaps there might be some value in exposing these to |
| 3241 | * userspace... |
| 3242 | */ |
| 3243 | I915_WRITE(GEN6_RC_STATE, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3244 | |
| 3245 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 3246 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 3247 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 3248 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 3249 | } |
| 3250 | |
| 3251 | gen6_gt_force_wake_get(dev_priv); |
| 3252 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3253 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 3254 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 3255 | |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 3256 | /* In units of 50MHz */ |
| 3257 | dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3258 | dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; |
| 3259 | dev_priv->rps.cur_delay = 0; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3260 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3261 | /* disable the counters and set deterministic thresholds */ |
| 3262 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3263 | |
| 3264 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 3265 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 3266 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 3267 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 3268 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 3269 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3270 | for_each_ring(ring, dev_priv, i) |
| 3271 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3272 | |
| 3273 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 3274 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
| 3275 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
Stéphane Marchesin | 0920a48 | 2013-01-29 19:41:59 -0800 | [diff] [blame] | 3276 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3277 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 3278 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3279 | /* Check if we are enabling RC6 */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3280 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 3281 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 3282 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 3283 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3284 | /* We don't use those on Haswell */ |
| 3285 | if (!IS_HASWELL(dev)) { |
| 3286 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 3287 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3288 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3289 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 3290 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 3291 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3292 | |
| 3293 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3294 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
| 3295 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
| 3296 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3297 | |
| 3298 | I915_WRITE(GEN6_RC_CONTROL, |
| 3299 | rc6_mask | |
| 3300 | GEN6_RC_CTL_EI_MODE(1) | |
| 3301 | GEN6_RC_CTL_HW_ENABLE); |
| 3302 | |
Rodrigo Vivi | 92bd1bf | 2013-03-25 17:55:49 -0300 | [diff] [blame] | 3303 | if (IS_HASWELL(dev)) { |
| 3304 | I915_WRITE(GEN6_RPNSWREQ, |
| 3305 | HSW_FREQUENCY(10)); |
| 3306 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 3307 | HSW_FREQUENCY(12)); |
| 3308 | } else { |
| 3309 | I915_WRITE(GEN6_RPNSWREQ, |
| 3310 | GEN6_FREQUENCY(10) | |
| 3311 | GEN6_OFFSET(0) | |
| 3312 | GEN6_AGGRESSIVE_TURBO); |
| 3313 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 3314 | GEN6_FREQUENCY(12)); |
| 3315 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3316 | |
| 3317 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
| 3318 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3319 | dev_priv->rps.max_delay << 24 | |
| 3320 | dev_priv->rps.min_delay << 16); |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3321 | |
Daniel Vetter | 1ee9ae3 | 2012-08-15 10:41:45 +0200 | [diff] [blame] | 3322 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 3323 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 3324 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 3325 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3326 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3327 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 3328 | I915_WRITE(GEN6_RP_CONTROL, |
| 3329 | GEN6_RP_MEDIA_TURBO | |
Jesse Barnes | 89ba829 | 2012-05-22 09:30:33 -0700 | [diff] [blame] | 3330 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3331 | GEN6_RP_MEDIA_IS_GFX | |
| 3332 | GEN6_RP_ENABLE | |
| 3333 | GEN6_RP_UP_BUSY_AVG | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3334 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3335 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3336 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
Ben Widawsky | 988b36e | 2013-04-23 17:33:02 -0700 | [diff] [blame] | 3337 | if (!ret) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3338 | pcu_mbox = 0; |
| 3339 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
Ben Widawsky | a2b3fc0 | 2013-03-19 20:19:56 -0700 | [diff] [blame] | 3340 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
Ben Widawsky | 10e0849 | 2013-04-05 14:29:23 -0700 | [diff] [blame] | 3341 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
Ben Widawsky | a2b3fc0 | 2013-03-19 20:19:56 -0700 | [diff] [blame] | 3342 | (dev_priv->rps.max_delay & 0xff) * 50, |
| 3343 | (pcu_mbox & 0xff) * 50); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 3344 | dev_priv->rps.hw_max = pcu_mbox & 0xff; |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3345 | } |
| 3346 | } else { |
| 3347 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3348 | } |
| 3349 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3350 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3351 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3352 | gen6_enable_rps_interrupts(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3353 | |
Ben Widawsky | 31643d5 | 2012-09-26 10:34:01 -0700 | [diff] [blame] | 3354 | rc6vids = 0; |
| 3355 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 3356 | if (IS_GEN6(dev) && ret) { |
| 3357 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
| 3358 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
| 3359 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
| 3360 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
| 3361 | rc6vids &= 0xffff00; |
| 3362 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
| 3363 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
| 3364 | if (ret) |
| 3365 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
| 3366 | } |
| 3367 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3368 | gen6_gt_force_wake_put(dev_priv); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3369 | } |
| 3370 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3371 | static void gen6_update_ring_freq(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3372 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3373 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3374 | int min_freq = 15; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3375 | unsigned int gpu_freq; |
| 3376 | unsigned int max_ia_freq, min_ring_freq; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3377 | int scaling_factor = 180; |
| 3378 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3379 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3380 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3381 | max_ia_freq = cpufreq_quick_get_max(0); |
| 3382 | /* |
| 3383 | * Default to measured freq if none found, PCU will ensure we don't go |
| 3384 | * over |
| 3385 | */ |
| 3386 | if (!max_ia_freq) |
| 3387 | max_ia_freq = tsc_khz; |
| 3388 | |
| 3389 | /* Convert from kHz to MHz */ |
| 3390 | max_ia_freq /= 1000; |
| 3391 | |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3392 | min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK); |
| 3393 | /* convert DDR frequency from units of 133.3MHz to bandwidth */ |
| 3394 | min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3; |
| 3395 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3396 | /* |
| 3397 | * For each potential GPU frequency, load a ring frequency we'd like |
| 3398 | * to use for memory access. We do this by specifying the IA frequency |
| 3399 | * the PCU should use as a reference to determine the ring frequency. |
| 3400 | */ |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3401 | for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3402 | gpu_freq--) { |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3403 | int diff = dev_priv->rps.max_delay - gpu_freq; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3404 | unsigned int ia_freq = 0, ring_freq = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3405 | |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3406 | if (IS_HASWELL(dev)) { |
| 3407 | ring_freq = (gpu_freq * 5 + 3) / 4; |
| 3408 | ring_freq = max(min_ring_freq, ring_freq); |
| 3409 | /* leave ia_freq as the default, chosen by cpufreq */ |
| 3410 | } else { |
| 3411 | /* On older processors, there is no separate ring |
| 3412 | * clock domain, so in order to boost the bandwidth |
| 3413 | * of the ring, we need to upclock the CPU (ia_freq). |
| 3414 | * |
| 3415 | * For GPU frequencies less than 750MHz, |
| 3416 | * just use the lowest ring freq. |
| 3417 | */ |
| 3418 | if (gpu_freq < min_freq) |
| 3419 | ia_freq = 800; |
| 3420 | else |
| 3421 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 3422 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 3423 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3424 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3425 | sandybridge_pcode_write(dev_priv, |
| 3426 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3427 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
| 3428 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
| 3429 | gpu_freq); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3430 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3431 | } |
| 3432 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3433 | int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
| 3434 | { |
| 3435 | u32 val, rp0; |
| 3436 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3437 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3438 | |
| 3439 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
| 3440 | /* Clamp to max */ |
| 3441 | rp0 = min_t(u32, rp0, 0xea); |
| 3442 | |
| 3443 | return rp0; |
| 3444 | } |
| 3445 | |
| 3446 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 3447 | { |
| 3448 | u32 val, rpe; |
| 3449 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3450 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3451 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3452 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3453 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
| 3454 | |
| 3455 | return rpe; |
| 3456 | } |
| 3457 | |
| 3458 | int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
| 3459 | { |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3460 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3461 | } |
| 3462 | |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 3463 | static void vlv_rps_timer_work(struct work_struct *work) |
| 3464 | { |
| 3465 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 3466 | rps.vlv_work.work); |
| 3467 | |
| 3468 | /* |
| 3469 | * Timer fired, we must be idle. Drop to min voltage state. |
| 3470 | * Note: we use RPe here since it should match the |
| 3471 | * Vmin we were shooting for. That should give us better |
| 3472 | * perf when we come back out of RC6 than if we used the |
| 3473 | * min freq available. |
| 3474 | */ |
| 3475 | mutex_lock(&dev_priv->rps.hw_lock); |
Ville Syrjälä | 6dc5848 | 2013-06-25 21:38:10 +0300 | [diff] [blame] | 3476 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) |
| 3477 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 3478 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3479 | } |
| 3480 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3481 | static void valleyview_setup_pctx(struct drm_device *dev) |
| 3482 | { |
| 3483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3484 | struct drm_i915_gem_object *pctx; |
| 3485 | unsigned long pctx_paddr; |
| 3486 | u32 pcbr; |
| 3487 | int pctx_size = 24*1024; |
| 3488 | |
| 3489 | pcbr = I915_READ(VLV_PCBR); |
| 3490 | if (pcbr) { |
| 3491 | /* BIOS set it up already, grab the pre-alloc'd space */ |
| 3492 | int pcbr_offset; |
| 3493 | |
| 3494 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
| 3495 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
| 3496 | pcbr_offset, |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 3497 | I915_GTT_OFFSET_NONE, |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3498 | pctx_size); |
| 3499 | goto out; |
| 3500 | } |
| 3501 | |
| 3502 | /* |
| 3503 | * From the Gunit register HAS: |
| 3504 | * The Gfx driver is expected to program this register and ensure |
| 3505 | * proper allocation within Gfx stolen memory. For example, this |
| 3506 | * register should be programmed such than the PCBR range does not |
| 3507 | * overlap with other ranges, such as the frame buffer, protected |
| 3508 | * memory, or any other relevant ranges. |
| 3509 | */ |
| 3510 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
| 3511 | if (!pctx) { |
| 3512 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
| 3513 | return; |
| 3514 | } |
| 3515 | |
| 3516 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
| 3517 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 3518 | |
| 3519 | out: |
| 3520 | dev_priv->vlv_pctx = pctx; |
| 3521 | } |
| 3522 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3523 | static void valleyview_enable_rps(struct drm_device *dev) |
| 3524 | { |
| 3525 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3526 | struct intel_ring_buffer *ring; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3527 | u32 gtfifodbg, val; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3528 | int i; |
| 3529 | |
| 3530 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 3531 | |
| 3532 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 3533 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 3534 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 3535 | } |
| 3536 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3537 | valleyview_setup_pctx(dev); |
| 3538 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3539 | gen6_gt_force_wake_get(dev_priv); |
| 3540 | |
| 3541 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 3542 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 3543 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 3544 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 3545 | |
| 3546 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 3547 | |
| 3548 | I915_WRITE(GEN6_RP_CONTROL, |
| 3549 | GEN6_RP_MEDIA_TURBO | |
| 3550 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3551 | GEN6_RP_MEDIA_IS_GFX | |
| 3552 | GEN6_RP_ENABLE | |
| 3553 | GEN6_RP_UP_BUSY_AVG | |
| 3554 | GEN6_RP_DOWN_IDLE_CONT); |
| 3555 | |
| 3556 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
| 3557 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 3558 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 3559 | |
| 3560 | for_each_ring(ring, dev_priv, i) |
| 3561 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 3562 | |
| 3563 | I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350); |
| 3564 | |
| 3565 | /* allows RC6 residency counter to work */ |
| 3566 | I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3)); |
| 3567 | I915_WRITE(GEN6_RC_CONTROL, |
| 3568 | GEN7_RC_CTL_TO_MODE); |
| 3569 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3570 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 2445966 | 2013-05-02 10:48:08 -0700 | [diff] [blame] | 3571 | switch ((val >> 6) & 3) { |
| 3572 | case 0: |
| 3573 | case 1: |
| 3574 | dev_priv->mem_freq = 800; |
| 3575 | break; |
| 3576 | case 2: |
| 3577 | dev_priv->mem_freq = 1066; |
| 3578 | break; |
| 3579 | case 3: |
| 3580 | dev_priv->mem_freq = 1333; |
| 3581 | break; |
| 3582 | } |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3583 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); |
| 3584 | |
| 3585 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); |
| 3586 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 3587 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3588 | dev_priv->rps.cur_delay = (val >> 8) & 0xff; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3589 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
| 3590 | vlv_gpu_freq(dev_priv->mem_freq, |
| 3591 | dev_priv->rps.cur_delay), |
| 3592 | dev_priv->rps.cur_delay); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3593 | |
| 3594 | dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); |
| 3595 | dev_priv->rps.hw_max = dev_priv->rps.max_delay; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3596 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
| 3597 | vlv_gpu_freq(dev_priv->mem_freq, |
| 3598 | dev_priv->rps.max_delay), |
| 3599 | dev_priv->rps.max_delay); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3600 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3601 | dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); |
| 3602 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
| 3603 | vlv_gpu_freq(dev_priv->mem_freq, |
| 3604 | dev_priv->rps.rpe_delay), |
| 3605 | dev_priv->rps.rpe_delay); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3606 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3607 | dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); |
| 3608 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
| 3609 | vlv_gpu_freq(dev_priv->mem_freq, |
| 3610 | dev_priv->rps.min_delay), |
| 3611 | dev_priv->rps.min_delay); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3612 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3613 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
| 3614 | vlv_gpu_freq(dev_priv->mem_freq, |
| 3615 | dev_priv->rps.rpe_delay), |
| 3616 | dev_priv->rps.rpe_delay); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3617 | |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 3618 | INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); |
| 3619 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3620 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3621 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3622 | gen6_enable_rps_interrupts(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3623 | |
| 3624 | gen6_gt_force_wake_put(dev_priv); |
| 3625 | } |
| 3626 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3627 | void ironlake_teardown_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3628 | { |
| 3629 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3630 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3631 | if (dev_priv->ips.renderctx) { |
| 3632 | i915_gem_object_unpin(dev_priv->ips.renderctx); |
| 3633 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
| 3634 | dev_priv->ips.renderctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3635 | } |
| 3636 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3637 | if (dev_priv->ips.pwrctx) { |
| 3638 | i915_gem_object_unpin(dev_priv->ips.pwrctx); |
| 3639 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
| 3640 | dev_priv->ips.pwrctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3641 | } |
| 3642 | } |
| 3643 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3644 | static void ironlake_disable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3645 | { |
| 3646 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3647 | |
| 3648 | if (I915_READ(PWRCTXA)) { |
| 3649 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
| 3650 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
| 3651 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
| 3652 | 50); |
| 3653 | |
| 3654 | I915_WRITE(PWRCTXA, 0); |
| 3655 | POSTING_READ(PWRCTXA); |
| 3656 | |
| 3657 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
| 3658 | POSTING_READ(RSTDBYCTL); |
| 3659 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3660 | } |
| 3661 | |
| 3662 | static int ironlake_setup_rc6(struct drm_device *dev) |
| 3663 | { |
| 3664 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3665 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3666 | if (dev_priv->ips.renderctx == NULL) |
| 3667 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
| 3668 | if (!dev_priv->ips.renderctx) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3669 | return -ENOMEM; |
| 3670 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3671 | if (dev_priv->ips.pwrctx == NULL) |
| 3672 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
| 3673 | if (!dev_priv->ips.pwrctx) { |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3674 | ironlake_teardown_rc6(dev); |
| 3675 | return -ENOMEM; |
| 3676 | } |
| 3677 | |
| 3678 | return 0; |
| 3679 | } |
| 3680 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3681 | static void ironlake_enable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3682 | { |
| 3683 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3684 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3685 | bool was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3686 | int ret; |
| 3687 | |
| 3688 | /* rc6 disabled by default due to repeated reports of hanging during |
| 3689 | * boot and resume. |
| 3690 | */ |
| 3691 | if (!intel_enable_rc6(dev)) |
| 3692 | return; |
| 3693 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3694 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 3695 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3696 | ret = ironlake_setup_rc6(dev); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3697 | if (ret) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3698 | return; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3699 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3700 | was_interruptible = dev_priv->mm.interruptible; |
| 3701 | dev_priv->mm.interruptible = false; |
| 3702 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3703 | /* |
| 3704 | * GPU can automatically power down the render unit if given a page |
| 3705 | * to save state. |
| 3706 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3707 | ret = intel_ring_begin(ring, 6); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3708 | if (ret) { |
| 3709 | ironlake_teardown_rc6(dev); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3710 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3711 | return; |
| 3712 | } |
| 3713 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3714 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
| 3715 | intel_ring_emit(ring, MI_SET_CONTEXT); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3716 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3717 | MI_MM_SPACE_GTT | |
| 3718 | MI_SAVE_EXT_STATE_EN | |
| 3719 | MI_RESTORE_EXT_STATE_EN | |
| 3720 | MI_RESTORE_INHIBIT); |
| 3721 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
| 3722 | intel_ring_emit(ring, MI_NOOP); |
| 3723 | intel_ring_emit(ring, MI_FLUSH); |
| 3724 | intel_ring_advance(ring); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3725 | |
| 3726 | /* |
| 3727 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
| 3728 | * does an implicit flush, combined with MI_FLUSH above, it should be |
| 3729 | * safe to assume that renderctx is valid |
| 3730 | */ |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3731 | ret = intel_ring_idle(ring); |
| 3732 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3733 | if (ret) { |
Jani Nikula | def27a5 | 2013-03-12 10:49:19 +0200 | [diff] [blame] | 3734 | DRM_ERROR("failed to enable ironlake power savings\n"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3735 | ironlake_teardown_rc6(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3736 | return; |
| 3737 | } |
| 3738 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3739 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3740 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3741 | } |
| 3742 | |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 3743 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 3744 | { |
| 3745 | unsigned long freq; |
| 3746 | int div = (vidfreq & 0x3f0000) >> 16; |
| 3747 | int post = (vidfreq & 0x3000) >> 12; |
| 3748 | int pre = (vidfreq & 0x7); |
| 3749 | |
| 3750 | if (!pre) |
| 3751 | return 0; |
| 3752 | |
| 3753 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 3754 | |
| 3755 | return freq; |
| 3756 | } |
| 3757 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3758 | static const struct cparams { |
| 3759 | u16 i; |
| 3760 | u16 t; |
| 3761 | u16 m; |
| 3762 | u16 c; |
| 3763 | } cparams[] = { |
| 3764 | { 1, 1333, 301, 28664 }, |
| 3765 | { 1, 1066, 294, 24460 }, |
| 3766 | { 1, 800, 294, 25192 }, |
| 3767 | { 0, 1333, 276, 27605 }, |
| 3768 | { 0, 1066, 276, 27605 }, |
| 3769 | { 0, 800, 231, 23784 }, |
| 3770 | }; |
| 3771 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 3772 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3773 | { |
| 3774 | u64 total_count, diff, ret; |
| 3775 | u32 count1, count2, count3, m = 0, c = 0; |
| 3776 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 3777 | int i; |
| 3778 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 3779 | assert_spin_locked(&mchdev_lock); |
| 3780 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3781 | diff1 = now - dev_priv->ips.last_time1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3782 | |
| 3783 | /* Prevent division-by-zero if we are asking too fast. |
| 3784 | * Also, we don't get interesting results if we are polling |
| 3785 | * faster than once in 10ms, so just return the saved value |
| 3786 | * in such cases. |
| 3787 | */ |
| 3788 | if (diff1 <= 10) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3789 | return dev_priv->ips.chipset_power; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3790 | |
| 3791 | count1 = I915_READ(DMIEC); |
| 3792 | count2 = I915_READ(DDREC); |
| 3793 | count3 = I915_READ(CSIEC); |
| 3794 | |
| 3795 | total_count = count1 + count2 + count3; |
| 3796 | |
| 3797 | /* FIXME: handle per-counter overflow */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3798 | if (total_count < dev_priv->ips.last_count1) { |
| 3799 | diff = ~0UL - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3800 | diff += total_count; |
| 3801 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3802 | diff = total_count - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3803 | } |
| 3804 | |
| 3805 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3806 | if (cparams[i].i == dev_priv->ips.c_m && |
| 3807 | cparams[i].t == dev_priv->ips.r_t) { |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3808 | m = cparams[i].m; |
| 3809 | c = cparams[i].c; |
| 3810 | break; |
| 3811 | } |
| 3812 | } |
| 3813 | |
| 3814 | diff = div_u64(diff, diff1); |
| 3815 | ret = ((m * diff) + c); |
| 3816 | ret = div_u64(ret, 10); |
| 3817 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3818 | dev_priv->ips.last_count1 = total_count; |
| 3819 | dev_priv->ips.last_time1 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3820 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3821 | dev_priv->ips.chipset_power = ret; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3822 | |
| 3823 | return ret; |
| 3824 | } |
| 3825 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 3826 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 3827 | { |
| 3828 | unsigned long val; |
| 3829 | |
| 3830 | if (dev_priv->info->gen != 5) |
| 3831 | return 0; |
| 3832 | |
| 3833 | spin_lock_irq(&mchdev_lock); |
| 3834 | |
| 3835 | val = __i915_chipset_val(dev_priv); |
| 3836 | |
| 3837 | spin_unlock_irq(&mchdev_lock); |
| 3838 | |
| 3839 | return val; |
| 3840 | } |
| 3841 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3842 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 3843 | { |
| 3844 | unsigned long m, x, b; |
| 3845 | u32 tsfs; |
| 3846 | |
| 3847 | tsfs = I915_READ(TSFS); |
| 3848 | |
| 3849 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 3850 | x = I915_READ8(TR1); |
| 3851 | |
| 3852 | b = tsfs & TSFS_INTR_MASK; |
| 3853 | |
| 3854 | return ((m * x) / 127) - b; |
| 3855 | } |
| 3856 | |
| 3857 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
| 3858 | { |
| 3859 | static const struct v_table { |
| 3860 | u16 vd; /* in .1 mil */ |
| 3861 | u16 vm; /* in .1 mil */ |
| 3862 | } v_table[] = { |
| 3863 | { 0, 0, }, |
| 3864 | { 375, 0, }, |
| 3865 | { 500, 0, }, |
| 3866 | { 625, 0, }, |
| 3867 | { 750, 0, }, |
| 3868 | { 875, 0, }, |
| 3869 | { 1000, 0, }, |
| 3870 | { 1125, 0, }, |
| 3871 | { 4125, 3000, }, |
| 3872 | { 4125, 3000, }, |
| 3873 | { 4125, 3000, }, |
| 3874 | { 4125, 3000, }, |
| 3875 | { 4125, 3000, }, |
| 3876 | { 4125, 3000, }, |
| 3877 | { 4125, 3000, }, |
| 3878 | { 4125, 3000, }, |
| 3879 | { 4125, 3000, }, |
| 3880 | { 4125, 3000, }, |
| 3881 | { 4125, 3000, }, |
| 3882 | { 4125, 3000, }, |
| 3883 | { 4125, 3000, }, |
| 3884 | { 4125, 3000, }, |
| 3885 | { 4125, 3000, }, |
| 3886 | { 4125, 3000, }, |
| 3887 | { 4125, 3000, }, |
| 3888 | { 4125, 3000, }, |
| 3889 | { 4125, 3000, }, |
| 3890 | { 4125, 3000, }, |
| 3891 | { 4125, 3000, }, |
| 3892 | { 4125, 3000, }, |
| 3893 | { 4125, 3000, }, |
| 3894 | { 4125, 3000, }, |
| 3895 | { 4250, 3125, }, |
| 3896 | { 4375, 3250, }, |
| 3897 | { 4500, 3375, }, |
| 3898 | { 4625, 3500, }, |
| 3899 | { 4750, 3625, }, |
| 3900 | { 4875, 3750, }, |
| 3901 | { 5000, 3875, }, |
| 3902 | { 5125, 4000, }, |
| 3903 | { 5250, 4125, }, |
| 3904 | { 5375, 4250, }, |
| 3905 | { 5500, 4375, }, |
| 3906 | { 5625, 4500, }, |
| 3907 | { 5750, 4625, }, |
| 3908 | { 5875, 4750, }, |
| 3909 | { 6000, 4875, }, |
| 3910 | { 6125, 5000, }, |
| 3911 | { 6250, 5125, }, |
| 3912 | { 6375, 5250, }, |
| 3913 | { 6500, 5375, }, |
| 3914 | { 6625, 5500, }, |
| 3915 | { 6750, 5625, }, |
| 3916 | { 6875, 5750, }, |
| 3917 | { 7000, 5875, }, |
| 3918 | { 7125, 6000, }, |
| 3919 | { 7250, 6125, }, |
| 3920 | { 7375, 6250, }, |
| 3921 | { 7500, 6375, }, |
| 3922 | { 7625, 6500, }, |
| 3923 | { 7750, 6625, }, |
| 3924 | { 7875, 6750, }, |
| 3925 | { 8000, 6875, }, |
| 3926 | { 8125, 7000, }, |
| 3927 | { 8250, 7125, }, |
| 3928 | { 8375, 7250, }, |
| 3929 | { 8500, 7375, }, |
| 3930 | { 8625, 7500, }, |
| 3931 | { 8750, 7625, }, |
| 3932 | { 8875, 7750, }, |
| 3933 | { 9000, 7875, }, |
| 3934 | { 9125, 8000, }, |
| 3935 | { 9250, 8125, }, |
| 3936 | { 9375, 8250, }, |
| 3937 | { 9500, 8375, }, |
| 3938 | { 9625, 8500, }, |
| 3939 | { 9750, 8625, }, |
| 3940 | { 9875, 8750, }, |
| 3941 | { 10000, 8875, }, |
| 3942 | { 10125, 9000, }, |
| 3943 | { 10250, 9125, }, |
| 3944 | { 10375, 9250, }, |
| 3945 | { 10500, 9375, }, |
| 3946 | { 10625, 9500, }, |
| 3947 | { 10750, 9625, }, |
| 3948 | { 10875, 9750, }, |
| 3949 | { 11000, 9875, }, |
| 3950 | { 11125, 10000, }, |
| 3951 | { 11250, 10125, }, |
| 3952 | { 11375, 10250, }, |
| 3953 | { 11500, 10375, }, |
| 3954 | { 11625, 10500, }, |
| 3955 | { 11750, 10625, }, |
| 3956 | { 11875, 10750, }, |
| 3957 | { 12000, 10875, }, |
| 3958 | { 12125, 11000, }, |
| 3959 | { 12250, 11125, }, |
| 3960 | { 12375, 11250, }, |
| 3961 | { 12500, 11375, }, |
| 3962 | { 12625, 11500, }, |
| 3963 | { 12750, 11625, }, |
| 3964 | { 12875, 11750, }, |
| 3965 | { 13000, 11875, }, |
| 3966 | { 13125, 12000, }, |
| 3967 | { 13250, 12125, }, |
| 3968 | { 13375, 12250, }, |
| 3969 | { 13500, 12375, }, |
| 3970 | { 13625, 12500, }, |
| 3971 | { 13750, 12625, }, |
| 3972 | { 13875, 12750, }, |
| 3973 | { 14000, 12875, }, |
| 3974 | { 14125, 13000, }, |
| 3975 | { 14250, 13125, }, |
| 3976 | { 14375, 13250, }, |
| 3977 | { 14500, 13375, }, |
| 3978 | { 14625, 13500, }, |
| 3979 | { 14750, 13625, }, |
| 3980 | { 14875, 13750, }, |
| 3981 | { 15000, 13875, }, |
| 3982 | { 15125, 14000, }, |
| 3983 | { 15250, 14125, }, |
| 3984 | { 15375, 14250, }, |
| 3985 | { 15500, 14375, }, |
| 3986 | { 15625, 14500, }, |
| 3987 | { 15750, 14625, }, |
| 3988 | { 15875, 14750, }, |
| 3989 | { 16000, 14875, }, |
| 3990 | { 16125, 15000, }, |
| 3991 | }; |
| 3992 | if (dev_priv->info->is_mobile) |
| 3993 | return v_table[pxvid].vm; |
| 3994 | else |
| 3995 | return v_table[pxvid].vd; |
| 3996 | } |
| 3997 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 3998 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3999 | { |
| 4000 | struct timespec now, diff1; |
| 4001 | u64 diff; |
| 4002 | unsigned long diffms; |
| 4003 | u32 count; |
| 4004 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4005 | assert_spin_locked(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4006 | |
| 4007 | getrawmonotonic(&now); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4008 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4009 | |
| 4010 | /* Don't divide by 0 */ |
| 4011 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
| 4012 | if (!diffms) |
| 4013 | return; |
| 4014 | |
| 4015 | count = I915_READ(GFXEC); |
| 4016 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4017 | if (count < dev_priv->ips.last_count2) { |
| 4018 | diff = ~0UL - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4019 | diff += count; |
| 4020 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4021 | diff = count - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4022 | } |
| 4023 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4024 | dev_priv->ips.last_count2 = count; |
| 4025 | dev_priv->ips.last_time2 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4026 | |
| 4027 | /* More magic constants... */ |
| 4028 | diff = diff * 1181; |
| 4029 | diff = div_u64(diff, diffms * 10); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4030 | dev_priv->ips.gfx_power = diff; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4031 | } |
| 4032 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4033 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 4034 | { |
| 4035 | if (dev_priv->info->gen != 5) |
| 4036 | return; |
| 4037 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4038 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4039 | |
| 4040 | __i915_update_gfx_val(dev_priv); |
| 4041 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4042 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4043 | } |
| 4044 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4045 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4046 | { |
| 4047 | unsigned long t, corr, state1, corr2, state2; |
| 4048 | u32 pxvid, ext_v; |
| 4049 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4050 | assert_spin_locked(&mchdev_lock); |
| 4051 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 4052 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4053 | pxvid = (pxvid >> 24) & 0x7f; |
| 4054 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 4055 | |
| 4056 | state1 = ext_v; |
| 4057 | |
| 4058 | t = i915_mch_val(dev_priv); |
| 4059 | |
| 4060 | /* Revel in the empirically derived constants */ |
| 4061 | |
| 4062 | /* Correction factor in 1/100000 units */ |
| 4063 | if (t > 80) |
| 4064 | corr = ((t * 2349) + 135940); |
| 4065 | else if (t >= 50) |
| 4066 | corr = ((t * 964) + 29317); |
| 4067 | else /* < 50 */ |
| 4068 | corr = ((t * 301) + 1004); |
| 4069 | |
| 4070 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 4071 | corr /= 100000; |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4072 | corr2 = (corr * dev_priv->ips.corr); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4073 | |
| 4074 | state2 = (corr2 * state1) / 10000; |
| 4075 | state2 /= 100; /* convert to mW */ |
| 4076 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4077 | __i915_update_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4078 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4079 | return dev_priv->ips.gfx_power + state2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4080 | } |
| 4081 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4082 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 4083 | { |
| 4084 | unsigned long val; |
| 4085 | |
| 4086 | if (dev_priv->info->gen != 5) |
| 4087 | return 0; |
| 4088 | |
| 4089 | spin_lock_irq(&mchdev_lock); |
| 4090 | |
| 4091 | val = __i915_gfx_val(dev_priv); |
| 4092 | |
| 4093 | spin_unlock_irq(&mchdev_lock); |
| 4094 | |
| 4095 | return val; |
| 4096 | } |
| 4097 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4098 | /** |
| 4099 | * i915_read_mch_val - return value for IPS use |
| 4100 | * |
| 4101 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 4102 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 4103 | */ |
| 4104 | unsigned long i915_read_mch_val(void) |
| 4105 | { |
| 4106 | struct drm_i915_private *dev_priv; |
| 4107 | unsigned long chipset_val, graphics_val, ret = 0; |
| 4108 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4109 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4110 | if (!i915_mch_dev) |
| 4111 | goto out_unlock; |
| 4112 | dev_priv = i915_mch_dev; |
| 4113 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4114 | chipset_val = __i915_chipset_val(dev_priv); |
| 4115 | graphics_val = __i915_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4116 | |
| 4117 | ret = chipset_val + graphics_val; |
| 4118 | |
| 4119 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4120 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4121 | |
| 4122 | return ret; |
| 4123 | } |
| 4124 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 4125 | |
| 4126 | /** |
| 4127 | * i915_gpu_raise - raise GPU frequency limit |
| 4128 | * |
| 4129 | * Raise the limit; IPS indicates we have thermal headroom. |
| 4130 | */ |
| 4131 | bool i915_gpu_raise(void) |
| 4132 | { |
| 4133 | struct drm_i915_private *dev_priv; |
| 4134 | bool ret = true; |
| 4135 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4136 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4137 | if (!i915_mch_dev) { |
| 4138 | ret = false; |
| 4139 | goto out_unlock; |
| 4140 | } |
| 4141 | dev_priv = i915_mch_dev; |
| 4142 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4143 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
| 4144 | dev_priv->ips.max_delay--; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4145 | |
| 4146 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4147 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4148 | |
| 4149 | return ret; |
| 4150 | } |
| 4151 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 4152 | |
| 4153 | /** |
| 4154 | * i915_gpu_lower - lower GPU frequency limit |
| 4155 | * |
| 4156 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 4157 | * frequency maximum. |
| 4158 | */ |
| 4159 | bool i915_gpu_lower(void) |
| 4160 | { |
| 4161 | struct drm_i915_private *dev_priv; |
| 4162 | bool ret = true; |
| 4163 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4164 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4165 | if (!i915_mch_dev) { |
| 4166 | ret = false; |
| 4167 | goto out_unlock; |
| 4168 | } |
| 4169 | dev_priv = i915_mch_dev; |
| 4170 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4171 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
| 4172 | dev_priv->ips.max_delay++; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4173 | |
| 4174 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4175 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4176 | |
| 4177 | return ret; |
| 4178 | } |
| 4179 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 4180 | |
| 4181 | /** |
| 4182 | * i915_gpu_busy - indicate GPU business to IPS |
| 4183 | * |
| 4184 | * Tell the IPS driver whether or not the GPU is busy. |
| 4185 | */ |
| 4186 | bool i915_gpu_busy(void) |
| 4187 | { |
| 4188 | struct drm_i915_private *dev_priv; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4189 | struct intel_ring_buffer *ring; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4190 | bool ret = false; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4191 | int i; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4192 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4193 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4194 | if (!i915_mch_dev) |
| 4195 | goto out_unlock; |
| 4196 | dev_priv = i915_mch_dev; |
| 4197 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4198 | for_each_ring(ring, dev_priv, i) |
| 4199 | ret |= !list_empty(&ring->request_list); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4200 | |
| 4201 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4202 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4203 | |
| 4204 | return ret; |
| 4205 | } |
| 4206 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 4207 | |
| 4208 | /** |
| 4209 | * i915_gpu_turbo_disable - disable graphics turbo |
| 4210 | * |
| 4211 | * Disable graphics turbo by resetting the max frequency and setting the |
| 4212 | * current frequency to the default. |
| 4213 | */ |
| 4214 | bool i915_gpu_turbo_disable(void) |
| 4215 | { |
| 4216 | struct drm_i915_private *dev_priv; |
| 4217 | bool ret = true; |
| 4218 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4219 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4220 | if (!i915_mch_dev) { |
| 4221 | ret = false; |
| 4222 | goto out_unlock; |
| 4223 | } |
| 4224 | dev_priv = i915_mch_dev; |
| 4225 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4226 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4227 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4228 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4229 | ret = false; |
| 4230 | |
| 4231 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4232 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4233 | |
| 4234 | return ret; |
| 4235 | } |
| 4236 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 4237 | |
| 4238 | /** |
| 4239 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 4240 | * IPS got loaded first. |
| 4241 | * |
| 4242 | * This awkward dance is so that neither module has to depend on the |
| 4243 | * other in order for IPS to do the appropriate communication of |
| 4244 | * GPU turbo limits to i915. |
| 4245 | */ |
| 4246 | static void |
| 4247 | ips_ping_for_i915_load(void) |
| 4248 | { |
| 4249 | void (*link)(void); |
| 4250 | |
| 4251 | link = symbol_get(ips_link_to_i915_driver); |
| 4252 | if (link) { |
| 4253 | link(); |
| 4254 | symbol_put(ips_link_to_i915_driver); |
| 4255 | } |
| 4256 | } |
| 4257 | |
| 4258 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
| 4259 | { |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4260 | /* We only register the i915 ips part with intel-ips once everything is |
| 4261 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4262 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4263 | i915_mch_dev = dev_priv; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4264 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4265 | |
| 4266 | ips_ping_for_i915_load(); |
| 4267 | } |
| 4268 | |
| 4269 | void intel_gpu_ips_teardown(void) |
| 4270 | { |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4271 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4272 | i915_mch_dev = NULL; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4273 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4274 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4275 | static void intel_init_emon(struct drm_device *dev) |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 4276 | { |
| 4277 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4278 | u32 lcfuse; |
| 4279 | u8 pxw[16]; |
| 4280 | int i; |
| 4281 | |
| 4282 | /* Disable to program */ |
| 4283 | I915_WRITE(ECR, 0); |
| 4284 | POSTING_READ(ECR); |
| 4285 | |
| 4286 | /* Program energy weights for various events */ |
| 4287 | I915_WRITE(SDEW, 0x15040d00); |
| 4288 | I915_WRITE(CSIEW0, 0x007f0000); |
| 4289 | I915_WRITE(CSIEW1, 0x1e220004); |
| 4290 | I915_WRITE(CSIEW2, 0x04000004); |
| 4291 | |
| 4292 | for (i = 0; i < 5; i++) |
| 4293 | I915_WRITE(PEW + (i * 4), 0); |
| 4294 | for (i = 0; i < 3; i++) |
| 4295 | I915_WRITE(DEW + (i * 4), 0); |
| 4296 | |
| 4297 | /* Program P-state weights to account for frequency power adjustment */ |
| 4298 | for (i = 0; i < 16; i++) { |
| 4299 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 4300 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 4301 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 4302 | PXVFREQ_PX_SHIFT; |
| 4303 | unsigned long val; |
| 4304 | |
| 4305 | val = vid * vid; |
| 4306 | val *= (freq / 1000); |
| 4307 | val *= 255; |
| 4308 | val /= (127*127*900); |
| 4309 | if (val > 0xff) |
| 4310 | DRM_ERROR("bad pxval: %ld\n", val); |
| 4311 | pxw[i] = val; |
| 4312 | } |
| 4313 | /* Render standby states get 0 weight */ |
| 4314 | pxw[14] = 0; |
| 4315 | pxw[15] = 0; |
| 4316 | |
| 4317 | for (i = 0; i < 4; i++) { |
| 4318 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 4319 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 4320 | I915_WRITE(PXW + (i * 4), val); |
| 4321 | } |
| 4322 | |
| 4323 | /* Adjust magic regs to magic values (more experimental results) */ |
| 4324 | I915_WRITE(OGW0, 0); |
| 4325 | I915_WRITE(OGW1, 0); |
| 4326 | I915_WRITE(EG0, 0x00007f00); |
| 4327 | I915_WRITE(EG1, 0x0000000e); |
| 4328 | I915_WRITE(EG2, 0x000e0000); |
| 4329 | I915_WRITE(EG3, 0x68000300); |
| 4330 | I915_WRITE(EG4, 0x42000000); |
| 4331 | I915_WRITE(EG5, 0x00140031); |
| 4332 | I915_WRITE(EG6, 0); |
| 4333 | I915_WRITE(EG7, 0); |
| 4334 | |
| 4335 | for (i = 0; i < 8; i++) |
| 4336 | I915_WRITE(PXWL + (i * 4), 0); |
| 4337 | |
| 4338 | /* Enable PMON + select events */ |
| 4339 | I915_WRITE(ECR, 0x80000019); |
| 4340 | |
| 4341 | lcfuse = I915_READ(LCFUSE02); |
| 4342 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4343 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 4344 | } |
| 4345 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4346 | void intel_disable_gt_powersave(struct drm_device *dev) |
| 4347 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4348 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4349 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 4350 | /* Interrupts should be disabled already to avoid re-arming. */ |
| 4351 | WARN_ON(dev->irq_enabled); |
| 4352 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4353 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4354 | ironlake_disable_drps(dev); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4355 | ironlake_disable_rc6(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4356 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4357 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
Jesse Barnes | 250848c | 2013-04-23 10:09:27 -0700 | [diff] [blame] | 4358 | cancel_work_sync(&dev_priv->rps.work); |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 4359 | if (IS_VALLEYVIEW(dev)) |
| 4360 | cancel_delayed_work_sync(&dev_priv->rps.vlv_work); |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4361 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 4362 | if (IS_VALLEYVIEW(dev)) |
| 4363 | valleyview_disable_rps(dev); |
| 4364 | else |
| 4365 | gen6_disable_rps(dev); |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4366 | mutex_unlock(&dev_priv->rps.hw_lock); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4367 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4368 | } |
| 4369 | |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4370 | static void intel_gen6_powersave_work(struct work_struct *work) |
| 4371 | { |
| 4372 | struct drm_i915_private *dev_priv = |
| 4373 | container_of(work, struct drm_i915_private, |
| 4374 | rps.delayed_resume_work.work); |
| 4375 | struct drm_device *dev = dev_priv->dev; |
| 4376 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4377 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4378 | |
| 4379 | if (IS_VALLEYVIEW(dev)) { |
| 4380 | valleyview_enable_rps(dev); |
| 4381 | } else { |
| 4382 | gen6_enable_rps(dev); |
| 4383 | gen6_update_ring_freq(dev); |
| 4384 | } |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4385 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4386 | } |
| 4387 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4388 | void intel_enable_gt_powersave(struct drm_device *dev) |
| 4389 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4390 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4391 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4392 | if (IS_IRONLAKE_M(dev)) { |
| 4393 | ironlake_enable_drps(dev); |
| 4394 | ironlake_enable_rc6(dev); |
| 4395 | intel_init_emon(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4396 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4397 | /* |
| 4398 | * PCU communication is slow and this doesn't need to be |
| 4399 | * done at any specific time, so do this out of our fast path |
| 4400 | * to make resume and init faster. |
| 4401 | */ |
| 4402 | schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
| 4403 | round_jiffies_up_relative(HZ)); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4404 | } |
| 4405 | } |
| 4406 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4407 | static void ibx_init_clock_gating(struct drm_device *dev) |
| 4408 | { |
| 4409 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4410 | |
| 4411 | /* |
| 4412 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 4413 | * gating for the panel power sequencer or it will fail to |
| 4414 | * start up when no ports are active. |
| 4415 | */ |
| 4416 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 4417 | } |
| 4418 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4419 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
| 4420 | { |
| 4421 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4422 | int pipe; |
| 4423 | |
| 4424 | for_each_pipe(pipe) { |
| 4425 | I915_WRITE(DSPCNTR(pipe), |
| 4426 | I915_READ(DSPCNTR(pipe)) | |
| 4427 | DISPPLANE_TRICKLE_FEED_DISABLE); |
| 4428 | intel_flush_display_plane(dev_priv, pipe); |
| 4429 | } |
| 4430 | } |
| 4431 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4432 | static void ironlake_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4433 | { |
| 4434 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4435 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4436 | |
Damien Lespiau | f1e8fa5 | 2013-06-07 17:41:09 +0100 | [diff] [blame] | 4437 | /* |
| 4438 | * Required for FBC |
| 4439 | * WaFbcDisableDpfcClockGating:ilk |
| 4440 | */ |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 4441 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 4442 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
| 4443 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4444 | |
| 4445 | I915_WRITE(PCH_3DCGDIS0, |
| 4446 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 4447 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 4448 | I915_WRITE(PCH_3DCGDIS1, |
| 4449 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 4450 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4451 | /* |
| 4452 | * According to the spec the following bits should be set in |
| 4453 | * order to enable memory self-refresh |
| 4454 | * The bit 22/21 of 0x42004 |
| 4455 | * The bit 5 of 0x42020 |
| 4456 | * The bit 15 of 0x45000 |
| 4457 | */ |
| 4458 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4459 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4460 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 4461 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4462 | I915_WRITE(DISP_ARB_CTL, |
| 4463 | (I915_READ(DISP_ARB_CTL) | |
| 4464 | DISP_FBC_WM_DIS)); |
| 4465 | I915_WRITE(WM3_LP_ILK, 0); |
| 4466 | I915_WRITE(WM2_LP_ILK, 0); |
| 4467 | I915_WRITE(WM1_LP_ILK, 0); |
| 4468 | |
| 4469 | /* |
| 4470 | * Based on the document from hardware guys the following bits |
| 4471 | * should be set unconditionally in order to enable FBC. |
| 4472 | * The bit 22 of 0x42000 |
| 4473 | * The bit 22 of 0x42004 |
| 4474 | * The bit 7,8,9 of 0x42020. |
| 4475 | */ |
| 4476 | if (IS_IRONLAKE_M(dev)) { |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 4477 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4478 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 4479 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 4480 | ILK_FBCQ_DIS); |
| 4481 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4482 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4483 | ILK_DPARB_GATE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4484 | } |
| 4485 | |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 4486 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
| 4487 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4488 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4489 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4490 | ILK_ELPIN_409_SELECT); |
| 4491 | I915_WRITE(_3D_CHICKEN2, |
| 4492 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 4493 | _3D_CHICKEN2_WM_READ_PIPELINED); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 4494 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4495 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 4496 | I915_WRITE(CACHE_MODE_0, |
| 4497 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4498 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4499 | g4x_disable_trickle_feed(dev); |
Ville Syrjälä | bdad2b2 | 2013-06-07 10:47:03 +0300 | [diff] [blame] | 4500 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4501 | ibx_init_clock_gating(dev); |
| 4502 | } |
| 4503 | |
| 4504 | static void cpt_init_clock_gating(struct drm_device *dev) |
| 4505 | { |
| 4506 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4507 | int pipe; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4508 | uint32_t val; |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4509 | |
| 4510 | /* |
| 4511 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 4512 | * gating for the panel power sequencer or it will fail to |
| 4513 | * start up when no ports are active. |
| 4514 | */ |
| 4515 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 4516 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 4517 | DPLS_EDP_PPS_FIX_DIS); |
Takashi Iwai | 335c07b | 2012-12-11 11:46:29 +0100 | [diff] [blame] | 4518 | /* The below fixes the weird display corruption, a few pixels shifted |
| 4519 | * downward, on (only) LVDS of some HP laptops with IVY. |
| 4520 | */ |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4521 | for_each_pipe(pipe) { |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 4522 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
| 4523 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 4524 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 4525 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4526 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 4527 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
| 4528 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
| 4529 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4530 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
| 4531 | } |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4532 | /* WADP0ClockGatingDisable */ |
| 4533 | for_each_pipe(pipe) { |
| 4534 | I915_WRITE(TRANS_CHICKEN1(pipe), |
| 4535 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
| 4536 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4537 | } |
| 4538 | |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 4539 | static void gen6_check_mch_setup(struct drm_device *dev) |
| 4540 | { |
| 4541 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4542 | uint32_t tmp; |
| 4543 | |
| 4544 | tmp = I915_READ(MCH_SSKPD); |
| 4545 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { |
| 4546 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); |
| 4547 | DRM_INFO("This can cause pipe underruns and display issues.\n"); |
| 4548 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); |
| 4549 | } |
| 4550 | } |
| 4551 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4552 | static void gen6_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4553 | { |
| 4554 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4555 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4556 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4557 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4558 | |
| 4559 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4560 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4561 | ILK_ELPIN_409_SELECT); |
| 4562 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4563 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
Daniel Vetter | 4283908 | 2012-12-14 23:38:28 +0100 | [diff] [blame] | 4564 | I915_WRITE(_3D_CHICKEN, |
| 4565 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
| 4566 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4567 | /* WaSetupGtModeTdRowDispatch:snb */ |
Daniel Vetter | 6547fbd | 2012-12-14 23:38:29 +0100 | [diff] [blame] | 4568 | if (IS_SNB_GT1(dev)) |
| 4569 | I915_WRITE(GEN6_GT_MODE, |
| 4570 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); |
| 4571 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4572 | I915_WRITE(WM3_LP_ILK, 0); |
| 4573 | I915_WRITE(WM2_LP_ILK, 0); |
| 4574 | I915_WRITE(WM1_LP_ILK, 0); |
| 4575 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4576 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4577 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4578 | |
| 4579 | I915_WRITE(GEN6_UCGCTL1, |
| 4580 | I915_READ(GEN6_UCGCTL1) | |
| 4581 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
| 4582 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
| 4583 | |
| 4584 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 4585 | * gating disable must be set. Failure to set it results in |
| 4586 | * flickering pixels due to Z write ordering failures after |
| 4587 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 4588 | * Sanctuary and Tropics, and apparently anything else with |
| 4589 | * alpha test or pixel discard. |
| 4590 | * |
| 4591 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 4592 | * but we didn't debug actual testcases to find it out. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4593 | * |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4594 | * Also apply WaDisableVDSUnitClockGating:snb and |
| 4595 | * WaDisableRCPBUnitClockGating:snb. |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4596 | */ |
| 4597 | I915_WRITE(GEN6_UCGCTL2, |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4598 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4599 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 4600 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 4601 | |
| 4602 | /* Bspec says we need to always set all mask bits. */ |
Kenneth Graunke | 26b6e44 | 2012-10-07 08:51:07 -0700 | [diff] [blame] | 4603 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
| 4604 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4605 | |
| 4606 | /* |
| 4607 | * According to the spec the following bits should be |
| 4608 | * set in order to enable memory self-refresh and fbc: |
| 4609 | * The bit21 and bit22 of 0x42000 |
| 4610 | * The bit21 and bit22 of 0x42004 |
| 4611 | * The bit5 and bit7 of 0x42020 |
| 4612 | * The bit14 of 0x70180 |
| 4613 | * The bit14 of 0x71180 |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 4614 | * |
| 4615 | * WaFbcAsynchFlipDisableFbcQueue:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4616 | */ |
| 4617 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 4618 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 4619 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 4620 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4621 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4622 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4623 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 4624 | I915_READ(ILK_DSPCLK_GATE_D) | |
| 4625 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
| 4626 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4627 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4628 | /* WaMbcDriverBootEnable:snb */ |
Jesse Barnes | b4ae3f2 | 2012-06-14 11:04:48 -0700 | [diff] [blame] | 4629 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 4630 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 4631 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4632 | g4x_disable_trickle_feed(dev); |
Ben Widawsky | f8f2ac9 | 2012-10-03 19:34:24 -0700 | [diff] [blame] | 4633 | |
| 4634 | /* The default value should be 0x200 according to docs, but the two |
| 4635 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ |
| 4636 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); |
| 4637 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4638 | |
| 4639 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 4640 | |
| 4641 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4642 | } |
| 4643 | |
| 4644 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
| 4645 | { |
| 4646 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
| 4647 | |
| 4648 | reg &= ~GEN7_FF_SCHED_MASK; |
| 4649 | reg |= GEN7_FF_TS_SCHED_HW; |
| 4650 | reg |= GEN7_FF_VS_SCHED_HW; |
| 4651 | reg |= GEN7_FF_DS_SCHED_HW; |
| 4652 | |
Ben Widawsky | 41c0b3a | 2013-01-26 11:52:00 -0800 | [diff] [blame] | 4653 | if (IS_HASWELL(dev_priv->dev)) |
| 4654 | reg &= ~GEN7_FF_VS_REF_CNT_FFME; |
| 4655 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4656 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
| 4657 | } |
| 4658 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 4659 | static void lpt_init_clock_gating(struct drm_device *dev) |
| 4660 | { |
| 4661 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4662 | |
| 4663 | /* |
| 4664 | * TODO: this bit should only be enabled when really needed, then |
| 4665 | * disabled when not needed anymore in order to save power. |
| 4666 | */ |
| 4667 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
| 4668 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
| 4669 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
| 4670 | PCH_LP_PARTITION_LEVEL_DISABLE); |
Paulo Zanoni | 0a790cd | 2013-04-17 18:15:49 -0300 | [diff] [blame] | 4671 | |
| 4672 | /* WADPOClockGatingDisable:hsw */ |
| 4673 | I915_WRITE(_TRANSA_CHICKEN1, |
| 4674 | I915_READ(_TRANSA_CHICKEN1) | |
| 4675 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 4676 | } |
| 4677 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 4678 | static void lpt_suspend_hw(struct drm_device *dev) |
| 4679 | { |
| 4680 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4681 | |
| 4682 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 4683 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 4684 | |
| 4685 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 4686 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 4687 | } |
| 4688 | } |
| 4689 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4690 | static void haswell_init_clock_gating(struct drm_device *dev) |
| 4691 | { |
| 4692 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4693 | |
| 4694 | I915_WRITE(WM3_LP_ILK, 0); |
| 4695 | I915_WRITE(WM2_LP_ILK, 0); |
| 4696 | I915_WRITE(WM1_LP_ILK, 0); |
| 4697 | |
| 4698 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4699 | * This implements the WaDisableRCZUnitClockGating:hsw workaround. |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4700 | */ |
| 4701 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
| 4702 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4703 | /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4704 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 4705 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 4706 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4707 | /* WaApplyL3ControlAndL3ChickenMode:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4708 | I915_WRITE(GEN7_L3CNTLREG1, |
| 4709 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 4710 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
| 4711 | GEN7_WA_L3_CHICKEN_MODE); |
| 4712 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4713 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4714 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 4715 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 4716 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 4717 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4718 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4719 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4720 | /* WaVSRefCountFullforceMissDisable:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4721 | gen7_setup_fixed_func_scheduler(dev_priv); |
| 4722 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4723 | /* WaDisable4x2SubspanOptimization:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4724 | I915_WRITE(CACHE_MODE_1, |
| 4725 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 4726 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4727 | /* WaMbcDriverBootEnable:hsw */ |
Paulo Zanoni | b3bf076 | 2012-11-20 13:27:44 -0200 | [diff] [blame] | 4728 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 4729 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 4730 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4731 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
Ben Widawsky | e3dff58 | 2013-03-20 14:49:14 -0700 | [diff] [blame] | 4732 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
| 4733 | |
Paulo Zanoni | 90a8864 | 2013-05-03 17:23:45 -0300 | [diff] [blame] | 4734 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
| 4735 | I915_WRITE(CHICKEN_PAR1_1, |
| 4736 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 4737 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 4738 | lpt_init_clock_gating(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 4739 | } |
| 4740 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4741 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4742 | { |
| 4743 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 4744 | uint32_t snpcr; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4745 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4746 | I915_WRITE(WM3_LP_ILK, 0); |
| 4747 | I915_WRITE(WM2_LP_ILK, 0); |
| 4748 | I915_WRITE(WM1_LP_ILK, 0); |
| 4749 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4750 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4751 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4752 | /* WaDisableEarlyCull:ivb */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 4753 | I915_WRITE(_3D_CHICKEN3, |
| 4754 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 4755 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4756 | /* WaDisableBackToBackFlipFix:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4757 | I915_WRITE(IVB_CHICKEN3, |
| 4758 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 4759 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 4760 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4761 | /* WaDisablePSDDualDispatchEnable:ivb */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 4762 | if (IS_IVB_GT1(dev)) |
| 4763 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 4764 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
| 4765 | else |
| 4766 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, |
| 4767 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
| 4768 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4769 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4770 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 4771 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 4772 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4773 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4774 | I915_WRITE(GEN7_L3CNTLREG1, |
| 4775 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 4776 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 4777 | GEN7_WA_L3_CHICKEN_MODE); |
| 4778 | if (IS_IVB_GT1(dev)) |
| 4779 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 4780 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 4781 | else |
| 4782 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
| 4783 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 4784 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4785 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4786 | /* WaForceL3Serialization:ivb */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 4787 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 4788 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 4789 | |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4790 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 4791 | * gating disable must be set. Failure to set it results in |
| 4792 | * flickering pixels due to Z write ordering failures after |
| 4793 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 4794 | * Sanctuary and Tropics, and apparently anything else with |
| 4795 | * alpha test or pixel discard. |
| 4796 | * |
| 4797 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 4798 | * but we didn't debug actual testcases to find it out. |
| 4799 | * |
| 4800 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4801 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4802 | */ |
| 4803 | I915_WRITE(GEN6_UCGCTL2, |
| 4804 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
| 4805 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 4806 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4807 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4808 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 4809 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 4810 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 4811 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4812 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4813 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4814 | /* WaMbcDriverBootEnable:ivb */ |
Jesse Barnes | b4ae3f2 | 2012-06-14 11:04:48 -0700 | [diff] [blame] | 4815 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 4816 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 4817 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4818 | /* WaVSRefCountFullforceMissDisable:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4819 | gen7_setup_fixed_func_scheduler(dev_priv); |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 4820 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4821 | /* WaDisable4x2SubspanOptimization:ivb */ |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 4822 | I915_WRITE(CACHE_MODE_1, |
| 4823 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 4824 | |
| 4825 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 4826 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 4827 | snpcr |= GEN6_MBC_SNPCR_MED; |
| 4828 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4829 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 4830 | if (!HAS_PCH_NOP(dev)) |
| 4831 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 4832 | |
| 4833 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4834 | } |
| 4835 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4836 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4837 | { |
| 4838 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4839 | |
Ville Syrjälä | d7fe0cc | 2013-05-21 18:01:50 +0300 | [diff] [blame] | 4840 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4841 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4842 | /* WaDisableEarlyCull:vlv */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 4843 | I915_WRITE(_3D_CHICKEN3, |
| 4844 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 4845 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4846 | /* WaDisableBackToBackFlipFix:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4847 | I915_WRITE(IVB_CHICKEN3, |
| 4848 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 4849 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 4850 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4851 | /* WaDisablePSDDualDispatchEnable:vlv */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 4852 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
Jesse Barnes | d3bc030 | 2013-03-08 10:45:51 -0800 | [diff] [blame] | 4853 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
| 4854 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 4855 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4856 | /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4857 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 4858 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 4859 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4860 | /* WaApplyL3ControlAndL3ChickenMode:vlv */ |
Jesse Barnes | d0cf5ea | 2012-10-25 12:15:41 -0700 | [diff] [blame] | 4861 | I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4862 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
| 4863 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4864 | /* WaForceL3Serialization:vlv */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 4865 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 4866 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 4867 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4868 | /* WaDisableDopClockGating:vlv */ |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 4869 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 4870 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 4871 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4872 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4873 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 4874 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 4875 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 4876 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4877 | /* WaMbcDriverBootEnable:vlv */ |
Jesse Barnes | b4ae3f2 | 2012-06-14 11:04:48 -0700 | [diff] [blame] | 4878 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
| 4879 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
| 4880 | |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4881 | |
| 4882 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 4883 | * gating disable must be set. Failure to set it results in |
| 4884 | * flickering pixels due to Z write ordering failures after |
| 4885 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 4886 | * Sanctuary and Tropics, and apparently anything else with |
| 4887 | * alpha test or pixel discard. |
| 4888 | * |
| 4889 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 4890 | * but we didn't debug actual testcases to find it out. |
| 4891 | * |
| 4892 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4893 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4894 | * |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4895 | * Also apply WaDisableVDSUnitClockGating:vlv and |
| 4896 | * WaDisableRCPBUnitClockGating:vlv. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4897 | */ |
| 4898 | I915_WRITE(GEN6_UCGCTL2, |
| 4899 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
Jesse Barnes | 6edaa7f | 2012-06-14 11:04:49 -0700 | [diff] [blame] | 4900 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4901 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
| 4902 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 4903 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 4904 | |
Jesse Barnes | e3f33d4 | 2012-06-14 11:04:50 -0700 | [diff] [blame] | 4905 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
| 4906 | |
Ville Syrjälä | e0d8d59 | 2013-06-12 22:11:18 +0300 | [diff] [blame] | 4907 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4908 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4909 | I915_WRITE(CACHE_MODE_1, |
| 4910 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Jesse Barnes | 7983117 | 2012-06-20 10:53:12 -0700 | [diff] [blame] | 4911 | |
| 4912 | /* |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4913 | * WaDisableVLVClockGating_VBIIssue:vlv |
Jesse Barnes | 2d80957 | 2012-10-25 12:15:44 -0700 | [diff] [blame] | 4914 | * Disable clock gating on th GCFG unit to prevent a delay |
| 4915 | * in the reporting of vblank events. |
| 4916 | */ |
Jesse Barnes | 4e8c84a | 2013-03-08 10:45:54 -0800 | [diff] [blame] | 4917 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff); |
| 4918 | |
| 4919 | /* Conservative clock gating settings for now */ |
| 4920 | I915_WRITE(0x9400, 0xffffffff); |
| 4921 | I915_WRITE(0x9404, 0xffffffff); |
| 4922 | I915_WRITE(0x9408, 0xffffffff); |
| 4923 | I915_WRITE(0x940c, 0xffffffff); |
| 4924 | I915_WRITE(0x9410, 0xffffffff); |
| 4925 | I915_WRITE(0x9414, 0xffffffff); |
| 4926 | I915_WRITE(0x9418, 0xffffffff); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4927 | } |
| 4928 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4929 | static void g4x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4930 | { |
| 4931 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4932 | uint32_t dspclk_gate; |
| 4933 | |
| 4934 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 4935 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 4936 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 4937 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 4938 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 4939 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 4940 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 4941 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 4942 | if (IS_GM45(dev)) |
| 4943 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 4944 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 4945 | |
| 4946 | /* WaDisableRenderCachePipelinedFlush */ |
| 4947 | I915_WRITE(CACHE_MODE_0, |
| 4948 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 4949 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4950 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4951 | } |
| 4952 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4953 | static void crestline_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4954 | { |
| 4955 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4956 | |
| 4957 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 4958 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 4959 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 4960 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 4961 | I915_WRITE16(DEUC, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 4962 | I915_WRITE(MI_ARB_STATE, |
| 4963 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4964 | } |
| 4965 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4966 | static void broadwater_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4967 | { |
| 4968 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4969 | |
| 4970 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 4971 | I965_RCC_CLOCK_GATE_DISABLE | |
| 4972 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 4973 | I965_ISC_CLOCK_GATE_DISABLE | |
| 4974 | I965_FBC_CLOCK_GATE_DISABLE); |
| 4975 | I915_WRITE(RENCLK_GATE_D2, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 4976 | I915_WRITE(MI_ARB_STATE, |
| 4977 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4978 | } |
| 4979 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4980 | static void gen3_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4981 | { |
| 4982 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4983 | u32 dstate = I915_READ(D_STATE); |
| 4984 | |
| 4985 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 4986 | DSTATE_DOT_CLOCK_GATING; |
| 4987 | I915_WRITE(D_STATE, dstate); |
Chris Wilson | 13a86b8 | 2012-04-24 14:51:43 +0100 | [diff] [blame] | 4988 | |
| 4989 | if (IS_PINEVIEW(dev)) |
| 4990 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
Daniel Vetter | 974a3b0 | 2012-09-09 11:54:16 +0200 | [diff] [blame] | 4991 | |
| 4992 | /* IIR "flip pending" means done if this bit is set */ |
| 4993 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4994 | } |
| 4995 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4996 | static void i85x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4997 | { |
| 4998 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4999 | |
| 5000 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 5001 | } |
| 5002 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5003 | static void i830_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5004 | { |
| 5005 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5006 | |
| 5007 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 5008 | } |
| 5009 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5010 | void intel_init_clock_gating(struct drm_device *dev) |
| 5011 | { |
| 5012 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5013 | |
| 5014 | dev_priv->display.init_clock_gating(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5015 | } |
| 5016 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 5017 | void intel_suspend_hw(struct drm_device *dev) |
| 5018 | { |
| 5019 | if (HAS_PCH_LPT(dev)) |
| 5020 | lpt_suspend_hw(dev); |
| 5021 | } |
| 5022 | |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5023 | /** |
| 5024 | * We should only use the power well if we explicitly asked the hardware to |
| 5025 | * enable it, so check if it's enabled and also check if we've requested it to |
| 5026 | * be enabled. |
| 5027 | */ |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 5028 | bool intel_display_power_enabled(struct drm_device *dev, |
| 5029 | enum intel_display_power_domain domain) |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5030 | { |
| 5031 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5032 | |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 5033 | if (!HAS_POWER_WELL(dev)) |
| 5034 | return true; |
| 5035 | |
| 5036 | switch (domain) { |
| 5037 | case POWER_DOMAIN_PIPE_A: |
| 5038 | case POWER_DOMAIN_TRANSCODER_EDP: |
| 5039 | return true; |
| 5040 | case POWER_DOMAIN_PIPE_B: |
| 5041 | case POWER_DOMAIN_PIPE_C: |
| 5042 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: |
| 5043 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: |
| 5044 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: |
| 5045 | case POWER_DOMAIN_TRANSCODER_A: |
| 5046 | case POWER_DOMAIN_TRANSCODER_B: |
| 5047 | case POWER_DOMAIN_TRANSCODER_C: |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5048 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
| 5049 | (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE); |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 5050 | default: |
| 5051 | BUG(); |
| 5052 | } |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5053 | } |
| 5054 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5055 | static void __intel_set_power_well(struct drm_device *dev, bool enable) |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5056 | { |
| 5057 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5058 | bool is_enabled, enable_requested; |
| 5059 | uint32_t tmp; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5060 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5061 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
| 5062 | is_enabled = tmp & HSW_PWR_WELL_STATE; |
| 5063 | enable_requested = tmp & HSW_PWR_WELL_ENABLE; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5064 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5065 | if (enable) { |
| 5066 | if (!enable_requested) |
| 5067 | I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5068 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5069 | if (!is_enabled) { |
| 5070 | DRM_DEBUG_KMS("Enabling power well\n"); |
| 5071 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
| 5072 | HSW_PWR_WELL_STATE), 20)) |
| 5073 | DRM_ERROR("Timeout enabling power well\n"); |
| 5074 | } |
| 5075 | } else { |
| 5076 | if (enable_requested) { |
| 5077 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
| 5078 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5079 | } |
| 5080 | } |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5081 | } |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5082 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5083 | static struct i915_power_well *hsw_pwr; |
| 5084 | |
| 5085 | /* Display audio driver power well request */ |
| 5086 | void i915_request_power_well(void) |
| 5087 | { |
| 5088 | if (WARN_ON(!hsw_pwr)) |
| 5089 | return; |
| 5090 | |
| 5091 | spin_lock_irq(&hsw_pwr->lock); |
| 5092 | if (!hsw_pwr->count++ && |
| 5093 | !hsw_pwr->i915_request) |
| 5094 | __intel_set_power_well(hsw_pwr->device, true); |
| 5095 | spin_unlock_irq(&hsw_pwr->lock); |
| 5096 | } |
| 5097 | EXPORT_SYMBOL_GPL(i915_request_power_well); |
| 5098 | |
| 5099 | /* Display audio driver power well release */ |
| 5100 | void i915_release_power_well(void) |
| 5101 | { |
| 5102 | if (WARN_ON(!hsw_pwr)) |
| 5103 | return; |
| 5104 | |
| 5105 | spin_lock_irq(&hsw_pwr->lock); |
| 5106 | WARN_ON(!hsw_pwr->count); |
| 5107 | if (!--hsw_pwr->count && |
| 5108 | !hsw_pwr->i915_request) |
| 5109 | __intel_set_power_well(hsw_pwr->device, false); |
| 5110 | spin_unlock_irq(&hsw_pwr->lock); |
| 5111 | } |
| 5112 | EXPORT_SYMBOL_GPL(i915_release_power_well); |
| 5113 | |
| 5114 | int i915_init_power_well(struct drm_device *dev) |
| 5115 | { |
| 5116 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5117 | |
| 5118 | hsw_pwr = &dev_priv->power_well; |
| 5119 | |
| 5120 | hsw_pwr->device = dev; |
| 5121 | spin_lock_init(&hsw_pwr->lock); |
| 5122 | hsw_pwr->count = 0; |
| 5123 | |
| 5124 | return 0; |
| 5125 | } |
| 5126 | |
| 5127 | void i915_remove_power_well(struct drm_device *dev) |
| 5128 | { |
| 5129 | hsw_pwr = NULL; |
| 5130 | } |
| 5131 | |
| 5132 | void intel_set_power_well(struct drm_device *dev, bool enable) |
| 5133 | { |
| 5134 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5135 | struct i915_power_well *power_well = &dev_priv->power_well; |
| 5136 | |
| 5137 | if (!HAS_POWER_WELL(dev)) |
| 5138 | return; |
| 5139 | |
| 5140 | if (!i915_disable_power_well && !enable) |
| 5141 | return; |
| 5142 | |
| 5143 | spin_lock_irq(&power_well->lock); |
| 5144 | power_well->i915_request = enable; |
| 5145 | |
| 5146 | /* only reject "disable" power well request */ |
| 5147 | if (power_well->count && !enable) { |
| 5148 | spin_unlock_irq(&power_well->lock); |
| 5149 | return; |
| 5150 | } |
| 5151 | |
| 5152 | __intel_set_power_well(dev, enable); |
| 5153 | spin_unlock_irq(&power_well->lock); |
| 5154 | } |
| 5155 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5156 | /* |
| 5157 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
| 5158 | * when not needed anymore. We have 4 registers that can request the power well |
| 5159 | * to be enabled, and it will only be disabled if none of the registers is |
| 5160 | * requesting it to be enabled. |
| 5161 | */ |
| 5162 | void intel_init_power_well(struct drm_device *dev) |
| 5163 | { |
| 5164 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5165 | |
Paulo Zanoni | 86d52df | 2013-03-06 20:03:18 -0300 | [diff] [blame] | 5166 | if (!HAS_POWER_WELL(dev)) |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5167 | return; |
| 5168 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5169 | /* For now, we need the power well to be always enabled. */ |
| 5170 | intel_set_power_well(dev, true); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5171 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5172 | /* We're taking over the BIOS, so clear any requests made by it since |
| 5173 | * the driver is in charge now. */ |
| 5174 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) |
| 5175 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5176 | } |
| 5177 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5178 | /* Set up chip specific power management-related functions */ |
| 5179 | void intel_init_pm(struct drm_device *dev) |
| 5180 | { |
| 5181 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5182 | |
| 5183 | if (I915_HAS_FBC(dev)) { |
| 5184 | if (HAS_PCH_SPLIT(dev)) { |
| 5185 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 5186 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 5187 | dev_priv->display.enable_fbc = |
| 5188 | gen7_enable_fbc; |
| 5189 | else |
| 5190 | dev_priv->display.enable_fbc = |
| 5191 | ironlake_enable_fbc; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5192 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 5193 | } else if (IS_GM45(dev)) { |
| 5194 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 5195 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 5196 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
| 5197 | } else if (IS_CRESTLINE(dev)) { |
| 5198 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 5199 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 5200 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
| 5201 | } |
| 5202 | /* 855GM needs testing */ |
| 5203 | } |
| 5204 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 5205 | /* For cxsr */ |
| 5206 | if (IS_PINEVIEW(dev)) |
| 5207 | i915_pineview_get_mem_freq(dev); |
| 5208 | else if (IS_GEN5(dev)) |
| 5209 | i915_ironlake_get_mem_freq(dev); |
| 5210 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5211 | /* For FIFO watermark updates */ |
| 5212 | if (HAS_PCH_SPLIT(dev)) { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5213 | if (IS_GEN5(dev)) { |
| 5214 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
| 5215 | dev_priv->display.update_wm = ironlake_update_wm; |
| 5216 | else { |
| 5217 | DRM_DEBUG_KMS("Failed to get proper latency. " |
| 5218 | "Disable CxSR\n"); |
| 5219 | dev_priv->display.update_wm = NULL; |
| 5220 | } |
| 5221 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
| 5222 | } else if (IS_GEN6(dev)) { |
| 5223 | if (SNB_READ_WM0_LATENCY()) { |
| 5224 | dev_priv->display.update_wm = sandybridge_update_wm; |
| 5225 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
| 5226 | } else { |
| 5227 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 5228 | "Disable CxSR\n"); |
| 5229 | dev_priv->display.update_wm = NULL; |
| 5230 | } |
| 5231 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
| 5232 | } else if (IS_IVYBRIDGE(dev)) { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5233 | if (SNB_READ_WM0_LATENCY()) { |
Chris Wilson | c43d018 | 2012-12-11 12:01:42 +0000 | [diff] [blame] | 5234 | dev_priv->display.update_wm = ivybridge_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5235 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
| 5236 | } else { |
| 5237 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 5238 | "Disable CxSR\n"); |
| 5239 | dev_priv->display.update_wm = NULL; |
| 5240 | } |
| 5241 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Eugeni Dodonov | 6b8a5ee | 2012-05-09 15:37:23 -0300 | [diff] [blame] | 5242 | } else if (IS_HASWELL(dev)) { |
Paulo Zanoni | 3e1f726 | 2013-05-03 17:23:44 -0300 | [diff] [blame] | 5243 | if (I915_READ64(MCH_SSKPD)) { |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 5244 | dev_priv->display.update_wm = haswell_update_wm; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 5245 | dev_priv->display.update_sprite_wm = |
| 5246 | haswell_update_sprite_wm; |
Eugeni Dodonov | 6b8a5ee | 2012-05-09 15:37:23 -0300 | [diff] [blame] | 5247 | } else { |
| 5248 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 5249 | "Disable CxSR\n"); |
| 5250 | dev_priv->display.update_wm = NULL; |
| 5251 | } |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5252 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5253 | } else |
| 5254 | dev_priv->display.update_wm = NULL; |
| 5255 | } else if (IS_VALLEYVIEW(dev)) { |
| 5256 | dev_priv->display.update_wm = valleyview_update_wm; |
| 5257 | dev_priv->display.init_clock_gating = |
| 5258 | valleyview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5259 | } else if (IS_PINEVIEW(dev)) { |
| 5260 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
| 5261 | dev_priv->is_ddr3, |
| 5262 | dev_priv->fsb_freq, |
| 5263 | dev_priv->mem_freq)) { |
| 5264 | DRM_INFO("failed to find known CxSR latency " |
| 5265 | "(found ddr%s fsb freq %d, mem freq %d), " |
| 5266 | "disabling CxSR\n", |
| 5267 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
| 5268 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 5269 | /* Disable CxSR and never update its watermark again */ |
| 5270 | pineview_disable_cxsr(dev); |
| 5271 | dev_priv->display.update_wm = NULL; |
| 5272 | } else |
| 5273 | dev_priv->display.update_wm = pineview_update_wm; |
| 5274 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 5275 | } else if (IS_G4X(dev)) { |
| 5276 | dev_priv->display.update_wm = g4x_update_wm; |
| 5277 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 5278 | } else if (IS_GEN4(dev)) { |
| 5279 | dev_priv->display.update_wm = i965_update_wm; |
| 5280 | if (IS_CRESTLINE(dev)) |
| 5281 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 5282 | else if (IS_BROADWATER(dev)) |
| 5283 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 5284 | } else if (IS_GEN3(dev)) { |
| 5285 | dev_priv->display.update_wm = i9xx_update_wm; |
| 5286 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 5287 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 5288 | } else if (IS_I865G(dev)) { |
| 5289 | dev_priv->display.update_wm = i830_update_wm; |
| 5290 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 5291 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
| 5292 | } else if (IS_I85X(dev)) { |
| 5293 | dev_priv->display.update_wm = i9xx_update_wm; |
| 5294 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; |
| 5295 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 5296 | } else { |
| 5297 | dev_priv->display.update_wm = i830_update_wm; |
| 5298 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
| 5299 | if (IS_845G(dev)) |
| 5300 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
| 5301 | else |
| 5302 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
| 5303 | } |
| 5304 | } |
| 5305 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 5306 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
| 5307 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5308 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 5309 | |
| 5310 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 5311 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
| 5312 | return -EAGAIN; |
| 5313 | } |
| 5314 | |
| 5315 | I915_WRITE(GEN6_PCODE_DATA, *val); |
| 5316 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 5317 | |
| 5318 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 5319 | 500)) { |
| 5320 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
| 5321 | return -ETIMEDOUT; |
| 5322 | } |
| 5323 | |
| 5324 | *val = I915_READ(GEN6_PCODE_DATA); |
| 5325 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 5326 | |
| 5327 | return 0; |
| 5328 | } |
| 5329 | |
| 5330 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) |
| 5331 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5332 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 5333 | |
| 5334 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 5335 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
| 5336 | return -EAGAIN; |
| 5337 | } |
| 5338 | |
| 5339 | I915_WRITE(GEN6_PCODE_DATA, val); |
| 5340 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 5341 | |
| 5342 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 5343 | 500)) { |
| 5344 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
| 5345 | return -ETIMEDOUT; |
| 5346 | } |
| 5347 | |
| 5348 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 5349 | |
| 5350 | return 0; |
| 5351 | } |
Jesse Barnes | a0e4e19 | 2013-04-02 11:23:05 -0700 | [diff] [blame] | 5352 | |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 5353 | int vlv_gpu_freq(int ddr_freq, int val) |
| 5354 | { |
| 5355 | int mult, base; |
| 5356 | |
| 5357 | switch (ddr_freq) { |
| 5358 | case 800: |
| 5359 | mult = 20; |
| 5360 | base = 120; |
| 5361 | break; |
| 5362 | case 1066: |
| 5363 | mult = 22; |
| 5364 | base = 133; |
| 5365 | break; |
| 5366 | case 1333: |
| 5367 | mult = 21; |
| 5368 | base = 125; |
| 5369 | break; |
| 5370 | default: |
| 5371 | return -1; |
| 5372 | } |
| 5373 | |
| 5374 | return ((val - 0xbd) * mult) + base; |
| 5375 | } |
| 5376 | |
| 5377 | int vlv_freq_opcode(int ddr_freq, int val) |
| 5378 | { |
| 5379 | int mult, base; |
| 5380 | |
| 5381 | switch (ddr_freq) { |
| 5382 | case 800: |
| 5383 | mult = 20; |
| 5384 | base = 120; |
| 5385 | break; |
| 5386 | case 1066: |
| 5387 | mult = 22; |
| 5388 | base = 133; |
| 5389 | break; |
| 5390 | case 1333: |
| 5391 | mult = 21; |
| 5392 | base = 125; |
| 5393 | break; |
| 5394 | default: |
| 5395 | return -1; |
| 5396 | } |
| 5397 | |
| 5398 | val /= mult; |
| 5399 | val -= base / mult; |
| 5400 | val += 0xbd; |
| 5401 | |
| 5402 | if (val > 0xea) |
| 5403 | val = 0xea; |
| 5404 | |
| 5405 | return val; |
| 5406 | } |
| 5407 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 5408 | void intel_pm_init(struct drm_device *dev) |
| 5409 | { |
| 5410 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5411 | |
| 5412 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
| 5413 | intel_gen6_powersave_work); |
| 5414 | } |
| 5415 | |