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Jacob Panaf2730f2010-02-12 10:31:47 -08001/*
2 * mrst.h: Intel Moorestown platform specific setup code
3 *
4 * (C) Copyright 2009 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11#ifndef _ASM_X86_MRST_H
12#define _ASM_X86_MRST_H
Feng Tangc20b5c32010-09-13 15:08:55 +080013
14#include <linux/sfi.h>
15
Jacob Panaf2730f2010-02-12 10:31:47 -080016extern int pci_mrst_init(void);
Feng Tang73092822010-11-10 17:29:00 +000017extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
18extern int sfi_mrtc_num;
19extern struct sfi_rtc_table_entry sfi_mrtc_array[];
Jacob Panaf2730f2010-02-12 10:31:47 -080020
Jacob Pana0c173b2010-05-19 12:01:24 -070021/*
22 * Medfield is the follow-up of Moorestown, it combines two chip solution into
23 * one. Other than that it also added always-on and constant tsc and lapic
24 * timers. Medfield is the platform name, and the chip name is called Penwell
25 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
26 * identified via MSRs.
27 */
28enum mrst_cpu_type {
29 MRST_CPU_CHIP_LINCROFT = 1,
30 MRST_CPU_CHIP_PENWELL,
31};
32
H. Peter Anvina75af582010-05-19 13:40:14 -070033extern enum mrst_cpu_type __mrst_cpu_chip;
Mathias Nyman35d47692011-11-15 14:46:52 -080034
35#ifdef CONFIG_X86_INTEL_MID
36
H. Peter Anvin55572b22010-10-07 16:42:54 -070037static inline enum mrst_cpu_type mrst_identify_cpu(void)
H. Peter Anvina75af582010-05-19 13:40:14 -070038{
39 return __mrst_cpu_chip;
40}
41
Mathias Nyman35d47692011-11-15 14:46:52 -080042#else /* !CONFIG_X86_INTEL_MID */
43
44#define mrst_identify_cpu() (0)
45
46#endif /* !CONFIG_X86_INTEL_MID */
47
Jacob Pana0c173b2010-05-19 12:01:24 -070048enum mrst_timer_options {
49 MRST_TIMER_DEFAULT,
50 MRST_TIMER_APBT_ONLY,
51 MRST_TIMER_LAPIC_APBT,
52};
53
H. Peter Anvin14671382010-05-19 14:37:40 -070054extern enum mrst_timer_options mrst_timer_options;
55
Dirk Brandewie0a915322011-11-10 13:42:53 +000056/*
57 * Penwell uses spread spectrum clock, so the freq number is not exactly
58 * the same as reported by MSR based on SDM.
59 */
60#define PENWELL_FSB_FREQ_83SKU 83200
61#define PENWELL_FSB_FREQ_100SKU 99840
62
Jacob Pan16ab5392010-02-12 03:08:30 -080063#define SFI_MTMR_MAX_NUM 8
Feng Tangcf089452010-02-12 03:37:38 -080064#define SFI_MRTC_MAX 8
Jacob Pan16ab5392010-02-12 03:08:30 -080065
Feng Tangc20b5c32010-09-13 15:08:55 +080066extern struct console early_mrst_console;
67extern void mrst_early_console_init(void);
Feng Tang4d033552010-09-13 15:08:56 +080068
69extern struct console early_hsu_console;
Mika Westerbergb82e3242011-11-10 13:18:09 +000070extern void hsu_early_console_init(const char *);
Feng Tang1da4b1c2010-11-09 11:22:58 +000071
72extern void intel_scu_devices_create(void);
73extern void intel_scu_devices_destroy(void);
74
Feng Tang73092822010-11-10 17:29:00 +000075/* VRTC timer */
76#define MRST_VRTC_MAP_SZ (1024)
77/*#define MRST_VRTC_PGOFFSET (0xc00) */
78
79extern void mrst_rtc_init(void);
80
Jacob Panaf2730f2010-02-12 10:31:47 -080081#endif /* _ASM_X86_MRST_H */