Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "drm_crtc_helper.h" |
| 28 | #include "radeon_drm.h" |
| 29 | #include "radeon.h" |
| 30 | #include "atom.h" |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 31 | #include <linux/backlight.h> |
| 32 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 33 | #include <asm/backlight.h> |
| 34 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 36 | static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) |
| 37 | { |
| 38 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 39 | struct drm_encoder_helper_funcs *encoder_funcs; |
| 40 | |
| 41 | encoder_funcs = encoder->helper_private; |
| 42 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 43 | radeon_encoder->active_device = 0; |
| 44 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 45 | |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 46 | static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 47 | { |
| 48 | struct drm_device *dev = encoder->dev; |
| 49 | struct radeon_device *rdev = dev->dev_private; |
| 50 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 51 | uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; |
| 52 | int panel_pwr_delay = 2000; |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 53 | bool is_mac = false; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 54 | uint8_t backlight_level; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 55 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 56 | |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 57 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
| 58 | backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
| 59 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 60 | if (radeon_encoder->enc_priv) { |
| 61 | if (rdev->is_atom_bios) { |
| 62 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
| 63 | panel_pwr_delay = lvds->panel_pwr_delay; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 64 | if (lvds->bl_dev) |
| 65 | backlight_level = lvds->backlight_level; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 66 | } else { |
| 67 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
| 68 | panel_pwr_delay = lvds->panel_pwr_delay; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 69 | if (lvds->bl_dev) |
| 70 | backlight_level = lvds->backlight_level; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | } |
| 72 | } |
| 73 | |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 74 | /* macs (and possibly some x86 oem systems?) wire up LVDS strangely |
| 75 | * Taken from radeonfb. |
| 76 | */ |
| 77 | if ((rdev->mode_info.connector_table == CT_IBOOK) || |
| 78 | (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || |
| 79 | (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || |
| 80 | (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) |
| 81 | is_mac = true; |
| 82 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 83 | switch (mode) { |
| 84 | case DRM_MODE_DPMS_ON: |
| 85 | disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); |
| 86 | disp_pwr_man |= RADEON_AUTO_PWRUP_EN; |
| 87 | WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); |
| 88 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
| 89 | lvds_pll_cntl |= RADEON_LVDS_PLL_EN; |
| 90 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 91 | mdelay(1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 92 | |
| 93 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
| 94 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; |
| 95 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
| 96 | |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 97 | lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | |
| 98 | RADEON_LVDS_BL_MOD_LEVEL_MASK); |
| 99 | lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | |
| 100 | RADEON_LVDS_DIGON | RADEON_LVDS_BLON | |
| 101 | (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 102 | if (is_mac) |
| 103 | lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 104 | mdelay(panel_pwr_delay); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 106 | break; |
| 107 | case DRM_MODE_DPMS_STANDBY: |
| 108 | case DRM_MODE_DPMS_SUSPEND: |
| 109 | case DRM_MODE_DPMS_OFF: |
| 110 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 111 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 112 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 113 | if (is_mac) { |
| 114 | lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; |
| 115 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 116 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); |
| 117 | } else { |
| 118 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 119 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); |
| 120 | } |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 121 | mdelay(panel_pwr_delay); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 123 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 124 | mdelay(panel_pwr_delay); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 125 | break; |
| 126 | } |
| 127 | |
| 128 | if (rdev->is_atom_bios) |
| 129 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 130 | else |
| 131 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 132 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 133 | } |
| 134 | |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 135 | static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) |
| 136 | { |
| 137 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 138 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 139 | DRM_DEBUG("\n"); |
| 140 | |
| 141 | if (radeon_encoder->enc_priv) { |
| 142 | if (rdev->is_atom_bios) { |
| 143 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
| 144 | lvds->dpms_mode = mode; |
| 145 | } else { |
| 146 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
| 147 | lvds->dpms_mode = mode; |
| 148 | } |
| 149 | } |
| 150 | |
| 151 | radeon_legacy_lvds_update(encoder, mode); |
| 152 | } |
| 153 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 154 | static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) |
| 155 | { |
| 156 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 157 | |
| 158 | if (rdev->is_atom_bios) |
| 159 | radeon_atom_output_lock(encoder, true); |
| 160 | else |
| 161 | radeon_combios_output_lock(encoder, true); |
| 162 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 163 | } |
| 164 | |
| 165 | static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) |
| 166 | { |
| 167 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 168 | |
| 169 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); |
| 170 | if (rdev->is_atom_bios) |
| 171 | radeon_atom_output_lock(encoder, false); |
| 172 | else |
| 173 | radeon_combios_output_lock(encoder, false); |
| 174 | } |
| 175 | |
| 176 | static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, |
| 177 | struct drm_display_mode *mode, |
| 178 | struct drm_display_mode *adjusted_mode) |
| 179 | { |
| 180 | struct drm_device *dev = encoder->dev; |
| 181 | struct radeon_device *rdev = dev->dev_private; |
| 182 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 183 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 184 | uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; |
| 185 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 186 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 187 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 188 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
| 189 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; |
| 190 | |
| 191 | lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
Alex Deucher | 32f48ff | 2009-11-30 01:54:16 -0500 | [diff] [blame] | 192 | if (rdev->is_atom_bios) { |
| 193 | /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl |
| 194 | * need to call that on resume to set up the reg properly. |
| 195 | */ |
| 196 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| 197 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
| 198 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
| 199 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 200 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
| 201 | if (lvds) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 202 | DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | lvds_gen_cntl = lvds->lvds_gen_cntl; |
| 204 | lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
| 205 | (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
| 206 | lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
| 207 | (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
| 208 | } else |
| 209 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
Alex Deucher | 32f48ff | 2009-11-30 01:54:16 -0500 | [diff] [blame] | 210 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 211 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
| 212 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | |
| 213 | RADEON_LVDS_BLON | |
| 214 | RADEON_LVDS_EN | |
| 215 | RADEON_LVDS_RST_FM); |
| 216 | |
| 217 | if (ASIC_IS_R300(rdev)) |
| 218 | lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); |
| 219 | |
| 220 | if (radeon_crtc->crtc_id == 0) { |
| 221 | if (ASIC_IS_R300(rdev)) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 222 | if (radeon_encoder->rmx_type != RMX_OFF) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 223 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; |
| 224 | } else |
| 225 | lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; |
| 226 | } else { |
| 227 | if (ASIC_IS_R300(rdev)) |
| 228 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; |
| 229 | else |
| 230 | lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; |
| 231 | } |
| 232 | |
| 233 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 234 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
| 235 | WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); |
| 236 | |
| 237 | if (rdev->family == CHIP_RV410) |
| 238 | WREG32(RADEON_CLOCK_CNTL_INDEX, 0); |
| 239 | |
| 240 | if (rdev->is_atom_bios) |
| 241 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 242 | else |
| 243 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 244 | } |
| 245 | |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 246 | static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 247 | const struct drm_display_mode *mode, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 248 | struct drm_display_mode *adjusted_mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 249 | { |
| 250 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 251 | |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 252 | /* set the active encoder to connector routing */ |
| 253 | radeon_encoder_set_active_device(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 254 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 255 | |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 256 | /* get the native mode for LVDS */ |
Alex Deucher | 3515387 | 2010-04-30 12:00:44 -0400 | [diff] [blame] | 257 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
| 258 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 259 | |
| 260 | return true; |
| 261 | } |
| 262 | |
| 263 | static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { |
| 264 | .dpms = radeon_legacy_lvds_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 265 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 266 | .prepare = radeon_legacy_lvds_prepare, |
| 267 | .mode_set = radeon_legacy_lvds_mode_set, |
| 268 | .commit = radeon_legacy_lvds_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 269 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | }; |
| 271 | |
Michel Dänzer | 88a2b75 | 2011-04-07 16:20:49 +0200 | [diff] [blame] | 272 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 273 | |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 274 | static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) |
| 275 | { |
| 276 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
| 277 | uint8_t level; |
| 278 | |
| 279 | /* Convert brightness to hardware level */ |
| 280 | if (bd->props.brightness < 0) |
| 281 | level = 0; |
Alex Deucher | 9103088 | 2012-07-26 11:05:22 -0400 | [diff] [blame] | 282 | else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) |
| 283 | level = RADEON_MAX_BL_LEVEL; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 284 | else |
| 285 | level = bd->props.brightness; |
| 286 | |
| 287 | if (pdata->negative) |
Alex Deucher | 9103088 | 2012-07-26 11:05:22 -0400 | [diff] [blame] | 288 | level = RADEON_MAX_BL_LEVEL - level; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 289 | |
| 290 | return level; |
| 291 | } |
| 292 | |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 293 | void |
| 294 | radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 295 | { |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 296 | struct drm_device *dev = radeon_encoder->base.dev; |
| 297 | struct radeon_device *rdev = dev->dev_private; |
| 298 | int dpms_mode = DRM_MODE_DPMS_ON; |
| 299 | |
| 300 | if (radeon_encoder->enc_priv) { |
| 301 | if (rdev->is_atom_bios) { |
| 302 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 303 | if (lvds->backlight_level > 0) |
| 304 | dpms_mode = lvds->dpms_mode; |
| 305 | else |
| 306 | dpms_mode = DRM_MODE_DPMS_OFF; |
| 307 | lvds->backlight_level = level; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 308 | } else { |
| 309 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 310 | if (lvds->backlight_level > 0) |
| 311 | dpms_mode = lvds->dpms_mode; |
| 312 | else |
| 313 | dpms_mode = DRM_MODE_DPMS_OFF; |
| 314 | lvds->backlight_level = level; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 315 | } |
| 316 | } |
| 317 | |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame^] | 318 | radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); |
| 319 | } |
| 320 | |
| 321 | static int radeon_legacy_backlight_update_status(struct backlight_device *bd) |
| 322 | { |
| 323 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
| 324 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
| 325 | |
| 326 | radeon_legacy_set_backlight_level(radeon_encoder, |
| 327 | radeon_legacy_lvds_level(bd)); |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 328 | |
| 329 | return 0; |
| 330 | } |
| 331 | |
| 332 | static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) |
| 333 | { |
| 334 | struct radeon_backlight_privdata *pdata = bl_get_data(bd); |
| 335 | struct radeon_encoder *radeon_encoder = pdata->encoder; |
| 336 | struct drm_device *dev = radeon_encoder->base.dev; |
| 337 | struct radeon_device *rdev = dev->dev_private; |
| 338 | uint8_t backlight_level; |
| 339 | |
| 340 | backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> |
| 341 | RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
| 342 | |
Alex Deucher | 9103088 | 2012-07-26 11:05:22 -0400 | [diff] [blame] | 343 | return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | static const struct backlight_ops radeon_backlight_ops = { |
| 347 | .get_brightness = radeon_legacy_backlight_get_brightness, |
| 348 | .update_status = radeon_legacy_backlight_update_status, |
| 349 | }; |
| 350 | |
| 351 | void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, |
| 352 | struct drm_connector *drm_connector) |
| 353 | { |
| 354 | struct drm_device *dev = radeon_encoder->base.dev; |
| 355 | struct radeon_device *rdev = dev->dev_private; |
| 356 | struct backlight_device *bd; |
| 357 | struct backlight_properties props; |
| 358 | struct radeon_backlight_privdata *pdata; |
| 359 | uint8_t backlight_level; |
| 360 | |
| 361 | if (!radeon_encoder->enc_priv) |
| 362 | return; |
| 363 | |
| 364 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 365 | if (!pmac_has_backlight_type("ati") && |
| 366 | !pmac_has_backlight_type("mnca")) |
| 367 | return; |
| 368 | #endif |
| 369 | |
| 370 | pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); |
| 371 | if (!pdata) { |
| 372 | DRM_ERROR("Memory allocation failed\n"); |
| 373 | goto error; |
| 374 | } |
| 375 | |
Corentin Chary | af437cf | 2012-05-22 10:29:46 +0100 | [diff] [blame] | 376 | memset(&props, 0, sizeof(props)); |
Alex Deucher | 9103088 | 2012-07-26 11:05:22 -0400 | [diff] [blame] | 377 | props.max_brightness = RADEON_MAX_BL_LEVEL; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 378 | props.type = BACKLIGHT_RAW; |
| 379 | bd = backlight_device_register("radeon_bl", &drm_connector->kdev, |
| 380 | pdata, &radeon_backlight_ops, &props); |
| 381 | if (IS_ERR(bd)) { |
| 382 | DRM_ERROR("Backlight registration failed\n"); |
| 383 | goto error; |
| 384 | } |
| 385 | |
| 386 | pdata->encoder = radeon_encoder; |
| 387 | |
| 388 | backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> |
| 389 | RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; |
| 390 | |
| 391 | /* First, try to detect backlight level sense based on the assumption |
| 392 | * that firmware set it up at full brightness |
| 393 | */ |
| 394 | if (backlight_level == 0) |
| 395 | pdata->negative = true; |
| 396 | else if (backlight_level == 0xff) |
| 397 | pdata->negative = false; |
| 398 | else { |
| 399 | /* XXX hack... maybe some day we can figure out in what direction |
| 400 | * backlight should work on a given panel? |
| 401 | */ |
| 402 | pdata->negative = (rdev->family != CHIP_RV200 && |
| 403 | rdev->family != CHIP_RV250 && |
| 404 | rdev->family != CHIP_RV280 && |
| 405 | rdev->family != CHIP_RV350); |
| 406 | |
| 407 | #ifdef CONFIG_PMAC_BACKLIGHT |
| 408 | pdata->negative = (pdata->negative || |
| 409 | of_machine_is_compatible("PowerBook4,3") || |
| 410 | of_machine_is_compatible("PowerBook6,3") || |
| 411 | of_machine_is_compatible("PowerBook6,5")); |
| 412 | #endif |
| 413 | } |
| 414 | |
| 415 | if (rdev->is_atom_bios) { |
| 416 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
| 417 | lvds->bl_dev = bd; |
| 418 | } else { |
| 419 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
| 420 | lvds->bl_dev = bd; |
| 421 | } |
| 422 | |
| 423 | bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); |
| 424 | bd->props.power = FB_BLANK_UNBLANK; |
| 425 | backlight_update_status(bd); |
| 426 | |
| 427 | DRM_INFO("radeon legacy LVDS backlight initialized\n"); |
| 428 | |
| 429 | return; |
| 430 | |
| 431 | error: |
| 432 | kfree(pdata); |
| 433 | return; |
| 434 | } |
| 435 | |
| 436 | static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) |
| 437 | { |
| 438 | struct drm_device *dev = radeon_encoder->base.dev; |
| 439 | struct radeon_device *rdev = dev->dev_private; |
| 440 | struct backlight_device *bd = NULL; |
| 441 | |
| 442 | if (!radeon_encoder->enc_priv) |
| 443 | return; |
| 444 | |
| 445 | if (rdev->is_atom_bios) { |
| 446 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
| 447 | bd = lvds->bl_dev; |
| 448 | lvds->bl_dev = NULL; |
| 449 | } else { |
| 450 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
| 451 | bd = lvds->bl_dev; |
| 452 | lvds->bl_dev = NULL; |
| 453 | } |
| 454 | |
| 455 | if (bd) { |
Alex Deucher | 9103088 | 2012-07-26 11:05:22 -0400 | [diff] [blame] | 456 | struct radeon_backlight_privdata *pdata; |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 457 | |
| 458 | pdata = bl_get_data(bd); |
| 459 | backlight_device_unregister(bd); |
| 460 | kfree(pdata); |
| 461 | |
| 462 | DRM_INFO("radeon legacy LVDS backlight unloaded\n"); |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ |
| 467 | |
| 468 | void radeon_legacy_backlight_init(struct radeon_encoder *encoder) |
| 469 | { |
| 470 | } |
| 471 | |
| 472 | static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) |
| 473 | { |
| 474 | } |
| 475 | |
| 476 | #endif |
| 477 | |
| 478 | |
| 479 | static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) |
| 480 | { |
| 481 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 482 | |
| 483 | if (radeon_encoder->enc_priv) { |
| 484 | radeon_legacy_backlight_exit(radeon_encoder); |
| 485 | kfree(radeon_encoder->enc_priv); |
| 486 | } |
| 487 | drm_encoder_cleanup(encoder); |
| 488 | kfree(radeon_encoder); |
| 489 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 490 | |
| 491 | static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { |
Michel Dänzer | 63ec011 | 2011-03-22 16:30:23 -0700 | [diff] [blame] | 492 | .destroy = radeon_lvds_enc_destroy, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 493 | }; |
| 494 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 495 | static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) |
| 496 | { |
| 497 | struct drm_device *dev = encoder->dev; |
| 498 | struct radeon_device *rdev = dev->dev_private; |
| 499 | uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| 500 | uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); |
| 501 | uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
| 502 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 503 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 504 | |
| 505 | switch (mode) { |
| 506 | case DRM_MODE_DPMS_ON: |
| 507 | crtc_ext_cntl |= RADEON_CRTC_CRT_ON; |
| 508 | dac_cntl &= ~RADEON_DAC_PDWN; |
| 509 | dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | |
| 510 | RADEON_DAC_PDWN_G | |
| 511 | RADEON_DAC_PDWN_B); |
| 512 | break; |
| 513 | case DRM_MODE_DPMS_STANDBY: |
| 514 | case DRM_MODE_DPMS_SUSPEND: |
| 515 | case DRM_MODE_DPMS_OFF: |
| 516 | crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; |
| 517 | dac_cntl |= RADEON_DAC_PDWN; |
| 518 | dac_macro_cntl |= (RADEON_DAC_PDWN_R | |
| 519 | RADEON_DAC_PDWN_G | |
| 520 | RADEON_DAC_PDWN_B); |
| 521 | break; |
| 522 | } |
| 523 | |
| 524 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| 525 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
| 526 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
| 527 | |
| 528 | if (rdev->is_atom_bios) |
| 529 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 530 | else |
| 531 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 532 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) |
| 536 | { |
| 537 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 538 | |
| 539 | if (rdev->is_atom_bios) |
| 540 | radeon_atom_output_lock(encoder, true); |
| 541 | else |
| 542 | radeon_combios_output_lock(encoder, true); |
| 543 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 544 | } |
| 545 | |
| 546 | static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) |
| 547 | { |
| 548 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 549 | |
| 550 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
| 551 | |
| 552 | if (rdev->is_atom_bios) |
| 553 | radeon_atom_output_lock(encoder, false); |
| 554 | else |
| 555 | radeon_combios_output_lock(encoder, false); |
| 556 | } |
| 557 | |
| 558 | static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, |
| 559 | struct drm_display_mode *mode, |
| 560 | struct drm_display_mode *adjusted_mode) |
| 561 | { |
| 562 | struct drm_device *dev = encoder->dev; |
| 563 | struct radeon_device *rdev = dev->dev_private; |
| 564 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 565 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 566 | uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; |
| 567 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 568 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 569 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 570 | if (radeon_crtc->crtc_id == 0) { |
| 571 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
| 572 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
| 573 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
| 574 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 575 | } else { |
| 576 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); |
| 577 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 578 | } |
| 579 | } else { |
| 580 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
| 581 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
| 582 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
| 583 | disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; |
| 584 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 585 | } else { |
| 586 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; |
| 587 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | dac_cntl = (RADEON_DAC_MASK_ALL | |
| 592 | RADEON_DAC_VGA_ADR_EN | |
| 593 | /* TODO 6-bits */ |
| 594 | RADEON_DAC_8BIT_EN); |
| 595 | |
| 596 | WREG32_P(RADEON_DAC_CNTL, |
| 597 | dac_cntl, |
| 598 | RADEON_DAC_RANGE_CNTL | |
| 599 | RADEON_DAC_BLANKING); |
| 600 | |
| 601 | if (radeon_encoder->enc_priv) { |
| 602 | struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; |
| 603 | dac_macro_cntl = p_dac->ps2_pdac_adj; |
| 604 | } else |
| 605 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
| 606 | dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; |
| 607 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
| 608 | |
| 609 | if (rdev->is_atom_bios) |
| 610 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 611 | else |
| 612 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 613 | } |
| 614 | |
| 615 | static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, |
| 616 | struct drm_connector *connector) |
| 617 | { |
| 618 | struct drm_device *dev = encoder->dev; |
| 619 | struct radeon_device *rdev = dev->dev_private; |
| 620 | uint32_t vclk_ecp_cntl, crtc_ext_cntl; |
| 621 | uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; |
| 622 | enum drm_connector_status found = connector_status_disconnected; |
| 623 | bool color = true; |
| 624 | |
| 625 | /* save the regs we need */ |
| 626 | vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 627 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| 628 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
| 629 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
| 630 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
| 631 | |
| 632 | tmp = vclk_ecp_cntl & |
| 633 | ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| 634 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 635 | |
| 636 | tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; |
| 637 | WREG32(RADEON_CRTC_EXT_CNTL, tmp); |
| 638 | |
| 639 | tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | |
| 640 | RADEON_DAC_FORCE_DATA_EN; |
| 641 | |
| 642 | if (color) |
| 643 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
| 644 | else |
| 645 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
| 646 | |
| 647 | if (ASIC_IS_R300(rdev)) |
| 648 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 649 | else |
| 650 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 651 | |
| 652 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
| 653 | |
| 654 | tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); |
| 655 | tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; |
| 656 | WREG32(RADEON_DAC_CNTL, tmp); |
| 657 | |
| 658 | tmp &= ~(RADEON_DAC_PDWN_R | |
| 659 | RADEON_DAC_PDWN_G | |
| 660 | RADEON_DAC_PDWN_B); |
| 661 | |
| 662 | WREG32(RADEON_DAC_MACRO_CNTL, tmp); |
| 663 | |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 664 | mdelay(2); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 665 | |
| 666 | if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) |
| 667 | found = connector_status_connected; |
| 668 | |
| 669 | /* restore the regs we used */ |
| 670 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
| 671 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
| 672 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
| 673 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| 674 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); |
| 675 | |
| 676 | return found; |
| 677 | } |
| 678 | |
| 679 | static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { |
| 680 | .dpms = radeon_legacy_primary_dac_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 681 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 682 | .prepare = radeon_legacy_primary_dac_prepare, |
| 683 | .mode_set = radeon_legacy_primary_dac_mode_set, |
| 684 | .commit = radeon_legacy_primary_dac_commit, |
| 685 | .detect = radeon_legacy_primary_dac_detect, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 686 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 687 | }; |
| 688 | |
| 689 | |
| 690 | static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { |
| 691 | .destroy = radeon_enc_destroy, |
| 692 | }; |
| 693 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 694 | static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) |
| 695 | { |
| 696 | struct drm_device *dev = encoder->dev; |
| 697 | struct radeon_device *rdev = dev->dev_private; |
| 698 | uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 699 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 700 | |
| 701 | switch (mode) { |
| 702 | case DRM_MODE_DPMS_ON: |
| 703 | fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
| 704 | break; |
| 705 | case DRM_MODE_DPMS_STANDBY: |
| 706 | case DRM_MODE_DPMS_SUSPEND: |
| 707 | case DRM_MODE_DPMS_OFF: |
| 708 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
| 709 | break; |
| 710 | } |
| 711 | |
| 712 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
| 713 | |
| 714 | if (rdev->is_atom_bios) |
| 715 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 716 | else |
| 717 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 718 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 719 | } |
| 720 | |
| 721 | static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) |
| 722 | { |
| 723 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 724 | |
| 725 | if (rdev->is_atom_bios) |
| 726 | radeon_atom_output_lock(encoder, true); |
| 727 | else |
| 728 | radeon_combios_output_lock(encoder, true); |
| 729 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 730 | } |
| 731 | |
| 732 | static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) |
| 733 | { |
| 734 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 735 | |
| 736 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); |
| 737 | |
| 738 | if (rdev->is_atom_bios) |
| 739 | radeon_atom_output_lock(encoder, true); |
| 740 | else |
| 741 | radeon_combios_output_lock(encoder, true); |
| 742 | } |
| 743 | |
| 744 | static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, |
| 745 | struct drm_display_mode *mode, |
| 746 | struct drm_display_mode *adjusted_mode) |
| 747 | { |
| 748 | struct drm_device *dev = encoder->dev; |
| 749 | struct radeon_device *rdev = dev->dev_private; |
| 750 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 751 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 752 | uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; |
| 753 | int i; |
| 754 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 755 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 756 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 757 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); |
| 758 | tmp &= 0xfffff; |
| 759 | if (rdev->family == CHIP_RV280) { |
| 760 | /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ |
| 761 | tmp ^= (1 << 22); |
| 762 | tmds_pll_cntl ^= (1 << 22); |
| 763 | } |
| 764 | |
| 765 | if (radeon_encoder->enc_priv) { |
| 766 | struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; |
| 767 | |
| 768 | for (i = 0; i < 4; i++) { |
| 769 | if (tmds->tmds_pll[i].freq == 0) |
| 770 | break; |
| 771 | if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { |
| 772 | tmp = tmds->tmds_pll[i].value ; |
| 773 | break; |
| 774 | } |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { |
| 779 | if (tmp & 0xfff00000) |
| 780 | tmds_pll_cntl = tmp; |
| 781 | else { |
| 782 | tmds_pll_cntl &= 0xfff00000; |
| 783 | tmds_pll_cntl |= tmp; |
| 784 | } |
| 785 | } else |
| 786 | tmds_pll_cntl = tmp; |
| 787 | |
| 788 | tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & |
| 789 | ~(RADEON_TMDS_TRANSMITTER_PLLRST); |
| 790 | |
| 791 | if (rdev->family == CHIP_R200 || |
| 792 | rdev->family == CHIP_R100 || |
| 793 | ASIC_IS_R300(rdev)) |
| 794 | tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); |
| 795 | else /* RV chips got this bit reversed */ |
| 796 | tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; |
| 797 | |
| 798 | fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | |
| 799 | (RADEON_FP_CRTC_DONT_SHADOW_VPAR | |
| 800 | RADEON_FP_CRTC_DONT_SHADOW_HEND)); |
| 801 | |
| 802 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
| 803 | |
Alex Deucher | 1b4d7d7 | 2009-10-15 01:33:35 -0400 | [diff] [blame] | 804 | fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | |
| 805 | RADEON_FP_DFP_SYNC_SEL | |
| 806 | RADEON_FP_CRT_SYNC_SEL | |
| 807 | RADEON_FP_CRTC_LOCK_8DOT | |
| 808 | RADEON_FP_USE_SHADOW_EN | |
| 809 | RADEON_FP_CRTC_USE_SHADOW_VEND | |
| 810 | RADEON_FP_CRT_SYNC_ALT); |
| 811 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 812 | if (1) /* FIXME rgbBits == 8 */ |
| 813 | fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ |
| 814 | else |
| 815 | fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ |
| 816 | |
| 817 | if (radeon_crtc->crtc_id == 0) { |
| 818 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
| 819 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 820 | if (radeon_encoder->rmx_type != RMX_OFF) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 821 | fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; |
| 822 | else |
| 823 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; |
| 824 | } else |
Alex Deucher | 1b4d7d7 | 2009-10-15 01:33:35 -0400 | [diff] [blame] | 825 | fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 826 | } else { |
| 827 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
| 828 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
| 829 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; |
| 830 | } else |
| 831 | fp_gen_cntl |= RADEON_FP_SEL_CRTC2; |
| 832 | } |
| 833 | |
| 834 | WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); |
| 835 | WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); |
| 836 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
| 837 | |
| 838 | if (rdev->is_atom_bios) |
| 839 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 840 | else |
| 841 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 842 | } |
| 843 | |
| 844 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { |
| 845 | .dpms = radeon_legacy_tmds_int_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 846 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 847 | .prepare = radeon_legacy_tmds_int_prepare, |
| 848 | .mode_set = radeon_legacy_tmds_int_mode_set, |
| 849 | .commit = radeon_legacy_tmds_int_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 850 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 851 | }; |
| 852 | |
| 853 | |
| 854 | static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { |
| 855 | .destroy = radeon_enc_destroy, |
| 856 | }; |
| 857 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 858 | static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) |
| 859 | { |
| 860 | struct drm_device *dev = encoder->dev; |
| 861 | struct radeon_device *rdev = dev->dev_private; |
| 862 | uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 863 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 864 | |
| 865 | switch (mode) { |
| 866 | case DRM_MODE_DPMS_ON: |
| 867 | fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; |
| 868 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 869 | break; |
| 870 | case DRM_MODE_DPMS_STANDBY: |
| 871 | case DRM_MODE_DPMS_SUSPEND: |
| 872 | case DRM_MODE_DPMS_OFF: |
| 873 | fp2_gen_cntl |= RADEON_FP2_BLANK_EN; |
| 874 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 875 | break; |
| 876 | } |
| 877 | |
| 878 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 879 | |
| 880 | if (rdev->is_atom_bios) |
| 881 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 882 | else |
| 883 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 884 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 885 | } |
| 886 | |
| 887 | static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) |
| 888 | { |
| 889 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 890 | |
| 891 | if (rdev->is_atom_bios) |
| 892 | radeon_atom_output_lock(encoder, true); |
| 893 | else |
| 894 | radeon_combios_output_lock(encoder, true); |
| 895 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 896 | } |
| 897 | |
| 898 | static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) |
| 899 | { |
| 900 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 901 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); |
| 902 | |
| 903 | if (rdev->is_atom_bios) |
| 904 | radeon_atom_output_lock(encoder, false); |
| 905 | else |
| 906 | radeon_combios_output_lock(encoder, false); |
| 907 | } |
| 908 | |
| 909 | static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, |
| 910 | struct drm_display_mode *mode, |
| 911 | struct drm_display_mode *adjusted_mode) |
| 912 | { |
| 913 | struct drm_device *dev = encoder->dev; |
| 914 | struct radeon_device *rdev = dev->dev_private; |
| 915 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 916 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 917 | uint32_t fp2_gen_cntl; |
| 918 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 919 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 920 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 921 | if (rdev->is_atom_bios) { |
| 922 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
Alex Deucher | 99999aa | 2010-11-16 12:09:41 -0500 | [diff] [blame] | 923 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 924 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 925 | } else { |
| 926 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 927 | |
| 928 | if (1) /* FIXME rgbBits == 8 */ |
| 929 | fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ |
| 930 | else |
| 931 | fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ |
| 932 | |
| 933 | fp2_gen_cntl &= ~(RADEON_FP2_ON | |
| 934 | RADEON_FP2_DVO_EN | |
| 935 | RADEON_FP2_DVO_RATE_SEL_SDR); |
| 936 | |
| 937 | /* XXX: these are oem specific */ |
| 938 | if (ASIC_IS_R300(rdev)) { |
| 939 | if ((dev->pdev->device == 0x4850) && |
| 940 | (dev->pdev->subsystem_vendor == 0x1028) && |
| 941 | (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ |
| 942 | fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; |
| 943 | else |
| 944 | fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; |
| 945 | |
| 946 | /*if (mode->clock > 165000) |
| 947 | fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ |
| 948 | } |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 949 | if (!radeon_combios_external_tmds_setup(encoder)) |
| 950 | radeon_external_tmds_setup(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 951 | } |
| 952 | |
| 953 | if (radeon_crtc->crtc_id == 0) { |
| 954 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
| 955 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 956 | if (radeon_encoder->rmx_type != RMX_OFF) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 957 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; |
| 958 | else |
| 959 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; |
| 960 | } else |
| 961 | fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; |
| 962 | } else { |
| 963 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
| 964 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
| 965 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
| 966 | } else |
| 967 | fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; |
| 968 | } |
| 969 | |
| 970 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 971 | |
| 972 | if (rdev->is_atom_bios) |
| 973 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 974 | else |
| 975 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 976 | } |
| 977 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 978 | static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) |
| 979 | { |
| 980 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 981 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
| 982 | if (tmds) { |
| 983 | if (tmds->i2c_bus) |
| 984 | radeon_i2c_destroy(tmds->i2c_bus); |
| 985 | } |
| 986 | kfree(radeon_encoder->enc_priv); |
| 987 | drm_encoder_cleanup(encoder); |
| 988 | kfree(radeon_encoder); |
| 989 | } |
| 990 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 991 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { |
| 992 | .dpms = radeon_legacy_tmds_ext_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 993 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 994 | .prepare = radeon_legacy_tmds_ext_prepare, |
| 995 | .mode_set = radeon_legacy_tmds_ext_mode_set, |
| 996 | .commit = radeon_legacy_tmds_ext_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 997 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 998 | }; |
| 999 | |
| 1000 | |
| 1001 | static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1002 | .destroy = radeon_ext_tmds_enc_destroy, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1003 | }; |
| 1004 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1005 | static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) |
| 1006 | { |
| 1007 | struct drm_device *dev = encoder->dev; |
| 1008 | struct radeon_device *rdev = dev->dev_private; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1009 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1010 | uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1011 | uint32_t tv_master_cntl = 0; |
| 1012 | bool is_tv; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1013 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1014 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1015 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
| 1016 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1017 | if (rdev->family == CHIP_R200) |
| 1018 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 1019 | else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1020 | if (is_tv) |
| 1021 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
| 1022 | else |
| 1023 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1024 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1025 | } |
| 1026 | |
| 1027 | switch (mode) { |
| 1028 | case DRM_MODE_DPMS_ON: |
| 1029 | if (rdev->family == CHIP_R200) { |
| 1030 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 1031 | } else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1032 | if (is_tv) |
| 1033 | tv_master_cntl |= RADEON_TV_ON; |
| 1034 | else |
| 1035 | crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; |
| 1036 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1037 | if (rdev->family == CHIP_R420 || |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1038 | rdev->family == CHIP_R423 || |
| 1039 | rdev->family == CHIP_RV410) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1040 | tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1041 | R420_TV_DAC_GDACPD | |
| 1042 | R420_TV_DAC_BDACPD | |
| 1043 | RADEON_TV_DAC_BGSLEEP); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1044 | else |
| 1045 | tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1046 | RADEON_TV_DAC_GDACPD | |
| 1047 | RADEON_TV_DAC_BDACPD | |
| 1048 | RADEON_TV_DAC_BGSLEEP); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1049 | } |
| 1050 | break; |
| 1051 | case DRM_MODE_DPMS_STANDBY: |
| 1052 | case DRM_MODE_DPMS_SUSPEND: |
| 1053 | case DRM_MODE_DPMS_OFF: |
| 1054 | if (rdev->family == CHIP_R200) |
| 1055 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 1056 | else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1057 | if (is_tv) |
| 1058 | tv_master_cntl &= ~RADEON_TV_ON; |
| 1059 | else |
| 1060 | crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; |
| 1061 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1062 | if (rdev->family == CHIP_R420 || |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 1063 | rdev->family == CHIP_R423 || |
| 1064 | rdev->family == CHIP_RV410) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1065 | tv_dac_cntl |= (R420_TV_DAC_RDACPD | |
| 1066 | R420_TV_DAC_GDACPD | |
| 1067 | R420_TV_DAC_BDACPD | |
| 1068 | RADEON_TV_DAC_BGSLEEP); |
| 1069 | else |
| 1070 | tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | |
| 1071 | RADEON_TV_DAC_GDACPD | |
| 1072 | RADEON_TV_DAC_BDACPD | |
| 1073 | RADEON_TV_DAC_BGSLEEP); |
| 1074 | } |
| 1075 | break; |
| 1076 | } |
| 1077 | |
| 1078 | if (rdev->family == CHIP_R200) { |
| 1079 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 1080 | } else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1081 | if (is_tv) |
| 1082 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
| 1083 | else |
| 1084 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1085 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1086 | } |
| 1087 | |
| 1088 | if (rdev->is_atom_bios) |
| 1089 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 1090 | else |
| 1091 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1092 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1093 | } |
| 1094 | |
| 1095 | static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) |
| 1096 | { |
| 1097 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 1098 | |
| 1099 | if (rdev->is_atom_bios) |
| 1100 | radeon_atom_output_lock(encoder, true); |
| 1101 | else |
| 1102 | radeon_combios_output_lock(encoder, true); |
| 1103 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 1104 | } |
| 1105 | |
| 1106 | static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) |
| 1107 | { |
| 1108 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 1109 | |
| 1110 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
| 1111 | |
| 1112 | if (rdev->is_atom_bios) |
| 1113 | radeon_atom_output_lock(encoder, true); |
| 1114 | else |
| 1115 | radeon_combios_output_lock(encoder, true); |
| 1116 | } |
| 1117 | |
| 1118 | static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, |
| 1119 | struct drm_display_mode *mode, |
| 1120 | struct drm_display_mode *adjusted_mode) |
| 1121 | { |
| 1122 | struct drm_device *dev = encoder->dev; |
| 1123 | struct radeon_device *rdev = dev->dev_private; |
| 1124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1125 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1126 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1127 | uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1128 | uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; |
| 1129 | bool is_tv = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1130 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1131 | DRM_DEBUG_KMS("\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1132 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1133 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
| 1134 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1135 | if (rdev->family != CHIP_R200) { |
| 1136 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1137 | if (rdev->family == CHIP_R420 || |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 1138 | rdev->family == CHIP_R423 || |
| 1139 | rdev->family == CHIP_RV410) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1140 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 1141 | RADEON_TV_DAC_BGADJ_MASK | |
| 1142 | R420_TV_DAC_DACADJ_MASK | |
| 1143 | R420_TV_DAC_RDACPD | |
| 1144 | R420_TV_DAC_GDACPD | |
| 1145 | R420_TV_DAC_BDACPD | |
| 1146 | R420_TV_DAC_TVENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1147 | } else { |
| 1148 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 1149 | RADEON_TV_DAC_BGADJ_MASK | |
| 1150 | RADEON_TV_DAC_DACADJ_MASK | |
| 1151 | RADEON_TV_DAC_RDACPD | |
| 1152 | RADEON_TV_DAC_GDACPD | |
| 1153 | RADEON_TV_DAC_BDACPD); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1154 | } |
| 1155 | |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 1156 | tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; |
| 1157 | |
| 1158 | if (is_tv) { |
| 1159 | if (tv_dac->tv_std == TV_STD_NTSC || |
| 1160 | tv_dac->tv_std == TV_STD_NTSC_J || |
| 1161 | tv_dac->tv_std == TV_STD_PAL_M || |
| 1162 | tv_dac->tv_std == TV_STD_PAL_60) |
| 1163 | tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; |
| 1164 | else |
| 1165 | tv_dac_cntl |= tv_dac->pal_tvdac_adj; |
| 1166 | |
| 1167 | if (tv_dac->tv_std == TV_STD_NTSC || |
| 1168 | tv_dac->tv_std == TV_STD_NTSC_J) |
| 1169 | tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; |
| 1170 | else |
| 1171 | tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1172 | } else |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 1173 | tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | |
| 1174 | tv_dac->ps2_tvdac_adj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1175 | |
| 1176 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1177 | } |
| 1178 | |
| 1179 | if (ASIC_IS_R300(rdev)) { |
| 1180 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; |
| 1181 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
Dave Airlie | 1ab064d | 2010-06-09 14:03:48 +1000 | [diff] [blame] | 1182 | } else if (rdev->family != CHIP_R200) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1183 | disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
Dave Airlie | 1ab064d | 2010-06-09 14:03:48 +1000 | [diff] [blame] | 1184 | else if (rdev->family == CHIP_R200) |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1185 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1186 | |
Dave Airlie | 1ab064d | 2010-06-09 14:03:48 +1000 | [diff] [blame] | 1187 | if (rdev->family >= CHIP_R200) |
| 1188 | disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); |
| 1189 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1190 | if (is_tv) { |
| 1191 | uint32_t dac_cntl; |
| 1192 | |
| 1193 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
| 1194 | dac_cntl &= ~RADEON_DAC_TVO_EN; |
| 1195 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
| 1196 | |
| 1197 | if (ASIC_IS_R300(rdev)) |
| 1198 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; |
| 1199 | |
| 1200 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; |
| 1201 | if (radeon_crtc->crtc_id == 0) { |
| 1202 | if (ASIC_IS_R300(rdev)) { |
| 1203 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1204 | disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | |
| 1205 | RADEON_DISP_TV_SOURCE_CRTC); |
| 1206 | } |
| 1207 | if (rdev->family >= CHIP_R200) { |
| 1208 | disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; |
| 1209 | } else { |
| 1210 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 1211 | } |
| 1212 | } else { |
| 1213 | if (ASIC_IS_R300(rdev)) { |
| 1214 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1215 | disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; |
| 1216 | } |
| 1217 | if (rdev->family >= CHIP_R200) { |
| 1218 | disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; |
| 1219 | } else { |
| 1220 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
| 1221 | } |
| 1222 | } |
| 1223 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1224 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1225 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1226 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; |
| 1227 | |
| 1228 | if (radeon_crtc->crtc_id == 0) { |
| 1229 | if (ASIC_IS_R300(rdev)) { |
| 1230 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1231 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; |
| 1232 | } else if (rdev->family == CHIP_R200) { |
| 1233 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
| 1234 | RADEON_FP2_DVO_RATE_SEL_SDR); |
| 1235 | } else |
| 1236 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 1237 | } else { |
| 1238 | if (ASIC_IS_R300(rdev)) { |
| 1239 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1240 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
| 1241 | } else if (rdev->family == CHIP_R200) { |
| 1242 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
| 1243 | RADEON_FP2_DVO_RATE_SEL_SDR); |
| 1244 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
| 1245 | } else |
| 1246 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
| 1247 | } |
| 1248 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 1249 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1250 | |
| 1251 | if (ASIC_IS_R300(rdev)) { |
| 1252 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1253 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
Dave Airlie | 1ab064d | 2010-06-09 14:03:48 +1000 | [diff] [blame] | 1254 | } else if (rdev->family != CHIP_R200) |
| 1255 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 1256 | else if (rdev->family == CHIP_R200) |
| 1257 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1258 | |
| 1259 | if (rdev->family >= CHIP_R200) |
| 1260 | WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1261 | |
| 1262 | if (is_tv) |
| 1263 | radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); |
| 1264 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1265 | if (rdev->is_atom_bios) |
| 1266 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 1267 | else |
| 1268 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 1269 | |
| 1270 | } |
| 1271 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1272 | static bool r300_legacy_tv_detect(struct drm_encoder *encoder, |
| 1273 | struct drm_connector *connector) |
| 1274 | { |
| 1275 | struct drm_device *dev = encoder->dev; |
| 1276 | struct radeon_device *rdev = dev->dev_private; |
| 1277 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
| 1278 | uint32_t disp_output_cntl, gpiopad_a, tmp; |
| 1279 | bool found = false; |
| 1280 | |
| 1281 | /* save regs needed */ |
| 1282 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
| 1283 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
| 1284 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 1285 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
| 1286 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1287 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
| 1288 | |
| 1289 | WREG32_P(RADEON_GPIOPAD_A, 0, ~1); |
| 1290 | |
| 1291 | WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); |
| 1292 | |
| 1293 | WREG32(RADEON_CRTC2_GEN_CNTL, |
| 1294 | RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); |
| 1295 | |
| 1296 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1297 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
| 1298 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
| 1299 | |
| 1300 | WREG32(RADEON_DAC_EXT_CNTL, |
| 1301 | RADEON_DAC2_FORCE_BLANK_OFF_EN | |
| 1302 | RADEON_DAC2_FORCE_DATA_EN | |
| 1303 | RADEON_DAC_FORCE_DATA_SEL_RGB | |
| 1304 | (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); |
| 1305 | |
| 1306 | WREG32(RADEON_TV_DAC_CNTL, |
| 1307 | RADEON_TV_DAC_STD_NTSC | |
| 1308 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
| 1309 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
| 1310 | |
| 1311 | RREG32(RADEON_TV_DAC_CNTL); |
| 1312 | mdelay(4); |
| 1313 | |
| 1314 | WREG32(RADEON_TV_DAC_CNTL, |
| 1315 | RADEON_TV_DAC_NBLANK | |
| 1316 | RADEON_TV_DAC_NHOLD | |
| 1317 | RADEON_TV_MONITOR_DETECT_EN | |
| 1318 | RADEON_TV_DAC_STD_NTSC | |
| 1319 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
| 1320 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
| 1321 | |
| 1322 | RREG32(RADEON_TV_DAC_CNTL); |
| 1323 | mdelay(6); |
| 1324 | |
| 1325 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
| 1326 | if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { |
| 1327 | found = true; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1328 | DRM_DEBUG_KMS("S-video TV connection detected\n"); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1329 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
| 1330 | found = true; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1331 | DRM_DEBUG_KMS("Composite TV connection detected\n"); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1332 | } |
| 1333 | |
| 1334 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1335 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
| 1336 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| 1337 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 1338 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
| 1339 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
| 1340 | return found; |
| 1341 | } |
| 1342 | |
| 1343 | static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, |
| 1344 | struct drm_connector *connector) |
| 1345 | { |
| 1346 | struct drm_device *dev = encoder->dev; |
| 1347 | struct radeon_device *rdev = dev->dev_private; |
| 1348 | uint32_t tv_dac_cntl, dac_cntl2; |
| 1349 | uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; |
| 1350 | bool found = false; |
| 1351 | |
| 1352 | if (ASIC_IS_R300(rdev)) |
| 1353 | return r300_legacy_tv_detect(encoder, connector); |
| 1354 | |
| 1355 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
| 1356 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
| 1357 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1358 | config_cntl = RREG32(RADEON_CONFIG_CNTL); |
| 1359 | tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); |
| 1360 | |
| 1361 | tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; |
| 1362 | WREG32(RADEON_DAC_CNTL2, tmp); |
| 1363 | |
| 1364 | tmp = tv_master_cntl | RADEON_TV_ON; |
| 1365 | tmp &= ~(RADEON_TV_ASYNC_RST | |
| 1366 | RADEON_RESTART_PHASE_FIX | |
| 1367 | RADEON_CRT_FIFO_CE_EN | |
| 1368 | RADEON_TV_FIFO_CE_EN | |
| 1369 | RADEON_RE_SYNC_NOW_SEL_MASK); |
| 1370 | tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; |
| 1371 | WREG32(RADEON_TV_MASTER_CNTL, tmp); |
| 1372 | |
| 1373 | tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | |
| 1374 | RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | |
| 1375 | (8 << RADEON_TV_DAC_BGADJ_SHIFT); |
| 1376 | |
| 1377 | if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) |
| 1378 | tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); |
| 1379 | else |
| 1380 | tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); |
| 1381 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
| 1382 | |
| 1383 | tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | |
| 1384 | RADEON_RED_MX_FORCE_DAC_DATA | |
| 1385 | RADEON_GRN_MX_FORCE_DAC_DATA | |
| 1386 | RADEON_BLU_MX_FORCE_DAC_DATA | |
| 1387 | (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); |
| 1388 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); |
| 1389 | |
| 1390 | mdelay(3); |
| 1391 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
| 1392 | if (tmp & RADEON_TV_DAC_GDACDET) { |
| 1393 | found = true; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1394 | DRM_DEBUG_KMS("S-video TV connection detected\n"); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1395 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
| 1396 | found = true; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1397 | DRM_DEBUG_KMS("Composite TV connection detected\n"); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1398 | } |
| 1399 | |
| 1400 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); |
| 1401 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1402 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
| 1403 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
| 1404 | return found; |
| 1405 | } |
| 1406 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1407 | static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, |
| 1408 | struct drm_connector *connector) |
| 1409 | { |
| 1410 | struct drm_device *dev = encoder->dev; |
| 1411 | struct radeon_device *rdev = dev->dev_private; |
| 1412 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
| 1413 | uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; |
| 1414 | enum drm_connector_status found = connector_status_disconnected; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1415 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1416 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1417 | bool color = true; |
Dave Airlie | b62e948 | 2010-06-08 10:42:28 +1000 | [diff] [blame] | 1418 | struct drm_crtc *crtc; |
| 1419 | |
| 1420 | /* find out if crtc2 is in use or if this encoder is using it */ |
| 1421 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 1422 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1423 | if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { |
| 1424 | if (encoder->crtc != crtc) { |
| 1425 | return connector_status_disconnected; |
| 1426 | } |
| 1427 | } |
| 1428 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1429 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1430 | if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || |
| 1431 | connector->connector_type == DRM_MODE_CONNECTOR_Composite || |
| 1432 | connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { |
| 1433 | bool tv_detect; |
| 1434 | |
| 1435 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) |
| 1436 | return connector_status_disconnected; |
| 1437 | |
| 1438 | tv_detect = radeon_legacy_tv_detect(encoder, connector); |
| 1439 | if (tv_detect && tv_dac) |
| 1440 | found = connector_status_connected; |
| 1441 | return found; |
| 1442 | } |
| 1443 | |
| 1444 | /* don't probe if the encoder is being used for something else not CRT related */ |
| 1445 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { |
| 1446 | DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); |
| 1447 | return connector_status_disconnected; |
| 1448 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1449 | |
| 1450 | /* save the regs we need */ |
| 1451 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 1452 | gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0; |
| 1453 | disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0; |
| 1454 | disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG); |
| 1455 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 1456 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1457 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
| 1458 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
| 1459 | |
| 1460 | tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb |
| 1461 | | RADEON_PIX2CLK_DAC_ALWAYS_ONb); |
| 1462 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 1463 | |
| 1464 | if (ASIC_IS_R300(rdev)) |
| 1465 | WREG32_P(RADEON_GPIOPAD_A, 1, ~1); |
| 1466 | |
| 1467 | tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; |
| 1468 | tmp |= RADEON_CRTC2_CRT2_ON | |
| 1469 | (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); |
| 1470 | |
| 1471 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
| 1472 | |
| 1473 | if (ASIC_IS_R300(rdev)) { |
| 1474 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1475 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
| 1476 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
| 1477 | } else { |
| 1478 | tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; |
| 1479 | WREG32(RADEON_DISP_HW_DEBUG, tmp); |
| 1480 | } |
| 1481 | |
| 1482 | tmp = RADEON_TV_DAC_NBLANK | |
| 1483 | RADEON_TV_DAC_NHOLD | |
| 1484 | RADEON_TV_MONITOR_DETECT_EN | |
| 1485 | RADEON_TV_DAC_STD_PS2; |
| 1486 | |
| 1487 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
| 1488 | |
| 1489 | tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | |
| 1490 | RADEON_DAC2_FORCE_DATA_EN; |
| 1491 | |
| 1492 | if (color) |
| 1493 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
| 1494 | else |
| 1495 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
| 1496 | |
| 1497 | if (ASIC_IS_R300(rdev)) |
| 1498 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 1499 | else |
| 1500 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 1501 | |
| 1502 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
| 1503 | |
| 1504 | tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; |
| 1505 | WREG32(RADEON_DAC_CNTL2, tmp); |
| 1506 | |
Arnd Bergmann | 4de833c | 2012-04-05 12:58:22 -0600 | [diff] [blame] | 1507 | mdelay(10); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1508 | |
| 1509 | if (ASIC_IS_R300(rdev)) { |
| 1510 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) |
| 1511 | found = connector_status_connected; |
| 1512 | } else { |
| 1513 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) |
| 1514 | found = connector_status_connected; |
| 1515 | } |
| 1516 | |
| 1517 | /* restore regs we used */ |
| 1518 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
| 1519 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
| 1520 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1521 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| 1522 | |
| 1523 | if (ASIC_IS_R300(rdev)) { |
| 1524 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 1525 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
| 1526 | } else { |
| 1527 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 1528 | } |
| 1529 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
| 1530 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1531 | return found; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1532 | |
| 1533 | } |
| 1534 | |
| 1535 | static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { |
| 1536 | .dpms = radeon_legacy_tv_dac_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 1537 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1538 | .prepare = radeon_legacy_tv_dac_prepare, |
| 1539 | .mode_set = radeon_legacy_tv_dac_mode_set, |
| 1540 | .commit = radeon_legacy_tv_dac_commit, |
| 1541 | .detect = radeon_legacy_tv_dac_detect, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1542 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1543 | }; |
| 1544 | |
| 1545 | |
| 1546 | static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { |
| 1547 | .destroy = radeon_enc_destroy, |
| 1548 | }; |
| 1549 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1550 | |
| 1551 | static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) |
| 1552 | { |
| 1553 | struct drm_device *dev = encoder->base.dev; |
| 1554 | struct radeon_device *rdev = dev->dev_private; |
| 1555 | struct radeon_encoder_int_tmds *tmds = NULL; |
| 1556 | bool ret; |
| 1557 | |
| 1558 | tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
| 1559 | |
| 1560 | if (!tmds) |
| 1561 | return NULL; |
| 1562 | |
| 1563 | if (rdev->is_atom_bios) |
| 1564 | ret = radeon_atombios_get_tmds_info(encoder, tmds); |
| 1565 | else |
| 1566 | ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); |
| 1567 | |
| 1568 | if (ret == false) |
| 1569 | radeon_legacy_get_tmds_info_from_table(encoder, tmds); |
| 1570 | |
| 1571 | return tmds; |
| 1572 | } |
| 1573 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1574 | static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) |
| 1575 | { |
| 1576 | struct drm_device *dev = encoder->base.dev; |
| 1577 | struct radeon_device *rdev = dev->dev_private; |
| 1578 | struct radeon_encoder_ext_tmds *tmds = NULL; |
| 1579 | bool ret; |
| 1580 | |
| 1581 | if (rdev->is_atom_bios) |
| 1582 | return NULL; |
| 1583 | |
| 1584 | tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); |
| 1585 | |
| 1586 | if (!tmds) |
| 1587 | return NULL; |
| 1588 | |
| 1589 | ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); |
| 1590 | |
| 1591 | if (ret == false) |
| 1592 | radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); |
| 1593 | |
| 1594 | return tmds; |
| 1595 | } |
| 1596 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1597 | void |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1598 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1599 | { |
| 1600 | struct radeon_device *rdev = dev->dev_private; |
| 1601 | struct drm_encoder *encoder; |
| 1602 | struct radeon_encoder *radeon_encoder; |
| 1603 | |
| 1604 | /* see if we already added it */ |
| 1605 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1606 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1607 | if (radeon_encoder->encoder_enum == encoder_enum) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1608 | radeon_encoder->devices |= supported_device; |
| 1609 | return; |
| 1610 | } |
| 1611 | |
| 1612 | } |
| 1613 | |
| 1614 | /* add a new one */ |
| 1615 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
| 1616 | if (!radeon_encoder) |
| 1617 | return; |
| 1618 | |
| 1619 | encoder = &radeon_encoder->base; |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 1620 | if (rdev->flags & RADEON_SINGLE_CRTC) |
| 1621 | encoder->possible_crtcs = 0x1; |
| 1622 | else |
| 1623 | encoder->possible_crtcs = 0x3; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1624 | |
| 1625 | radeon_encoder->enc_priv = NULL; |
| 1626 | |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1627 | radeon_encoder->encoder_enum = encoder_enum; |
| 1628 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1629 | radeon_encoder->devices = supported_device; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1630 | radeon_encoder->rmx_type = RMX_OFF; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1631 | |
| 1632 | switch (radeon_encoder->encoder_id) { |
| 1633 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
Dave Airlie | 80e6914 | 2009-08-17 10:22:37 +1000 | [diff] [blame] | 1634 | encoder->possible_crtcs = 0x1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1635 | drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 1636 | drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); |
| 1637 | if (rdev->is_atom_bios) |
| 1638 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
| 1639 | else |
| 1640 | radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); |
| 1641 | radeon_encoder->rmx_type = RMX_FULL; |
| 1642 | break; |
| 1643 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1644 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1645 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1646 | radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1647 | break; |
| 1648 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1649 | drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); |
| 1650 | drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1651 | if (rdev->is_atom_bios) |
| 1652 | radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); |
| 1653 | else |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1654 | radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); |
| 1655 | break; |
| 1656 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1657 | drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
| 1658 | drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1659 | if (rdev->is_atom_bios) |
| 1660 | radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); |
| 1661 | else |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1662 | radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); |
| 1663 | break; |
| 1664 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1665 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1666 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); |
| 1667 | if (!rdev->is_atom_bios) |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1668 | radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1669 | break; |
| 1670 | } |
| 1671 | } |