Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2005 Stephane Marchesin |
| 3 | * Copyright 2008 Stuart Bennett |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include <linux/swab.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 27 | #include <linux/slab.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "drm_sarea.h" |
| 31 | #include "drm_crtc_helper.h" |
| 32 | #include <linux/vgaarb.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 33 | #include <linux/vga_switcheroo.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 34 | |
| 35 | #include "nouveau_drv.h" |
Ben Skeggs | 9458029 | 2012-07-06 12:14:00 +1000 | [diff] [blame] | 36 | #include <nouveau_drm.h> |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 37 | #include "nouveau_fbcon.h" |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame] | 38 | #include <core/ramht.h> |
Ben Skeggs | 330c598 | 2010-09-16 15:39:49 +1000 | [diff] [blame] | 39 | #include "nouveau_pm.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 40 | #include "nv50_display.h" |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame] | 41 | #include <engine/fifo.h> |
Ben Skeggs | 5e120f6 | 2012-04-30 13:55:29 +1000 | [diff] [blame] | 42 | #include "nouveau_fence.h" |
Ben Skeggs | 20abd16 | 2012-04-30 11:33:43 -0500 | [diff] [blame] | 43 | #include "nouveau_software.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 44 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 45 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
Ben Skeggs | ee2e013 | 2010-07-26 09:28:25 +1000 | [diff] [blame] | 46 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 47 | |
| 48 | static int nouveau_init_engine_ptrs(struct drm_device *dev) |
| 49 | { |
| 50 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 51 | struct nouveau_engine *engine = &dev_priv->engine; |
| 52 | |
| 53 | switch (dev_priv->chipset & 0xf0) { |
| 54 | case 0x00: |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 55 | engine->display.early_init = nv04_display_early_init; |
| 56 | engine->display.late_takedown = nv04_display_late_takedown; |
| 57 | engine->display.create = nv04_display_create; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 58 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 59 | engine->display.init = nv04_display_init; |
| 60 | engine->display.fini = nv04_display_fini; |
Ben Skeggs | 36f1317 | 2011-10-27 10:24:12 +1000 | [diff] [blame] | 61 | engine->pm.clocks_get = nv04_pm_clocks_get; |
| 62 | engine->pm.clocks_pre = nv04_pm_clocks_pre; |
| 63 | engine->pm.clocks_set = nv04_pm_clocks_set; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 64 | break; |
| 65 | case 0x10: |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 66 | engine->display.early_init = nv04_display_early_init; |
| 67 | engine->display.late_takedown = nv04_display_late_takedown; |
| 68 | engine->display.create = nv04_display_create; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 69 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 70 | engine->display.init = nv04_display_init; |
| 71 | engine->display.fini = nv04_display_fini; |
Ben Skeggs | 36f1317 | 2011-10-27 10:24:12 +1000 | [diff] [blame] | 72 | engine->pm.clocks_get = nv04_pm_clocks_get; |
| 73 | engine->pm.clocks_pre = nv04_pm_clocks_pre; |
| 74 | engine->pm.clocks_set = nv04_pm_clocks_set; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 75 | break; |
| 76 | case 0x20: |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 77 | engine->display.early_init = nv04_display_early_init; |
| 78 | engine->display.late_takedown = nv04_display_late_takedown; |
| 79 | engine->display.create = nv04_display_create; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 80 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 81 | engine->display.init = nv04_display_init; |
| 82 | engine->display.fini = nv04_display_fini; |
Ben Skeggs | 36f1317 | 2011-10-27 10:24:12 +1000 | [diff] [blame] | 83 | engine->pm.clocks_get = nv04_pm_clocks_get; |
| 84 | engine->pm.clocks_pre = nv04_pm_clocks_pre; |
| 85 | engine->pm.clocks_set = nv04_pm_clocks_set; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 86 | break; |
| 87 | case 0x30: |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 88 | engine->display.early_init = nv04_display_early_init; |
| 89 | engine->display.late_takedown = nv04_display_late_takedown; |
| 90 | engine->display.create = nv04_display_create; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 91 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 92 | engine->display.init = nv04_display_init; |
| 93 | engine->display.fini = nv04_display_fini; |
Ben Skeggs | 36f1317 | 2011-10-27 10:24:12 +1000 | [diff] [blame] | 94 | engine->pm.clocks_get = nv04_pm_clocks_get; |
| 95 | engine->pm.clocks_pre = nv04_pm_clocks_pre; |
| 96 | engine->pm.clocks_set = nv04_pm_clocks_set; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 97 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 98 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 99 | break; |
| 100 | case 0x40: |
| 101 | case 0x60: |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 102 | engine->display.early_init = nv04_display_early_init; |
| 103 | engine->display.late_takedown = nv04_display_late_takedown; |
| 104 | engine->display.create = nv04_display_create; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 105 | engine->display.destroy = nv04_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 106 | engine->display.init = nv04_display_init; |
| 107 | engine->display.fini = nv04_display_fini; |
Ben Skeggs | 1262a20 | 2011-07-18 15:15:34 +1000 | [diff] [blame] | 108 | engine->pm.clocks_get = nv40_pm_clocks_get; |
| 109 | engine->pm.clocks_pre = nv40_pm_clocks_pre; |
| 110 | engine->pm.clocks_set = nv40_pm_clocks_set; |
Ben Skeggs | 442b626 | 2010-09-16 16:25:26 +1000 | [diff] [blame] | 111 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 112 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Francisco Jerez | 8155cac | 2010-09-23 20:58:38 +0200 | [diff] [blame] | 113 | engine->pm.temp_get = nv40_temp_get; |
Ben Skeggs | 6934618 | 2011-09-17 02:11:39 +1000 | [diff] [blame] | 114 | engine->pm.pwm_get = nv40_pm_pwm_get; |
| 115 | engine->pm.pwm_set = nv40_pm_pwm_set; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 116 | break; |
| 117 | case 0x50: |
| 118 | case 0x80: /* gotta love NVIDIA's consistency.. */ |
| 119 | case 0x90: |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 120 | case 0xa0: |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 121 | engine->display.early_init = nv50_display_early_init; |
| 122 | engine->display.late_takedown = nv50_display_late_takedown; |
| 123 | engine->display.create = nv50_display_create; |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 124 | engine->display.destroy = nv50_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 125 | engine->display.init = nv50_display_init; |
| 126 | engine->display.fini = nv50_display_fini; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 127 | switch (dev_priv->chipset) { |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 128 | case 0x84: |
| 129 | case 0x86: |
| 130 | case 0x92: |
| 131 | case 0x94: |
| 132 | case 0x96: |
| 133 | case 0x98: |
| 134 | case 0xa0: |
Ben Skeggs | 5f80198 | 2010-10-22 08:44:09 +1000 | [diff] [blame] | 135 | case 0xaa: |
| 136 | case 0xac: |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 137 | case 0x50: |
Ben Skeggs | f3fbaf3 | 2011-10-26 09:11:02 +1000 | [diff] [blame] | 138 | engine->pm.clocks_get = nv50_pm_clocks_get; |
| 139 | engine->pm.clocks_pre = nv50_pm_clocks_pre; |
| 140 | engine->pm.clocks_set = nv50_pm_clocks_set; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 141 | break; |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 142 | default: |
Ben Skeggs | ca94a71 | 2011-06-17 15:38:48 +1000 | [diff] [blame] | 143 | engine->pm.clocks_get = nva3_pm_clocks_get; |
| 144 | engine->pm.clocks_pre = nva3_pm_clocks_pre; |
| 145 | engine->pm.clocks_set = nva3_pm_clocks_set; |
Ben Skeggs | bd2e597 | 2010-10-19 20:06:01 +1000 | [diff] [blame] | 146 | break; |
Ben Skeggs | fade7ad | 2010-09-27 11:18:14 +1000 | [diff] [blame] | 147 | } |
Ben Skeggs | 02c30ca | 2010-09-16 16:17:35 +1000 | [diff] [blame] | 148 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 149 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Francisco Jerez | 8155cac | 2010-09-23 20:58:38 +0200 | [diff] [blame] | 150 | if (dev_priv->chipset >= 0x84) |
| 151 | engine->pm.temp_get = nv84_temp_get; |
| 152 | else |
| 153 | engine->pm.temp_get = nv40_temp_get; |
Ben Skeggs | 5a4267a | 2011-09-17 02:01:24 +1000 | [diff] [blame] | 154 | engine->pm.pwm_get = nv50_pm_pwm_get; |
| 155 | engine->pm.pwm_set = nv50_pm_pwm_set; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 156 | break; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 157 | case 0xc0: |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 158 | engine->display.early_init = nv50_display_early_init; |
| 159 | engine->display.late_takedown = nv50_display_late_takedown; |
| 160 | engine->display.create = nv50_display_create; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 161 | engine->display.destroy = nv50_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 162 | engine->display.init = nv50_display_init; |
| 163 | engine->display.fini = nv50_display_fini; |
Martin Peres | 74cfad1 | 2011-05-12 22:40:47 +0200 | [diff] [blame] | 164 | engine->pm.temp_get = nv84_temp_get; |
Ben Skeggs | 354d078 | 2011-06-19 01:44:36 +1000 | [diff] [blame] | 165 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
Ben Skeggs | 045da4e | 2011-10-29 00:22:49 +1000 | [diff] [blame] | 166 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
| 167 | engine->pm.clocks_set = nvc0_pm_clocks_set; |
Ben Skeggs | 3c71c23 | 2011-06-09 17:34:02 +1000 | [diff] [blame] | 168 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
Ben Skeggs | da1dc4c | 2011-06-10 12:07:09 +1000 | [diff] [blame] | 169 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Ben Skeggs | 5a4267a | 2011-09-17 02:01:24 +1000 | [diff] [blame] | 170 | engine->pm.pwm_get = nv50_pm_pwm_get; |
| 171 | engine->pm.pwm_set = nv50_pm_pwm_set; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 172 | break; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 173 | case 0xd0: |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 174 | engine->display.early_init = nouveau_stub_init; |
| 175 | engine->display.late_takedown = nouveau_stub_takedown; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 176 | engine->display.create = nvd0_display_create; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 177 | engine->display.destroy = nvd0_display_destroy; |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 178 | engine->display.init = nvd0_display_init; |
| 179 | engine->display.fini = nvd0_display_fini; |
Martin Peres | 6109183 | 2011-10-22 01:40:40 +0200 | [diff] [blame] | 180 | engine->pm.temp_get = nv84_temp_get; |
Ben Skeggs | 4784e4a | 2011-07-04 14:06:07 +1000 | [diff] [blame] | 181 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
Ben Skeggs | 045da4e | 2011-10-29 00:22:49 +1000 | [diff] [blame] | 182 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
| 183 | engine->pm.clocks_set = nvc0_pm_clocks_set; |
Ben Skeggs | 4784e4a | 2011-07-04 14:06:07 +1000 | [diff] [blame] | 184 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
| 185 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
Ben Skeggs | d9f61c2 | 2011-07-04 13:25:17 +1000 | [diff] [blame] | 186 | break; |
Ben Skeggs | 68455a4 | 2012-03-04 14:47:55 +1000 | [diff] [blame] | 187 | case 0xe0: |
Ben Skeggs | 68455a4 | 2012-03-04 14:47:55 +1000 | [diff] [blame] | 188 | engine->display.early_init = nouveau_stub_init; |
| 189 | engine->display.late_takedown = nouveau_stub_takedown; |
| 190 | engine->display.create = nvd0_display_create; |
| 191 | engine->display.destroy = nvd0_display_destroy; |
| 192 | engine->display.init = nvd0_display_init; |
| 193 | engine->display.fini = nvd0_display_fini; |
Ben Skeggs | 68455a4 | 2012-03-04 14:47:55 +1000 | [diff] [blame] | 194 | break; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 195 | default: |
| 196 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); |
| 197 | return 1; |
| 198 | } |
| 199 | |
Ben Skeggs | 03bc967 | 2011-07-04 13:14:05 +1000 | [diff] [blame] | 200 | /* headless mode */ |
| 201 | if (nouveau_modeset == 2) { |
| 202 | engine->display.early_init = nouveau_stub_init; |
| 203 | engine->display.late_takedown = nouveau_stub_takedown; |
| 204 | engine->display.create = nouveau_stub_init; |
| 205 | engine->display.init = nouveau_stub_init; |
| 206 | engine->display.destroy = nouveau_stub_takedown; |
| 207 | } |
| 208 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static unsigned int |
| 213 | nouveau_vga_set_decode(void *priv, bool state) |
| 214 | { |
Marcin Kościelnicki | 9967b94 | 2010-02-08 00:20:17 +0000 | [diff] [blame] | 215 | struct drm_device *dev = priv; |
| 216 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 217 | |
| 218 | if (dev_priv->chipset >= 0x40) |
| 219 | nv_wr32(dev, 0x88054, state); |
| 220 | else |
| 221 | nv_wr32(dev, 0x1854, state); |
| 222 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 223 | if (state) |
| 224 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 225 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 226 | else |
| 227 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 228 | } |
| 229 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 230 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
| 231 | enum vga_switcheroo_state state) |
| 232 | { |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 233 | struct drm_device *dev = pci_get_drvdata(pdev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 234 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 235 | if (state == VGA_SWITCHEROO_ON) { |
| 236 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 237 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 238 | nouveau_pci_resume(pdev); |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 239 | drm_kms_helper_poll_enable(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 240 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 241 | } else { |
| 242 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 243 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 244 | drm_kms_helper_poll_disable(dev); |
Peter Lekensteyn | d099230 | 2011-12-17 12:54:04 +0100 | [diff] [blame] | 245 | nouveau_switcheroo_optimus_dsm(); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 246 | nouveau_pci_suspend(pdev, pmm); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 247 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 248 | } |
| 249 | } |
| 250 | |
Dave Airlie | 8d608aa | 2010-12-07 08:57:57 +1000 | [diff] [blame] | 251 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
| 252 | { |
| 253 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 254 | nouveau_fbcon_output_poll_changed(dev); |
| 255 | } |
| 256 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 257 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
| 258 | { |
| 259 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 260 | bool can_switch; |
| 261 | |
| 262 | spin_lock(&dev->count_lock); |
| 263 | can_switch = (dev->open_count == 0); |
| 264 | spin_unlock(&dev->count_lock); |
| 265 | return can_switch; |
| 266 | } |
| 267 | |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 268 | static void |
| 269 | nouveau_card_channel_fini(struct drm_device *dev) |
| 270 | { |
| 271 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 272 | |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 273 | if (dev_priv->channel) { |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 274 | nouveau_channel_put_unlocked(&dev_priv->channel); |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 275 | nouveau_vm_ref(NULL, &dev_priv->chan_vm, NULL); |
| 276 | } |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | static int |
| 280 | nouveau_card_channel_init(struct drm_device *dev) |
| 281 | { |
| 282 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 283 | struct nouveau_channel *chan; |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 284 | int ret; |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 285 | |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 286 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x1000, &dev_priv->chan_vm); |
| 287 | if (ret) |
| 288 | return ret; |
| 289 | |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 290 | ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT); |
| 291 | dev_priv->channel = chan; |
| 292 | if (ret) |
| 293 | return ret; |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 294 | mutex_unlock(&dev_priv->channel->mutex); |
| 295 | |
Ben Skeggs | d1b167e | 2012-05-04 14:01:52 +1000 | [diff] [blame] | 296 | nouveau_bo_move_init(chan); |
| 297 | return 0; |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 298 | } |
| 299 | |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 300 | static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = { |
| 301 | .set_gpu_state = nouveau_switcheroo_set_state, |
| 302 | .reprobe = nouveau_switcheroo_reprobe, |
| 303 | .can_switch = nouveau_switcheroo_can_switch, |
| 304 | }; |
| 305 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 306 | int |
| 307 | nouveau_card_init(struct drm_device *dev) |
| 308 | { |
| 309 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 310 | struct nouveau_engine *engine; |
Ben Skeggs | eea55c8 | 2011-04-18 08:57:51 +1000 | [diff] [blame] | 311 | int ret, e = 0; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 312 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 313 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 314 | vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 315 | |
| 316 | /* Initialise internal driver API hooks */ |
| 317 | ret = nouveau_init_engine_ptrs(dev); |
| 318 | if (ret) |
Marcin Kościelnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 319 | goto out; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 320 | engine = &dev_priv->engine; |
Ben Skeggs | cff5c13 | 2010-10-06 16:16:59 +1000 | [diff] [blame] | 321 | spin_lock_init(&dev_priv->channels.lock); |
Francisco Jerez | a5cf68b | 2010-10-24 16:14:41 +0200 | [diff] [blame] | 322 | spin_lock_init(&dev_priv->tile.lock); |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 323 | spin_lock_init(&dev_priv->context_switch_lock); |
Ben Skeggs | 04eb34a | 2011-04-06 13:28:35 +1000 | [diff] [blame] | 324 | spin_lock_init(&dev_priv->vm_lock); |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 325 | INIT_LIST_HEAD(&dev_priv->classes); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 326 | |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 327 | /* Make the CRTCs and I2C buses accessible */ |
| 328 | ret = engine->display.early_init(dev); |
| 329 | if (ret) |
| 330 | goto out; |
| 331 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 332 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 333 | ret = nouveau_bios_init(dev); |
| 334 | if (ret) |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 335 | goto out_display_early; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 336 | |
Ben Skeggs | 4c5df49 | 2011-10-28 10:59:45 +1000 | [diff] [blame] | 337 | /* workaround an odd issue on nvc1 by disabling the device's |
| 338 | * nosnoop capability. hopefully won't cause issues until a |
| 339 | * better fix is found - assuming there is one... |
| 340 | */ |
| 341 | if (dev_priv->chipset == 0xc1) { |
| 342 | nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); |
| 343 | } |
| 344 | |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 345 | ret = nouveau_mem_vram_init(dev); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 346 | if (ret) |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 347 | goto out_bios; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 348 | |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 349 | ret = nouveau_mem_gart_init(dev); |
| 350 | if (ret) |
| 351 | goto out_ttmvram; |
| 352 | |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 353 | if (!dev_priv->noaccel) { |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 354 | switch (dev_priv->card_type) { |
| 355 | case NV_04: |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 356 | nv04_fifo_create(dev); |
| 357 | break; |
| 358 | case NV_10: |
| 359 | case NV_20: |
| 360 | case NV_30: |
| 361 | if (dev_priv->chipset < 0x17) |
| 362 | nv10_fifo_create(dev); |
| 363 | else |
| 364 | nv17_fifo_create(dev); |
| 365 | break; |
| 366 | case NV_40: |
| 367 | nv40_fifo_create(dev); |
| 368 | break; |
| 369 | case NV_50: |
| 370 | if (dev_priv->chipset == 0x50) |
| 371 | nv50_fifo_create(dev); |
| 372 | else |
| 373 | nv84_fifo_create(dev); |
| 374 | break; |
| 375 | case NV_C0: |
| 376 | case NV_D0: |
| 377 | nvc0_fifo_create(dev); |
| 378 | break; |
| 379 | case NV_E0: |
| 380 | nve0_fifo_create(dev); |
| 381 | break; |
| 382 | default: |
| 383 | break; |
| 384 | } |
| 385 | |
| 386 | switch (dev_priv->card_type) { |
| 387 | case NV_04: |
Ben Skeggs | 5e120f6 | 2012-04-30 13:55:29 +1000 | [diff] [blame] | 388 | nv04_fence_create(dev); |
| 389 | break; |
| 390 | case NV_10: |
| 391 | case NV_20: |
| 392 | case NV_30: |
| 393 | case NV_40: |
| 394 | case NV_50: |
| 395 | if (dev_priv->chipset < 0x84) |
| 396 | nv10_fence_create(dev); |
| 397 | else |
| 398 | nv84_fence_create(dev); |
| 399 | break; |
| 400 | case NV_C0: |
| 401 | case NV_D0: |
| 402 | case NV_E0: |
| 403 | nvc0_fence_create(dev); |
| 404 | break; |
| 405 | default: |
| 406 | break; |
| 407 | } |
| 408 | |
| 409 | switch (dev_priv->card_type) { |
| 410 | case NV_04: |
Ben Skeggs | 20abd16 | 2012-04-30 11:33:43 -0500 | [diff] [blame] | 411 | case NV_10: |
| 412 | case NV_20: |
| 413 | case NV_30: |
| 414 | case NV_40: |
| 415 | nv04_software_create(dev); |
| 416 | break; |
| 417 | case NV_50: |
| 418 | nv50_software_create(dev); |
| 419 | break; |
| 420 | case NV_C0: |
| 421 | case NV_D0: |
| 422 | case NV_E0: |
| 423 | nvc0_software_create(dev); |
| 424 | break; |
| 425 | default: |
| 426 | break; |
| 427 | } |
| 428 | |
| 429 | switch (dev_priv->card_type) { |
| 430 | case NV_04: |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 431 | nv04_graph_create(dev); |
| 432 | break; |
| 433 | case NV_10: |
| 434 | nv10_graph_create(dev); |
| 435 | break; |
| 436 | case NV_20: |
| 437 | case NV_30: |
| 438 | nv20_graph_create(dev); |
| 439 | break; |
| 440 | case NV_40: |
| 441 | nv40_graph_create(dev); |
| 442 | break; |
| 443 | case NV_50: |
| 444 | nv50_graph_create(dev); |
| 445 | break; |
| 446 | case NV_C0: |
Ben Skeggs | 0678409 | 2011-07-11 15:57:54 +1000 | [diff] [blame] | 447 | case NV_D0: |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 448 | nvc0_graph_create(dev); |
| 449 | break; |
Ben Skeggs | ab39454 | 2012-03-13 13:05:13 +1000 | [diff] [blame] | 450 | case NV_E0: |
| 451 | nve0_graph_create(dev); |
| 452 | break; |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 453 | default: |
Ben Skeggs | 7ff5441 | 2011-03-18 10:25:59 +1000 | [diff] [blame] | 454 | break; |
| 455 | } |
Ben Skeggs | 7ff5441 | 2011-03-18 10:25:59 +1000 | [diff] [blame] | 456 | |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 457 | switch (dev_priv->chipset) { |
| 458 | case 0x84: |
| 459 | case 0x86: |
| 460 | case 0x92: |
| 461 | case 0x94: |
| 462 | case 0x96: |
| 463 | case 0xa0: |
| 464 | nv84_crypt_create(dev); |
| 465 | break; |
Ben Skeggs | 8f27c54 | 2011-08-11 14:58:06 +1000 | [diff] [blame] | 466 | case 0x98: |
| 467 | case 0xaa: |
| 468 | case 0xac: |
| 469 | nv98_crypt_create(dev); |
| 470 | break; |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 471 | } |
Ben Skeggs | a02ccc7 | 2011-04-04 16:08:24 +1000 | [diff] [blame] | 472 | |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 473 | switch (dev_priv->card_type) { |
| 474 | case NV_50: |
| 475 | switch (dev_priv->chipset) { |
| 476 | case 0xa3: |
| 477 | case 0xa5: |
| 478 | case 0xa8: |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 479 | nva3_copy_create(dev); |
| 480 | break; |
| 481 | } |
| 482 | break; |
| 483 | case NV_C0: |
Ben Skeggs | 14f0458 | 2012-08-27 16:22:49 +1000 | [diff] [blame] | 484 | if (!(nv_rd32(dev, 0x022500) & 0x00000200)) |
| 485 | nvc0_copy_create(dev, 1); |
Ben Skeggs | 0c75f33 | 2012-05-04 17:16:46 +1000 | [diff] [blame] | 486 | case NV_D0: |
Ben Skeggs | 14f0458 | 2012-08-27 16:22:49 +1000 | [diff] [blame] | 487 | if (!(nv_rd32(dev, 0x022500) & 0x00000100)) |
| 488 | nvc0_copy_create(dev, 0); |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 489 | break; |
| 490 | default: |
| 491 | break; |
| 492 | } |
| 493 | |
Ben Skeggs | 8f27c54 | 2011-08-11 14:58:06 +1000 | [diff] [blame] | 494 | if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) { |
| 495 | nv84_bsp_create(dev); |
| 496 | nv84_vp_create(dev); |
| 497 | nv98_ppp_create(dev); |
| 498 | } else |
| 499 | if (dev_priv->chipset >= 0x84) { |
| 500 | nv50_mpeg_create(dev); |
| 501 | nv84_bsp_create(dev); |
| 502 | nv84_vp_create(dev); |
| 503 | } else |
| 504 | if (dev_priv->chipset >= 0x50) { |
| 505 | nv50_mpeg_create(dev); |
| 506 | } else |
Ben Skeggs | 52d0733 | 2011-06-23 16:44:05 +1000 | [diff] [blame] | 507 | if (dev_priv->card_type == NV_40 || |
| 508 | dev_priv->chipset == 0x31 || |
| 509 | dev_priv->chipset == 0x34 || |
Ben Skeggs | 8f27c54 | 2011-08-11 14:58:06 +1000 | [diff] [blame] | 510 | dev_priv->chipset == 0x36) { |
Ben Skeggs | 323dcac | 2011-06-23 16:21:21 +1000 | [diff] [blame] | 511 | nv31_mpeg_create(dev); |
Ben Skeggs | 8f27c54 | 2011-08-11 14:58:06 +1000 | [diff] [blame] | 512 | } |
Ben Skeggs | 18b54c4 | 2011-05-25 15:22:33 +1000 | [diff] [blame] | 513 | |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 514 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { |
| 515 | if (dev_priv->eng[e]) { |
| 516 | ret = dev_priv->eng[e]->init(dev, e); |
| 517 | if (ret) |
| 518 | goto out_engine; |
| 519 | } |
| 520 | } |
Marcin Kościelnicki | a32ed69 | 2010-01-26 14:00:42 +0000 | [diff] [blame] | 521 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 522 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 523 | ret = nouveau_irq_init(dev); |
| 524 | if (ret) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 525 | goto out_engine; |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 526 | |
Ben Skeggs | 27d5030 | 2011-10-06 12:46:40 +1000 | [diff] [blame] | 527 | ret = nouveau_display_create(dev); |
Ben Skeggs | e88efe0 | 2010-07-09 10:56:08 +1000 | [diff] [blame] | 528 | if (ret) |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 529 | goto out_irq; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 530 | |
Ben Skeggs | 10b461e | 2011-08-02 19:29:37 +1000 | [diff] [blame] | 531 | nouveau_backlight_init(dev); |
Ben Skeggs | 7d3a766 | 2012-02-01 15:17:07 +1000 | [diff] [blame] | 532 | nouveau_pm_init(dev); |
Ben Skeggs | 10b461e | 2011-08-02 19:29:37 +1000 | [diff] [blame] | 533 | |
Ben Skeggs | c61205b | 2012-03-23 09:10:22 +1000 | [diff] [blame] | 534 | if (dev_priv->eng[NVOBJ_ENGINE_GR]) { |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 535 | ret = nouveau_card_channel_init(dev); |
Francisco Jerez | 0c6c1c2 | 2010-09-22 00:58:54 +0200 | [diff] [blame] | 536 | if (ret) |
Ben Skeggs | 5e120f6 | 2012-04-30 13:55:29 +1000 | [diff] [blame] | 537 | goto out_pm; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 538 | } |
| 539 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 540 | if (dev->mode_config.num_crtc) { |
Ben Skeggs | f62b27d | 2011-11-09 15:18:47 +1000 | [diff] [blame] | 541 | ret = nouveau_display_init(dev); |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 542 | if (ret) |
| 543 | goto out_chan; |
| 544 | |
| 545 | nouveau_fbcon_init(dev); |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 546 | } |
| 547 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 548 | return 0; |
Marcin Kościelnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 549 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 550 | out_chan: |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 551 | nouveau_card_channel_fini(dev); |
Ben Skeggs | 7d3a766 | 2012-02-01 15:17:07 +1000 | [diff] [blame] | 552 | out_pm: |
| 553 | nouveau_pm_fini(dev); |
Ben Skeggs | 10b461e | 2011-08-02 19:29:37 +1000 | [diff] [blame] | 554 | nouveau_backlight_exit(dev); |
Ben Skeggs | 27d5030 | 2011-10-06 12:46:40 +1000 | [diff] [blame] | 555 | nouveau_display_destroy(dev); |
Marcin Kościelnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 556 | out_irq: |
Ben Skeggs | 35fa2f2 | 2010-10-21 14:07:03 +1000 | [diff] [blame] | 557 | nouveau_irq_fini(dev); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 558 | out_engine: |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 559 | if (!dev_priv->noaccel) { |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 560 | for (e = e - 1; e >= 0; e--) { |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 561 | if (!dev_priv->eng[e]) |
| 562 | continue; |
Ben Skeggs | 6c320fe | 2011-07-20 11:22:33 +1000 | [diff] [blame] | 563 | dev_priv->eng[e]->fini(dev, e, false); |
Ben Skeggs | 2703c21 | 2011-04-01 09:50:18 +1000 | [diff] [blame] | 564 | dev_priv->eng[e]->destroy(dev,e ); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 565 | } |
| 566 | } |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 567 | nouveau_mem_gart_fini(dev); |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 568 | out_ttmvram: |
| 569 | nouveau_mem_vram_fini(dev); |
Marcin Kościelnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 570 | out_bios: |
| 571 | nouveau_bios_takedown(dev); |
Francisco Jerez | c88c2e0 | 2010-07-24 17:37:33 +0200 | [diff] [blame] | 572 | out_display_early: |
| 573 | engine->display.late_takedown(dev); |
Marcin Kościelnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 574 | out: |
Andreas Heider | 5c5ed6e | 2012-05-21 00:14:51 +0100 | [diff] [blame] | 575 | vga_switcheroo_unregister_client(dev->pdev); |
Marcin Kościelnicki | c5804be | 2009-12-14 20:58:39 +0000 | [diff] [blame] | 576 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
| 577 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | static void nouveau_card_takedown(struct drm_device *dev) |
| 581 | { |
| 582 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 583 | struct nouveau_engine *engine = &dev_priv->engine; |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 584 | int e; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 585 | |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 586 | if (dev->mode_config.num_crtc) { |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 587 | nouveau_fbcon_fini(dev); |
Ben Skeggs | f62b27d | 2011-11-09 15:18:47 +1000 | [diff] [blame] | 588 | nouveau_display_fini(dev); |
Ben Skeggs | 1575b36 | 2011-07-04 11:55:39 +1000 | [diff] [blame] | 589 | } |
Ben Skeggs | 06b75e3 | 2011-06-08 18:29:12 +1000 | [diff] [blame] | 590 | |
Ben Skeggs | 48aca13 | 2012-03-18 00:40:41 +1000 | [diff] [blame] | 591 | nouveau_card_channel_fini(dev); |
Ben Skeggs | 7d3a766 | 2012-02-01 15:17:07 +1000 | [diff] [blame] | 592 | nouveau_pm_fini(dev); |
Ben Skeggs | 10b461e | 2011-08-02 19:29:37 +1000 | [diff] [blame] | 593 | nouveau_backlight_exit(dev); |
Ben Skeggs | 27d5030 | 2011-10-06 12:46:40 +1000 | [diff] [blame] | 594 | nouveau_display_destroy(dev); |
Ben Skeggs | 06b75e3 | 2011-06-08 18:29:12 +1000 | [diff] [blame] | 595 | |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 596 | if (!dev_priv->noaccel) { |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 597 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { |
| 598 | if (dev_priv->eng[e]) { |
Ben Skeggs | 6c320fe | 2011-07-20 11:22:33 +1000 | [diff] [blame] | 599 | dev_priv->eng[e]->fini(dev, e, false); |
Ben Skeggs | 6dfdd7a | 2011-03-31 15:40:43 +1000 | [diff] [blame] | 600 | dev_priv->eng[e]->destroy(dev,e ); |
| 601 | } |
| 602 | } |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 603 | } |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 604 | |
Jimmy Rentz | 9766610 | 2011-04-17 16:15:09 -0400 | [diff] [blame] | 605 | if (dev_priv->vga_ram) { |
| 606 | nouveau_bo_unpin(dev_priv->vga_ram); |
| 607 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); |
| 608 | } |
| 609 | |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 610 | mutex_lock(&dev->struct_mutex); |
| 611 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); |
| 612 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); |
| 613 | mutex_unlock(&dev->struct_mutex); |
Ben Skeggs | fbd2895 | 2010-09-01 15:24:34 +1000 | [diff] [blame] | 614 | nouveau_mem_gart_fini(dev); |
Ben Skeggs | 24f246a | 2011-06-10 13:36:08 +1000 | [diff] [blame] | 615 | nouveau_mem_vram_fini(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 616 | |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 617 | nouveau_bios_takedown(dev); |
Ben Skeggs | 668b6c0 | 2011-12-15 10:43:03 +1000 | [diff] [blame] | 618 | engine->display.late_takedown(dev); |
| 619 | |
| 620 | nouveau_irq_fini(dev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 621 | |
Andreas Heider | 5c5ed6e | 2012-05-21 00:14:51 +0100 | [diff] [blame] | 622 | vga_switcheroo_unregister_client(dev->pdev); |
Ben Skeggs | b6d3d87 | 2010-06-07 15:38:27 +1000 | [diff] [blame] | 623 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 624 | } |
| 625 | |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 626 | int |
| 627 | nouveau_open(struct drm_device *dev, struct drm_file *file_priv) |
| 628 | { |
Ben Skeggs | fe32b16 | 2011-06-03 10:07:08 +1000 | [diff] [blame] | 629 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 630 | struct nouveau_fpriv *fpriv; |
Ben Skeggs | e41f26e | 2011-06-07 15:35:37 +1000 | [diff] [blame] | 631 | int ret; |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 632 | |
| 633 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 634 | if (unlikely(!fpriv)) |
| 635 | return -ENOMEM; |
| 636 | |
| 637 | spin_lock_init(&fpriv->lock); |
Ben Skeggs | e8a863c | 2011-06-01 19:18:48 +1000 | [diff] [blame] | 638 | INIT_LIST_HEAD(&fpriv->channels); |
| 639 | |
Ben Skeggs | e41f26e | 2011-06-07 15:35:37 +1000 | [diff] [blame] | 640 | if (dev_priv->card_type == NV_50) { |
| 641 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL, |
| 642 | &fpriv->vm); |
| 643 | if (ret) { |
| 644 | kfree(fpriv); |
| 645 | return ret; |
| 646 | } |
| 647 | } else |
| 648 | if (dev_priv->card_type >= NV_C0) { |
Ben Skeggs | 5de8037 | 2011-06-08 18:17:41 +1000 | [diff] [blame] | 649 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL, |
| 650 | &fpriv->vm); |
| 651 | if (ret) { |
| 652 | kfree(fpriv); |
| 653 | return ret; |
| 654 | } |
Ben Skeggs | e41f26e | 2011-06-07 15:35:37 +1000 | [diff] [blame] | 655 | } |
Ben Skeggs | fe32b16 | 2011-06-03 10:07:08 +1000 | [diff] [blame] | 656 | |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 657 | file_priv->driver_priv = fpriv; |
| 658 | return 0; |
| 659 | } |
| 660 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 661 | /* here a client dies, release the stuff that was allocated for its |
| 662 | * file_priv */ |
| 663 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) |
| 664 | { |
| 665 | nouveau_channel_cleanup(dev, file_priv); |
| 666 | } |
| 667 | |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 668 | void |
| 669 | nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv) |
| 670 | { |
| 671 | struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv); |
Ben Skeggs | fe32b16 | 2011-06-03 10:07:08 +1000 | [diff] [blame] | 672 | nouveau_vm_ref(NULL, &fpriv->vm, NULL); |
Ben Skeggs | 3f0a68d | 2011-05-31 11:11:28 +1000 | [diff] [blame] | 673 | kfree(fpriv); |
| 674 | } |
| 675 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 676 | /* first module load, setup the mmio/fb mapping */ |
| 677 | /* KMS: we need mmio at load time, not when the first drm client opens. */ |
| 678 | int nouveau_firstopen(struct drm_device *dev) |
| 679 | { |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | /* if we have an OF card, copy vbios to RAMIN */ |
| 684 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) |
| 685 | { |
| 686 | #if defined(__powerpc__) |
| 687 | int size, i; |
| 688 | const uint32_t *bios; |
| 689 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); |
| 690 | if (!dn) { |
| 691 | NV_INFO(dev, "Unable to get the OF node\n"); |
| 692 | return; |
| 693 | } |
| 694 | |
| 695 | bios = of_get_property(dn, "NVDA,BMP", &size); |
| 696 | if (bios) { |
| 697 | for (i = 0; i < size; i += 4) |
| 698 | nv_wi32(dev, i, bios[i/4]); |
| 699 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); |
| 700 | } else { |
| 701 | NV_INFO(dev, "Unable to get the OF bios\n"); |
| 702 | } |
| 703 | #endif |
| 704 | } |
| 705 | |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 706 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
| 707 | { |
| 708 | struct pci_dev *pdev = dev->pdev; |
| 709 | struct apertures_struct *aper = alloc_apertures(3); |
| 710 | if (!aper) |
| 711 | return NULL; |
| 712 | |
| 713 | aper->ranges[0].base = pci_resource_start(pdev, 1); |
| 714 | aper->ranges[0].size = pci_resource_len(pdev, 1); |
| 715 | aper->count = 1; |
| 716 | |
| 717 | if (pci_resource_len(pdev, 2)) { |
| 718 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); |
| 719 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); |
| 720 | aper->count++; |
| 721 | } |
| 722 | |
| 723 | if (pci_resource_len(pdev, 3)) { |
| 724 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); |
| 725 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); |
| 726 | aper->count++; |
| 727 | } |
| 728 | |
| 729 | return aper; |
| 730 | } |
| 731 | |
| 732 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) |
| 733 | { |
| 734 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Marcin Slusarz | 3b9676e | 2010-05-16 17:33:09 +0200 | [diff] [blame] | 735 | bool primary = false; |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 736 | dev_priv->apertures = nouveau_get_apertures(dev); |
| 737 | if (!dev_priv->apertures) |
| 738 | return -ENOMEM; |
| 739 | |
Marcin Slusarz | 3b9676e | 2010-05-16 17:33:09 +0200 | [diff] [blame] | 740 | #ifdef CONFIG_X86 |
| 741 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; |
| 742 | #endif |
Emil Velikov | f212949 | 2011-03-19 23:31:52 +0000 | [diff] [blame] | 743 | |
Marcin Slusarz | 3b9676e | 2010-05-16 17:33:09 +0200 | [diff] [blame] | 744 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 745 | return 0; |
| 746 | } |
| 747 | |
Ben Skeggs | 9458029 | 2012-07-06 12:14:00 +1000 | [diff] [blame] | 748 | void * |
| 749 | nouveau_newpriv(struct drm_device *dev) |
| 750 | { |
| 751 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 752 | return dev_priv->newpriv; |
| 753 | } |
| 754 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 755 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
| 756 | { |
| 757 | struct drm_nouveau_private *dev_priv; |
Ben Skeggs | 2f5394c | 2012-03-12 15:55:43 +1000 | [diff] [blame] | 758 | uint32_t reg0 = ~0, strap; |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 759 | int ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 760 | |
| 761 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 762 | if (!dev_priv) { |
| 763 | ret = -ENOMEM; |
| 764 | goto err_out; |
| 765 | } |
Ben Skeggs | 9458029 | 2012-07-06 12:14:00 +1000 | [diff] [blame] | 766 | dev_priv->newpriv = dev->dev_private; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 767 | dev->dev_private = dev_priv; |
| 768 | dev_priv->dev = dev; |
| 769 | |
| 770 | dev_priv->flags = flags & NOUVEAU_FLAGS; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 771 | |
| 772 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", |
| 773 | dev->pci_vendor, dev->pci_device, dev->pdev->class); |
| 774 | |
Ben Skeggs | 586c55f | 2012-07-09 14:14:48 +1000 | [diff] [blame] | 775 | /* determine chipset and derive architecture from it */ |
| 776 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); |
| 777 | if ((reg0 & 0x0f000000) > 0) { |
| 778 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; |
| 779 | switch (dev_priv->chipset & 0xf0) { |
| 780 | case 0x10: |
| 781 | case 0x20: |
| 782 | case 0x30: |
| 783 | dev_priv->card_type = dev_priv->chipset & 0xf0; |
| 784 | break; |
| 785 | case 0x40: |
| 786 | case 0x60: |
| 787 | dev_priv->card_type = NV_40; |
| 788 | break; |
| 789 | case 0x50: |
| 790 | case 0x80: |
| 791 | case 0x90: |
| 792 | case 0xa0: |
| 793 | dev_priv->card_type = NV_50; |
| 794 | break; |
| 795 | case 0xc0: |
| 796 | dev_priv->card_type = NV_C0; |
| 797 | break; |
| 798 | case 0xd0: |
| 799 | dev_priv->card_type = NV_D0; |
| 800 | break; |
| 801 | case 0xe0: |
| 802 | dev_priv->card_type = NV_E0; |
| 803 | break; |
| 804 | default: |
| 805 | break; |
Ben Skeggs | 2f5394c | 2012-03-12 15:55:43 +1000 | [diff] [blame] | 806 | } |
Ben Skeggs | 586c55f | 2012-07-09 14:14:48 +1000 | [diff] [blame] | 807 | } else |
| 808 | if ((reg0 & 0xff00fff0) == 0x20004000) { |
| 809 | if (reg0 & 0x00f00000) |
| 810 | dev_priv->chipset = 0x05; |
| 811 | else |
| 812 | dev_priv->chipset = 0x04; |
| 813 | dev_priv->card_type = NV_04; |
Ben Skeggs | 2f5394c | 2012-03-12 15:55:43 +1000 | [diff] [blame] | 814 | } |
| 815 | |
| 816 | if (!dev_priv->card_type) { |
| 817 | NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0); |
| 818 | ret = -EINVAL; |
| 819 | goto err_priv; |
| 820 | } |
| 821 | |
Ben Skeggs | 42eddbd | 2012-05-09 20:17:07 +1000 | [diff] [blame] | 822 | NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n", |
Ben Skeggs | 2f5394c | 2012-03-12 15:55:43 +1000 | [diff] [blame] | 823 | dev_priv->card_type, reg0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 824 | |
Ben Skeggs | f2cbe46 | 2011-07-21 15:39:06 +1000 | [diff] [blame] | 825 | /* determine frequency of timing crystal */ |
| 826 | strap = nv_rd32(dev, 0x101000); |
| 827 | if ( dev_priv->chipset < 0x17 || |
| 828 | (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25)) |
| 829 | strap &= 0x00000040; |
| 830 | else |
| 831 | strap &= 0x00400040; |
| 832 | |
| 833 | switch (strap) { |
| 834 | case 0x00000000: dev_priv->crystal = 13500; break; |
| 835 | case 0x00000040: dev_priv->crystal = 14318; break; |
| 836 | case 0x00400000: dev_priv->crystal = 27000; break; |
| 837 | case 0x00400040: dev_priv->crystal = 25000; break; |
| 838 | } |
| 839 | |
| 840 | NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal); |
| 841 | |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 842 | /* Determine whether we'll attempt acceleration or not, some |
| 843 | * cards are disabled by default here due to them being known |
| 844 | * non-functional, or never been tested due to lack of hw. |
| 845 | */ |
| 846 | dev_priv->noaccel = !!nouveau_noaccel; |
| 847 | if (nouveau_noaccel == -1) { |
| 848 | switch (dev_priv->chipset) { |
Ben Skeggs | 0678409 | 2011-07-11 15:57:54 +1000 | [diff] [blame] | 849 | case 0xd9: /* known broken */ |
Ben Skeggs | ab39454 | 2012-03-13 13:05:13 +1000 | [diff] [blame] | 850 | case 0xe4: /* needs binary driver firmware */ |
| 851 | case 0xe7: /* needs binary driver firmware */ |
Ben Skeggs | ad830d2 | 2011-05-27 16:18:10 +1000 | [diff] [blame] | 852 | NV_INFO(dev, "acceleration disabled by default, pass " |
| 853 | "noaccel=0 to force enable\n"); |
Ben Skeggs | aba99a8 | 2011-05-25 14:48:50 +1000 | [diff] [blame] | 854 | dev_priv->noaccel = true; |
| 855 | break; |
| 856 | default: |
| 857 | dev_priv->noaccel = false; |
| 858 | break; |
| 859 | } |
| 860 | } |
| 861 | |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 862 | ret = nouveau_remove_conflicting_drivers(dev); |
| 863 | if (ret) |
Ben Skeggs | 586c55f | 2012-07-09 14:14:48 +1000 | [diff] [blame] | 864 | goto err_priv; |
Marcin Slusarz | 06415c5 | 2010-05-16 17:29:56 +0200 | [diff] [blame] | 865 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 866 | nouveau_OF_copy_vbios_to_ramin(dev); |
| 867 | |
| 868 | /* Special flags */ |
| 869 | if (dev->pci_device == 0x01a0) |
| 870 | dev_priv->flags |= NV_NFORCE; |
| 871 | else if (dev->pci_device == 0x01f0) |
| 872 | dev_priv->flags |= NV_NFORCE2; |
| 873 | |
| 874 | /* For kernel modesetting, init card now and bring up fbcon */ |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 875 | ret = nouveau_card_init(dev); |
| 876 | if (ret) |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 877 | goto err_priv; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 878 | |
| 879 | return 0; |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 880 | |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 881 | err_priv: |
Ben Skeggs | 9458029 | 2012-07-06 12:14:00 +1000 | [diff] [blame] | 882 | dev->dev_private = dev_priv->newpriv; |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 883 | kfree(dev_priv); |
Dan Carpenter | a0d069e | 2010-07-30 17:04:32 +0200 | [diff] [blame] | 884 | err_out: |
| 885 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 886 | } |
| 887 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 888 | void nouveau_lastclose(struct drm_device *dev) |
| 889 | { |
Dave Airlie | 5ccb377 | 2010-12-07 13:56:26 +1000 | [diff] [blame] | 890 | vga_switcheroo_process_delayed_switch(); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 891 | } |
| 892 | |
| 893 | int nouveau_unload(struct drm_device *dev) |
| 894 | { |
| 895 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 896 | |
Ben Skeggs | cd0b072 | 2010-06-01 15:56:22 +1000 | [diff] [blame] | 897 | nouveau_card_takedown(dev); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 898 | |
Ben Skeggs | 9458029 | 2012-07-06 12:14:00 +1000 | [diff] [blame] | 899 | dev->dev_private = dev_priv->newpriv; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 900 | kfree(dev_priv); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 901 | return 0; |
| 902 | } |
| 903 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 904 | /* Waits for PGRAPH to go completely idle */ |
| 905 | bool nouveau_wait_for_idle(struct drm_device *dev) |
| 906 | { |
Francisco Jerez | 0541324a | 2010-10-18 16:15:15 +0200 | [diff] [blame] | 907 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 908 | uint32_t mask = ~0; |
| 909 | |
| 910 | if (dev_priv->card_type == NV_40) |
| 911 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; |
| 912 | |
| 913 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 914 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
| 915 | nv_rd32(dev, NV04_PGRAPH_STATUS)); |
| 916 | return false; |
| 917 | } |
| 918 | |
| 919 | return true; |
| 920 | } |
| 921 | |