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Catalin Marinas382266a2007-02-05 14:48:19 +01001/*
2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
Catalin Marinas07620972007-07-20 11:42:40 +010020#include <linux/spinlock.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010022
23#include <asm/cacheflush.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010024#include <asm/hardware/cache-l2x0.h>
25
26#define CACHE_LINE_SIZE 32
27
28static void __iomem *l2x0_base;
Catalin Marinas07620972007-07-20 11:42:40 +010029static DEFINE_SPINLOCK(l2x0_lock);
Jason McMullan64039be2010-05-05 18:59:37 +010030static uint32_t l2x0_way_mask; /* Bitmask of active ways */
Santosh Shilimkar5ba70372010-07-11 14:35:37 +053031static uint32_t l2x0_size;
Catalin Marinas382266a2007-02-05 14:48:19 +010032
Catalin Marinas9a6655e2010-08-31 13:05:22 +010033static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010034{
Catalin Marinas9a6655e2010-08-31 13:05:22 +010035 /* wait for cache operation by line or way to complete */
Catalin Marinas6775a552010-07-28 22:01:25 +010036 while (readl_relaxed(reg) & mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010037 ;
Catalin Marinas382266a2007-02-05 14:48:19 +010038}
39
Catalin Marinas9a6655e2010-08-31 13:05:22 +010040#ifdef CONFIG_CACHE_PL310
41static inline void cache_wait(void __iomem *reg, unsigned long mask)
42{
43 /* cache operations by line are atomic on PL310 */
44}
45#else
46#define cache_wait cache_wait_way
47#endif
48
Catalin Marinas382266a2007-02-05 14:48:19 +010049static inline void cache_sync(void)
50{
Russell King3d107432009-11-19 11:41:09 +000051 void __iomem *base = l2x0_base;
Srinidhi Kasagar885028e2011-02-17 07:03:51 +010052
53#ifdef CONFIG_ARM_ERRATA_753970
54 /* write to an unmmapped register */
55 writel_relaxed(0, base + L2X0_DUMMY_REG);
56#else
Catalin Marinas6775a552010-07-28 22:01:25 +010057 writel_relaxed(0, base + L2X0_CACHE_SYNC);
Srinidhi Kasagar885028e2011-02-17 07:03:51 +010058#endif
Russell King3d107432009-11-19 11:41:09 +000059 cache_wait(base + L2X0_CACHE_SYNC, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +010060}
61
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010062static inline void l2x0_clean_line(unsigned long addr)
63{
64 void __iomem *base = l2x0_base;
65 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010066 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010067}
68
69static inline void l2x0_inv_line(unsigned long addr)
70{
71 void __iomem *base = l2x0_base;
72 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010073 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010074}
75
Santosh Shilimkar2839e062011-03-08 06:59:54 +010076#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
Santosh Shilimkar9e655822010-02-04 19:42:42 +010077
Santosh Shilimkar2839e062011-03-08 06:59:54 +010078#define debug_writel(val) outer_cache.set_debug(val)
79
80static void l2x0_set_debug(unsigned long val)
81{
82 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
83}
84#else
85/* Optimised out for non-errata case */
86static inline void debug_writel(unsigned long val)
87{
Santosh Shilimkar9e655822010-02-04 19:42:42 +010088}
89
Santosh Shilimkar2839e062011-03-08 06:59:54 +010090#define l2x0_set_debug NULL
91#endif
92
93#ifdef CONFIG_PL310_ERRATA_588369
Santosh Shilimkar9e655822010-02-04 19:42:42 +010094static inline void l2x0_flush_line(unsigned long addr)
95{
96 void __iomem *base = l2x0_base;
97
98 /* Clean by PA followed by Invalidate by PA */
99 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100100 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100101 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100102 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100103}
104#else
105
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100106static inline void l2x0_flush_line(unsigned long addr)
107{
108 void __iomem *base = l2x0_base;
109 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100110 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100111}
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100112#endif
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100113
Catalin Marinas23107c52010-03-24 16:48:53 +0100114static void l2x0_cache_sync(void)
115{
116 unsigned long flags;
117
118 spin_lock_irqsave(&l2x0_lock, flags);
119 cache_sync();
120 spin_unlock_irqrestore(&l2x0_lock, flags);
121}
122
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530123static void l2x0_flush_all(void)
124{
125 unsigned long flags;
126
127 /* clean all ways */
128 spin_lock_irqsave(&l2x0_lock, flags);
Santosh Shilimkar2839e062011-03-08 06:59:54 +0100129 debug_writel(0x03);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530130 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
131 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
132 cache_sync();
Santosh Shilimkar2839e062011-03-08 06:59:54 +0100133 debug_writel(0x00);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530134 spin_unlock_irqrestore(&l2x0_lock, flags);
135}
136
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530137static void l2x0_clean_all(void)
138{
139 unsigned long flags;
140
141 /* clean all ways */
142 spin_lock_irqsave(&l2x0_lock, flags);
143 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
144 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
145 cache_sync();
146 spin_unlock_irqrestore(&l2x0_lock, flags);
147}
148
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530149static void l2x0_inv_all(void)
Catalin Marinas382266a2007-02-05 14:48:19 +0100150{
Russell King0eb948d2009-11-19 11:12:15 +0000151 unsigned long flags;
152
Catalin Marinas382266a2007-02-05 14:48:19 +0100153 /* invalidate all ways */
Russell King0eb948d2009-11-19 11:12:15 +0000154 spin_lock_irqsave(&l2x0_lock, flags);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530155 /* Invalidating when L2 is enabled is a nono */
156 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100157 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
Catalin Marinas9a6655e2010-08-31 13:05:22 +0100158 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
Catalin Marinas382266a2007-02-05 14:48:19 +0100159 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000160 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100161}
162
163static void l2x0_inv_range(unsigned long start, unsigned long end)
164{
Russell King3d107432009-11-19 11:41:09 +0000165 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000166 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100167
Russell King0eb948d2009-11-19 11:12:15 +0000168 spin_lock_irqsave(&l2x0_lock, flags);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100169 if (start & (CACHE_LINE_SIZE - 1)) {
170 start &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100171 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100172 l2x0_flush_line(start);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100173 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100174 start += CACHE_LINE_SIZE;
175 }
176
177 if (end & (CACHE_LINE_SIZE - 1)) {
178 end &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100179 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100180 l2x0_flush_line(end);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100181 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100182 }
183
Russell King0eb948d2009-11-19 11:12:15 +0000184 while (start < end) {
185 unsigned long blk_end = start + min(end - start, 4096UL);
186
187 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100188 l2x0_inv_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000189 start += CACHE_LINE_SIZE;
190 }
191
192 if (blk_end < end) {
193 spin_unlock_irqrestore(&l2x0_lock, flags);
194 spin_lock_irqsave(&l2x0_lock, flags);
195 }
196 }
Russell King3d107432009-11-19 11:41:09 +0000197 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100198 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000199 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100200}
201
202static void l2x0_clean_range(unsigned long start, unsigned long end)
203{
Russell King3d107432009-11-19 11:41:09 +0000204 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000205 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100206
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530207 if ((end - start) >= l2x0_size) {
208 l2x0_clean_all();
209 return;
210 }
211
Russell King0eb948d2009-11-19 11:12:15 +0000212 spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100213 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000214 while (start < end) {
215 unsigned long blk_end = start + min(end - start, 4096UL);
216
217 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100218 l2x0_clean_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000219 start += CACHE_LINE_SIZE;
220 }
221
222 if (blk_end < end) {
223 spin_unlock_irqrestore(&l2x0_lock, flags);
224 spin_lock_irqsave(&l2x0_lock, flags);
225 }
226 }
Russell King3d107432009-11-19 11:41:09 +0000227 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100228 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000229 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100230}
231
232static void l2x0_flush_range(unsigned long start, unsigned long end)
233{
Russell King3d107432009-11-19 11:41:09 +0000234 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000235 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100236
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530237 if ((end - start) >= l2x0_size) {
238 l2x0_flush_all();
239 return;
240 }
241
Russell King0eb948d2009-11-19 11:12:15 +0000242 spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100243 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000244 while (start < end) {
245 unsigned long blk_end = start + min(end - start, 4096UL);
246
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100247 debug_writel(0x03);
Russell King0eb948d2009-11-19 11:12:15 +0000248 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100249 l2x0_flush_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000250 start += CACHE_LINE_SIZE;
251 }
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100252 debug_writel(0x00);
Russell King0eb948d2009-11-19 11:12:15 +0000253
254 if (blk_end < end) {
255 spin_unlock_irqrestore(&l2x0_lock, flags);
256 spin_lock_irqsave(&l2x0_lock, flags);
257 }
258 }
Russell King3d107432009-11-19 11:41:09 +0000259 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100260 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000261 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100262}
263
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530264static void l2x0_disable(void)
265{
266 unsigned long flags;
267
268 spin_lock_irqsave(&l2x0_lock, flags);
269 writel(0, l2x0_base + L2X0_CTRL);
270 spin_unlock_irqrestore(&l2x0_lock, flags);
271}
272
Catalin Marinas382266a2007-02-05 14:48:19 +0100273void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
274{
275 __u32 aux;
Jason McMullan64039be2010-05-05 18:59:37 +0100276 __u32 cache_id;
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530277 __u32 way_size = 0;
Jason McMullan64039be2010-05-05 18:59:37 +0100278 int ways;
279 const char *type;
Catalin Marinas382266a2007-02-05 14:48:19 +0100280
281 l2x0_base = base;
282
Catalin Marinas6775a552010-07-28 22:01:25 +0100283 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
284 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
Jason McMullan64039be2010-05-05 18:59:37 +0100285
Sascha Hauer4082cfa2010-07-08 08:36:21 +0100286 aux &= aux_mask;
287 aux |= aux_val;
288
Jason McMullan64039be2010-05-05 18:59:37 +0100289 /* Determine the number of ways */
290 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
291 case L2X0_CACHE_ID_PART_L310:
292 if (aux & (1 << 16))
293 ways = 16;
294 else
295 ways = 8;
296 type = "L310";
297 break;
298 case L2X0_CACHE_ID_PART_L210:
299 ways = (aux >> 13) & 0xf;
300 type = "L210";
301 break;
302 default:
303 /* Assume unknown chips have 8 ways */
304 ways = 8;
305 type = "L2x0 series";
306 break;
307 }
308
309 l2x0_way_mask = (1 << ways) - 1;
310
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100311 /*
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530312 * L2 cache Size = Way size * Number of ways
313 */
314 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
315 way_size = 1 << (way_size + 3);
316 l2x0_size = ways * way_size * SZ_1K;
317
318 /*
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100319 * Check if l2x0 controller is already enabled.
320 * If you are booting from non-secure mode
321 * accessing the below registers will fault.
322 */
Catalin Marinas6775a552010-07-28 22:01:25 +0100323 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
Catalin Marinas382266a2007-02-05 14:48:19 +0100324
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100325 /* l2x0 controller is disabled */
Catalin Marinas6775a552010-07-28 22:01:25 +0100326 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
Catalin Marinas382266a2007-02-05 14:48:19 +0100327
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100328 l2x0_inv_all();
329
330 /* enable L2X0 */
Catalin Marinas6775a552010-07-28 22:01:25 +0100331 writel_relaxed(1, l2x0_base + L2X0_CTRL);
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100332 }
Catalin Marinas382266a2007-02-05 14:48:19 +0100333
334 outer_cache.inv_range = l2x0_inv_range;
335 outer_cache.clean_range = l2x0_clean_range;
336 outer_cache.flush_range = l2x0_flush_range;
Catalin Marinas23107c52010-03-24 16:48:53 +0100337 outer_cache.sync = l2x0_cache_sync;
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530338 outer_cache.flush_all = l2x0_flush_all;
339 outer_cache.inv_all = l2x0_inv_all;
340 outer_cache.disable = l2x0_disable;
Santosh Shilimkar2839e062011-03-08 06:59:54 +0100341 outer_cache.set_debug = l2x0_set_debug;
Catalin Marinas382266a2007-02-05 14:48:19 +0100342
Jason McMullan64039be2010-05-05 18:59:37 +0100343 printk(KERN_INFO "%s cache controller enabled\n", type);
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530344 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
345 ways, cache_id, aux, l2x0_size);
Catalin Marinas382266a2007-02-05 14:48:19 +0100346}