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Catalin Marinas382266a2007-02-05 14:48:19 +01001/*
2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
Catalin Marinas07620972007-07-20 11:42:40 +010020#include <linux/spinlock.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010022
23#include <asm/cacheflush.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010024#include <asm/hardware/cache-l2x0.h>
25
26#define CACHE_LINE_SIZE 32
27
28static void __iomem *l2x0_base;
Catalin Marinas07620972007-07-20 11:42:40 +010029static DEFINE_SPINLOCK(l2x0_lock);
Jason McMullan64039be2010-05-05 18:59:37 +010030static uint32_t l2x0_way_mask; /* Bitmask of active ways */
Santosh Shilimkar5ba70372010-07-11 14:35:37 +053031static uint32_t l2x0_size;
Catalin Marinas382266a2007-02-05 14:48:19 +010032
Catalin Marinas9a6655e2010-08-31 13:05:22 +010033static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010034{
Catalin Marinas9a6655e2010-08-31 13:05:22 +010035 /* wait for cache operation by line or way to complete */
Catalin Marinas6775a552010-07-28 22:01:25 +010036 while (readl_relaxed(reg) & mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010037 ;
Catalin Marinas382266a2007-02-05 14:48:19 +010038}
39
Catalin Marinas9a6655e2010-08-31 13:05:22 +010040#ifdef CONFIG_CACHE_PL310
41static inline void cache_wait(void __iomem *reg, unsigned long mask)
42{
43 /* cache operations by line are atomic on PL310 */
44}
45#else
46#define cache_wait cache_wait_way
47#endif
48
Catalin Marinas382266a2007-02-05 14:48:19 +010049static inline void cache_sync(void)
50{
Russell King3d107432009-11-19 11:41:09 +000051 void __iomem *base = l2x0_base;
Srinidhi Kasagar885028e2011-02-17 07:03:51 +010052
53#ifdef CONFIG_ARM_ERRATA_753970
54 /* write to an unmmapped register */
55 writel_relaxed(0, base + L2X0_DUMMY_REG);
56#else
Catalin Marinas6775a552010-07-28 22:01:25 +010057 writel_relaxed(0, base + L2X0_CACHE_SYNC);
Srinidhi Kasagar885028e2011-02-17 07:03:51 +010058#endif
Russell King3d107432009-11-19 11:41:09 +000059 cache_wait(base + L2X0_CACHE_SYNC, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +010060}
61
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010062static inline void l2x0_clean_line(unsigned long addr)
63{
64 void __iomem *base = l2x0_base;
65 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010066 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010067}
68
69static inline void l2x0_inv_line(unsigned long addr)
70{
71 void __iomem *base = l2x0_base;
72 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010073 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010074}
75
Santosh Shilimkar9e655822010-02-04 19:42:42 +010076#ifdef CONFIG_PL310_ERRATA_588369
77static void debug_writel(unsigned long val)
78{
79 extern void omap_smc1(u32 fn, u32 arg);
80
81 /*
82 * Texas Instrument secure monitor api to modify the
83 * PL310 Debug Control Register.
84 */
85 omap_smc1(0x100, val);
86}
87
88static inline void l2x0_flush_line(unsigned long addr)
89{
90 void __iomem *base = l2x0_base;
91
92 /* Clean by PA followed by Invalidate by PA */
93 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010094 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
Santosh Shilimkar9e655822010-02-04 19:42:42 +010095 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +010096 writel_relaxed(addr, base + L2X0_INV_LINE_PA);
Santosh Shilimkar9e655822010-02-04 19:42:42 +010097}
98#else
99
100/* Optimised out for non-errata case */
101static inline void debug_writel(unsigned long val)
102{
103}
104
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100105static inline void l2x0_flush_line(unsigned long addr)
106{
107 void __iomem *base = l2x0_base;
108 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100109 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100110}
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100111#endif
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100112
Catalin Marinas23107c52010-03-24 16:48:53 +0100113static void l2x0_cache_sync(void)
114{
115 unsigned long flags;
116
117 spin_lock_irqsave(&l2x0_lock, flags);
118 cache_sync();
119 spin_unlock_irqrestore(&l2x0_lock, flags);
120}
121
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530122static void l2x0_flush_all(void)
123{
124 unsigned long flags;
125
126 /* clean all ways */
127 spin_lock_irqsave(&l2x0_lock, flags);
128 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
129 cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
130 cache_sync();
131 spin_unlock_irqrestore(&l2x0_lock, flags);
132}
133
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530134static void l2x0_clean_all(void)
135{
136 unsigned long flags;
137
138 /* clean all ways */
139 spin_lock_irqsave(&l2x0_lock, flags);
140 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
141 cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
142 cache_sync();
143 spin_unlock_irqrestore(&l2x0_lock, flags);
144}
145
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530146static void l2x0_inv_all(void)
Catalin Marinas382266a2007-02-05 14:48:19 +0100147{
Russell King0eb948d2009-11-19 11:12:15 +0000148 unsigned long flags;
149
Catalin Marinas382266a2007-02-05 14:48:19 +0100150 /* invalidate all ways */
Russell King0eb948d2009-11-19 11:12:15 +0000151 spin_lock_irqsave(&l2x0_lock, flags);
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530152 /* Invalidating when L2 is enabled is a nono */
153 BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
Catalin Marinas6775a552010-07-28 22:01:25 +0100154 writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
Catalin Marinas9a6655e2010-08-31 13:05:22 +0100155 cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
Catalin Marinas382266a2007-02-05 14:48:19 +0100156 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000157 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100158}
159
160static void l2x0_inv_range(unsigned long start, unsigned long end)
161{
Russell King3d107432009-11-19 11:41:09 +0000162 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000163 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100164
Russell King0eb948d2009-11-19 11:12:15 +0000165 spin_lock_irqsave(&l2x0_lock, flags);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100166 if (start & (CACHE_LINE_SIZE - 1)) {
167 start &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100168 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100169 l2x0_flush_line(start);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100170 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100171 start += CACHE_LINE_SIZE;
172 }
173
174 if (end & (CACHE_LINE_SIZE - 1)) {
175 end &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100176 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100177 l2x0_flush_line(end);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100178 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100179 }
180
Russell King0eb948d2009-11-19 11:12:15 +0000181 while (start < end) {
182 unsigned long blk_end = start + min(end - start, 4096UL);
183
184 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100185 l2x0_inv_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000186 start += CACHE_LINE_SIZE;
187 }
188
189 if (blk_end < end) {
190 spin_unlock_irqrestore(&l2x0_lock, flags);
191 spin_lock_irqsave(&l2x0_lock, flags);
192 }
193 }
Russell King3d107432009-11-19 11:41:09 +0000194 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100195 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000196 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100197}
198
199static void l2x0_clean_range(unsigned long start, unsigned long end)
200{
Russell King3d107432009-11-19 11:41:09 +0000201 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000202 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100203
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530204 if ((end - start) >= l2x0_size) {
205 l2x0_clean_all();
206 return;
207 }
208
Russell King0eb948d2009-11-19 11:12:15 +0000209 spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100210 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000211 while (start < end) {
212 unsigned long blk_end = start + min(end - start, 4096UL);
213
214 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100215 l2x0_clean_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000216 start += CACHE_LINE_SIZE;
217 }
218
219 if (blk_end < end) {
220 spin_unlock_irqrestore(&l2x0_lock, flags);
221 spin_lock_irqsave(&l2x0_lock, flags);
222 }
223 }
Russell King3d107432009-11-19 11:41:09 +0000224 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100225 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000226 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100227}
228
229static void l2x0_flush_range(unsigned long start, unsigned long end)
230{
Russell King3d107432009-11-19 11:41:09 +0000231 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000232 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100233
Santosh Shilimkar444457c2010-07-11 14:58:41 +0530234 if ((end - start) >= l2x0_size) {
235 l2x0_flush_all();
236 return;
237 }
238
Russell King0eb948d2009-11-19 11:12:15 +0000239 spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100240 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000241 while (start < end) {
242 unsigned long blk_end = start + min(end - start, 4096UL);
243
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100244 debug_writel(0x03);
Russell King0eb948d2009-11-19 11:12:15 +0000245 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100246 l2x0_flush_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000247 start += CACHE_LINE_SIZE;
248 }
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100249 debug_writel(0x00);
Russell King0eb948d2009-11-19 11:12:15 +0000250
251 if (blk_end < end) {
252 spin_unlock_irqrestore(&l2x0_lock, flags);
253 spin_lock_irqsave(&l2x0_lock, flags);
254 }
255 }
Russell King3d107432009-11-19 11:41:09 +0000256 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100257 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000258 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100259}
260
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530261static void l2x0_disable(void)
262{
263 unsigned long flags;
264
265 spin_lock_irqsave(&l2x0_lock, flags);
266 writel(0, l2x0_base + L2X0_CTRL);
267 spin_unlock_irqrestore(&l2x0_lock, flags);
268}
269
Catalin Marinas382266a2007-02-05 14:48:19 +0100270void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
271{
272 __u32 aux;
Jason McMullan64039be2010-05-05 18:59:37 +0100273 __u32 cache_id;
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530274 __u32 way_size = 0;
Jason McMullan64039be2010-05-05 18:59:37 +0100275 int ways;
276 const char *type;
Catalin Marinas382266a2007-02-05 14:48:19 +0100277
278 l2x0_base = base;
279
Catalin Marinas6775a552010-07-28 22:01:25 +0100280 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
281 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
Jason McMullan64039be2010-05-05 18:59:37 +0100282
Sascha Hauer4082cfa2010-07-08 08:36:21 +0100283 aux &= aux_mask;
284 aux |= aux_val;
285
Jason McMullan64039be2010-05-05 18:59:37 +0100286 /* Determine the number of ways */
287 switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
288 case L2X0_CACHE_ID_PART_L310:
289 if (aux & (1 << 16))
290 ways = 16;
291 else
292 ways = 8;
293 type = "L310";
294 break;
295 case L2X0_CACHE_ID_PART_L210:
296 ways = (aux >> 13) & 0xf;
297 type = "L210";
298 break;
299 default:
300 /* Assume unknown chips have 8 ways */
301 ways = 8;
302 type = "L2x0 series";
303 break;
304 }
305
306 l2x0_way_mask = (1 << ways) - 1;
307
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100308 /*
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530309 * L2 cache Size = Way size * Number of ways
310 */
311 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
312 way_size = 1 << (way_size + 3);
313 l2x0_size = ways * way_size * SZ_1K;
314
315 /*
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100316 * Check if l2x0 controller is already enabled.
317 * If you are booting from non-secure mode
318 * accessing the below registers will fault.
319 */
Catalin Marinas6775a552010-07-28 22:01:25 +0100320 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
Catalin Marinas382266a2007-02-05 14:48:19 +0100321
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100322 /* l2x0 controller is disabled */
Catalin Marinas6775a552010-07-28 22:01:25 +0100323 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
Catalin Marinas382266a2007-02-05 14:48:19 +0100324
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100325 l2x0_inv_all();
326
327 /* enable L2X0 */
Catalin Marinas6775a552010-07-28 22:01:25 +0100328 writel_relaxed(1, l2x0_base + L2X0_CTRL);
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100329 }
Catalin Marinas382266a2007-02-05 14:48:19 +0100330
331 outer_cache.inv_range = l2x0_inv_range;
332 outer_cache.clean_range = l2x0_clean_range;
333 outer_cache.flush_range = l2x0_flush_range;
Catalin Marinas23107c52010-03-24 16:48:53 +0100334 outer_cache.sync = l2x0_cache_sync;
Thomas Gleixner2fd86582010-07-31 21:05:24 +0530335 outer_cache.flush_all = l2x0_flush_all;
336 outer_cache.inv_all = l2x0_inv_all;
337 outer_cache.disable = l2x0_disable;
Catalin Marinas382266a2007-02-05 14:48:19 +0100338
Jason McMullan64039be2010-05-05 18:59:37 +0100339 printk(KERN_INFO "%s cache controller enabled\n", type);
Santosh Shilimkar5ba70372010-07-11 14:35:37 +0530340 printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
341 ways, cache_id, aux, l2x0_size);
Catalin Marinas382266a2007-02-05 14:48:19 +0100342}