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David Howells108b42b2006-03-31 16:00:29 +01001 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
David Howells90fddab2010-03-24 09:43:00 +00006 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
David Howells108b42b2006-03-31 16:00:29 +01007
8Contents:
9
10 (*) Abstract memory access model.
11
12 - Device operations.
13 - Guarantees.
14
15 (*) What are memory barriers?
16
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
David Howells670bd952006-06-10 09:54:12 -070023 - Read memory barriers vs load speculation.
Paul E. McKenney241e6662011-02-10 16:54:50 -080024 - Transitivity
David Howells108b42b2006-03-31 16:00:29 +010025
26 (*) Explicit kernel barriers.
27
28 - Compiler barrier.
Jarek Poplawski81fc6322007-05-23 13:58:20 -070029 - CPU memory barriers.
David Howells108b42b2006-03-31 16:00:29 +010030 - MMIO write barrier.
31
32 (*) Implicit kernel memory barriers.
33
SeongJae Park166bda72016-04-12 08:52:50 -070034 - Lock acquisition functions.
David Howells108b42b2006-03-31 16:00:29 +010035 - Interrupt disabling functions.
David Howells50fa6102009-04-28 15:01:38 +010036 - Sleep and wake-up functions.
David Howells108b42b2006-03-31 16:00:29 +010037 - Miscellaneous functions.
38
SeongJae Park166bda72016-04-12 08:52:50 -070039 (*) Inter-CPU acquiring barrier effects.
David Howells108b42b2006-03-31 16:00:29 +010040
SeongJae Park166bda72016-04-12 08:52:50 -070041 - Acquires vs memory accesses.
42 - Acquires vs I/O accesses.
David Howells108b42b2006-03-31 16:00:29 +010043
44 (*) Where are memory barriers needed?
45
46 - Interprocessor interaction.
47 - Atomic operations.
48 - Accessing devices.
49 - Interrupts.
50
51 (*) Kernel I/O barrier effects.
52
53 (*) Assumed minimum execution ordering model.
54
55 (*) The effects of the cpu cache.
56
57 - Cache coherency.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
60
61 (*) The things CPUs get up to.
62
63 - And then there's the Alpha.
SeongJae Park01e1cd62016-04-12 08:52:51 -070064 - Virtual Machine Guests.
David Howells108b42b2006-03-31 16:00:29 +010065
David Howells90fddab2010-03-24 09:43:00 +000066 (*) Example uses.
67
68 - Circular buffers.
69
David Howells108b42b2006-03-31 16:00:29 +010070 (*) References.
71
72
73============================
74ABSTRACT MEMORY ACCESS MODEL
75============================
76
77Consider the following abstract model of the system:
78
79 : :
80 : :
81 : :
82 +-------+ : +--------+ : +-------+
83 | | : | | : | |
84 | | : | | : | |
85 | CPU 1 |<----->| Memory |<----->| CPU 2 |
86 | | : | | : | |
87 | | : | | : | |
88 +-------+ : +--------+ : +-------+
89 ^ : ^ : ^
90 | : | : |
91 | : | : |
92 | : v : |
93 | : +--------+ : |
94 | : | | : |
95 | : | | : |
96 +---------->| Device |<----------+
97 : | | :
98 : | | :
99 : +--------+ :
100 : :
101
102Each CPU executes a program that generates memory access operations. In the
103abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
104perform the memory operations in any order it likes, provided program causality
105appears to be maintained. Similarly, the compiler may also arrange the
106instructions it emits in any order it likes, provided it doesn't affect the
107apparent operation of the program.
108
109So in the above diagram, the effects of the memory operations performed by a
110CPU are perceived by the rest of the system as the operations cross the
111interface between the CPU and rest of the system (the dotted lines).
112
113
114For example, consider the following sequence of events:
115
116 CPU 1 CPU 2
117 =============== ===============
118 { A == 1; B == 2 }
Alexey Dobriyan615cc2c2014-06-06 14:36:41 -0700119 A = 3; x = B;
120 B = 4; y = A;
David Howells108b42b2006-03-31 16:00:29 +0100121
122The set of accesses as seen by the memory system in the middle can be arranged
123in 24 different combinations:
124
Pranith Kumar8ab8b3e2014-09-02 23:34:29 -0400125 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
126 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
127 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
128 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
129 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
130 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
131 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
David Howells108b42b2006-03-31 16:00:29 +0100132 STORE B=4, ...
133 ...
134
135and can thus result in four different combinations of values:
136
Pranith Kumar8ab8b3e2014-09-02 23:34:29 -0400137 x == 2, y == 1
138 x == 2, y == 3
139 x == 4, y == 1
140 x == 4, y == 3
David Howells108b42b2006-03-31 16:00:29 +0100141
142
143Furthermore, the stores committed by a CPU to the memory system may not be
144perceived by the loads made by another CPU in the same order as the stores were
145committed.
146
147
148As a further example, consider this sequence of events:
149
150 CPU 1 CPU 2
151 =============== ===============
SeongJae Park3dbf0912016-04-12 08:52:52 -0700152 { A == 1, B == 2, C == 3, P == &A, Q == &C }
David Howells108b42b2006-03-31 16:00:29 +0100153 B = 4; Q = P;
154 P = &B D = *Q;
155
156There is an obvious data dependency here, as the value loaded into D depends on
157the address retrieved from P by CPU 2. At the end of the sequence, any of the
158following results are possible:
159
160 (Q == &A) and (D == 1)
161 (Q == &B) and (D == 2)
162 (Q == &B) and (D == 4)
163
164Note that CPU 2 will never try and load C into D because the CPU will load P
165into Q before issuing the load of *Q.
166
167
168DEVICE OPERATIONS
169-----------------
170
171Some devices present their control interfaces as collections of memory
172locations, but the order in which the control registers are accessed is very
173important. For instance, imagine an ethernet card with a set of internal
174registers that are accessed through an address port register (A) and a data
175port register (D). To read internal register 5, the following code might then
176be used:
177
178 *A = 5;
179 x = *D;
180
181but this might show up as either of the following two sequences:
182
183 STORE *A = 5, x = LOAD *D
184 x = LOAD *D, STORE *A = 5
185
186the second of which will almost certainly result in a malfunction, since it set
187the address _after_ attempting to read the register.
188
189
190GUARANTEES
191----------
192
193There are some minimal guarantees that may be expected of a CPU:
194
195 (*) On any given CPU, dependent memory accesses will be issued in order, with
196 respect to itself. This means that for:
197
Chris Metcalff84cfbb2015-11-23 17:04:17 -0500198 Q = READ_ONCE(P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
David Howells108b42b2006-03-31 16:00:29 +0100199
200 the CPU will issue the following memory operations:
201
202 Q = LOAD P, D = LOAD *Q
203
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800204 and always in that order. On most systems, smp_read_barrier_depends()
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700205 does nothing, but it is required for DEC Alpha. The READ_ONCE()
Chris Metcalff84cfbb2015-11-23 17:04:17 -0500206 is required to prevent compiler mischief. Please note that you
207 should normally use something like rcu_dereference() instead of
208 open-coding smp_read_barrier_depends().
David Howells108b42b2006-03-31 16:00:29 +0100209
210 (*) Overlapping loads and stores within a particular CPU will appear to be
211 ordered within that CPU. This means that for:
212
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700213 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
David Howells108b42b2006-03-31 16:00:29 +0100214
215 the CPU will only issue the following sequence of memory operations:
216
217 a = LOAD *X, STORE *X = b
218
219 And for:
220
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700221 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
David Howells108b42b2006-03-31 16:00:29 +0100222
223 the CPU will only issue:
224
225 STORE *X = c, d = LOAD *X
226
Matt LaPlantefa00e7e2006-11-30 04:55:36 +0100227 (Loads and stores overlap if they are targeted at overlapping pieces of
David Howells108b42b2006-03-31 16:00:29 +0100228 memory).
229
230And there are a number of things that _must_ or _must_not_ be assumed:
231
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700232 (*) It _must_not_ be assumed that the compiler will do what you want
233 with memory references that are not protected by READ_ONCE() and
234 WRITE_ONCE(). Without them, the compiler is within its rights to
235 do all sorts of "creative" transformations, which are covered in
Paul E. McKenney895f5542016-01-06 14:23:03 -0800236 the COMPILER BARRIER section.
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800237
David Howells108b42b2006-03-31 16:00:29 +0100238 (*) It _must_not_ be assumed that independent loads and stores will be issued
239 in the order given. This means that for:
240
241 X = *A; Y = *B; *D = Z;
242
243 we may get any of the following sequences:
244
245 X = LOAD *A, Y = LOAD *B, STORE *D = Z
246 X = LOAD *A, STORE *D = Z, Y = LOAD *B
247 Y = LOAD *B, X = LOAD *A, STORE *D = Z
248 Y = LOAD *B, STORE *D = Z, X = LOAD *A
249 STORE *D = Z, X = LOAD *A, Y = LOAD *B
250 STORE *D = Z, Y = LOAD *B, X = LOAD *A
251
252 (*) It _must_ be assumed that overlapping memory accesses may be merged or
253 discarded. This means that for:
254
255 X = *A; Y = *(A + 4);
256
257 we may get any one of the following sequences:
258
259 X = LOAD *A; Y = LOAD *(A + 4);
260 Y = LOAD *(A + 4); X = LOAD *A;
261 {X, Y} = LOAD {*A, *(A + 4) };
262
263 And for:
264
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700265 *A = X; *(A + 4) = Y;
David Howells108b42b2006-03-31 16:00:29 +0100266
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700267 we may get any of:
David Howells108b42b2006-03-31 16:00:29 +0100268
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700269 STORE *A = X; STORE *(A + 4) = Y;
270 STORE *(A + 4) = Y; STORE *A = X;
271 STORE {*A, *(A + 4) } = {X, Y};
David Howells108b42b2006-03-31 16:00:29 +0100272
Paul E. McKenney432fbf32014-09-04 17:12:49 -0700273And there are anti-guarantees:
274
275 (*) These guarantees do not apply to bitfields, because compilers often
276 generate code to modify these using non-atomic read-modify-write
277 sequences. Do not attempt to use bitfields to synchronize parallel
278 algorithms.
279
280 (*) Even in cases where bitfields are protected by locks, all fields
281 in a given bitfield must be protected by one lock. If two fields
282 in a given bitfield are protected by different locks, the compiler's
283 non-atomic read-modify-write sequences can cause an update to one
284 field to corrupt the value of an adjacent field.
285
286 (*) These guarantees apply only to properly aligned and sized scalar
287 variables. "Properly sized" currently means variables that are
288 the same size as "char", "short", "int" and "long". "Properly
289 aligned" means the natural alignment, thus no constraints for
290 "char", two-byte alignment for "short", four-byte alignment for
291 "int", and either four-byte or eight-byte alignment for "long",
292 on 32-bit and 64-bit systems, respectively. Note that these
293 guarantees were introduced into the C11 standard, so beware when
294 using older pre-C11 compilers (for example, gcc 4.6). The portion
295 of the standard containing this guarantee is Section 3.14, which
296 defines "memory location" as follows:
297
298 memory location
299 either an object of scalar type, or a maximal sequence
300 of adjacent bit-fields all having nonzero width
301
302 NOTE 1: Two threads of execution can update and access
303 separate memory locations without interfering with
304 each other.
305
306 NOTE 2: A bit-field and an adjacent non-bit-field member
307 are in separate memory locations. The same applies
308 to two bit-fields, if one is declared inside a nested
309 structure declaration and the other is not, or if the two
310 are separated by a zero-length bit-field declaration,
311 or if they are separated by a non-bit-field member
312 declaration. It is not safe to concurrently update two
313 bit-fields in the same structure if all members declared
314 between them are also bit-fields, no matter what the
315 sizes of those intervening bit-fields happen to be.
316
David Howells108b42b2006-03-31 16:00:29 +0100317
318=========================
319WHAT ARE MEMORY BARRIERS?
320=========================
321
322As can be seen above, independent memory operations are effectively performed
323in random order, but this can be a problem for CPU-CPU interaction and for I/O.
324What is required is some way of intervening to instruct the compiler and the
325CPU to restrict the order.
326
327Memory barriers are such interventions. They impose a perceived partial
David Howells2b948952006-06-25 05:48:49 -0700328ordering over the memory operations on either side of the barrier.
329
330Such enforcement is important because the CPUs and other devices in a system
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700331can use a variety of tricks to improve performance, including reordering,
David Howells2b948952006-06-25 05:48:49 -0700332deferral and combination of memory operations; speculative loads; speculative
333branch prediction and various types of caching. Memory barriers are used to
334override or suppress these tricks, allowing the code to sanely control the
335interaction of multiple CPUs and/or devices.
David Howells108b42b2006-03-31 16:00:29 +0100336
337
338VARIETIES OF MEMORY BARRIER
339---------------------------
340
341Memory barriers come in four basic varieties:
342
343 (1) Write (or store) memory barriers.
344
345 A write memory barrier gives a guarantee that all the STORE operations
346 specified before the barrier will appear to happen before all the STORE
347 operations specified after the barrier with respect to the other
348 components of the system.
349
350 A write barrier is a partial ordering on stores only; it is not required
351 to have any effect on loads.
352
David Howells6bc39272006-06-25 05:49:22 -0700353 A CPU can be viewed as committing a sequence of store operations to the
David Howells108b42b2006-03-31 16:00:29 +0100354 memory system as time progresses. All stores before a write barrier will
355 occur in the sequence _before_ all the stores after the write barrier.
356
357 [!] Note that write barriers should normally be paired with read or data
358 dependency barriers; see the "SMP barrier pairing" subsection.
359
360
361 (2) Data dependency barriers.
362
363 A data dependency barrier is a weaker form of read barrier. In the case
364 where two loads are performed such that the second depends on the result
365 of the first (eg: the first load retrieves the address to which the second
366 load will be directed), a data dependency barrier would be required to
367 make sure that the target of the second load is updated before the address
368 obtained by the first load is accessed.
369
370 A data dependency barrier is a partial ordering on interdependent loads
371 only; it is not required to have any effect on stores, independent loads
372 or overlapping loads.
373
374 As mentioned in (1), the other CPUs in the system can be viewed as
375 committing sequences of stores to the memory system that the CPU being
376 considered can then perceive. A data dependency barrier issued by the CPU
377 under consideration guarantees that for any load preceding it, if that
378 load touches one of a sequence of stores from another CPU, then by the
379 time the barrier completes, the effects of all the stores prior to that
380 touched by the load will be perceptible to any loads issued after the data
381 dependency barrier.
382
383 See the "Examples of memory barrier sequences" subsection for diagrams
384 showing the ordering constraints.
385
386 [!] Note that the first load really has to have a _data_ dependency and
387 not a control dependency. If the address for the second load is dependent
388 on the first load, but the dependency is through a conditional rather than
389 actually loading the address itself, then it's a _control_ dependency and
390 a full read barrier or better is required. See the "Control dependencies"
391 subsection for more information.
392
393 [!] Note that data dependency barriers should normally be paired with
394 write barriers; see the "SMP barrier pairing" subsection.
395
396
397 (3) Read (or load) memory barriers.
398
399 A read barrier is a data dependency barrier plus a guarantee that all the
400 LOAD operations specified before the barrier will appear to happen before
401 all the LOAD operations specified after the barrier with respect to the
402 other components of the system.
403
404 A read barrier is a partial ordering on loads only; it is not required to
405 have any effect on stores.
406
407 Read memory barriers imply data dependency barriers, and so can substitute
408 for them.
409
410 [!] Note that read barriers should normally be paired with write barriers;
411 see the "SMP barrier pairing" subsection.
412
413
414 (4) General memory barriers.
415
David Howells670bd952006-06-10 09:54:12 -0700416 A general memory barrier gives a guarantee that all the LOAD and STORE
417 operations specified before the barrier will appear to happen before all
418 the LOAD and STORE operations specified after the barrier with respect to
419 the other components of the system.
420
421 A general memory barrier is a partial ordering over both loads and stores.
David Howells108b42b2006-03-31 16:00:29 +0100422
423 General memory barriers imply both read and write memory barriers, and so
424 can substitute for either.
425
426
427And a couple of implicit varieties:
428
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100429 (5) ACQUIRE operations.
David Howells108b42b2006-03-31 16:00:29 +0100430
431 This acts as a one-way permeable barrier. It guarantees that all memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100432 operations after the ACQUIRE operation will appear to happen after the
433 ACQUIRE operation with respect to the other components of the system.
434 ACQUIRE operations include LOCK operations and smp_load_acquire()
435 operations.
David Howells108b42b2006-03-31 16:00:29 +0100436
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100437 Memory operations that occur before an ACQUIRE operation may appear to
438 happen after it completes.
David Howells108b42b2006-03-31 16:00:29 +0100439
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100440 An ACQUIRE operation should almost always be paired with a RELEASE
441 operation.
David Howells108b42b2006-03-31 16:00:29 +0100442
443
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100444 (6) RELEASE operations.
David Howells108b42b2006-03-31 16:00:29 +0100445
446 This also acts as a one-way permeable barrier. It guarantees that all
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100447 memory operations before the RELEASE operation will appear to happen
448 before the RELEASE operation with respect to the other components of the
449 system. RELEASE operations include UNLOCK operations and
450 smp_store_release() operations.
David Howells108b42b2006-03-31 16:00:29 +0100451
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100452 Memory operations that occur after a RELEASE operation may appear to
David Howells108b42b2006-03-31 16:00:29 +0100453 happen before it completes.
454
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100455 The use of ACQUIRE and RELEASE operations generally precludes the need
456 for other sorts of memory barrier (but note the exceptions mentioned in
457 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
458 pair is -not- guaranteed to act as a full memory barrier. However, after
459 an ACQUIRE on a given variable, all memory accesses preceding any prior
460 RELEASE on that same variable are guaranteed to be visible. In other
461 words, within a given variable's critical section, all accesses of all
462 previous critical sections for that variable are guaranteed to have
463 completed.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -0800464
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100465 This means that ACQUIRE acts as a minimal "acquire" operation and
466 RELEASE acts as a minimal "release" operation.
David Howells108b42b2006-03-31 16:00:29 +0100467
468
469Memory barriers are only required where there's a possibility of interaction
470between two CPUs or between a CPU and a device. If it can be guaranteed that
471there won't be any such interaction in any particular piece of code, then
472memory barriers are unnecessary in that piece of code.
473
474
475Note that these are the _minimum_ guarantees. Different architectures may give
476more substantial guarantees, but they may _not_ be relied upon outside of arch
477specific code.
478
479
480WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
481----------------------------------------------
482
483There are certain things that the Linux kernel memory barriers do not guarantee:
484
485 (*) There is no guarantee that any of the memory accesses specified before a
486 memory barrier will be _complete_ by the completion of a memory barrier
487 instruction; the barrier can be considered to draw a line in that CPU's
488 access queue that accesses of the appropriate type may not cross.
489
490 (*) There is no guarantee that issuing a memory barrier on one CPU will have
491 any direct effect on another CPU or any other hardware in the system. The
492 indirect effect will be the order in which the second CPU sees the effects
493 of the first CPU's accesses occur, but see the next point:
494
David Howells6bc39272006-06-25 05:49:22 -0700495 (*) There is no guarantee that a CPU will see the correct order of effects
David Howells108b42b2006-03-31 16:00:29 +0100496 from a second CPU's accesses, even _if_ the second CPU uses a memory
497 barrier, unless the first CPU _also_ uses a matching memory barrier (see
498 the subsection on "SMP Barrier Pairing").
499
500 (*) There is no guarantee that some intervening piece of off-the-CPU
501 hardware[*] will not reorder the memory accesses. CPU cache coherency
502 mechanisms should propagate the indirect effects of a memory barrier
503 between CPUs, but might not do so in order.
504
505 [*] For information on bus mastering DMA and coherency please read:
506
Randy Dunlap4b5ff462008-03-10 17:16:32 -0700507 Documentation/PCI/pci.txt
Paul Bolle395cf962011-08-15 02:02:26 +0200508 Documentation/DMA-API-HOWTO.txt
David Howells108b42b2006-03-31 16:00:29 +0100509 Documentation/DMA-API.txt
510
511
512DATA DEPENDENCY BARRIERS
513------------------------
514
515The usage requirements of data dependency barriers are a little subtle, and
516it's not always obvious that they're needed. To illustrate, consider the
517following sequence of events:
518
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800519 CPU 1 CPU 2
520 =============== ===============
SeongJae Park3dbf0912016-04-12 08:52:52 -0700521 { A == 1, B == 2, C == 3, P == &A, Q == &C }
David Howells108b42b2006-03-31 16:00:29 +0100522 B = 4;
523 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700524 WRITE_ONCE(P, &B)
525 Q = READ_ONCE(P);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800526 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100527
528There's a clear data dependency here, and it would seem that by the end of the
529sequence, Q must be either &A or &B, and that:
530
531 (Q == &A) implies (D == 1)
532 (Q == &B) implies (D == 4)
533
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700534But! CPU 2's perception of P may be updated _before_ its perception of B, thus
David Howells108b42b2006-03-31 16:00:29 +0100535leading to the following situation:
536
537 (Q == &B) and (D == 2) ????
538
539Whilst this may seem like a failure of coherency or causality maintenance, it
540isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
541Alpha).
542
David Howells2b948952006-06-25 05:48:49 -0700543To deal with this, a data dependency barrier or better must be inserted
544between the address load and the data load:
David Howells108b42b2006-03-31 16:00:29 +0100545
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800546 CPU 1 CPU 2
547 =============== ===============
SeongJae Park3dbf0912016-04-12 08:52:52 -0700548 { A == 1, B == 2, C == 3, P == &A, Q == &C }
David Howells108b42b2006-03-31 16:00:29 +0100549 B = 4;
550 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700551 WRITE_ONCE(P, &B);
552 Q = READ_ONCE(P);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800553 <data dependency barrier>
554 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100555
556This enforces the occurrence of one of the two implications, and prevents the
557third possibility from arising.
558
Paul E. McKenney92a84dd2016-01-14 14:17:04 -0800559A data-dependency barrier must also order against dependent writes:
560
561 CPU 1 CPU 2
562 =============== ===============
563 { A == 1, B == 2, C = 3, P == &A, Q == &C }
564 B = 4;
565 <write barrier>
566 WRITE_ONCE(P, &B);
567 Q = READ_ONCE(P);
568 <data dependency barrier>
569 *Q = 5;
570
571The data-dependency barrier must order the read into Q with the store
572into *Q. This prohibits this outcome:
573
574 (Q == B) && (B == 4)
575
576Please note that this pattern should be rare. After all, the whole point
577of dependency ordering is to -prevent- writes to the data structure, along
578with the expensive cache misses associated with those writes. This pattern
579can be used to record rare error conditions and the like, and the ordering
580prevents such records from being lost.
581
582
David Howells108b42b2006-03-31 16:00:29 +0100583[!] Note that this extremely counterintuitive situation arises most easily on
584machines with split caches, so that, for example, one cache bank processes
585even-numbered cache lines and the other bank processes odd-numbered cache
586lines. The pointer P might be stored in an odd-numbered cache line, and the
587variable B might be stored in an even-numbered cache line. Then, if the
588even-numbered bank of the reading CPU's cache is extremely busy while the
589odd-numbered bank is idle, one can see the new value of the pointer P (&B),
David Howells6bc39272006-06-25 05:49:22 -0700590but the old value of the variable B (2).
David Howells108b42b2006-03-31 16:00:29 +0100591
592
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800593The data dependency barrier is very important to the RCU system,
594for example. See rcu_assign_pointer() and rcu_dereference() in
595include/linux/rcupdate.h. This permits the current target of an RCU'd
596pointer to be replaced with a new modified target, without the replacement
597target appearing to be incompletely initialised.
David Howells108b42b2006-03-31 16:00:29 +0100598
599See also the subsection on "Cache Coherency" for a more thorough example.
600
601
602CONTROL DEPENDENCIES
603--------------------
604
Paul E. McKenneyff382812015-02-17 10:00:06 -0800605A load-load control dependency requires a full read memory barrier, not
606simply a data dependency barrier to make it work correctly. Consider the
607following bit of code:
David Howells108b42b2006-03-31 16:00:29 +0100608
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700609 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800610 if (q) {
611 <data dependency barrier> /* BUG: No data dependency!!! */
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700612 p = READ_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700613 }
David Howells108b42b2006-03-31 16:00:29 +0100614
615This will not have the desired effect because there is no actual data
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800616dependency, but rather a control dependency that the CPU may short-circuit
617by attempting to predict the outcome in advance, so that other CPUs see
618the load from b as having happened before the load from a. In such a
619case what's actually required is:
David Howells108b42b2006-03-31 16:00:29 +0100620
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700621 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800622 if (q) {
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700623 <read barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700624 p = READ_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700625 }
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800626
627However, stores are not speculated. This means that ordering -is- provided
Paul E. McKenneyff382812015-02-17 10:00:06 -0800628for load-store control dependencies, as in the following example:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800629
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800630 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700631 if (q) {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700632 WRITE_ONCE(b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800633 }
634
Paul E. McKenney5af46922015-04-25 12:48:29 -0700635Control dependencies pair normally with other types of barriers. That
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800636said, please note that READ_ONCE() is not optional! Without the
637READ_ONCE(), the compiler might combine the load from 'a' with other
638loads from 'a', and the store to 'b' with other stores to 'b', with
639possible highly counterintuitive effects on ordering.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800640
641Worse yet, if the compiler is able to prove (say) that the value of
642variable 'a' is always non-zero, it would be well within its rights
643to optimize the original example by eliminating the "if" statement
644as follows:
645
646 q = a;
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700647 b = p; /* BUG: Compiler and CPU can both reorder!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800648
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800649So don't leave out the READ_ONCE().
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700650
651It is tempting to try to enforce ordering on identical stores on both
652branches of the "if" statement as follows:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800653
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800654 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800655 if (q) {
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800656 barrier();
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700657 WRITE_ONCE(b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800658 do_something();
659 } else {
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800660 barrier();
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700661 WRITE_ONCE(b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800662 do_something_else();
663 }
664
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700665Unfortunately, current compilers will transform this as follows at high
666optimization levels:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800667
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800668 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700669 barrier();
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700670 WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800671 if (q) {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700672 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800673 do_something();
674 } else {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700675 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800676 do_something_else();
677 }
678
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700679Now there is no conditional between the load from 'a' and the store to
680'b', which means that the CPU is within its rights to reorder them:
681The conditional is absolutely required, and must be present in the
682assembly code even after all compiler optimizations have been applied.
683Therefore, if you need ordering in this example, you need explicit
684memory barriers, for example, smp_store_release():
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800685
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700686 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700687 if (q) {
688 smp_store_release(&b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800689 do_something();
690 } else {
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700691 smp_store_release(&b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800692 do_something_else();
693 }
694
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700695In contrast, without explicit memory barriers, two-legged-if control
696ordering is guaranteed only when the stores differ, for example:
697
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800698 q = READ_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700699 if (q) {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700700 WRITE_ONCE(b, p);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700701 do_something();
702 } else {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700703 WRITE_ONCE(b, r);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700704 do_something_else();
705 }
706
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800707The initial READ_ONCE() is still required to prevent the compiler from
708proving the value of 'a'.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800709
710In addition, you need to be careful what you do with the local variable 'q',
711otherwise the compiler might be able to guess the value and again remove
712the needed conditional. For example:
713
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800714 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800715 if (q % MAX) {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700716 WRITE_ONCE(b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800717 do_something();
718 } else {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700719 WRITE_ONCE(b, r);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800720 do_something_else();
721 }
722
723If MAX is defined to be 1, then the compiler knows that (q % MAX) is
724equal to zero, in which case the compiler is within its rights to
725transform the above code into the following:
726
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800727 q = READ_ONCE(a);
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700728 WRITE_ONCE(b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800729 do_something_else();
730
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700731Given this transformation, the CPU is not required to respect the ordering
732between the load from variable 'a' and the store to variable 'b'. It is
733tempting to add a barrier(), but this does not help. The conditional
734is gone, and the barrier won't bring it back. Therefore, if you are
735relying on this ordering, you should make sure that MAX is greater than
736one, perhaps as follows:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800737
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800738 q = READ_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800739 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
740 if (q % MAX) {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700741 WRITE_ONCE(b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800742 do_something();
743 } else {
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700744 WRITE_ONCE(b, r);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800745 do_something_else();
746 }
747
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700748Please note once again that the stores to 'b' differ. If they were
749identical, as noted earlier, the compiler could pull this store outside
750of the 'if' statement.
751
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700752You must also be careful not to rely too much on boolean short-circuit
753evaluation. Consider this example:
754
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800755 q = READ_ONCE(a);
Paul E. McKenney57aecae2015-05-18 18:27:42 -0700756 if (q || 1 > 0)
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700757 WRITE_ONCE(b, 1);
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700758
Paul E. McKenney5af46922015-04-25 12:48:29 -0700759Because the first condition cannot fault and the second condition is
760always true, the compiler can transform this example as following,
761defeating control dependency:
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700762
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800763 q = READ_ONCE(a);
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700764 WRITE_ONCE(b, 1);
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700765
766This example underscores the need to ensure that the compiler cannot
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700767out-guess your code. More generally, although READ_ONCE() does force
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700768the compiler to actually emit code for a given load, it does not force
769the compiler to use the results.
770
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800771Finally, control dependencies do -not- provide transitivity. This is
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700772demonstrated by two related examples, with the initial values of
773x and y both being zero:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800774
775 CPU 0 CPU 1
Paul E. McKenney5af46922015-04-25 12:48:29 -0700776 ======================= =======================
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800777 r1 = READ_ONCE(x); r2 = READ_ONCE(y);
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700778 if (r1 > 0) if (r2 > 0)
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700779 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800780
781 assert(!(r1 == 1 && r2 == 1));
782
783The above two-CPU example will never trigger the assert(). However,
784if control dependencies guaranteed transitivity (which they do not),
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700785then adding the following CPU would guarantee a related assertion:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800786
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700787 CPU 2
788 =====================
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700789 WRITE_ONCE(x, 2);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800790
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700791 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800792
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700793But because control dependencies do -not- provide transitivity, the above
794assertion can fail after the combined three-CPU example completes. If you
795need the three-CPU example to provide ordering, you will need smp_mb()
796between the loads and stores in the CPU 0 and CPU 1 code fragments,
Paul E. McKenney5af46922015-04-25 12:48:29 -0700797that is, just before or just after the "if" statements. Furthermore,
798the original two-CPU example is very fragile and should be avoided.
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700799
800These two examples are the LB and WWC litmus tests from this paper:
801http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
802site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800803
804In summary:
805
806 (*) Control dependencies can order prior loads against later stores.
807 However, they do -not- guarantee any other sort of ordering:
808 Not prior loads against later loads, nor prior stores against
809 later anything. If you need these other forms of ordering,
Davidlohr Buesod87510c2014-12-28 01:11:16 -0800810 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800811 later loads, smp_mb().
812
Paul E. McKenney7817b792015-12-29 16:23:18 -0800813 (*) If both legs of the "if" statement begin with identical stores to
814 the same variable, then those stores must be ordered, either by
815 preceding both of them with smp_mb() or by using smp_store_release()
816 to carry out the stores. Please note that it is -not- sufficient
Paul E. McKenneya5052652016-04-12 08:52:49 -0700817 to use barrier() at beginning of each leg of the "if" statement
818 because, as shown by the example above, optimizing compilers can
819 destroy the control dependency while respecting the letter of the
820 barrier() law.
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800821
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800822 (*) Control dependencies require at least one run-time conditional
Paul E. McKenney586dd562014-02-11 12:28:06 -0800823 between the prior load and the subsequent store, and this
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700824 conditional must involve the prior load. If the compiler is able
825 to optimize the conditional away, it will have also optimized
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800826 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
827 can help to preserve the needed conditional.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800828
829 (*) Control dependencies require that the compiler avoid reordering the
Linus Torvalds105ff3c2015-11-03 17:22:17 -0800830 dependency into nonexistence. Careful use of READ_ONCE() or
831 atomic{,64}_read() can help to preserve your control dependency.
Paul E. McKenney895f5542016-01-06 14:23:03 -0800832 Please see the COMPILER BARRIER section for more information.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800833
Paul E. McKenneyff382812015-02-17 10:00:06 -0800834 (*) Control dependencies pair normally with other types of barriers.
835
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800836 (*) Control dependencies do -not- provide transitivity. If you
837 need transitivity, use smp_mb().
David Howells108b42b2006-03-31 16:00:29 +0100838
839
840SMP BARRIER PAIRING
841-------------------
842
843When dealing with CPU-CPU interactions, certain types of memory barrier should
844always be paired. A lack of appropriate pairing is almost certainly an error.
845
Paul E. McKenneyff382812015-02-17 10:00:06 -0800846General barriers pair with each other, though they also pair with most
847other types of barriers, albeit without transitivity. An acquire barrier
848pairs with a release barrier, but both may also pair with other barriers,
849including of course general barriers. A write barrier pairs with a data
850dependency barrier, a control dependency, an acquire barrier, a release
851barrier, a read barrier, or a general barrier. Similarly a read barrier,
852control dependency, or a data dependency barrier pairs with a write
853barrier, an acquire barrier, a release barrier, or a general barrier:
David Howells108b42b2006-03-31 16:00:29 +0100854
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800855 CPU 1 CPU 2
856 =============== ===============
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700857 WRITE_ONCE(a, 1);
David Howells108b42b2006-03-31 16:00:29 +0100858 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700859 WRITE_ONCE(b, 2); x = READ_ONCE(b);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800860 <read barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700861 y = READ_ONCE(a);
David Howells108b42b2006-03-31 16:00:29 +0100862
863Or:
864
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800865 CPU 1 CPU 2
866 =============== ===============================
David Howells108b42b2006-03-31 16:00:29 +0100867 a = 1;
868 <write barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700869 WRITE_ONCE(b, &a); x = READ_ONCE(b);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800870 <data dependency barrier>
871 y = *x;
David Howells108b42b2006-03-31 16:00:29 +0100872
Paul E. McKenneyff382812015-02-17 10:00:06 -0800873Or even:
874
875 CPU 1 CPU 2
876 =============== ===============================
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700877 r1 = READ_ONCE(y);
Paul E. McKenneyff382812015-02-17 10:00:06 -0800878 <general barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700879 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
Paul E. McKenneyff382812015-02-17 10:00:06 -0800880 <implicit control dependency>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700881 WRITE_ONCE(y, 1);
Paul E. McKenneyff382812015-02-17 10:00:06 -0800882 }
883
884 assert(r1 == 0 || r2 == 0);
885
David Howells108b42b2006-03-31 16:00:29 +0100886Basically, the read barrier always has to be there, even though it can be of
887the "weaker" type.
888
David Howells670bd952006-06-10 09:54:12 -0700889[!] Note that the stores before the write barrier would normally be expected to
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700890match the loads after the read barrier or the data dependency barrier, and vice
David Howells670bd952006-06-10 09:54:12 -0700891versa:
892
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800893 CPU 1 CPU 2
894 =================== ===================
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700895 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
896 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800897 <write barrier> \ <read barrier>
Paul E. McKenney9af194c2015-06-18 14:33:24 -0700898 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
899 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
David Howells670bd952006-06-10 09:54:12 -0700900
David Howells108b42b2006-03-31 16:00:29 +0100901
902EXAMPLES OF MEMORY BARRIER SEQUENCES
903------------------------------------
904
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700905Firstly, write barriers act as partial orderings on store operations.
David Howells108b42b2006-03-31 16:00:29 +0100906Consider the following sequence of events:
907
908 CPU 1
909 =======================
910 STORE A = 1
911 STORE B = 2
912 STORE C = 3
913 <write barrier>
914 STORE D = 4
915 STORE E = 5
916
917This sequence of events is committed to the memory coherence system in an order
918that the rest of the system might perceive as the unordered set of { STORE A,
Adrian Bunk80f72282006-06-30 18:27:16 +0200919STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
David Howells108b42b2006-03-31 16:00:29 +0100920}:
921
922 +-------+ : :
923 | | +------+
924 | |------>| C=3 | } /\
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700925 | | : +------+ }----- \ -----> Events perceptible to
926 | | : | A=1 | } \/ the rest of the system
David Howells108b42b2006-03-31 16:00:29 +0100927 | | : +------+ }
928 | CPU 1 | : | B=2 | }
929 | | +------+ }
930 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
931 | | +------+ } requires all stores prior to the
932 | | : | E=5 | } barrier to be committed before
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700933 | | : +------+ } further stores may take place
David Howells108b42b2006-03-31 16:00:29 +0100934 | |------>| D=4 | }
935 | | +------+
936 +-------+ : :
937 |
David Howells670bd952006-06-10 09:54:12 -0700938 | Sequence in which stores are committed to the
939 | memory system by CPU 1
David Howells108b42b2006-03-31 16:00:29 +0100940 V
941
942
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700943Secondly, data dependency barriers act as partial orderings on data-dependent
David Howells108b42b2006-03-31 16:00:29 +0100944loads. Consider the following sequence of events:
945
946 CPU 1 CPU 2
947 ======================= =======================
David Howellsc14038c2006-04-10 22:54:24 -0700948 { B = 7; X = 9; Y = 8; C = &Y }
David Howells108b42b2006-03-31 16:00:29 +0100949 STORE A = 1
950 STORE B = 2
951 <write barrier>
952 STORE C = &B LOAD X
953 STORE D = 4 LOAD C (gets &B)
954 LOAD *C (reads B)
955
956Without intervention, CPU 2 may perceive the events on CPU 1 in some
957effectively random order, despite the write barrier issued by CPU 1:
958
959 +-------+ : : : :
960 | | +------+ +-------+ | Sequence of update
961 | |------>| B=2 |----- --->| Y->8 | | of perception on
962 | | : +------+ \ +-------+ | CPU 2
963 | CPU 1 | : | A=1 | \ --->| C->&Y | V
964 | | +------+ | +-------+
965 | | wwwwwwwwwwwwwwww | : :
966 | | +------+ | : :
967 | | : | C=&B |--- | : : +-------+
968 | | : +------+ \ | +-------+ | |
969 | |------>| D=4 | ----------->| C->&B |------>| |
970 | | +------+ | +-------+ | |
971 +-------+ : : | : : | |
972 | : : | |
973 | : : | CPU 2 |
974 | +-------+ | |
975 Apparently incorrect ---> | | B->7 |------>| |
976 perception of B (!) | +-------+ | |
977 | : : | |
978 | +-------+ | |
979 The load of X holds ---> \ | X->9 |------>| |
980 up the maintenance \ +-------+ | |
981 of coherence of B ----->| B->2 | +-------+
982 +-------+
983 : :
984
985
986In the above example, CPU 2 perceives that B is 7, despite the load of *C
Paolo Ornati670e9f32006-10-03 22:57:56 +0200987(which would be B) coming after the LOAD of C.
David Howells108b42b2006-03-31 16:00:29 +0100988
989If, however, a data dependency barrier were to be placed between the load of C
David Howellsc14038c2006-04-10 22:54:24 -0700990and the load of *C (ie: B) on CPU 2:
991
992 CPU 1 CPU 2
993 ======================= =======================
994 { B = 7; X = 9; Y = 8; C = &Y }
995 STORE A = 1
996 STORE B = 2
997 <write barrier>
998 STORE C = &B LOAD X
999 STORE D = 4 LOAD C (gets &B)
1000 <data dependency barrier>
1001 LOAD *C (reads B)
1002
1003then the following will occur:
David Howells108b42b2006-03-31 16:00:29 +01001004
1005 +-------+ : : : :
1006 | | +------+ +-------+
1007 | |------>| B=2 |----- --->| Y->8 |
1008 | | : +------+ \ +-------+
1009 | CPU 1 | : | A=1 | \ --->| C->&Y |
1010 | | +------+ | +-------+
1011 | | wwwwwwwwwwwwwwww | : :
1012 | | +------+ | : :
1013 | | : | C=&B |--- | : : +-------+
1014 | | : +------+ \ | +-------+ | |
1015 | |------>| D=4 | ----------->| C->&B |------>| |
1016 | | +------+ | +-------+ | |
1017 +-------+ : : | : : | |
1018 | : : | |
1019 | : : | CPU 2 |
1020 | +-------+ | |
David Howells670bd952006-06-10 09:54:12 -07001021 | | X->9 |------>| |
1022 | +-------+ | |
1023 Makes sure all effects ---> \ ddddddddddddddddd | |
1024 prior to the store of C \ +-------+ | |
1025 are perceptible to ----->| B->2 |------>| |
1026 subsequent loads +-------+ | |
David Howells108b42b2006-03-31 16:00:29 +01001027 : : +-------+
1028
1029
1030And thirdly, a read barrier acts as a partial order on loads. Consider the
1031following sequence of events:
1032
1033 CPU 1 CPU 2
1034 ======================= =======================
David Howells670bd952006-06-10 09:54:12 -07001035 { A = 0, B = 9 }
David Howells108b42b2006-03-31 16:00:29 +01001036 STORE A=1
David Howells108b42b2006-03-31 16:00:29 +01001037 <write barrier>
David Howells670bd952006-06-10 09:54:12 -07001038 STORE B=2
David Howells108b42b2006-03-31 16:00:29 +01001039 LOAD B
David Howells670bd952006-06-10 09:54:12 -07001040 LOAD A
David Howells108b42b2006-03-31 16:00:29 +01001041
1042Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1043some effectively random order, despite the write barrier issued by CPU 1:
1044
David Howells670bd952006-06-10 09:54:12 -07001045 +-------+ : : : :
1046 | | +------+ +-------+
1047 | |------>| A=1 |------ --->| A->0 |
1048 | | +------+ \ +-------+
1049 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1050 | | +------+ | +-------+
1051 | |------>| B=2 |--- | : :
1052 | | +------+ \ | : : +-------+
1053 +-------+ : : \ | +-------+ | |
1054 ---------->| B->2 |------>| |
1055 | +-------+ | CPU 2 |
1056 | | A->0 |------>| |
1057 | +-------+ | |
1058 | : : +-------+
1059 \ : :
1060 \ +-------+
1061 ---->| A->1 |
1062 +-------+
1063 : :
David Howells108b42b2006-03-31 16:00:29 +01001064
1065
David Howells6bc39272006-06-25 05:49:22 -07001066If, however, a read barrier were to be placed between the load of B and the
David Howells670bd952006-06-10 09:54:12 -07001067load of A on CPU 2:
David Howells108b42b2006-03-31 16:00:29 +01001068
David Howells670bd952006-06-10 09:54:12 -07001069 CPU 1 CPU 2
1070 ======================= =======================
1071 { A = 0, B = 9 }
1072 STORE A=1
1073 <write barrier>
1074 STORE B=2
1075 LOAD B
1076 <read barrier>
1077 LOAD A
1078
1079then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
10802:
1081
1082 +-------+ : : : :
1083 | | +------+ +-------+
1084 | |------>| A=1 |------ --->| A->0 |
1085 | | +------+ \ +-------+
1086 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1087 | | +------+ | +-------+
1088 | |------>| B=2 |--- | : :
1089 | | +------+ \ | : : +-------+
1090 +-------+ : : \ | +-------+ | |
1091 ---------->| B->2 |------>| |
1092 | +-------+ | CPU 2 |
1093 | : : | |
1094 | : : | |
1095 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1096 barrier causes all effects \ +-------+ | |
1097 prior to the storage of B ---->| A->1 |------>| |
1098 to be perceptible to CPU 2 +-------+ | |
1099 : : +-------+
1100
1101
1102To illustrate this more completely, consider what could happen if the code
1103contained a load of A either side of the read barrier:
1104
1105 CPU 1 CPU 2
1106 ======================= =======================
1107 { A = 0, B = 9 }
1108 STORE A=1
1109 <write barrier>
1110 STORE B=2
1111 LOAD B
1112 LOAD A [first load of A]
1113 <read barrier>
1114 LOAD A [second load of A]
1115
1116Even though the two loads of A both occur after the load of B, they may both
1117come up with different values:
1118
1119 +-------+ : : : :
1120 | | +------+ +-------+
1121 | |------>| A=1 |------ --->| A->0 |
1122 | | +------+ \ +-------+
1123 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1124 | | +------+ | +-------+
1125 | |------>| B=2 |--- | : :
1126 | | +------+ \ | : : +-------+
1127 +-------+ : : \ | +-------+ | |
1128 ---------->| B->2 |------>| |
1129 | +-------+ | CPU 2 |
1130 | : : | |
1131 | : : | |
1132 | +-------+ | |
1133 | | A->0 |------>| 1st |
1134 | +-------+ | |
1135 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1136 barrier causes all effects \ +-------+ | |
1137 prior to the storage of B ---->| A->1 |------>| 2nd |
1138 to be perceptible to CPU 2 +-------+ | |
1139 : : +-------+
1140
1141
1142But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1143before the read barrier completes anyway:
1144
1145 +-------+ : : : :
1146 | | +------+ +-------+
1147 | |------>| A=1 |------ --->| A->0 |
1148 | | +------+ \ +-------+
1149 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1150 | | +------+ | +-------+
1151 | |------>| B=2 |--- | : :
1152 | | +------+ \ | : : +-------+
1153 +-------+ : : \ | +-------+ | |
1154 ---------->| B->2 |------>| |
1155 | +-------+ | CPU 2 |
1156 | : : | |
1157 \ : : | |
1158 \ +-------+ | |
1159 ---->| A->1 |------>| 1st |
1160 +-------+ | |
1161 rrrrrrrrrrrrrrrrr | |
1162 +-------+ | |
1163 | A->1 |------>| 2nd |
1164 +-------+ | |
1165 : : +-------+
1166
1167
1168The guarantee is that the second load will always come up with A == 1 if the
1169load of B came up with B == 2. No such guarantee exists for the first load of
1170A; that may come up with either A == 0 or A == 1.
1171
1172
1173READ MEMORY BARRIERS VS LOAD SPECULATION
1174----------------------------------------
1175
1176Many CPUs speculate with loads: that is they see that they will need to load an
1177item from memory, and they find a time where they're not using the bus for any
1178other loads, and so do the load in advance - even though they haven't actually
1179got to that point in the instruction execution flow yet. This permits the
1180actual load instruction to potentially complete immediately because the CPU
1181already has the value to hand.
1182
1183It may turn out that the CPU didn't actually need the value - perhaps because a
1184branch circumvented the load - in which case it can discard the value or just
1185cache it for later use.
1186
1187Consider:
1188
Ingo Molnare0edc782013-11-22 11:24:53 +01001189 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001190 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001191 LOAD B
1192 DIVIDE } Divide instructions generally
1193 DIVIDE } take a long time to perform
1194 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001195
1196Which might appear as this:
1197
1198 : : +-------+
1199 +-------+ | |
1200 --->| B->2 |------>| |
1201 +-------+ | CPU 2 |
1202 : :DIVIDE | |
1203 +-------+ | |
1204 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1205 division speculates on the +-------+ ~ | |
1206 LOAD of A : : ~ | |
1207 : :DIVIDE | |
1208 : : ~ | |
1209 Once the divisions are complete --> : : ~-->| |
1210 the CPU can then perform the : : | |
1211 LOAD with immediate effect : : +-------+
1212
1213
1214Placing a read barrier or a data dependency barrier just before the second
1215load:
1216
Ingo Molnare0edc782013-11-22 11:24:53 +01001217 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001218 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001219 LOAD B
1220 DIVIDE
1221 DIVIDE
David Howells670bd952006-06-10 09:54:12 -07001222 <read barrier>
Ingo Molnare0edc782013-11-22 11:24:53 +01001223 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001224
1225will force any value speculatively obtained to be reconsidered to an extent
1226dependent on the type of barrier used. If there was no change made to the
1227speculated memory location, then the speculated value will just be used:
1228
1229 : : +-------+
1230 +-------+ | |
1231 --->| B->2 |------>| |
1232 +-------+ | CPU 2 |
1233 : :DIVIDE | |
1234 +-------+ | |
1235 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1236 division speculates on the +-------+ ~ | |
1237 LOAD of A : : ~ | |
1238 : :DIVIDE | |
1239 : : ~ | |
1240 : : ~ | |
1241 rrrrrrrrrrrrrrrr~ | |
1242 : : ~ | |
1243 : : ~-->| |
1244 : : | |
1245 : : +-------+
1246
1247
1248but if there was an update or an invalidation from another CPU pending, then
1249the speculation will be cancelled and the value reloaded:
1250
1251 : : +-------+
1252 +-------+ | |
1253 --->| B->2 |------>| |
1254 +-------+ | CPU 2 |
1255 : :DIVIDE | |
1256 +-------+ | |
1257 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1258 division speculates on the +-------+ ~ | |
1259 LOAD of A : : ~ | |
1260 : :DIVIDE | |
1261 : : ~ | |
1262 : : ~ | |
1263 rrrrrrrrrrrrrrrrr | |
1264 +-------+ | |
1265 The speculation is discarded ---> --->| A->1 |------>| |
1266 and an updated value is +-------+ | |
1267 retrieved : : +-------+
David Howells108b42b2006-03-31 16:00:29 +01001268
1269
Paul E. McKenney241e6662011-02-10 16:54:50 -08001270TRANSITIVITY
1271------------
1272
1273Transitivity is a deeply intuitive notion about ordering that is not
1274always provided by real computer systems. The following example
Paul E. McKenneyf36fe1e2016-02-15 14:50:36 -08001275demonstrates transitivity:
Paul E. McKenney241e6662011-02-10 16:54:50 -08001276
1277 CPU 1 CPU 2 CPU 3
1278 ======================= ======================= =======================
1279 { X = 0, Y = 0 }
1280 STORE X=1 LOAD X STORE Y=1
1281 <general barrier> <general barrier>
1282 LOAD Y LOAD X
1283
1284Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1285This indicates that CPU 2's load from X in some sense follows CPU 1's
1286store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1287store to Y. The question is then "Can CPU 3's load from X return 0?"
1288
1289Because CPU 2's load from X in some sense came after CPU 1's store, it
1290is natural to expect that CPU 3's load from X must therefore return 1.
1291This expectation is an example of transitivity: if a load executing on
1292CPU A follows a load from the same variable executing on CPU B, then
1293CPU A's load must either return the same value that CPU B's load did,
1294or must return some later value.
1295
1296In the Linux kernel, use of general memory barriers guarantees
1297transitivity. Therefore, in the above example, if CPU 2's load from X
1298returns 1 and its load from Y returns 0, then CPU 3's load from X must
1299also return 1.
1300
1301However, transitivity is -not- guaranteed for read or write barriers.
1302For example, suppose that CPU 2's general barrier in the above example
1303is changed to a read barrier as shown below:
1304
1305 CPU 1 CPU 2 CPU 3
1306 ======================= ======================= =======================
1307 { X = 0, Y = 0 }
1308 STORE X=1 LOAD X STORE Y=1
1309 <read barrier> <general barrier>
1310 LOAD Y LOAD X
1311
1312This substitution destroys transitivity: in this example, it is perfectly
1313legal for CPU 2's load from X to return 1, its load from Y to return 0,
1314and CPU 3's load from X to return 0.
1315
1316The key point is that although CPU 2's read barrier orders its pair
1317of loads, it does not guarantee to order CPU 1's store. Therefore, if
1318this example runs on a system where CPUs 1 and 2 share a store buffer
1319or a level of cache, CPU 2 might have early access to CPU 1's writes.
1320General barriers are therefore required to ensure that all CPUs agree
1321on the combined order of CPU 1's and CPU 2's accesses.
1322
Paul E. McKenneyc535cc92016-01-15 09:30:42 -08001323General barriers provide "global transitivity", so that all CPUs will
1324agree on the order of operations. In contrast, a chain of release-acquire
1325pairs provides only "local transitivity", so that only those CPUs on
1326the chain are guaranteed to agree on the combined order of the accesses.
1327For example, switching to C code in deference to Herman Hollerith:
1328
1329 int u, v, x, y, z;
1330
1331 void cpu0(void)
1332 {
1333 r0 = smp_load_acquire(&x);
1334 WRITE_ONCE(u, 1);
1335 smp_store_release(&y, 1);
1336 }
1337
1338 void cpu1(void)
1339 {
1340 r1 = smp_load_acquire(&y);
1341 r4 = READ_ONCE(v);
1342 r5 = READ_ONCE(u);
1343 smp_store_release(&z, 1);
1344 }
1345
1346 void cpu2(void)
1347 {
1348 r2 = smp_load_acquire(&z);
1349 smp_store_release(&x, 1);
1350 }
1351
1352 void cpu3(void)
1353 {
1354 WRITE_ONCE(v, 1);
1355 smp_mb();
1356 r3 = READ_ONCE(u);
1357 }
1358
1359Because cpu0(), cpu1(), and cpu2() participate in a local transitive
1360chain of smp_store_release()/smp_load_acquire() pairs, the following
1361outcome is prohibited:
1362
1363 r0 == 1 && r1 == 1 && r2 == 1
1364
1365Furthermore, because of the release-acquire relationship between cpu0()
1366and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1367outcome is prohibited:
1368
1369 r1 == 1 && r5 == 0
1370
1371However, the transitivity of release-acquire is local to the participating
1372CPUs and does not apply to cpu3(). Therefore, the following outcome
1373is possible:
1374
1375 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1376
Paul E. McKenney37ef0342016-01-25 22:12:34 -08001377As an aside, the following outcome is also possible:
1378
1379 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1380
Paul E. McKenneyc535cc92016-01-15 09:30:42 -08001381Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1382writes in order, CPUs not involved in the release-acquire chain might
1383well disagree on the order. This disagreement stems from the fact that
1384the weak memory-barrier instructions used to implement smp_load_acquire()
1385and smp_store_release() are not required to order prior stores against
1386subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1387store to u as happening -after- cpu1()'s load from v, even though
1388both cpu0() and cpu1() agree that these two operations occurred in the
1389intended order.
1390
1391However, please keep in mind that smp_load_acquire() is not magic.
1392In particular, it simply reads from its argument with ordering. It does
1393-not- ensure that any particular value will be read. Therefore, the
1394following outcome is possible:
1395
1396 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1397
1398Note that this outcome can happen even on a mythical sequentially
1399consistent system where nothing is ever reordered.
1400
1401To reiterate, if your code requires global transitivity, use general
1402barriers throughout.
Paul E. McKenney241e6662011-02-10 16:54:50 -08001403
1404
David Howells108b42b2006-03-31 16:00:29 +01001405========================
1406EXPLICIT KERNEL BARRIERS
1407========================
1408
1409The Linux kernel has a variety of different barriers that act at different
1410levels:
1411
1412 (*) Compiler barrier.
1413
1414 (*) CPU memory barriers.
1415
1416 (*) MMIO write barrier.
1417
1418
1419COMPILER BARRIER
1420----------------
1421
1422The Linux kernel has an explicit compiler barrier function that prevents the
1423compiler from moving the memory accesses either side of it to the other side:
1424
1425 barrier();
1426
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001427This is a general barrier -- there are no read-read or write-write
1428variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1429thought of as weak forms of barrier() that affect only the specific
1430accesses flagged by the READ_ONCE() or WRITE_ONCE().
David Howells108b42b2006-03-31 16:00:29 +01001431
Paul E. McKenney692118d2013-12-11 13:59:07 -08001432The barrier() function has the following effects:
1433
1434 (*) Prevents the compiler from reordering accesses following the
1435 barrier() to precede any accesses preceding the barrier().
1436 One example use for this property is to ease communication between
1437 interrupt-handler code and the code that was interrupted.
1438
1439 (*) Within a loop, forces the compiler to load the variables used
1440 in that loop's conditional on each pass through that loop.
1441
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001442The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1443optimizations that, while perfectly safe in single-threaded code, can
1444be fatal in concurrent code. Here are some examples of these sorts
1445of optimizations:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001446
Paul E. McKenney449f7412014-01-02 15:03:50 -08001447 (*) The compiler is within its rights to reorder loads and stores
1448 to the same variable, and in some cases, the CPU is within its
1449 rights to reorder loads to the same variable. This means that
1450 the following code:
1451
1452 a[0] = x;
1453 a[1] = x;
1454
1455 Might result in an older value of x stored in a[1] than in a[0].
1456 Prevent both the compiler and the CPU from doing this as follows:
1457
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001458 a[0] = READ_ONCE(x);
1459 a[1] = READ_ONCE(x);
Paul E. McKenney449f7412014-01-02 15:03:50 -08001460
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001461 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1462 accesses from multiple CPUs to a single variable.
Paul E. McKenney449f7412014-01-02 15:03:50 -08001463
Paul E. McKenney692118d2013-12-11 13:59:07 -08001464 (*) The compiler is within its rights to merge successive loads from
1465 the same variable. Such merging can cause the compiler to "optimize"
1466 the following code:
1467
1468 while (tmp = a)
1469 do_something_with(tmp);
1470
1471 into the following code, which, although in some sense legitimate
1472 for single-threaded code, is almost certainly not what the developer
1473 intended:
1474
1475 if (tmp = a)
1476 for (;;)
1477 do_something_with(tmp);
1478
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001479 Use READ_ONCE() to prevent the compiler from doing this to you:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001480
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001481 while (tmp = READ_ONCE(a))
Paul E. McKenney692118d2013-12-11 13:59:07 -08001482 do_something_with(tmp);
1483
1484 (*) The compiler is within its rights to reload a variable, for example,
1485 in cases where high register pressure prevents the compiler from
1486 keeping all data of interest in registers. The compiler might
1487 therefore optimize the variable 'tmp' out of our previous example:
1488
1489 while (tmp = a)
1490 do_something_with(tmp);
1491
1492 This could result in the following code, which is perfectly safe in
1493 single-threaded code, but can be fatal in concurrent code:
1494
1495 while (a)
1496 do_something_with(a);
1497
1498 For example, the optimized version of this code could result in
1499 passing a zero to do_something_with() in the case where the variable
1500 a was modified by some other CPU between the "while" statement and
1501 the call to do_something_with().
1502
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001503 Again, use READ_ONCE() to prevent the compiler from doing this:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001504
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001505 while (tmp = READ_ONCE(a))
Paul E. McKenney692118d2013-12-11 13:59:07 -08001506 do_something_with(tmp);
1507
1508 Note that if the compiler runs short of registers, it might save
1509 tmp onto the stack. The overhead of this saving and later restoring
1510 is why compilers reload variables. Doing so is perfectly safe for
1511 single-threaded code, so you need to tell the compiler about cases
1512 where it is not safe.
1513
1514 (*) The compiler is within its rights to omit a load entirely if it knows
1515 what the value will be. For example, if the compiler can prove that
1516 the value of variable 'a' is always zero, it can optimize this code:
1517
1518 while (tmp = a)
1519 do_something_with(tmp);
1520
1521 Into this:
1522
1523 do { } while (0);
1524
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001525 This transformation is a win for single-threaded code because it
1526 gets rid of a load and a branch. The problem is that the compiler
1527 will carry out its proof assuming that the current CPU is the only
1528 one updating variable 'a'. If variable 'a' is shared, then the
1529 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1530 compiler that it doesn't know as much as it thinks it does:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001531
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001532 while (tmp = READ_ONCE(a))
Paul E. McKenney692118d2013-12-11 13:59:07 -08001533 do_something_with(tmp);
1534
1535 But please note that the compiler is also closely watching what you
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001536 do with the value after the READ_ONCE(). For example, suppose you
Paul E. McKenney692118d2013-12-11 13:59:07 -08001537 do the following and MAX is a preprocessor macro with the value 1:
1538
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001539 while ((tmp = READ_ONCE(a)) % MAX)
Paul E. McKenney692118d2013-12-11 13:59:07 -08001540 do_something_with(tmp);
1541
1542 Then the compiler knows that the result of the "%" operator applied
1543 to MAX will always be zero, again allowing the compiler to optimize
1544 the code into near-nonexistence. (It will still load from the
1545 variable 'a'.)
1546
1547 (*) Similarly, the compiler is within its rights to omit a store entirely
1548 if it knows that the variable already has the value being stored.
1549 Again, the compiler assumes that the current CPU is the only one
1550 storing into the variable, which can cause the compiler to do the
1551 wrong thing for shared variables. For example, suppose you have
1552 the following:
1553
1554 a = 0;
SeongJae Park65f95ff2016-02-22 08:28:29 -08001555 ... Code that does not store to variable a ...
Paul E. McKenney692118d2013-12-11 13:59:07 -08001556 a = 0;
1557
1558 The compiler sees that the value of variable 'a' is already zero, so
1559 it might well omit the second store. This would come as a fatal
1560 surprise if some other CPU might have stored to variable 'a' in the
1561 meantime.
1562
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001563 Use WRITE_ONCE() to prevent the compiler from making this sort of
Paul E. McKenney692118d2013-12-11 13:59:07 -08001564 wrong guess:
1565
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001566 WRITE_ONCE(a, 0);
SeongJae Park65f95ff2016-02-22 08:28:29 -08001567 ... Code that does not store to variable a ...
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001568 WRITE_ONCE(a, 0);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001569
1570 (*) The compiler is within its rights to reorder memory accesses unless
1571 you tell it not to. For example, consider the following interaction
1572 between process-level code and an interrupt handler:
1573
1574 void process_level(void)
1575 {
1576 msg = get_message();
1577 flag = true;
1578 }
1579
1580 void interrupt_handler(void)
1581 {
1582 if (flag)
1583 process_message(msg);
1584 }
1585
Masanari Iidadf5cbb22014-03-21 10:04:30 +09001586 There is nothing to prevent the compiler from transforming
Paul E. McKenney692118d2013-12-11 13:59:07 -08001587 process_level() to the following, in fact, this might well be a
1588 win for single-threaded code:
1589
1590 void process_level(void)
1591 {
1592 flag = true;
1593 msg = get_message();
1594 }
1595
1596 If the interrupt occurs between these two statement, then
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001597 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
Paul E. McKenney692118d2013-12-11 13:59:07 -08001598 to prevent this as follows:
1599
1600 void process_level(void)
1601 {
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001602 WRITE_ONCE(msg, get_message());
1603 WRITE_ONCE(flag, true);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001604 }
1605
1606 void interrupt_handler(void)
1607 {
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001608 if (READ_ONCE(flag))
1609 process_message(READ_ONCE(msg));
Paul E. McKenney692118d2013-12-11 13:59:07 -08001610 }
1611
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001612 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1613 interrupt_handler() are needed if this interrupt handler can itself
1614 be interrupted by something that also accesses 'flag' and 'msg',
1615 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1616 and WRITE_ONCE() are not needed in interrupt_handler() other than
1617 for documentation purposes. (Note also that nested interrupts
1618 do not typically occur in modern Linux kernels, in fact, if an
1619 interrupt handler returns with interrupts enabled, you will get a
1620 WARN_ONCE() splat.)
Paul E. McKenney692118d2013-12-11 13:59:07 -08001621
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001622 You should assume that the compiler can move READ_ONCE() and
1623 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1624 barrier(), or similar primitives.
Paul E. McKenney692118d2013-12-11 13:59:07 -08001625
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001626 This effect could also be achieved using barrier(), but READ_ONCE()
1627 and WRITE_ONCE() are more selective: With READ_ONCE() and
1628 WRITE_ONCE(), the compiler need only forget the contents of the
1629 indicated memory locations, while with barrier() the compiler must
1630 discard the value of all memory locations that it has currented
1631 cached in any machine registers. Of course, the compiler must also
1632 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1633 though the CPU of course need not do so.
Paul E. McKenney692118d2013-12-11 13:59:07 -08001634
1635 (*) The compiler is within its rights to invent stores to a variable,
1636 as in the following example:
1637
1638 if (a)
1639 b = a;
1640 else
1641 b = 42;
1642
1643 The compiler might save a branch by optimizing this as follows:
1644
1645 b = 42;
1646 if (a)
1647 b = a;
1648
1649 In single-threaded code, this is not only safe, but also saves
1650 a branch. Unfortunately, in concurrent code, this optimization
1651 could cause some other CPU to see a spurious value of 42 -- even
1652 if variable 'a' was never zero -- when loading variable 'b'.
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001653 Use WRITE_ONCE() to prevent this as follows:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001654
1655 if (a)
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001656 WRITE_ONCE(b, a);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001657 else
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001658 WRITE_ONCE(b, 42);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001659
1660 The compiler can also invent loads. These are usually less
1661 damaging, but they can result in cache-line bouncing and thus in
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001662 poor performance and scalability. Use READ_ONCE() to prevent
Paul E. McKenney692118d2013-12-11 13:59:07 -08001663 invented loads.
1664
1665 (*) For aligned memory locations whose size allows them to be accessed
1666 with a single memory-reference instruction, prevents "load tearing"
1667 and "store tearing," in which a single large access is replaced by
1668 multiple smaller accesses. For example, given an architecture having
1669 16-bit store instructions with 7-bit immediate fields, the compiler
1670 might be tempted to use two 16-bit store-immediate instructions to
1671 implement the following 32-bit store:
1672
1673 p = 0x00010002;
1674
1675 Please note that GCC really does use this sort of optimization,
1676 which is not surprising given that it would likely take more
1677 than two instructions to build the constant and then store it.
1678 This optimization can therefore be a win in single-threaded code.
1679 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1680 this optimization in a volatile store. In the absence of such bugs,
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001681 use of WRITE_ONCE() prevents store tearing in the following example:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001682
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001683 WRITE_ONCE(p, 0x00010002);
Paul E. McKenney692118d2013-12-11 13:59:07 -08001684
1685 Use of packed structures can also result in load and store tearing,
1686 as in this example:
1687
1688 struct __attribute__((__packed__)) foo {
1689 short a;
1690 int b;
1691 short c;
1692 };
1693 struct foo foo1, foo2;
1694 ...
1695
1696 foo2.a = foo1.a;
1697 foo2.b = foo1.b;
1698 foo2.c = foo1.c;
1699
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001700 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1701 volatile markings, the compiler would be well within its rights to
1702 implement these three assignment statements as a pair of 32-bit
1703 loads followed by a pair of 32-bit stores. This would result in
1704 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1705 and WRITE_ONCE() again prevent tearing in this example:
Paul E. McKenney692118d2013-12-11 13:59:07 -08001706
1707 foo2.a = foo1.a;
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001708 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
Paul E. McKenney692118d2013-12-11 13:59:07 -08001709 foo2.c = foo1.c;
1710
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001711All that aside, it is never necessary to use READ_ONCE() and
1712WRITE_ONCE() on a variable that has been marked volatile. For example,
1713because 'jiffies' is marked volatile, it is never necessary to
1714say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1715WRITE_ONCE() are implemented as volatile casts, which has no effect when
1716its argument is already marked volatile.
Paul E. McKenney692118d2013-12-11 13:59:07 -08001717
1718Please note that these compiler barriers have no direct effect on the CPU,
1719which may then reorder things however it wishes.
David Howells108b42b2006-03-31 16:00:29 +01001720
1721
1722CPU MEMORY BARRIERS
1723-------------------
1724
1725The Linux kernel has eight basic CPU memory barriers:
1726
1727 TYPE MANDATORY SMP CONDITIONAL
1728 =============== ======================= ===========================
1729 GENERAL mb() smp_mb()
1730 WRITE wmb() smp_wmb()
1731 READ rmb() smp_rmb()
1732 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1733
1734
Nick Piggin73f10282008-05-14 06:35:11 +02001735All memory barriers except the data dependency barriers imply a compiler
1736barrier. Data dependencies do not impose any additional compiler ordering.
1737
Paul E. McKenney9af194c2015-06-18 14:33:24 -07001738Aside: In the case of data dependencies, the compiler would be expected
1739to issue the loads in the correct order (eg. `a[b]` would have to load
1740the value of b before loading a[b]), however there is no guarantee in
1741the C specification that the compiler may not speculate the value of b
1742(eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1743tmp = a[b]; ). There is also the problem of a compiler reloading b after
1744having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1745has not yet been reached about these problems, however the READ_ONCE()
1746macro is a good place to start looking.
David Howells108b42b2006-03-31 16:00:29 +01001747
1748SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001749systems because it is assumed that a CPU will appear to be self-consistent,
David Howells108b42b2006-03-31 16:00:29 +01001750and will order overlapping accesses correctly with respect to itself.
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02001751However, see the subsection on "Virtual Machine Guests" below.
David Howells108b42b2006-03-31 16:00:29 +01001752
1753[!] Note that SMP memory barriers _must_ be used to control the ordering of
1754references to shared memory on SMP systems, though the use of locking instead
1755is sufficient.
1756
1757Mandatory barriers should not be used to control SMP effects, since mandatory
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02001758barriers impose unnecessary overhead on both SMP and UP systems. They may,
1759however, be used to control MMIO effects on accesses through relaxed memory I/O
1760windows. These barriers are required even on non-SMP systems as they affect
1761the order in which memory operations appear to a device by prohibiting both the
1762compiler and the CPU from reordering them.
David Howells108b42b2006-03-31 16:00:29 +01001763
1764
1765There are some more advanced barrier functions:
1766
Peter Zijlstrab92b8b32015-05-12 10:51:55 +02001767 (*) smp_store_mb(var, value)
David Howells108b42b2006-03-31 16:00:29 +01001768
Oleg Nesterov75b2bd52006-11-08 17:44:38 -08001769 This assigns the value to the variable and then inserts a full memory
Davidlohr Bueso2d142e52015-10-27 12:53:51 -07001770 barrier after it. It isn't guaranteed to insert anything more than a
1771 compiler barrier in a UP compilation.
David Howells108b42b2006-03-31 16:00:29 +01001772
1773
Peter Zijlstra1b156112014-03-13 19:00:35 +01001774 (*) smp_mb__before_atomic();
1775 (*) smp_mb__after_atomic();
David Howells108b42b2006-03-31 16:00:29 +01001776
Peter Zijlstra1b156112014-03-13 19:00:35 +01001777 These are for use with atomic (such as add, subtract, increment and
1778 decrement) functions that don't return a value, especially when used for
1779 reference counting. These functions do not imply memory barriers.
1780
1781 These are also used for atomic bitop functions that do not return a
1782 value (such as set_bit and clear_bit).
David Howells108b42b2006-03-31 16:00:29 +01001783
1784 As an example, consider a piece of code that marks an object as being dead
1785 and then decrements the object's reference count:
1786
1787 obj->dead = 1;
Peter Zijlstra1b156112014-03-13 19:00:35 +01001788 smp_mb__before_atomic();
David Howells108b42b2006-03-31 16:00:29 +01001789 atomic_dec(&obj->ref_count);
1790
1791 This makes sure that the death mark on the object is perceived to be set
1792 *before* the reference counter is decremented.
1793
1794 See Documentation/atomic_ops.txt for more information. See the "Atomic
1795 operations" subsection for information on where to use these.
1796
1797
Paul E. McKenneyad2ad5d2015-09-17 08:18:32 -07001798 (*) lockless_dereference();
1799 This can be thought of as a pointer-fetch wrapper around the
1800 smp_read_barrier_depends() data-dependency barrier.
1801
1802 This is also similar to rcu_dereference(), but in cases where
1803 object lifetime is handled by some mechanism other than RCU, for
1804 example, when the objects removed only when the system goes down.
1805 In addition, lockless_dereference() is used in some data structures
1806 that can be used both with and without RCU.
1807
1808
Alexander Duyck1077fa32014-12-11 15:02:06 -08001809 (*) dma_wmb();
1810 (*) dma_rmb();
1811
1812 These are for use with consistent memory to guarantee the ordering
1813 of writes or reads of shared memory accessible to both the CPU and a
1814 DMA capable device.
1815
1816 For example, consider a device driver that shares memory with a device
1817 and uses a descriptor status value to indicate if the descriptor belongs
1818 to the device or the CPU, and a doorbell to notify it when new
1819 descriptors are available:
1820
1821 if (desc->status != DEVICE_OWN) {
1822 /* do not read data until we own descriptor */
1823 dma_rmb();
1824
1825 /* read/modify data */
1826 read_data = desc->data;
1827 desc->data = write_data;
1828
1829 /* flush modifications before status update */
1830 dma_wmb();
1831
1832 /* assign ownership */
1833 desc->status = DEVICE_OWN;
1834
1835 /* force memory to sync before notifying device via MMIO */
1836 wmb();
1837
1838 /* notify device of new descriptors */
1839 writel(DESC_NOTIFY, doorbell);
1840 }
1841
1842 The dma_rmb() allows us guarantee the device has released ownership
Sylvain Trias7a458002015-04-08 10:27:57 +02001843 before we read the data from the descriptor, and the dma_wmb() allows
Alexander Duyck1077fa32014-12-11 15:02:06 -08001844 us to guarantee the data is written to the descriptor before the device
1845 can see it now has ownership. The wmb() is needed to guarantee that the
1846 cache coherent memory writes have completed before attempting a write to
1847 the cache incoherent MMIO region.
1848
1849 See Documentation/DMA-API.txt for more information on consistent memory.
1850
David Howells108b42b2006-03-31 16:00:29 +01001851MMIO WRITE BARRIER
1852------------------
1853
1854The Linux kernel also has a special barrier for use with memory-mapped I/O
1855writes:
1856
1857 mmiowb();
1858
1859This is a variation on the mandatory write barrier that causes writes to weakly
1860ordered I/O regions to be partially ordered. Its effects may go beyond the
1861CPU->Hardware interface and actually affect the hardware at some level.
1862
SeongJae Park166bda72016-04-12 08:52:50 -07001863See the subsection "Acquires vs I/O accesses" for more information.
David Howells108b42b2006-03-31 16:00:29 +01001864
1865
1866===============================
1867IMPLICIT KERNEL MEMORY BARRIERS
1868===============================
1869
1870Some of the other functions in the linux kernel imply memory barriers, amongst
David Howells670bd952006-06-10 09:54:12 -07001871which are locking and scheduling functions.
David Howells108b42b2006-03-31 16:00:29 +01001872
1873This specification is a _minimum_ guarantee; any particular architecture may
1874provide more substantial guarantees, but these may not be relied upon outside
1875of arch specific code.
1876
1877
SeongJae Park166bda72016-04-12 08:52:50 -07001878LOCK ACQUISITION FUNCTIONS
1879--------------------------
David Howells108b42b2006-03-31 16:00:29 +01001880
1881The Linux kernel has a number of locking constructs:
1882
1883 (*) spin locks
1884 (*) R/W spin locks
1885 (*) mutexes
1886 (*) semaphores
1887 (*) R/W semaphores
David Howells108b42b2006-03-31 16:00:29 +01001888
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001889In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
David Howells108b42b2006-03-31 16:00:29 +01001890for each construct. These operations all imply certain barriers:
1891
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001892 (1) ACQUIRE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001893
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001894 Memory operations issued after the ACQUIRE will be completed after the
1895 ACQUIRE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001896
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001897 Memory operations issued before the ACQUIRE may be completed after
1898 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
Will Deacond9560282015-03-31 09:39:41 +01001899 combined with a following ACQUIRE, orders prior stores against
1900 subsequent loads and stores. Note that this is weaker than smp_mb()!
1901 The smp_mb__before_spinlock() primitive is free on many architectures.
David Howells108b42b2006-03-31 16:00:29 +01001902
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001903 (2) RELEASE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001904
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001905 Memory operations issued before the RELEASE will be completed before the
1906 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001907
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001908 Memory operations issued after the RELEASE may be completed before the
1909 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001910
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001911 (3) ACQUIRE vs ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01001912
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001913 All ACQUIRE operations issued before another ACQUIRE operation will be
1914 completed before that ACQUIRE operation.
David Howells108b42b2006-03-31 16:00:29 +01001915
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001916 (4) ACQUIRE vs RELEASE implication:
David Howells108b42b2006-03-31 16:00:29 +01001917
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001918 All ACQUIRE operations issued before a RELEASE operation will be
1919 completed before the RELEASE operation.
David Howells108b42b2006-03-31 16:00:29 +01001920
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001921 (5) Failed conditional ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01001922
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001923 Certain locking variants of the ACQUIRE operation may fail, either due to
1924 being unable to get the lock immediately, or due to receiving an unblocked
David Howells108b42b2006-03-31 16:00:29 +01001925 signal whilst asleep waiting for the lock to become available. Failed
1926 locks do not imply any sort of barrier.
1927
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001928[!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1929one-way barriers is that the effects of instructions outside of a critical
1930section may seep into the inside of the critical section.
David Howells108b42b2006-03-31 16:00:29 +01001931
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001932An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1933because it is possible for an access preceding the ACQUIRE to happen after the
1934ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1935the two accesses can themselves then cross:
David Howells670bd952006-06-10 09:54:12 -07001936
1937 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001938 ACQUIRE M
1939 RELEASE M
David Howells670bd952006-06-10 09:54:12 -07001940 *B = b;
1941
1942may occur as:
1943
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001944 ACQUIRE M, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001945
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001946When the ACQUIRE and RELEASE are a lock acquisition and release,
1947respectively, this same reordering can occur if the lock's ACQUIRE and
1948RELEASE are to the same lock variable, but only from the perspective of
1949another CPU not holding that lock. In short, a ACQUIRE followed by an
1950RELEASE may -not- be assumed to be a full memory barrier.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001951
Paul E. McKenney12d560f2015-07-14 18:35:23 -07001952Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
1953not imply a full memory barrier. Therefore, the CPU's execution of the
1954critical sections corresponding to the RELEASE and the ACQUIRE can cross,
1955so that:
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001956
1957 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001958 RELEASE M
1959 ACQUIRE N
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001960 *B = b;
1961
1962could occur as:
1963
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001964 ACQUIRE N, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001965
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001966It might appear that this reordering could introduce a deadlock.
1967However, this cannot happen because if such a deadlock threatened,
1968the RELEASE would simply complete, thereby avoiding the deadlock.
1969
1970 Why does this work?
1971
1972 One key point is that we are only talking about the CPU doing
1973 the reordering, not the compiler. If the compiler (or, for
1974 that matter, the developer) switched the operations, deadlock
1975 -could- occur.
1976
1977 But suppose the CPU reordered the operations. In this case,
1978 the unlock precedes the lock in the assembly code. The CPU
1979 simply elected to try executing the later lock operation first.
1980 If there is a deadlock, this lock operation will simply spin (or
1981 try to sleep, but more on that later). The CPU will eventually
1982 execute the unlock operation (which preceded the lock operation
1983 in the assembly code), which will unravel the potential deadlock,
1984 allowing the lock operation to succeed.
1985
1986 But what if the lock is a sleeplock? In that case, the code will
1987 try to enter the scheduler, where it will eventually encounter
1988 a memory barrier, which will force the earlier unlock operation
1989 to complete, again unraveling the deadlock. There might be
1990 a sleep-unlock race, but the locking primitive needs to resolve
1991 such races properly in any case.
1992
David Howells108b42b2006-03-31 16:00:29 +01001993Locks and semaphores may not provide any guarantee of ordering on UP compiled
1994systems, and so cannot be counted on in such a situation to actually achieve
1995anything at all - especially with respect to I/O accesses - unless combined
1996with interrupt disabling operations.
1997
1998See also the section on "Inter-CPU locking barrier effects".
1999
2000
2001As an example, consider the following:
2002
2003 *A = a;
2004 *B = b;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002005 ACQUIRE
David Howells108b42b2006-03-31 16:00:29 +01002006 *C = c;
2007 *D = d;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002008 RELEASE
David Howells108b42b2006-03-31 16:00:29 +01002009 *E = e;
2010 *F = f;
2011
2012The following sequence of events is acceptable:
2013
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002014 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
David Howells108b42b2006-03-31 16:00:29 +01002015
2016 [+] Note that {*F,*A} indicates a combined access.
2017
2018But none of the following are:
2019
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002020 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2021 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2022 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2023 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
David Howells108b42b2006-03-31 16:00:29 +01002024
2025
2026
2027INTERRUPT DISABLING FUNCTIONS
2028-----------------------------
2029
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002030Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2031(RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
David Howells108b42b2006-03-31 16:00:29 +01002032barriers are required in such a situation, they must be provided from some
2033other means.
2034
2035
David Howells50fa6102009-04-28 15:01:38 +01002036SLEEP AND WAKE-UP FUNCTIONS
2037---------------------------
2038
2039Sleeping and waking on an event flagged in global data can be viewed as an
2040interaction between two pieces of data: the task state of the task waiting for
2041the event and the global data used to indicate the event. To make sure that
2042these appear to happen in the right order, the primitives to begin the process
2043of going to sleep, and the primitives to initiate a wake up imply certain
2044barriers.
2045
2046Firstly, the sleeper normally follows something like this sequence of events:
2047
2048 for (;;) {
2049 set_current_state(TASK_UNINTERRUPTIBLE);
2050 if (event_indicated)
2051 break;
2052 schedule();
2053 }
2054
2055A general memory barrier is interpolated automatically by set_current_state()
2056after it has altered the task state:
2057
2058 CPU 1
2059 ===============================
2060 set_current_state();
Peter Zijlstrab92b8b32015-05-12 10:51:55 +02002061 smp_store_mb();
David Howells50fa6102009-04-28 15:01:38 +01002062 STORE current->state
2063 <general barrier>
2064 LOAD event_indicated
2065
2066set_current_state() may be wrapped by:
2067
2068 prepare_to_wait();
2069 prepare_to_wait_exclusive();
2070
2071which therefore also imply a general memory barrier after setting the state.
2072The whole sequence above is available in various canned forms, all of which
2073interpolate the memory barrier in the right place:
2074
2075 wait_event();
2076 wait_event_interruptible();
2077 wait_event_interruptible_exclusive();
2078 wait_event_interruptible_timeout();
2079 wait_event_killable();
2080 wait_event_timeout();
2081 wait_on_bit();
2082 wait_on_bit_lock();
2083
2084
2085Secondly, code that performs a wake up normally follows something like this:
2086
2087 event_indicated = 1;
2088 wake_up(&event_wait_queue);
2089
2090or:
2091
2092 event_indicated = 1;
2093 wake_up_process(event_daemon);
2094
2095A write memory barrier is implied by wake_up() and co. if and only if they wake
2096something up. The barrier occurs before the task state is cleared, and so sits
2097between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2098
2099 CPU 1 CPU 2
2100 =============================== ===============================
2101 set_current_state(); STORE event_indicated
Peter Zijlstrab92b8b32015-05-12 10:51:55 +02002102 smp_store_mb(); wake_up();
David Howells50fa6102009-04-28 15:01:38 +01002103 STORE current->state <write barrier>
2104 <general barrier> STORE current->state
2105 LOAD event_indicated
2106
Paul E. McKenney5726ce02014-05-13 10:14:51 -07002107To repeat, this write memory barrier is present if and only if something
2108is actually awakened. To see this, consider the following sequence of
2109events, where X and Y are both initially zero:
2110
2111 CPU 1 CPU 2
2112 =============================== ===============================
2113 X = 1; STORE event_indicated
2114 smp_mb(); wake_up();
2115 Y = 1; wait_event(wq, Y == 1);
2116 wake_up(); load from Y sees 1, no memory barrier
2117 load from X might see 0
2118
2119In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2120to see 1.
2121
David Howells50fa6102009-04-28 15:01:38 +01002122The available waker functions include:
2123
2124 complete();
2125 wake_up();
2126 wake_up_all();
2127 wake_up_bit();
2128 wake_up_interruptible();
2129 wake_up_interruptible_all();
2130 wake_up_interruptible_nr();
2131 wake_up_interruptible_poll();
2132 wake_up_interruptible_sync();
2133 wake_up_interruptible_sync_poll();
2134 wake_up_locked();
2135 wake_up_locked_poll();
2136 wake_up_nr();
2137 wake_up_poll();
2138 wake_up_process();
2139
2140
2141[!] Note that the memory barriers implied by the sleeper and the waker do _not_
2142order multiple stores before the wake-up with respect to loads of those stored
2143values after the sleeper has called set_current_state(). For instance, if the
2144sleeper does:
2145
2146 set_current_state(TASK_INTERRUPTIBLE);
2147 if (event_indicated)
2148 break;
2149 __set_current_state(TASK_RUNNING);
2150 do_something(my_data);
2151
2152and the waker does:
2153
2154 my_data = value;
2155 event_indicated = 1;
2156 wake_up(&event_wait_queue);
2157
2158there's no guarantee that the change to event_indicated will be perceived by
2159the sleeper as coming after the change to my_data. In such a circumstance, the
2160code on both sides must interpolate its own memory barriers between the
2161separate data accesses. Thus the above sleeper ought to do:
2162
2163 set_current_state(TASK_INTERRUPTIBLE);
2164 if (event_indicated) {
2165 smp_rmb();
2166 do_something(my_data);
2167 }
2168
2169and the waker should do:
2170
2171 my_data = value;
2172 smp_wmb();
2173 event_indicated = 1;
2174 wake_up(&event_wait_queue);
2175
2176
David Howells108b42b2006-03-31 16:00:29 +01002177MISCELLANEOUS FUNCTIONS
2178-----------------------
2179
2180Other functions that imply barriers:
2181
2182 (*) schedule() and similar imply full memory barriers.
2183
David Howells108b42b2006-03-31 16:00:29 +01002184
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002185===================================
2186INTER-CPU ACQUIRING BARRIER EFFECTS
2187===================================
David Howells108b42b2006-03-31 16:00:29 +01002188
2189On SMP systems locking primitives give a more substantial form of barrier: one
2190that does affect memory access ordering on other CPUs, within the context of
2191conflict on any particular lock.
2192
2193
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002194ACQUIRES VS MEMORY ACCESSES
2195---------------------------
David Howells108b42b2006-03-31 16:00:29 +01002196
Aneesh Kumar79afecf2006-05-15 09:44:36 -07002197Consider the following: the system has a pair of spinlocks (M) and (Q), and
David Howells108b42b2006-03-31 16:00:29 +01002198three CPUs; then should the following sequence of events occur:
2199
2200 CPU 1 CPU 2
2201 =============================== ===============================
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002202 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002203 ACQUIRE M ACQUIRE Q
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002204 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2205 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002206 RELEASE M RELEASE Q
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002207 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
David Howells108b42b2006-03-31 16:00:29 +01002208
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002209Then there is no guarantee as to what order CPU 3 will see the accesses to *A
David Howells108b42b2006-03-31 16:00:29 +01002210through *H occur in, other than the constraints imposed by the separate locks
2211on the separate CPUs. It might, for example, see:
2212
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002213 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
David Howells108b42b2006-03-31 16:00:29 +01002214
2215But it won't see any of:
2216
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002217 *B, *C or *D preceding ACQUIRE M
2218 *A, *B or *C following RELEASE M
2219 *F, *G or *H preceding ACQUIRE Q
2220 *E, *F or *G following RELEASE Q
David Howells108b42b2006-03-31 16:00:29 +01002221
2222
David Howells108b42b2006-03-31 16:00:29 +01002223
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002224ACQUIRES VS I/O ACCESSES
2225------------------------
David Howells108b42b2006-03-31 16:00:29 +01002226
2227Under certain circumstances (especially involving NUMA), I/O accesses within
2228two spinlocked sections on two different CPUs may be seen as interleaved by the
2229PCI bridge, because the PCI bridge does not necessarily participate in the
2230cache-coherence protocol, and is therefore incapable of issuing the required
2231read memory barriers.
2232
2233For example:
2234
2235 CPU 1 CPU 2
2236 =============================== ===============================
2237 spin_lock(Q)
2238 writel(0, ADDR)
2239 writel(1, DATA);
2240 spin_unlock(Q);
2241 spin_lock(Q);
2242 writel(4, ADDR);
2243 writel(5, DATA);
2244 spin_unlock(Q);
2245
2246may be seen by the PCI bridge as follows:
2247
2248 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2249
2250which would probably cause the hardware to malfunction.
2251
2252
2253What is necessary here is to intervene with an mmiowb() before dropping the
2254spinlock, for example:
2255
2256 CPU 1 CPU 2
2257 =============================== ===============================
2258 spin_lock(Q)
2259 writel(0, ADDR)
2260 writel(1, DATA);
2261 mmiowb();
2262 spin_unlock(Q);
2263 spin_lock(Q);
2264 writel(4, ADDR);
2265 writel(5, DATA);
2266 mmiowb();
2267 spin_unlock(Q);
2268
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002269this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2270before either of the stores issued on CPU 2.
David Howells108b42b2006-03-31 16:00:29 +01002271
2272
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002273Furthermore, following a store by a load from the same device obviates the need
2274for the mmiowb(), because the load forces the store to complete before the load
David Howells108b42b2006-03-31 16:00:29 +01002275is performed:
2276
2277 CPU 1 CPU 2
2278 =============================== ===============================
2279 spin_lock(Q)
2280 writel(0, ADDR)
2281 a = readl(DATA);
2282 spin_unlock(Q);
2283 spin_lock(Q);
2284 writel(4, ADDR);
2285 b = readl(DATA);
2286 spin_unlock(Q);
2287
2288
2289See Documentation/DocBook/deviceiobook.tmpl for more information.
2290
2291
2292=================================
2293WHERE ARE MEMORY BARRIERS NEEDED?
2294=================================
2295
2296Under normal operation, memory operation reordering is generally not going to
2297be a problem as a single-threaded linear piece of code will still appear to
David Howells50fa6102009-04-28 15:01:38 +01002298work correctly, even if it's in an SMP kernel. There are, however, four
David Howells108b42b2006-03-31 16:00:29 +01002299circumstances in which reordering definitely _could_ be a problem:
2300
2301 (*) Interprocessor interaction.
2302
2303 (*) Atomic operations.
2304
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002305 (*) Accessing devices.
David Howells108b42b2006-03-31 16:00:29 +01002306
2307 (*) Interrupts.
2308
2309
2310INTERPROCESSOR INTERACTION
2311--------------------------
2312
2313When there's a system with more than one processor, more than one CPU in the
2314system may be working on the same data set at the same time. This can cause
2315synchronisation problems, and the usual way of dealing with them is to use
2316locks. Locks, however, are quite expensive, and so it may be preferable to
2317operate without the use of a lock if at all possible. In such a case
2318operations that affect both CPUs may have to be carefully ordered to prevent
2319a malfunction.
2320
2321Consider, for example, the R/W semaphore slow path. Here a waiting process is
2322queued on the semaphore, by virtue of it having a piece of its stack linked to
2323the semaphore's list of waiting processes:
2324
2325 struct rw_semaphore {
2326 ...
2327 spinlock_t lock;
2328 struct list_head waiters;
2329 };
2330
2331 struct rwsem_waiter {
2332 struct list_head list;
2333 struct task_struct *task;
2334 };
2335
2336To wake up a particular waiter, the up_read() or up_write() functions have to:
2337
2338 (1) read the next pointer from this waiter's record to know as to where the
2339 next waiter record is;
2340
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002341 (2) read the pointer to the waiter's task structure;
David Howells108b42b2006-03-31 16:00:29 +01002342
2343 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2344
2345 (4) call wake_up_process() on the task; and
2346
2347 (5) release the reference held on the waiter's task struct.
2348
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002349In other words, it has to perform this sequence of events:
David Howells108b42b2006-03-31 16:00:29 +01002350
2351 LOAD waiter->list.next;
2352 LOAD waiter->task;
2353 STORE waiter->task;
2354 CALL wakeup
2355 RELEASE task
2356
2357and if any of these steps occur out of order, then the whole thing may
2358malfunction.
2359
2360Once it has queued itself and dropped the semaphore lock, the waiter does not
2361get the lock again; it instead just waits for its task pointer to be cleared
2362before proceeding. Since the record is on the waiter's stack, this means that
2363if the task pointer is cleared _before_ the next pointer in the list is read,
2364another CPU might start processing the waiter and might clobber the waiter's
2365stack before the up*() function has a chance to read the next pointer.
2366
2367Consider then what might happen to the above sequence of events:
2368
2369 CPU 1 CPU 2
2370 =============================== ===============================
2371 down_xxx()
2372 Queue waiter
2373 Sleep
2374 up_yyy()
2375 LOAD waiter->task;
2376 STORE waiter->task;
2377 Woken up by other event
2378 <preempt>
2379 Resume processing
2380 down_xxx() returns
2381 call foo()
2382 foo() clobbers *waiter
2383 </preempt>
2384 LOAD waiter->list.next;
2385 --- OOPS ---
2386
2387This could be dealt with using the semaphore lock, but then the down_xxx()
2388function has to needlessly get the spinlock again after being woken up.
2389
2390The way to deal with this is to insert a general SMP memory barrier:
2391
2392 LOAD waiter->list.next;
2393 LOAD waiter->task;
2394 smp_mb();
2395 STORE waiter->task;
2396 CALL wakeup
2397 RELEASE task
2398
2399In this case, the barrier makes a guarantee that all memory accesses before the
2400barrier will appear to happen before all the memory accesses after the barrier
2401with respect to the other CPUs on the system. It does _not_ guarantee that all
2402the memory accesses before the barrier will be complete by the time the barrier
2403instruction itself is complete.
2404
2405On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2406compiler barrier, thus making sure the compiler emits the instructions in the
David Howells6bc39272006-06-25 05:49:22 -07002407right order without actually intervening in the CPU. Since there's only one
2408CPU, that CPU's dependency ordering logic will take care of everything else.
David Howells108b42b2006-03-31 16:00:29 +01002409
2410
2411ATOMIC OPERATIONS
2412-----------------
2413
David Howellsdbc87002006-04-10 22:54:23 -07002414Whilst they are technically interprocessor interaction considerations, atomic
2415operations are noted specially as some of them imply full memory barriers and
2416some don't, but they're very heavily relied on as a group throughout the
2417kernel.
2418
2419Any atomic operation that modifies some state in memory and returns information
2420about the state (old or new) implies an SMP-conditional general memory barrier
Nick Piggin26333572007-10-18 03:06:39 -07002421(smp_mb()) on each side of the actual operation (with the exception of
2422explicit lock operations, described later). These include:
David Howells108b42b2006-03-31 16:00:29 +01002423
2424 xchg();
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002425 atomic_xchg(); atomic_long_xchg();
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002426 atomic_inc_return(); atomic_long_inc_return();
2427 atomic_dec_return(); atomic_long_dec_return();
2428 atomic_add_return(); atomic_long_add_return();
2429 atomic_sub_return(); atomic_long_sub_return();
2430 atomic_inc_and_test(); atomic_long_inc_and_test();
2431 atomic_dec_and_test(); atomic_long_dec_and_test();
2432 atomic_sub_and_test(); atomic_long_sub_and_test();
2433 atomic_add_negative(); atomic_long_add_negative();
David Howellsdbc87002006-04-10 22:54:23 -07002434 test_and_set_bit();
2435 test_and_clear_bit();
2436 test_and_change_bit();
David Howells108b42b2006-03-31 16:00:29 +01002437
Will Deaconed2de9f2015-07-16 16:10:06 +01002438 /* when succeeds */
2439 cmpxchg();
2440 atomic_cmpxchg(); atomic_long_cmpxchg();
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002441 atomic_add_unless(); atomic_long_add_unless();
2442
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002443These are used for such things as implementing ACQUIRE-class and RELEASE-class
David Howellsdbc87002006-04-10 22:54:23 -07002444operations and adjusting reference counters towards object destruction, and as
2445such the implicit memory barrier effects are necessary.
David Howells108b42b2006-03-31 16:00:29 +01002446
David Howells108b42b2006-03-31 16:00:29 +01002447
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002448The following operations are potential problems as they do _not_ imply memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002449barriers, but might be used for implementing such things as RELEASE-class
David Howellsdbc87002006-04-10 22:54:23 -07002450operations:
2451
2452 atomic_set();
David Howells108b42b2006-03-31 16:00:29 +01002453 set_bit();
2454 clear_bit();
2455 change_bit();
David Howellsdbc87002006-04-10 22:54:23 -07002456
2457With these the appropriate explicit memory barrier should be used if necessary
Peter Zijlstra1b156112014-03-13 19:00:35 +01002458(smp_mb__before_atomic() for instance).
David Howells108b42b2006-03-31 16:00:29 +01002459
2460
David Howellsdbc87002006-04-10 22:54:23 -07002461The following also do _not_ imply memory barriers, and so may require explicit
Peter Zijlstra1b156112014-03-13 19:00:35 +01002462memory barriers under some circumstances (smp_mb__before_atomic() for
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002463instance):
David Howells108b42b2006-03-31 16:00:29 +01002464
2465 atomic_add();
2466 atomic_sub();
2467 atomic_inc();
2468 atomic_dec();
2469
2470If they're used for statistics generation, then they probably don't need memory
2471barriers, unless there's a coupling between statistical data.
2472
2473If they're used for reference counting on an object to control its lifetime,
2474they probably don't need memory barriers because either the reference count
2475will be adjusted inside a locked section, or the caller will already hold
2476sufficient references to make the lock, and thus a memory barrier unnecessary.
2477
2478If they're used for constructing a lock of some description, then they probably
2479do need memory barriers as a lock primitive generally has to do things in a
2480specific order.
2481
David Howells108b42b2006-03-31 16:00:29 +01002482Basically, each usage case has to be carefully considered as to whether memory
David Howellsdbc87002006-04-10 22:54:23 -07002483barriers are needed or not.
2484
Nick Piggin26333572007-10-18 03:06:39 -07002485The following operations are special locking primitives:
2486
2487 test_and_set_bit_lock();
2488 clear_bit_unlock();
2489 __clear_bit_unlock();
2490
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002491These implement ACQUIRE-class and RELEASE-class operations. These should be used in
Nick Piggin26333572007-10-18 03:06:39 -07002492preference to other operations when implementing locking primitives, because
2493their implementations can be optimised on many architectures.
2494
David Howellsdbc87002006-04-10 22:54:23 -07002495[!] Note that special memory barrier primitives are available for these
2496situations because on some CPUs the atomic instructions used imply full memory
2497barriers, and so barrier instructions are superfluous in conjunction with them,
2498and in such cases the special barrier primitives will be no-ops.
David Howells108b42b2006-03-31 16:00:29 +01002499
2500See Documentation/atomic_ops.txt for more information.
2501
2502
2503ACCESSING DEVICES
2504-----------------
2505
2506Many devices can be memory mapped, and so appear to the CPU as if they're just
2507a set of memory locations. To control such a device, the driver usually has to
2508make the right memory accesses in exactly the right order.
2509
2510However, having a clever CPU or a clever compiler creates a potential problem
2511in that the carefully sequenced accesses in the driver code won't reach the
2512device in the requisite order if the CPU or the compiler thinks it is more
2513efficient to reorder, combine or merge accesses - something that would cause
2514the device to malfunction.
2515
2516Inside of the Linux kernel, I/O should be done through the appropriate accessor
2517routines - such as inb() or writel() - which know how to make such accesses
2518appropriately sequential. Whilst this, for the most part, renders the explicit
2519use of memory barriers unnecessary, there are a couple of situations where they
2520might be needed:
2521
2522 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2523 so for _all_ general drivers locks should be used and mmiowb() must be
2524 issued prior to unlocking the critical section.
2525
2526 (2) If the accessor functions are used to refer to an I/O memory window with
2527 relaxed memory access properties, then _mandatory_ memory barriers are
2528 required to enforce ordering.
2529
2530See Documentation/DocBook/deviceiobook.tmpl for more information.
2531
2532
2533INTERRUPTS
2534----------
2535
2536A driver may be interrupted by its own interrupt service routine, and thus the
2537two parts of the driver may interfere with each other's attempts to control or
2538access the device.
2539
2540This may be alleviated - at least in part - by disabling local interrupts (a
2541form of locking), such that the critical operations are all contained within
2542the interrupt-disabled section in the driver. Whilst the driver's interrupt
2543routine is executing, the driver's core may not run on the same CPU, and its
2544interrupt is not permitted to happen again until the current interrupt has been
2545handled, thus the interrupt handler does not need to lock against that.
2546
2547However, consider a driver that was talking to an ethernet card that sports an
2548address register and a data register. If that driver's core talks to the card
2549under interrupt-disablement and then the driver's interrupt handler is invoked:
2550
2551 LOCAL IRQ DISABLE
2552 writew(ADDR, 3);
2553 writew(DATA, y);
2554 LOCAL IRQ ENABLE
2555 <interrupt>
2556 writew(ADDR, 4);
2557 q = readw(DATA);
2558 </interrupt>
2559
2560The store to the data register might happen after the second store to the
2561address register if ordering rules are sufficiently relaxed:
2562
2563 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2564
2565
2566If ordering rules are relaxed, it must be assumed that accesses done inside an
2567interrupt disabled section may leak outside of it and may interleave with
2568accesses performed in an interrupt - and vice versa - unless implicit or
2569explicit barriers are used.
2570
2571Normally this won't be a problem because the I/O accesses done inside such
2572sections will include synchronous load operations on strictly ordered I/O
2573registers that form implicit I/O barriers. If this isn't sufficient then an
2574mmiowb() may need to be used explicitly.
2575
2576
2577A similar situation may occur between an interrupt routine and two routines
2578running on separate CPUs that communicate with each other. If such a case is
2579likely, then interrupt-disabling locks should be used to guarantee ordering.
2580
2581
2582==========================
2583KERNEL I/O BARRIER EFFECTS
2584==========================
2585
2586When accessing I/O memory, drivers should use the appropriate accessor
2587functions:
2588
2589 (*) inX(), outX():
2590
2591 These are intended to talk to I/O space rather than memory space, but
2592 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2593 indeed have special I/O space access cycles and instructions, but many
2594 CPUs don't have such a concept.
2595
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002596 The PCI bus, amongst others, defines an I/O space concept which - on such
2597 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
David Howells6bc39272006-06-25 05:49:22 -07002598 space. However, it may also be mapped as a virtual I/O space in the CPU's
2599 memory map, particularly on those CPUs that don't support alternate I/O
2600 spaces.
David Howells108b42b2006-03-31 16:00:29 +01002601
2602 Accesses to this space may be fully synchronous (as on i386), but
2603 intermediary bridges (such as the PCI host bridge) may not fully honour
2604 that.
2605
2606 They are guaranteed to be fully ordered with respect to each other.
2607
2608 They are not guaranteed to be fully ordered with respect to other types of
2609 memory and I/O operation.
2610
2611 (*) readX(), writeX():
2612
2613 Whether these are guaranteed to be fully ordered and uncombined with
2614 respect to each other on the issuing CPU depends on the characteristics
2615 defined for the memory window through which they're accessing. On later
2616 i386 architecture machines, for example, this is controlled by way of the
2617 MTRR registers.
2618
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002619 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
David Howells108b42b2006-03-31 16:00:29 +01002620 provided they're not accessing a prefetchable device.
2621
2622 However, intermediary hardware (such as a PCI bridge) may indulge in
2623 deferral if it so wishes; to flush a store, a load from the same location
2624 is preferred[*], but a load from the same device or from configuration
2625 space should suffice for PCI.
2626
2627 [*] NOTE! attempting to load from the same location as was written to may
Ingo Molnare0edc782013-11-22 11:24:53 +01002628 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2629 example.
David Howells108b42b2006-03-31 16:00:29 +01002630
2631 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2632 force stores to be ordered.
2633
2634 Please refer to the PCI specification for more information on interactions
2635 between PCI transactions.
2636
Will Deacona8e0aea2013-09-04 12:30:08 +01002637 (*) readX_relaxed(), writeX_relaxed()
David Howells108b42b2006-03-31 16:00:29 +01002638
Will Deacona8e0aea2013-09-04 12:30:08 +01002639 These are similar to readX() and writeX(), but provide weaker memory
2640 ordering guarantees. Specifically, they do not guarantee ordering with
2641 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2642 ordering with respect to LOCK or UNLOCK operations. If the latter is
2643 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2644 the same peripheral are guaranteed to be ordered with respect to each
2645 other.
David Howells108b42b2006-03-31 16:00:29 +01002646
2647 (*) ioreadX(), iowriteX()
2648
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002649 These will perform appropriately for the type of access they're actually
David Howells108b42b2006-03-31 16:00:29 +01002650 doing, be it inX()/outX() or readX()/writeX().
2651
2652
2653========================================
2654ASSUMED MINIMUM EXECUTION ORDERING MODEL
2655========================================
2656
2657It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2658maintain the appearance of program causality with respect to itself. Some CPUs
2659(such as i386 or x86_64) are more constrained than others (such as powerpc or
2660frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2661of arch-specific code.
2662
2663This means that it must be considered that the CPU will execute its instruction
2664stream in any order it feels like - or even in parallel - provided that if an
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002665instruction in the stream depends on an earlier instruction, then that
David Howells108b42b2006-03-31 16:00:29 +01002666earlier instruction must be sufficiently complete[*] before the later
2667instruction may proceed; in other words: provided that the appearance of
2668causality is maintained.
2669
2670 [*] Some instructions have more than one effect - such as changing the
2671 condition codes, changing registers or changing memory - and different
2672 instructions may depend on different effects.
2673
2674A CPU may also discard any instruction sequence that winds up having no
2675ultimate effect. For example, if two adjacent instructions both load an
2676immediate value into the same register, the first may be discarded.
2677
2678
2679Similarly, it has to be assumed that compiler might reorder the instruction
2680stream in any way it sees fit, again provided the appearance of causality is
2681maintained.
2682
2683
2684============================
2685THE EFFECTS OF THE CPU CACHE
2686============================
2687
2688The way cached memory operations are perceived across the system is affected to
2689a certain extent by the caches that lie between CPUs and memory, and by the
2690memory coherence system that maintains the consistency of state in the system.
2691
2692As far as the way a CPU interacts with another part of the system through the
2693caches goes, the memory system has to include the CPU's caches, and memory
2694barriers for the most part act at the interface between the CPU and its cache
2695(memory barriers logically act on the dotted line in the following diagram):
2696
2697 <--- CPU ---> : <----------- Memory ----------->
2698 :
2699 +--------+ +--------+ : +--------+ +-----------+
2700 | | | | : | | | | +--------+
Ingo Molnare0edc782013-11-22 11:24:53 +01002701 | CPU | | Memory | : | CPU | | | | |
2702 | Core |--->| Access |----->| Cache |<-->| | | |
David Howells108b42b2006-03-31 16:00:29 +01002703 | | | Queue | : | | | |--->| Memory |
Ingo Molnare0edc782013-11-22 11:24:53 +01002704 | | | | : | | | | | |
2705 +--------+ +--------+ : +--------+ | | | |
David Howells108b42b2006-03-31 16:00:29 +01002706 : | Cache | +--------+
2707 : | Coherency |
2708 : | Mechanism | +--------+
2709 +--------+ +--------+ : +--------+ | | | |
2710 | | | | : | | | | | |
2711 | CPU | | Memory | : | CPU | | |--->| Device |
Ingo Molnare0edc782013-11-22 11:24:53 +01002712 | Core |--->| Access |----->| Cache |<-->| | | |
2713 | | | Queue | : | | | | | |
David Howells108b42b2006-03-31 16:00:29 +01002714 | | | | : | | | | +--------+
2715 +--------+ +--------+ : +--------+ +-----------+
2716 :
2717 :
2718
2719Although any particular load or store may not actually appear outside of the
2720CPU that issued it since it may have been satisfied within the CPU's own cache,
2721it will still appear as if the full memory access had taken place as far as the
2722other CPUs are concerned since the cache coherency mechanisms will migrate the
2723cacheline over to the accessing CPU and propagate the effects upon conflict.
2724
2725The CPU core may execute instructions in any order it deems fit, provided the
2726expected program causality appears to be maintained. Some of the instructions
2727generate load and store operations which then go into the queue of memory
2728accesses to be performed. The core may place these in the queue in any order
2729it wishes, and continue execution until it is forced to wait for an instruction
2730to complete.
2731
2732What memory barriers are concerned with is controlling the order in which
2733accesses cross from the CPU side of things to the memory side of things, and
2734the order in which the effects are perceived to happen by the other observers
2735in the system.
2736
2737[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2738their own loads and stores as if they had happened in program order.
2739
2740[!] MMIO or other device accesses may bypass the cache system. This depends on
2741the properties of the memory window through which devices are accessed and/or
2742the use of any special device communication instructions the CPU may have.
2743
2744
2745CACHE COHERENCY
2746---------------
2747
2748Life isn't quite as simple as it may appear above, however: for while the
2749caches are expected to be coherent, there's no guarantee that that coherency
2750will be ordered. This means that whilst changes made on one CPU will
2751eventually become visible on all CPUs, there's no guarantee that they will
2752become apparent in the same order on those other CPUs.
2753
2754
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002755Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2756has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
David Howells108b42b2006-03-31 16:00:29 +01002757
2758 :
2759 : +--------+
2760 : +---------+ | |
2761 +--------+ : +--->| Cache A |<------->| |
2762 | | : | +---------+ | |
2763 | CPU 1 |<---+ | |
2764 | | : | +---------+ | |
2765 +--------+ : +--->| Cache B |<------->| |
2766 : +---------+ | |
2767 : | Memory |
2768 : +---------+ | System |
2769 +--------+ : +--->| Cache C |<------->| |
2770 | | : | +---------+ | |
2771 | CPU 2 |<---+ | |
2772 | | : | +---------+ | |
2773 +--------+ : +--->| Cache D |<------->| |
2774 : +---------+ | |
2775 : +--------+
2776 :
2777
2778Imagine the system has the following properties:
2779
2780 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2781 resident in memory;
2782
2783 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2784 resident in memory;
2785
2786 (*) whilst the CPU core is interrogating one cache, the other cache may be
2787 making use of the bus to access the rest of the system - perhaps to
2788 displace a dirty cacheline or to do a speculative load;
2789
2790 (*) each cache has a queue of operations that need to be applied to that cache
2791 to maintain coherency with the rest of the system;
2792
2793 (*) the coherency queue is not flushed by normal loads to lines already
2794 present in the cache, even though the contents of the queue may
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002795 potentially affect those loads.
David Howells108b42b2006-03-31 16:00:29 +01002796
2797Imagine, then, that two writes are made on the first CPU, with a write barrier
2798between them to guarantee that they will appear to reach that CPU's caches in
2799the requisite order:
2800
2801 CPU 1 CPU 2 COMMENT
2802 =============== =============== =======================================
2803 u == 0, v == 1 and p == &u, q == &u
2804 v = 2;
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002805 smp_wmb(); Make sure change to v is visible before
David Howells108b42b2006-03-31 16:00:29 +01002806 change to p
2807 <A:modify v=2> v is now in cache A exclusively
2808 p = &v;
2809 <B:modify p=&v> p is now in cache B exclusively
2810
2811The write memory barrier forces the other CPUs in the system to perceive that
2812the local CPU's caches have apparently been updated in the correct order. But
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002813now imagine that the second CPU wants to read those values:
David Howells108b42b2006-03-31 16:00:29 +01002814
2815 CPU 1 CPU 2 COMMENT
2816 =============== =============== =======================================
2817 ...
2818 q = p;
2819 x = *q;
2820
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002821The above pair of reads may then fail to happen in the expected order, as the
David Howells108b42b2006-03-31 16:00:29 +01002822cacheline holding p may get updated in one of the second CPU's caches whilst
2823the update to the cacheline holding v is delayed in the other of the second
2824CPU's caches by some other cache event:
2825
2826 CPU 1 CPU 2 COMMENT
2827 =============== =============== =======================================
2828 u == 0, v == 1 and p == &u, q == &u
2829 v = 2;
2830 smp_wmb();
2831 <A:modify v=2> <C:busy>
2832 <C:queue v=2>
Aneesh Kumar79afecf2006-05-15 09:44:36 -07002833 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01002834 <D:request p>
2835 <B:modify p=&v> <D:commit p=&v>
Ingo Molnare0edc782013-11-22 11:24:53 +01002836 <D:read p>
David Howells108b42b2006-03-31 16:00:29 +01002837 x = *q;
2838 <C:read *q> Reads from v before v updated in cache
2839 <C:unbusy>
2840 <C:commit v=2>
2841
2842Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2843no guarantee that, without intervention, the order of update will be the same
2844as that committed on CPU 1.
2845
2846
2847To intervene, we need to interpolate a data dependency barrier or a read
2848barrier between the loads. This will force the cache to commit its coherency
2849queue before processing any further requests:
2850
2851 CPU 1 CPU 2 COMMENT
2852 =============== =============== =======================================
2853 u == 0, v == 1 and p == &u, q == &u
2854 v = 2;
2855 smp_wmb();
2856 <A:modify v=2> <C:busy>
2857 <C:queue v=2>
Paolo 'Blaisorblade' Giarrusso3fda9822006-10-19 23:28:19 -07002858 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01002859 <D:request p>
2860 <B:modify p=&v> <D:commit p=&v>
Ingo Molnare0edc782013-11-22 11:24:53 +01002861 <D:read p>
David Howells108b42b2006-03-31 16:00:29 +01002862 smp_read_barrier_depends()
2863 <C:unbusy>
2864 <C:commit v=2>
2865 x = *q;
2866 <C:read *q> Reads from v after v updated in cache
2867
2868
2869This sort of problem can be encountered on DEC Alpha processors as they have a
2870split cache that improves performance by making better use of the data bus.
2871Whilst most CPUs do imply a data dependency barrier on the read when a memory
2872access depends on a read, not all do, so it may not be relied on.
2873
2874Other CPUs may also have split caches, but must coordinate between the various
Matt LaPlante3f6dee92006-10-03 22:45:33 +02002875cachelets for normal memory accesses. The semantics of the Alpha removes the
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002876need for coordination in the absence of memory barriers.
David Howells108b42b2006-03-31 16:00:29 +01002877
2878
2879CACHE COHERENCY VS DMA
2880----------------------
2881
2882Not all systems maintain cache coherency with respect to devices doing DMA. In
2883such cases, a device attempting DMA may obtain stale data from RAM because
2884dirty cache lines may be resident in the caches of various CPUs, and may not
2885have been written back to RAM yet. To deal with this, the appropriate part of
2886the kernel must flush the overlapping bits of cache on each CPU (and maybe
2887invalidate them as well).
2888
2889In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2890cache lines being written back to RAM from a CPU's cache after the device has
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002891installed its own data, or cache lines present in the CPU's cache may simply
2892obscure the fact that RAM has been updated, until at such time as the cacheline
2893is discarded from the CPU's cache and reloaded. To deal with this, the
2894appropriate part of the kernel must invalidate the overlapping bits of the
David Howells108b42b2006-03-31 16:00:29 +01002895cache on each CPU.
2896
2897See Documentation/cachetlb.txt for more information on cache management.
2898
2899
2900CACHE COHERENCY VS MMIO
2901-----------------------
2902
2903Memory mapped I/O usually takes place through memory locations that are part of
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002904a window in the CPU's memory space that has different properties assigned than
David Howells108b42b2006-03-31 16:00:29 +01002905the usual RAM directed window.
2906
2907Amongst these properties is usually the fact that such accesses bypass the
2908caching entirely and go directly to the device buses. This means MMIO accesses
2909may, in effect, overtake accesses to cached memory that were emitted earlier.
2910A memory barrier isn't sufficient in such a case, but rather the cache must be
2911flushed between the cached memory write and the MMIO access if the two are in
2912any way dependent.
2913
2914
2915=========================
2916THE THINGS CPUS GET UP TO
2917=========================
2918
2919A programmer might take it for granted that the CPU will perform memory
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002920operations in exactly the order specified, so that if the CPU is, for example,
David Howells108b42b2006-03-31 16:00:29 +01002921given the following piece of code to execute:
2922
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002923 a = READ_ONCE(*A);
2924 WRITE_ONCE(*B, b);
2925 c = READ_ONCE(*C);
2926 d = READ_ONCE(*D);
2927 WRITE_ONCE(*E, e);
David Howells108b42b2006-03-31 16:00:29 +01002928
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002929they would then expect that the CPU will complete the memory operation for each
David Howells108b42b2006-03-31 16:00:29 +01002930instruction before moving on to the next one, leading to a definite sequence of
2931operations as seen by external observers in the system:
2932
2933 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2934
2935
2936Reality is, of course, much messier. With many CPUs and compilers, the above
2937assumption doesn't hold because:
2938
2939 (*) loads are more likely to need to be completed immediately to permit
2940 execution progress, whereas stores can often be deferred without a
2941 problem;
2942
2943 (*) loads may be done speculatively, and the result discarded should it prove
2944 to have been unnecessary;
2945
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002946 (*) loads may be done speculatively, leading to the result having been fetched
2947 at the wrong time in the expected sequence of events;
David Howells108b42b2006-03-31 16:00:29 +01002948
2949 (*) the order of the memory accesses may be rearranged to promote better use
2950 of the CPU buses and caches;
2951
2952 (*) loads and stores may be combined to improve performance when talking to
2953 memory or I/O hardware that can do batched accesses of adjacent locations,
2954 thus cutting down on transaction setup costs (memory and PCI devices may
2955 both be able to do this); and
2956
2957 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2958 mechanisms may alleviate this - once the store has actually hit the cache
2959 - there's no guarantee that the coherency management will be propagated in
2960 order to other CPUs.
2961
2962So what another CPU, say, might actually observe from the above piece of code
2963is:
2964
2965 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2966
2967 (Where "LOAD {*C,*D}" is a combined load)
2968
2969
2970However, it is guaranteed that a CPU will be self-consistent: it will see its
2971_own_ accesses appear to be correctly ordered, without the need for a memory
2972barrier. For instance with the following code:
2973
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002974 U = READ_ONCE(*A);
2975 WRITE_ONCE(*A, V);
2976 WRITE_ONCE(*A, W);
2977 X = READ_ONCE(*A);
2978 WRITE_ONCE(*A, Y);
2979 Z = READ_ONCE(*A);
David Howells108b42b2006-03-31 16:00:29 +01002980
2981and assuming no intervention by an external influence, it can be assumed that
2982the final result will appear to be:
2983
2984 U == the original value of *A
2985 X == W
2986 Z == Y
2987 *A == Y
2988
2989The code above may cause the CPU to generate the full sequence of memory
2990accesses:
2991
2992 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2993
2994in that order, but, without intervention, the sequence may have almost any
Paul E. McKenney9af194c2015-06-18 14:33:24 -07002995combination of elements combined or discarded, provided the program's view
2996of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2997are -not- optional in the above example, as there are architectures
2998where a given CPU might reorder successive loads to the same location.
2999On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
3000necessary to prevent this, for example, on Itanium the volatile casts
3001used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
3002and st.rel instructions (respectively) that prevent such reordering.
David Howells108b42b2006-03-31 16:00:29 +01003003
3004The compiler may also combine, discard or defer elements of the sequence before
3005the CPU even sees them.
3006
3007For instance:
3008
3009 *A = V;
3010 *A = W;
3011
3012may be reduced to:
3013
3014 *A = W;
3015
Paul E. McKenney9af194c2015-06-18 14:33:24 -07003016since, without either a write barrier or an WRITE_ONCE(), it can be
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08003017assumed that the effect of the storage of V to *A is lost. Similarly:
David Howells108b42b2006-03-31 16:00:29 +01003018
3019 *A = Y;
3020 Z = *A;
3021
Paul E. McKenney9af194c2015-06-18 14:33:24 -07003022may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
3023reduced to:
David Howells108b42b2006-03-31 16:00:29 +01003024
3025 *A = Y;
3026 Z = Y;
3027
3028and the LOAD operation never appear outside of the CPU.
3029
3030
3031AND THEN THERE'S THE ALPHA
3032--------------------------
3033
3034The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
3035some versions of the Alpha CPU have a split data cache, permitting them to have
Jarek Poplawski81fc6322007-05-23 13:58:20 -07003036two semantically-related cache lines updated at separate times. This is where
David Howells108b42b2006-03-31 16:00:29 +01003037the data dependency barrier really becomes necessary as this synchronises both
3038caches with the memory coherence system, thus making it seem like pointer
3039changes vs new data occur in the right order.
3040
Jarek Poplawski81fc6322007-05-23 13:58:20 -07003041The Alpha defines the Linux kernel's memory barrier model.
David Howells108b42b2006-03-31 16:00:29 +01003042
3043See the subsection on "Cache Coherency" above.
3044
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02003045VIRTUAL MACHINE GUESTS
SeongJae Park3dbf0912016-04-12 08:52:52 -07003046----------------------
Michael S. Tsirkin6a65d262015-12-27 18:23:01 +02003047
3048Guests running within virtual machines might be affected by SMP effects even if
3049the guest itself is compiled without SMP support. This is an artifact of
3050interfacing with an SMP host while running an UP kernel. Using mandatory
3051barriers for this use-case would be possible but is often suboptimal.
3052
3053To handle this case optimally, low-level virt_mb() etc macros are available.
3054These have the same effect as smp_mb() etc when SMP is enabled, but generate
3055identical code for SMP and non-SMP systems. For example, virtual machine guests
3056should use virt_mb() rather than smp_mb() when synchronizing against a
3057(possibly SMP) host.
3058
3059These are equivalent to smp_mb() etc counterparts in all other respects,
3060in particular, they do not control MMIO effects: to control
3061MMIO effects, use mandatory barriers.
David Howells108b42b2006-03-31 16:00:29 +01003062
David Howells90fddab2010-03-24 09:43:00 +00003063============
3064EXAMPLE USES
3065============
3066
3067CIRCULAR BUFFERS
3068----------------
3069
3070Memory barriers can be used to implement circular buffering without the need
3071of a lock to serialise the producer with the consumer. See:
3072
3073 Documentation/circular-buffers.txt
3074
3075for details.
3076
3077
David Howells108b42b2006-03-31 16:00:29 +01003078==========
3079REFERENCES
3080==========
3081
3082Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
3083Digital Press)
3084 Chapter 5.2: Physical Address Space Characteristics
3085 Chapter 5.4: Caches and Write Buffers
3086 Chapter 5.5: Data Sharing
3087 Chapter 5.6: Read/Write Ordering
3088
3089AMD64 Architecture Programmer's Manual Volume 2: System Programming
3090 Chapter 7.1: Memory-Access Ordering
3091 Chapter 7.4: Buffering and Combining Memory Writes
3092
3093IA-32 Intel Architecture Software Developer's Manual, Volume 3:
3094System Programming Guide
3095 Chapter 7.1: Locked Atomic Operations
3096 Chapter 7.2: Memory Ordering
3097 Chapter 7.4: Serializing Instructions
3098
3099The SPARC Architecture Manual, Version 9
3100 Chapter 8: Memory Models
3101 Appendix D: Formal Specification of the Memory Models
3102 Appendix J: Programming with the Memory Models
3103
3104UltraSPARC Programmer Reference Manual
3105 Chapter 5: Memory Accesses and Cacheability
3106 Chapter 15: Sparc-V9 Memory Models
3107
3108UltraSPARC III Cu User's Manual
3109 Chapter 9: Memory Models
3110
3111UltraSPARC IIIi Processor User's Manual
3112 Chapter 8: Memory Models
3113
3114UltraSPARC Architecture 2005
3115 Chapter 9: Memory
3116 Appendix D: Formal Specifications of the Memory Models
3117
3118UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3119 Chapter 8: Memory Models
3120 Appendix F: Caches and Cache Coherency
3121
3122Solaris Internals, Core Kernel Architecture, p63-68:
3123 Chapter 3.3: Hardware Considerations for Locks and
3124 Synchronization
3125
3126Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3127for Kernel Programmers:
3128 Chapter 13: Other Memory Models
3129
3130Intel Itanium Architecture Software Developer's Manual: Volume 1:
3131 Section 2.6: Speculation
3132 Section 4.4: Memory Access