Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1 | /* |
| 2 | * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform |
| 3 | * driver source file |
| 4 | * |
Sujit Reddy Thumma | bf1aecc | 2014-01-10 10:58:54 +0530 | [diff] [blame] | 5 | * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 and |
| 9 | * only version 2 as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/mmc/host.h> |
| 20 | #include <linux/mmc/card.h> |
| 21 | #include <linux/mmc/sdio_func.h> |
| 22 | #include <linux/gfp.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/of_gpio.h> |
| 25 | #include <linux/regulator/consumer.h> |
| 26 | #include <linux/types.h> |
| 27 | #include <linux/input.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/wait.h> |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 30 | #include <linux/io.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/scatterlist.h> |
| 33 | #include <linux/slab.h> |
| 34 | #include <linux/mmc/mmc.h> |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 35 | #include <linux/mmc/slot-gpio.h> |
Sahitya Tummala | eaa2186 | 2013-03-20 19:34:59 +0530 | [diff] [blame] | 36 | #include <linux/dma-mapping.h> |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 37 | #include <linux/iopoll.h> |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 38 | #include <linux/pinctrl/consumer.h> |
| 39 | #include <linux/iopoll.h> |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 40 | #include <linux/msm-bus.h> |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 41 | |
| 42 | #include "sdhci-pltfm.h" |
| 43 | |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 44 | #define SDHCI_VER_100 0x2B |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 45 | |
| 46 | #define CORE_VERSION_MAJOR_MASK 0xF0000000 |
| 47 | #define CORE_VERSION_MAJOR_SHIFT 28 |
| 48 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 49 | #define CORE_HC_MODE 0x78 |
| 50 | #define HC_MODE_EN 0x1 |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 51 | #define FF_CLK_SW_RST_DIS (1 << 13) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 52 | |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 53 | #define CORE_GENERICS 0x70 |
| 54 | #define SWITCHABLE_SIGNALLING_VOL (1 << 29) |
| 55 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 56 | #define CORE_POWER 0x0 |
| 57 | #define CORE_SW_RST (1 << 7) |
| 58 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 59 | #define CORE_MCI_VERSION 0x050 |
| 60 | #define CORE_TESTBUS_CONFIG 0x0CC |
| 61 | #define CORE_TESTBUS_ENA (1 << 3) |
| 62 | #define CORE_SDCC_DEBUG_REG 0x124 |
| 63 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 64 | #define CORE_PWRCTL_STATUS 0xDC |
| 65 | #define CORE_PWRCTL_MASK 0xE0 |
| 66 | #define CORE_PWRCTL_CLEAR 0xE4 |
| 67 | #define CORE_PWRCTL_CTL 0xE8 |
| 68 | |
| 69 | #define CORE_PWRCTL_BUS_OFF 0x01 |
| 70 | #define CORE_PWRCTL_BUS_ON (1 << 1) |
| 71 | #define CORE_PWRCTL_IO_LOW (1 << 2) |
| 72 | #define CORE_PWRCTL_IO_HIGH (1 << 3) |
| 73 | |
| 74 | #define CORE_PWRCTL_BUS_SUCCESS 0x01 |
| 75 | #define CORE_PWRCTL_BUS_FAIL (1 << 1) |
| 76 | #define CORE_PWRCTL_IO_SUCCESS (1 << 2) |
| 77 | #define CORE_PWRCTL_IO_FAIL (1 << 3) |
| 78 | |
| 79 | #define INT_MASK 0xF |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 80 | #define MAX_PHASES 16 |
| 81 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 82 | #define CORE_DLL_CONFIG 0x100 |
| 83 | #define CORE_CMD_DAT_TRACK_SEL (1 << 0) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 84 | #define CORE_DLL_EN (1 << 16) |
| 85 | #define CORE_CDR_EN (1 << 17) |
| 86 | #define CORE_CK_OUT_EN (1 << 18) |
| 87 | #define CORE_CDR_EXT_EN (1 << 19) |
| 88 | #define CORE_DLL_PDN (1 << 29) |
| 89 | #define CORE_DLL_RST (1 << 30) |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 90 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 91 | #define CORE_DLL_STATUS 0x108 |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 92 | #define CORE_DLL_LOCK (1 << 7) |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 93 | #define CORE_DDR_DLL_LOCK (1 << 11) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 94 | |
| 95 | #define CORE_VENDOR_SPEC 0x10C |
| 96 | #define CORE_CLK_PWRSAVE (1 << 1) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 97 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
| 98 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) |
| 99 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 100 | #define CORE_HC_AUTO_CMD21_EN (1 << 6) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 101 | #define CORE_IO_PAD_PWR_SWITCH (1 << 16) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 102 | #define CORE_HC_SELECT_IN_EN (1 << 18) |
| 103 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) |
| 104 | #define CORE_HC_SELECT_IN_MASK (7 << 19) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 105 | |
Krishna Konda | 7feab35 | 2013-09-17 23:55:40 -0700 | [diff] [blame] | 106 | #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11C |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 107 | #define CORE_8_BIT_SUPPORT (1 << 18) |
| 108 | #define CORE_3_3V_SUPPORT (1 << 24) |
| 109 | #define CORE_3_0V_SUPPORT (1 << 25) |
| 110 | #define CORE_1_8V_SUPPORT (1 << 26) |
Krishna Konda | 7feab35 | 2013-09-17 23:55:40 -0700 | [diff] [blame] | 111 | #define CORE_SYS_BUS_SUPPORT_64_BIT 28 |
| 112 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 113 | #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114 |
| 114 | #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118 |
| 115 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 116 | #define CORE_CSR_CDC_CTLR_CFG0 0x130 |
| 117 | #define CORE_SW_TRIG_FULL_CALIB (1 << 16) |
| 118 | #define CORE_HW_AUTOCAL_ENA (1 << 17) |
| 119 | |
| 120 | #define CORE_CSR_CDC_CTLR_CFG1 0x134 |
| 121 | #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 |
| 122 | #define CORE_TIMER_ENA (1 << 16) |
| 123 | |
| 124 | #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C |
| 125 | #define CORE_CSR_CDC_REFCOUNT_CFG 0x140 |
| 126 | #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 |
| 127 | #define CORE_CDC_OFFSET_CFG 0x14C |
| 128 | #define CORE_CSR_CDC_DELAY_CFG 0x150 |
| 129 | #define CORE_CDC_SLAVE_DDA_CFG 0x160 |
| 130 | #define CORE_CSR_CDC_STATUS0 0x164 |
| 131 | #define CORE_CALIBRATION_DONE (1 << 0) |
| 132 | |
| 133 | #define CORE_CDC_ERROR_CODE_MASK 0x7000000 |
| 134 | |
| 135 | #define CORE_CSR_CDC_GEN_CFG 0x178 |
| 136 | #define CORE_CDC_SWITCH_BYPASS_OFF (1 << 0) |
| 137 | #define CORE_CDC_SWITCH_RC_EN (1 << 1) |
| 138 | |
| 139 | #define CORE_DDR_200_CFG 0x184 |
| 140 | #define CORE_CDC_T4_DLY_SEL (1 << 0) |
| 141 | #define CORE_START_CDC_TRAFFIC (1 << 6) |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 142 | #define CORE_VENDOR_SPEC3 0x1B0 |
| 143 | #define CORE_PWRSAVE_DLL (1 << 3) |
| 144 | |
| 145 | #define CORE_DLL_CONFIG_2 0x1B4 |
| 146 | #define CORE_DDR_CAL_EN (1 << 0) |
| 147 | |
| 148 | #define CORE_DDR_CONFIG 0x1B8 |
| 149 | #define DDR_CONFIG_POR_VAL 0x80040853 |
| 150 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 151 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 152 | #define CORE_MCI_DATA_CNT 0x30 |
| 153 | #define CORE_MCI_STATUS 0x34 |
| 154 | #define CORE_MCI_FIFO_CNT 0x44 |
| 155 | |
| 156 | #define CORE_TESTBUS_SEL2_BIT 4 |
| 157 | #define CORE_TESTBUS_SEL2 (1 << CORE_TESTBUS_SEL2_BIT) |
| 158 | |
Venkat Gopalakrishnan | 450745e | 2014-07-24 20:39:34 -0700 | [diff] [blame^] | 159 | /* 512 descriptors */ |
| 160 | #define SDHCI_MSM_MAX_SEGMENTS (1 << 9) |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 161 | #define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */ |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 162 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 163 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
| 164 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 165 | #define INVALID_TUNING_PHASE -1 |
| 166 | |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 167 | #define CORE_VERSION_TARGET_MASK 0x000000FF |
| 168 | |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 169 | #define NUM_TUNING_PHASES 16 |
| 170 | #define MAX_DRV_TYPES_SUPPORTED_HS200 3 |
| 171 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 172 | static const u32 tuning_block_64[] = { |
| 173 | 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE, |
| 174 | 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777, |
| 175 | 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF, |
| 176 | 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7 |
| 177 | }; |
| 178 | |
| 179 | static const u32 tuning_block_128[] = { |
| 180 | 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC, |
| 181 | 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF, |
| 182 | 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF, |
| 183 | 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB, |
| 184 | 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC, |
| 185 | 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF, |
| 186 | 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB, |
| 187 | 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77 |
| 188 | }; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 189 | |
Venkat Gopalakrishnan | 270580a | 2013-03-11 12:17:57 -0700 | [diff] [blame] | 190 | static int disable_slots; |
| 191 | /* root can write, others read */ |
| 192 | module_param(disable_slots, int, S_IRUGO|S_IWUSR); |
| 193 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 194 | /* This structure keeps information per regulator */ |
| 195 | struct sdhci_msm_reg_data { |
| 196 | /* voltage regulator handle */ |
| 197 | struct regulator *reg; |
| 198 | /* regulator name */ |
| 199 | const char *name; |
| 200 | /* voltage level to be set */ |
| 201 | u32 low_vol_level; |
| 202 | u32 high_vol_level; |
| 203 | /* Load values for low power and high power mode */ |
| 204 | u32 lpm_uA; |
| 205 | u32 hpm_uA; |
| 206 | |
| 207 | /* is this regulator enabled? */ |
| 208 | bool is_enabled; |
| 209 | /* is this regulator needs to be always on? */ |
| 210 | bool is_always_on; |
| 211 | /* is low power mode setting required for this regulator? */ |
| 212 | bool lpm_sup; |
| 213 | bool set_voltage_sup; |
| 214 | }; |
| 215 | |
Asutosh Das | 598a4d4 | 2014-02-05 16:38:23 +0530 | [diff] [blame] | 216 | #define MSM_MMC_DEFAULT_CPU_DMA_LATENCY 200 /* usecs */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 217 | /* |
| 218 | * This structure keeps information for all the |
| 219 | * regulators required for a SDCC slot. |
| 220 | */ |
| 221 | struct sdhci_msm_slot_reg_data { |
| 222 | /* keeps VDD/VCC regulator info */ |
| 223 | struct sdhci_msm_reg_data *vdd_data; |
| 224 | /* keeps VDD IO regulator info */ |
| 225 | struct sdhci_msm_reg_data *vdd_io_data; |
| 226 | }; |
| 227 | |
| 228 | struct sdhci_msm_gpio { |
| 229 | u32 no; |
| 230 | const char *name; |
| 231 | bool is_enabled; |
| 232 | }; |
| 233 | |
| 234 | struct sdhci_msm_gpio_data { |
| 235 | struct sdhci_msm_gpio *gpio; |
| 236 | u8 size; |
| 237 | }; |
| 238 | |
| 239 | struct sdhci_msm_pin_data { |
| 240 | /* |
| 241 | * = 1 if controller pins are using gpios |
| 242 | * = 0 if controller has dedicated MSM pads |
| 243 | */ |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 244 | u8 is_gpio; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 245 | struct sdhci_msm_gpio_data *gpio_data; |
| 246 | }; |
| 247 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 248 | struct sdhci_pinctrl_data { |
| 249 | struct pinctrl *pctrl; |
| 250 | struct pinctrl_state *pins_active; |
| 251 | struct pinctrl_state *pins_sleep; |
| 252 | }; |
| 253 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 254 | struct sdhci_msm_bus_voting_data { |
| 255 | struct msm_bus_scale_pdata *bus_pdata; |
| 256 | unsigned int *bw_vecs; |
| 257 | unsigned int bw_vecs_size; |
| 258 | }; |
| 259 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 260 | struct sdhci_msm_pltfm_data { |
| 261 | /* Supported UHS-I Modes */ |
| 262 | u32 caps; |
| 263 | |
| 264 | /* More capabilities */ |
| 265 | u32 caps2; |
| 266 | |
| 267 | unsigned long mmc_bus_width; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 268 | struct sdhci_msm_slot_reg_data *vreg_data; |
| 269 | bool nonremovable; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 270 | bool pin_cfg_sts; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 271 | struct sdhci_msm_pin_data *pin_data; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 272 | struct sdhci_pinctrl_data *pctrl_data; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 273 | u32 cpu_dma_latency_us; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 274 | int status_gpio; /* card detection GPIO that is configured as IRQ */ |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 275 | struct sdhci_msm_bus_voting_data *voting_data; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 276 | u32 *sup_clk_table; |
| 277 | unsigned char sup_clk_cnt; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 278 | }; |
| 279 | |
| 280 | struct sdhci_msm_bus_vote { |
| 281 | uint32_t client_handle; |
| 282 | uint32_t curr_vote; |
| 283 | int min_bw_vote; |
| 284 | int max_bw_vote; |
| 285 | bool is_max_bw_needed; |
| 286 | struct delayed_work vote_work; |
| 287 | struct device_attribute max_bus_bw; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | struct sdhci_msm_host { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 291 | struct platform_device *pdev; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 292 | void __iomem *core_mem; /* MSM SDCC mapped address */ |
| 293 | struct clk *clk; /* main SD/MMC bus clock */ |
| 294 | struct clk *pclk; /* SDHC peripheral bus clock */ |
| 295 | struct clk *bus_clk; /* SDHC bus voter clock */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 296 | struct clk *ff_clk; /* CDC calibration fixed feedback clock */ |
| 297 | struct clk *sleep_clk; /* CDC calibration sleep clock */ |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 298 | atomic_t clks_on; /* Set if clocks are enabled */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 299 | struct sdhci_msm_pltfm_data *pdata; |
| 300 | struct mmc_host *mmc; |
| 301 | struct sdhci_pltfm_data sdhci_msm_pdata; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 302 | u32 curr_pwr_state; |
| 303 | u32 curr_io_level; |
| 304 | struct completion pwr_irq_completion; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 305 | struct sdhci_msm_bus_vote msm_bus_vote; |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 306 | struct device_attribute polling; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 307 | u32 clk_rate; /* Keeps track of current clock rate that is set */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 308 | bool tuning_done; |
| 309 | bool calibration_done; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 310 | u8 saved_tuning_phase; |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 311 | bool en_auto_cmd21; |
| 312 | struct device_attribute auto_cmd21_attr; |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 313 | atomic_t controller_clock; |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 314 | bool use_cdclp533; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | enum vdd_io_level { |
| 318 | /* set vdd_io_data->low_vol_level */ |
| 319 | VDD_IO_LOW, |
| 320 | /* set vdd_io_data->high_vol_level */ |
| 321 | VDD_IO_HIGH, |
| 322 | /* |
| 323 | * set whatever there in voltage_level (third argument) of |
| 324 | * sdhci_msm_set_vdd_io_vol() function. |
| 325 | */ |
| 326 | VDD_IO_SET_LEVEL, |
| 327 | }; |
| 328 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 329 | /* MSM platform specific tuning */ |
| 330 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, |
| 331 | u8 poll) |
| 332 | { |
| 333 | int rc = 0; |
| 334 | u32 wait_cnt = 50; |
| 335 | u8 ck_out_en = 0; |
| 336 | struct mmc_host *mmc = host->mmc; |
| 337 | |
| 338 | /* poll for CK_OUT_EN bit. max. poll time = 50us */ |
| 339 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & |
| 340 | CORE_CK_OUT_EN); |
| 341 | |
| 342 | while (ck_out_en != poll) { |
| 343 | if (--wait_cnt == 0) { |
| 344 | pr_err("%s: %s: CK_OUT_EN bit is not %d\n", |
| 345 | mmc_hostname(mmc), __func__, poll); |
| 346 | rc = -ETIMEDOUT; |
| 347 | goto out; |
| 348 | } |
| 349 | udelay(1); |
| 350 | |
| 351 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
| 352 | CORE_DLL_CONFIG) & CORE_CK_OUT_EN); |
| 353 | } |
| 354 | out: |
| 355 | return rc; |
| 356 | } |
| 357 | |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 358 | /* |
| 359 | * Enable CDR to track changes of DAT lines and adjust sampling |
| 360 | * point according to voltage/temperature variations |
| 361 | */ |
| 362 | static int msm_enable_cdr_cm_sdc4_dll(struct sdhci_host *host) |
| 363 | { |
| 364 | int rc = 0; |
| 365 | u32 config; |
| 366 | |
| 367 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 368 | config |= CORE_CDR_EN; |
| 369 | config &= ~(CORE_CDR_EXT_EN | CORE_CK_OUT_EN); |
| 370 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 371 | |
| 372 | rc = msm_dll_poll_ck_out_en(host, 0); |
| 373 | if (rc) |
| 374 | goto err; |
| 375 | |
| 376 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) | |
| 377 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 378 | |
| 379 | rc = msm_dll_poll_ck_out_en(host, 1); |
| 380 | if (rc) |
| 381 | goto err; |
| 382 | goto out; |
| 383 | err: |
| 384 | pr_err("%s: %s: failed\n", mmc_hostname(host->mmc), __func__); |
| 385 | out: |
| 386 | return rc; |
| 387 | } |
| 388 | |
| 389 | static ssize_t store_auto_cmd21(struct device *dev, struct device_attribute |
| 390 | *attr, const char *buf, size_t count) |
| 391 | { |
| 392 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 393 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 394 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 395 | u32 tmp; |
| 396 | unsigned long flags; |
| 397 | |
| 398 | if (!kstrtou32(buf, 0, &tmp)) { |
| 399 | spin_lock_irqsave(&host->lock, flags); |
| 400 | msm_host->en_auto_cmd21 = !!tmp; |
| 401 | spin_unlock_irqrestore(&host->lock, flags); |
| 402 | } |
| 403 | return count; |
| 404 | } |
| 405 | |
| 406 | static ssize_t show_auto_cmd21(struct device *dev, |
| 407 | struct device_attribute *attr, char *buf) |
| 408 | { |
| 409 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 410 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 411 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 412 | |
| 413 | return snprintf(buf, PAGE_SIZE, "%d\n", msm_host->en_auto_cmd21); |
| 414 | } |
| 415 | |
| 416 | /* MSM auto-tuning handler */ |
| 417 | static int sdhci_msm_config_auto_tuning_cmd(struct sdhci_host *host, |
| 418 | bool enable, |
| 419 | u32 type) |
| 420 | { |
| 421 | int rc = 0; |
| 422 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 423 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 424 | u32 val = 0; |
| 425 | |
| 426 | if (!msm_host->en_auto_cmd21) |
| 427 | return 0; |
| 428 | |
| 429 | if (type == MMC_SEND_TUNING_BLOCK_HS200) |
| 430 | val = CORE_HC_AUTO_CMD21_EN; |
| 431 | else |
| 432 | return 0; |
| 433 | |
| 434 | if (enable) { |
| 435 | rc = msm_enable_cdr_cm_sdc4_dll(host); |
| 436 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | |
| 437 | val, host->ioaddr + CORE_VENDOR_SPEC); |
| 438 | } else { |
| 439 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 440 | ~val, host->ioaddr + CORE_VENDOR_SPEC); |
| 441 | } |
| 442 | return rc; |
| 443 | } |
| 444 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 445 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) |
| 446 | { |
| 447 | int rc = 0; |
| 448 | u8 grey_coded_phase_table[] = {0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, |
| 449 | 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, |
| 450 | 0x8}; |
| 451 | unsigned long flags; |
| 452 | u32 config; |
| 453 | struct mmc_host *mmc = host->mmc; |
| 454 | |
| 455 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 456 | spin_lock_irqsave(&host->lock, flags); |
| 457 | |
| 458 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 459 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); |
| 460 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); |
| 461 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 462 | |
| 463 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ |
| 464 | rc = msm_dll_poll_ck_out_en(host, 0); |
| 465 | if (rc) |
| 466 | goto err_out; |
| 467 | |
| 468 | /* |
| 469 | * Write the selected DLL clock output phase (0 ... 15) |
| 470 | * to CDR_SELEXT bit field of DLL_CONFIG register. |
| 471 | */ |
| 472 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 473 | & ~(0xF << 20)) |
| 474 | | (grey_coded_phase_table[phase] << 20)), |
| 475 | host->ioaddr + CORE_DLL_CONFIG); |
| 476 | |
| 477 | /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ |
| 478 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 479 | | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 480 | |
| 481 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ |
| 482 | rc = msm_dll_poll_ck_out_en(host, 1); |
| 483 | if (rc) |
| 484 | goto err_out; |
| 485 | |
| 486 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 487 | config |= CORE_CDR_EN; |
| 488 | config &= ~CORE_CDR_EXT_EN; |
| 489 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 490 | goto out; |
| 491 | |
| 492 | err_out: |
| 493 | pr_err("%s: %s: Failed to set DLL phase: %d\n", |
| 494 | mmc_hostname(mmc), __func__, phase); |
| 495 | out: |
| 496 | spin_unlock_irqrestore(&host->lock, flags); |
| 497 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 498 | return rc; |
| 499 | } |
| 500 | |
| 501 | /* |
| 502 | * Find out the greatest range of consecuitive selected |
| 503 | * DLL clock output phases that can be used as sampling |
| 504 | * setting for SD3.0 UHS-I card read operation (in SDR104 |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 505 | * timing mode) or for eMMC4.5 card read operation (in |
| 506 | * HS400/HS200 timing mode). |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 507 | * Select the 3/4 of the range and configure the DLL with the |
| 508 | * selected DLL clock output phase. |
| 509 | */ |
| 510 | |
| 511 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, |
| 512 | u8 *phase_table, u8 total_phases) |
| 513 | { |
| 514 | int ret; |
| 515 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; |
| 516 | u8 phases_per_row[MAX_PHASES] = {0}; |
| 517 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; |
| 518 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; |
| 519 | bool phase_0_found = false, phase_15_found = false; |
| 520 | struct mmc_host *mmc = host->mmc; |
| 521 | |
| 522 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 523 | if (!total_phases || (total_phases > MAX_PHASES)) { |
| 524 | pr_err("%s: %s: invalid argument: total_phases=%d\n", |
| 525 | mmc_hostname(mmc), __func__, total_phases); |
| 526 | return -EINVAL; |
| 527 | } |
| 528 | |
| 529 | for (cnt = 0; cnt < total_phases; cnt++) { |
| 530 | ranges[row_index][col_index] = phase_table[cnt]; |
| 531 | phases_per_row[row_index] += 1; |
| 532 | col_index++; |
| 533 | |
| 534 | if ((cnt + 1) == total_phases) { |
| 535 | continue; |
| 536 | /* check if next phase in phase_table is consecutive or not */ |
| 537 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { |
| 538 | row_index++; |
| 539 | col_index = 0; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | if (row_index >= MAX_PHASES) |
| 544 | return -EINVAL; |
| 545 | |
| 546 | /* Check if phase-0 is present in first valid window? */ |
| 547 | if (!ranges[0][0]) { |
| 548 | phase_0_found = true; |
| 549 | phase_0_raw_index = 0; |
| 550 | /* Check if cycle exist between 2 valid windows */ |
| 551 | for (cnt = 1; cnt <= row_index; cnt++) { |
| 552 | if (phases_per_row[cnt]) { |
| 553 | for (i = 0; i < phases_per_row[cnt]; i++) { |
| 554 | if (ranges[cnt][i] == 15) { |
| 555 | phase_15_found = true; |
| 556 | phase_15_raw_index = cnt; |
| 557 | break; |
| 558 | } |
| 559 | } |
| 560 | } |
| 561 | } |
| 562 | } |
| 563 | |
| 564 | /* If 2 valid windows form cycle then merge them as single window */ |
| 565 | if (phase_0_found && phase_15_found) { |
| 566 | /* number of phases in raw where phase 0 is present */ |
| 567 | u8 phases_0 = phases_per_row[phase_0_raw_index]; |
| 568 | /* number of phases in raw where phase 15 is present */ |
| 569 | u8 phases_15 = phases_per_row[phase_15_raw_index]; |
| 570 | |
| 571 | if (phases_0 + phases_15 >= MAX_PHASES) |
| 572 | /* |
| 573 | * If there are more than 1 phase windows then total |
| 574 | * number of phases in both the windows should not be |
| 575 | * more than or equal to MAX_PHASES. |
| 576 | */ |
| 577 | return -EINVAL; |
| 578 | |
| 579 | /* Merge 2 cyclic windows */ |
| 580 | i = phases_15; |
| 581 | for (cnt = 0; cnt < phases_0; cnt++) { |
| 582 | ranges[phase_15_raw_index][i] = |
| 583 | ranges[phase_0_raw_index][cnt]; |
| 584 | if (++i >= MAX_PHASES) |
| 585 | break; |
| 586 | } |
| 587 | |
| 588 | phases_per_row[phase_0_raw_index] = 0; |
| 589 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; |
| 590 | } |
| 591 | |
| 592 | for (cnt = 0; cnt <= row_index; cnt++) { |
| 593 | if (phases_per_row[cnt] > curr_max) { |
| 594 | curr_max = phases_per_row[cnt]; |
| 595 | selected_row_index = cnt; |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | i = ((curr_max * 3) / 4); |
| 600 | if (i) |
| 601 | i--; |
| 602 | |
| 603 | ret = (int)ranges[selected_row_index][i]; |
| 604 | |
| 605 | if (ret >= MAX_PHASES) { |
| 606 | ret = -EINVAL; |
| 607 | pr_err("%s: %s: invalid phase selected=%d\n", |
| 608 | mmc_hostname(mmc), __func__, ret); |
| 609 | } |
| 610 | |
| 611 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 612 | return ret; |
| 613 | } |
| 614 | |
| 615 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) |
| 616 | { |
| 617 | u32 mclk_freq = 0; |
| 618 | |
| 619 | /* Program the MCLK value to MCLK_FREQ bit field */ |
| 620 | if (host->clock <= 112000000) |
| 621 | mclk_freq = 0; |
| 622 | else if (host->clock <= 125000000) |
| 623 | mclk_freq = 1; |
| 624 | else if (host->clock <= 137000000) |
| 625 | mclk_freq = 2; |
| 626 | else if (host->clock <= 150000000) |
| 627 | mclk_freq = 3; |
| 628 | else if (host->clock <= 162000000) |
| 629 | mclk_freq = 4; |
| 630 | else if (host->clock <= 175000000) |
| 631 | mclk_freq = 5; |
| 632 | else if (host->clock <= 187000000) |
| 633 | mclk_freq = 6; |
| 634 | else if (host->clock <= 200000000) |
| 635 | mclk_freq = 7; |
| 636 | |
| 637 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 638 | & ~(7 << 24)) | (mclk_freq << 24)), |
| 639 | host->ioaddr + CORE_DLL_CONFIG); |
| 640 | } |
| 641 | |
| 642 | /* Initialize the DLL (Programmable Delay Line ) */ |
| 643 | static int msm_init_cm_dll(struct sdhci_host *host) |
| 644 | { |
| 645 | struct mmc_host *mmc = host->mmc; |
| 646 | int rc = 0; |
| 647 | unsigned long flags; |
| 648 | u32 wait_cnt; |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 649 | bool prev_pwrsave, curr_pwrsave; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 650 | |
| 651 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 652 | spin_lock_irqsave(&host->lock, flags); |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 653 | prev_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 654 | CORE_CLK_PWRSAVE); |
| 655 | curr_pwrsave = prev_pwrsave; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 656 | /* |
| 657 | * Make sure that clock is always enabled when DLL |
| 658 | * tuning is in progress. Keeping PWRSAVE ON may |
| 659 | * turn off the clock. So let's disable the PWRSAVE |
| 660 | * here and re-enable it once tuning is completed. |
| 661 | */ |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 662 | if (prev_pwrsave) { |
| 663 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 664 | & ~CORE_CLK_PWRSAVE), |
| 665 | host->ioaddr + CORE_VENDOR_SPEC); |
| 666 | curr_pwrsave = false; |
| 667 | } |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 668 | |
| 669 | /* Write 1 to DLL_RST bit of DLL_CONFIG register */ |
| 670 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 671 | | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); |
| 672 | |
| 673 | /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ |
| 674 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 675 | | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); |
| 676 | msm_cm_dll_set_freq(host); |
| 677 | |
| 678 | /* Write 0 to DLL_RST bit of DLL_CONFIG register */ |
| 679 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 680 | & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); |
| 681 | |
| 682 | /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ |
| 683 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 684 | & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); |
| 685 | |
| 686 | /* Set DLL_EN bit to 1. */ |
| 687 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 688 | | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 689 | |
| 690 | /* Set CK_OUT_EN bit to 1. */ |
| 691 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 692 | | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 693 | |
| 694 | wait_cnt = 50; |
| 695 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ |
| 696 | while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & |
| 697 | CORE_DLL_LOCK)) { |
| 698 | /* max. wait for 50us sec for LOCK bit to be set */ |
| 699 | if (--wait_cnt == 0) { |
| 700 | pr_err("%s: %s: DLL failed to LOCK\n", |
| 701 | mmc_hostname(mmc), __func__); |
| 702 | rc = -ETIMEDOUT; |
| 703 | goto out; |
| 704 | } |
| 705 | /* wait for 1us before polling again */ |
| 706 | udelay(1); |
| 707 | } |
| 708 | |
| 709 | out: |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 710 | /* Restore the correct PWRSAVE state */ |
| 711 | if (prev_pwrsave ^ curr_pwrsave) { |
| 712 | u32 reg = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); |
| 713 | |
| 714 | if (prev_pwrsave) |
| 715 | reg |= CORE_CLK_PWRSAVE; |
| 716 | else |
| 717 | reg &= ~CORE_CLK_PWRSAVE; |
| 718 | |
| 719 | writel_relaxed(reg, host->ioaddr + CORE_VENDOR_SPEC); |
| 720 | } |
| 721 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 722 | spin_unlock_irqrestore(&host->lock, flags); |
| 723 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 724 | return rc; |
| 725 | } |
| 726 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 727 | static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) |
| 728 | { |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 729 | u32 calib_done; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 730 | int ret = 0; |
| 731 | int cdc_err = 0; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 732 | |
| 733 | pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); |
| 734 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 735 | /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */ |
| 736 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG) |
| 737 | & ~CORE_CDC_T4_DLY_SEL), |
| 738 | host->ioaddr + CORE_DDR_200_CFG); |
| 739 | |
| 740 | /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */ |
| 741 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG) |
| 742 | & ~CORE_CDC_SWITCH_BYPASS_OFF), |
| 743 | host->ioaddr + CORE_CSR_CDC_GEN_CFG); |
| 744 | |
| 745 | /* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */ |
| 746 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG) |
| 747 | | CORE_CDC_SWITCH_RC_EN), |
| 748 | host->ioaddr + CORE_CSR_CDC_GEN_CFG); |
| 749 | |
| 750 | /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ |
| 751 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG) |
| 752 | & ~CORE_START_CDC_TRAFFIC), |
| 753 | host->ioaddr + CORE_DDR_200_CFG); |
| 754 | |
| 755 | /* |
| 756 | * Perform CDC Register Initialization Sequence |
| 757 | * |
| 758 | * CORE_CSR_CDC_CTLR_CFG0 0x11800EC |
| 759 | * CORE_CSR_CDC_CTLR_CFG1 0x3011111 |
| 760 | * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000 |
| 761 | * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4 |
| 762 | * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020 |
| 763 | * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19 |
| 764 | * CORE_CSR_CDC_DELAY_CFG 0x3AC |
| 765 | * CORE_CDC_OFFSET_CFG 0x0 |
| 766 | * CORE_CDC_SLAVE_DDA_CFG 0x16334 |
| 767 | */ |
| 768 | |
| 769 | writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 770 | writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); |
| 771 | writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); |
| 772 | writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); |
| 773 | writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); |
| 774 | writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); |
Subhash Jadavani | be406d9 | 2014-06-17 16:47:48 -0700 | [diff] [blame] | 775 | writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 776 | writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); |
| 777 | writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); |
| 778 | |
| 779 | /* CDC HW Calibration */ |
| 780 | |
| 781 | /* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */ |
| 782 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) |
| 783 | | CORE_SW_TRIG_FULL_CALIB), |
| 784 | host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 785 | |
| 786 | /* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */ |
| 787 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) |
| 788 | & ~CORE_SW_TRIG_FULL_CALIB), |
| 789 | host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 790 | |
| 791 | /* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */ |
| 792 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) |
| 793 | | CORE_HW_AUTOCAL_ENA), |
| 794 | host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); |
| 795 | |
| 796 | /* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */ |
| 797 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 798 | CORE_CSR_CDC_CAL_TIMER_CFG0) | CORE_TIMER_ENA), |
| 799 | host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); |
| 800 | |
| 801 | mb(); |
| 802 | |
| 803 | /* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */ |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 804 | ret = readl_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, |
| 805 | calib_done, (calib_done & CORE_CALIBRATION_DONE), 1, 50); |
| 806 | |
| 807 | if (ret == -ETIMEDOUT) { |
| 808 | pr_err("%s: %s: CDC Calibration was not completed\n", |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 809 | mmc_hostname(host->mmc), __func__); |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 810 | goto out; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | /* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */ |
| 814 | cdc_err = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) |
| 815 | & CORE_CDC_ERROR_CODE_MASK; |
| 816 | if (cdc_err) { |
| 817 | pr_err("%s: %s: CDC Error Code %d\n", |
| 818 | mmc_hostname(host->mmc), __func__, cdc_err); |
| 819 | ret = -EINVAL; |
| 820 | goto out; |
| 821 | } |
| 822 | |
| 823 | /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ |
| 824 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DDR_200_CFG) |
| 825 | | CORE_START_CDC_TRAFFIC), |
| 826 | host->ioaddr + CORE_DDR_200_CFG); |
| 827 | out: |
| 828 | pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), |
| 829 | __func__, ret); |
| 830 | return ret; |
| 831 | } |
| 832 | |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 833 | static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) |
| 834 | { |
| 835 | u32 dll_status; |
| 836 | int ret = 0; |
| 837 | |
| 838 | pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); |
| 839 | |
| 840 | /* |
| 841 | * Currently the CORE_DDR_CONFIG register defaults to desired |
| 842 | * configuration on reset. Currently reprogramming the power on |
| 843 | * reset (POR) value in case it might have been modified by |
| 844 | * bootloaders. In the future, if this changes, then the desired |
| 845 | * values will need to be programmed appropriately. |
| 846 | */ |
| 847 | writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG); |
| 848 | |
| 849 | /* Write 1 to DDR_CAL_EN field in CORE_DLL_CONFIG_2 */ |
| 850 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2) |
| 851 | | CORE_DDR_CAL_EN), |
| 852 | host->ioaddr + CORE_DLL_CONFIG_2); |
| 853 | |
| 854 | /* Poll on DDR_DLL_LOCK bit in CORE_DLL_STATUS to be set */ |
| 855 | ret = readl_poll_timeout(host->ioaddr + CORE_DLL_STATUS, |
| 856 | dll_status, (dll_status & CORE_DDR_DLL_LOCK), 10, 1000); |
| 857 | |
| 858 | if (ret == -ETIMEDOUT) { |
| 859 | pr_err("%s: %s: CM_DLL_SDC4 Calibration was not completed\n", |
| 860 | mmc_hostname(host->mmc), __func__); |
| 861 | goto out; |
| 862 | } |
| 863 | |
| 864 | /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */ |
| 865 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3) |
| 866 | | CORE_PWRSAVE_DLL), |
| 867 | host->ioaddr + CORE_VENDOR_SPEC3); |
| 868 | mb(); |
| 869 | out: |
| 870 | pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), |
| 871 | __func__, ret); |
| 872 | return ret; |
| 873 | } |
| 874 | |
| 875 | static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) |
| 876 | { |
| 877 | int ret = 0; |
| 878 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 879 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 880 | |
| 881 | pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); |
| 882 | |
| 883 | /* |
| 884 | * Retuning in HS400 (DDR mode) will fail, just reset the |
| 885 | * tuning block and restore the saved tuning phase. |
| 886 | */ |
| 887 | ret = msm_init_cm_dll(host); |
| 888 | if (ret) |
| 889 | goto out; |
| 890 | |
| 891 | /* Set the selected phase in delay line hw block */ |
| 892 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); |
| 893 | if (ret) |
| 894 | goto out; |
| 895 | |
Krishna Konda | 0e8efba | 2014-06-23 14:50:38 -0700 | [diff] [blame] | 896 | /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */ |
| 897 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 898 | | CORE_CMD_DAT_TRACK_SEL), |
| 899 | host->ioaddr + CORE_DLL_CONFIG); |
| 900 | |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 901 | if (msm_host->use_cdclp533) |
| 902 | /* Calibrate CDCLP533 DLL HW */ |
| 903 | ret = sdhci_msm_cdclp533_calibration(host); |
| 904 | else |
| 905 | /* Calibrate CM_DLL_SDC4 HW */ |
| 906 | ret = sdhci_msm_cm_dll_sdc4_calibration(host); |
| 907 | out: |
| 908 | pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), |
| 909 | __func__, ret); |
| 910 | return ret; |
| 911 | } |
| 912 | |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 913 | static void sdhci_msm_set_mmc_drv_type(struct sdhci_host *host, u32 opcode, |
| 914 | u8 drv_type) |
| 915 | { |
| 916 | struct mmc_command cmd = {0}; |
| 917 | struct mmc_request mrq = {NULL}; |
| 918 | struct mmc_host *mmc = host->mmc; |
| 919 | u8 val = ((drv_type << 4) | 2); |
| 920 | |
| 921 | cmd.opcode = MMC_SWITCH; |
| 922 | cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | |
| 923 | (EXT_CSD_HS_TIMING << 16) | |
| 924 | (val << 8) | |
| 925 | EXT_CSD_CMD_SET_NORMAL; |
| 926 | cmd.flags = MMC_CMD_AC | MMC_RSP_R1B; |
| 927 | /* 1 sec */ |
| 928 | cmd.busy_timeout = 1000 * 1000; |
| 929 | |
| 930 | memset(cmd.resp, 0, sizeof(cmd.resp)); |
| 931 | cmd.retries = 3; |
| 932 | |
| 933 | mrq.cmd = &cmd; |
| 934 | cmd.data = NULL; |
| 935 | |
| 936 | mmc_wait_for_req(mmc, &mrq); |
| 937 | pr_debug("%s: %s: set card drive type to %d\n", |
| 938 | mmc_hostname(mmc), __func__, |
| 939 | drv_type); |
| 940 | } |
| 941 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 942 | int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) |
| 943 | { |
| 944 | unsigned long flags; |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 945 | int tuning_seq_cnt = 3; |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 946 | u8 phase, *data_buf, tuned_phases[NUM_TUNING_PHASES], tuned_phase_cnt; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 947 | const u32 *tuning_block_pattern = tuning_block_64; |
| 948 | int size = sizeof(tuning_block_64); /* Tuning pattern size in bytes */ |
| 949 | int rc; |
| 950 | struct mmc_host *mmc = host->mmc; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 951 | struct mmc_ios ios = host->mmc->ios; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 952 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 953 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 954 | u8 drv_type = 0; |
| 955 | bool drv_type_changed = false; |
| 956 | struct mmc_card *card = host->mmc->card; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 957 | |
| 958 | /* |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 959 | * Tuning is required for SDR104, HS200 and HS400 cards and |
| 960 | * if clock frequency is greater than 100MHz in these modes. |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 961 | */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 962 | if (host->clock <= CORE_FREQ_100MHZ || |
| 963 | !((ios.timing == MMC_TIMING_MMC_HS400) || |
| 964 | (ios.timing == MMC_TIMING_MMC_HS200) || |
| 965 | (ios.timing == MMC_TIMING_UHS_SDR104))) |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 966 | return 0; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 967 | |
| 968 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 969 | |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 970 | /* CDC/SDC4 DLL HW calibration is only required for HS400 mode*/ |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 971 | if (msm_host->tuning_done && !msm_host->calibration_done && |
| 972 | (mmc->ios.timing == MMC_TIMING_MMC_HS400)) { |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 973 | rc = sdhci_msm_hs400_dll_calibration(host); |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 974 | spin_lock_irqsave(&host->lock, flags); |
| 975 | if (!rc) |
| 976 | msm_host->calibration_done = true; |
| 977 | spin_unlock_irqrestore(&host->lock, flags); |
| 978 | goto out; |
| 979 | } |
| 980 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 981 | spin_lock_irqsave(&host->lock, flags); |
| 982 | |
| 983 | if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) && |
| 984 | (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) { |
| 985 | tuning_block_pattern = tuning_block_128; |
| 986 | size = sizeof(tuning_block_128); |
| 987 | } |
| 988 | spin_unlock_irqrestore(&host->lock, flags); |
| 989 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 990 | data_buf = kmalloc(size, GFP_KERNEL); |
| 991 | if (!data_buf) { |
| 992 | rc = -ENOMEM; |
| 993 | goto out; |
| 994 | } |
| 995 | |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 996 | retry: |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 997 | tuned_phase_cnt = 0; |
| 998 | |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 999 | /* first of all reset the tuning block */ |
| 1000 | rc = msm_init_cm_dll(host); |
| 1001 | if (rc) |
| 1002 | goto kfree; |
| 1003 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1004 | phase = 0; |
| 1005 | do { |
| 1006 | struct mmc_command cmd = {0}; |
| 1007 | struct mmc_data data = {0}; |
| 1008 | struct mmc_request mrq = { |
| 1009 | .cmd = &cmd, |
| 1010 | .data = &data |
| 1011 | }; |
| 1012 | struct scatterlist sg; |
| 1013 | |
| 1014 | /* set the phase in delay line hw block */ |
| 1015 | rc = msm_config_cm_dll_phase(host, phase); |
| 1016 | if (rc) |
| 1017 | goto kfree; |
| 1018 | |
| 1019 | cmd.opcode = opcode; |
| 1020 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 1021 | |
| 1022 | data.blksz = size; |
| 1023 | data.blocks = 1; |
| 1024 | data.flags = MMC_DATA_READ; |
| 1025 | data.timeout_ns = 1000 * 1000 * 1000; /* 1 sec */ |
| 1026 | |
| 1027 | data.sg = &sg; |
| 1028 | data.sg_len = 1; |
| 1029 | sg_init_one(&sg, data_buf, size); |
| 1030 | memset(data_buf, 0, size); |
| 1031 | mmc_wait_for_req(mmc, &mrq); |
| 1032 | |
| 1033 | if (!cmd.error && !data.error && |
| 1034 | !memcmp(data_buf, tuning_block_pattern, size)) { |
| 1035 | /* tuning is successful at this tuning point */ |
| 1036 | tuned_phases[tuned_phase_cnt++] = phase; |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 1037 | pr_debug("%s: %s: found *** good *** phase = %d\n", |
| 1038 | mmc_hostname(mmc), __func__, phase); |
| 1039 | } else { |
| 1040 | pr_debug("%s: %s: found ## bad ## phase = %d\n", |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1041 | mmc_hostname(mmc), __func__, phase); |
| 1042 | } |
| 1043 | } while (++phase < 16); |
| 1044 | |
Sahitya Tummala | dfdb4af | 2014-04-01 14:29:13 +0530 | [diff] [blame] | 1045 | if ((tuned_phase_cnt == NUM_TUNING_PHASES) && |
| 1046 | card && mmc_card_mmc(card)) { |
Krishna Konda | 96e6b11 | 2013-10-28 15:25:03 -0700 | [diff] [blame] | 1047 | /* |
| 1048 | * If all phases pass then its a problem. So change the card's |
| 1049 | * drive type to a different value, if supported and repeat |
| 1050 | * tuning until at least one phase fails. Then set the original |
| 1051 | * drive type back. |
| 1052 | * |
| 1053 | * If all the phases still pass after trying all possible |
| 1054 | * drive types, then one of those 16 phases will be picked. |
| 1055 | * This is no different from what was going on before the |
| 1056 | * modification to change drive type and retune. |
| 1057 | */ |
| 1058 | pr_debug("%s: tuned phases count: %d\n", mmc_hostname(mmc), |
| 1059 | tuned_phase_cnt); |
| 1060 | |
| 1061 | /* set drive type to other value . default setting is 0x0 */ |
| 1062 | while (++drv_type <= MAX_DRV_TYPES_SUPPORTED_HS200) { |
| 1063 | if (card->ext_csd.raw_driver_strength & |
| 1064 | (1 << drv_type)) { |
| 1065 | sdhci_msm_set_mmc_drv_type(host, opcode, |
| 1066 | drv_type); |
| 1067 | if (!drv_type_changed) |
| 1068 | drv_type_changed = true; |
| 1069 | goto retry; |
| 1070 | } |
| 1071 | } |
| 1072 | } |
| 1073 | |
| 1074 | /* reset drive type to default (50 ohm) if changed */ |
| 1075 | if (drv_type_changed) |
| 1076 | sdhci_msm_set_mmc_drv_type(host, opcode, 0); |
| 1077 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1078 | if (tuned_phase_cnt) { |
| 1079 | rc = msm_find_most_appropriate_phase(host, tuned_phases, |
| 1080 | tuned_phase_cnt); |
| 1081 | if (rc < 0) |
| 1082 | goto kfree; |
| 1083 | else |
| 1084 | phase = (u8)rc; |
| 1085 | |
| 1086 | /* |
| 1087 | * Finally set the selected phase in delay |
| 1088 | * line hw block. |
| 1089 | */ |
| 1090 | rc = msm_config_cm_dll_phase(host, phase); |
| 1091 | if (rc) |
| 1092 | goto kfree; |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 1093 | msm_host->saved_tuning_phase = phase; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1094 | pr_debug("%s: %s: finally setting the tuning phase to %d\n", |
| 1095 | mmc_hostname(mmc), __func__, phase); |
| 1096 | } else { |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 1097 | if (--tuning_seq_cnt) |
| 1098 | goto retry; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1099 | /* tuning failed */ |
| 1100 | pr_err("%s: %s: no tuning point found\n", |
| 1101 | mmc_hostname(mmc), __func__); |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 1102 | rc = -EIO; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | kfree: |
| 1106 | kfree(data_buf); |
| 1107 | out: |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 1108 | spin_lock_irqsave(&host->lock, flags); |
| 1109 | if (!rc) |
| 1110 | msm_host->tuning_done = true; |
| 1111 | spin_unlock_irqrestore(&host->lock, flags); |
| 1112 | pr_debug("%s: Exit %s, err(%d)\n", mmc_hostname(mmc), __func__, rc); |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1113 | return rc; |
| 1114 | } |
| 1115 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1116 | static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 1117 | { |
| 1118 | struct sdhci_msm_gpio_data *curr; |
| 1119 | int i, ret = 0; |
| 1120 | |
| 1121 | curr = pdata->pin_data->gpio_data; |
| 1122 | for (i = 0; i < curr->size; i++) { |
| 1123 | if (!gpio_is_valid(curr->gpio[i].no)) { |
| 1124 | ret = -EINVAL; |
| 1125 | pr_err("%s: Invalid gpio = %d\n", __func__, |
| 1126 | curr->gpio[i].no); |
| 1127 | goto free_gpios; |
| 1128 | } |
| 1129 | if (enable) { |
| 1130 | ret = gpio_request(curr->gpio[i].no, |
| 1131 | curr->gpio[i].name); |
| 1132 | if (ret) { |
| 1133 | pr_err("%s: gpio_request(%d, %s) failed %d\n", |
| 1134 | __func__, curr->gpio[i].no, |
| 1135 | curr->gpio[i].name, ret); |
| 1136 | goto free_gpios; |
| 1137 | } |
| 1138 | curr->gpio[i].is_enabled = true; |
| 1139 | } else { |
| 1140 | gpio_free(curr->gpio[i].no); |
| 1141 | curr->gpio[i].is_enabled = false; |
| 1142 | } |
| 1143 | } |
| 1144 | return ret; |
| 1145 | |
| 1146 | free_gpios: |
| 1147 | for (i--; i >= 0; i--) { |
| 1148 | gpio_free(curr->gpio[i].no); |
| 1149 | curr->gpio[i].is_enabled = false; |
| 1150 | } |
| 1151 | return ret; |
| 1152 | } |
| 1153 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1154 | static int sdhci_msm_setup_pinctrl(struct sdhci_msm_pltfm_data *pdata, |
| 1155 | bool enable) |
| 1156 | { |
| 1157 | int ret = 0; |
| 1158 | |
| 1159 | if (enable) |
| 1160 | ret = pinctrl_select_state(pdata->pctrl_data->pctrl, |
| 1161 | pdata->pctrl_data->pins_active); |
| 1162 | else |
| 1163 | ret = pinctrl_select_state(pdata->pctrl_data->pctrl, |
| 1164 | pdata->pctrl_data->pins_sleep); |
| 1165 | |
| 1166 | if (ret < 0) |
| 1167 | pr_err("%s state for pinctrl failed with %d\n", |
| 1168 | enable ? "Enabling" : "Disabling", ret); |
| 1169 | |
| 1170 | return ret; |
| 1171 | } |
| 1172 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1173 | static int sdhci_msm_setup_pins(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 1174 | { |
| 1175 | int ret = 0; |
| 1176 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1177 | if (pdata->pin_cfg_sts == enable) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1178 | return 0; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1179 | } else if (pdata->pctrl_data) { |
| 1180 | ret = sdhci_msm_setup_pinctrl(pdata, enable); |
| 1181 | goto out; |
| 1182 | } else if (!pdata->pin_data) { |
| 1183 | return 0; |
| 1184 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1185 | |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 1186 | if (pdata->pin_data->is_gpio) |
| 1187 | ret = sdhci_msm_setup_gpio(pdata, enable); |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1188 | out: |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1189 | if (!ret) |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1190 | pdata->pin_cfg_sts = enable; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1191 | |
| 1192 | return ret; |
| 1193 | } |
| 1194 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1195 | static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name, |
| 1196 | u32 **out, int *len, u32 size) |
| 1197 | { |
| 1198 | int ret = 0; |
| 1199 | struct device_node *np = dev->of_node; |
| 1200 | size_t sz; |
| 1201 | u32 *arr = NULL; |
| 1202 | |
| 1203 | if (!of_get_property(np, prop_name, len)) { |
| 1204 | ret = -EINVAL; |
| 1205 | goto out; |
| 1206 | } |
| 1207 | sz = *len = *len / sizeof(*arr); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 1208 | if (sz <= 0 || (size > 0 && (sz > size))) { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1209 | dev_err(dev, "%s invalid size\n", prop_name); |
| 1210 | ret = -EINVAL; |
| 1211 | goto out; |
| 1212 | } |
| 1213 | |
| 1214 | arr = devm_kzalloc(dev, sz * sizeof(*arr), GFP_KERNEL); |
| 1215 | if (!arr) { |
| 1216 | dev_err(dev, "%s failed allocating memory\n", prop_name); |
| 1217 | ret = -ENOMEM; |
| 1218 | goto out; |
| 1219 | } |
| 1220 | |
| 1221 | ret = of_property_read_u32_array(np, prop_name, arr, sz); |
| 1222 | if (ret < 0) { |
| 1223 | dev_err(dev, "%s failed reading array %d\n", prop_name, ret); |
| 1224 | goto out; |
| 1225 | } |
| 1226 | *out = arr; |
| 1227 | out: |
| 1228 | if (ret) |
| 1229 | *len = 0; |
| 1230 | return ret; |
| 1231 | } |
| 1232 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1233 | #define MAX_PROP_SIZE 32 |
| 1234 | static int sdhci_msm_dt_parse_vreg_info(struct device *dev, |
| 1235 | struct sdhci_msm_reg_data **vreg_data, const char *vreg_name) |
| 1236 | { |
| 1237 | int len, ret = 0; |
| 1238 | const __be32 *prop; |
| 1239 | char prop_name[MAX_PROP_SIZE]; |
| 1240 | struct sdhci_msm_reg_data *vreg; |
| 1241 | struct device_node *np = dev->of_node; |
| 1242 | |
| 1243 | snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name); |
| 1244 | if (!of_parse_phandle(np, prop_name, 0)) { |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1245 | dev_info(dev, "No vreg data found for %s\n", vreg_name); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1246 | return ret; |
| 1247 | } |
| 1248 | |
| 1249 | vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); |
| 1250 | if (!vreg) { |
| 1251 | dev_err(dev, "No memory for vreg: %s\n", vreg_name); |
| 1252 | ret = -ENOMEM; |
| 1253 | return ret; |
| 1254 | } |
| 1255 | |
| 1256 | vreg->name = vreg_name; |
| 1257 | |
| 1258 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1259 | "qcom,%s-always-on", vreg_name); |
| 1260 | if (of_get_property(np, prop_name, NULL)) |
| 1261 | vreg->is_always_on = true; |
| 1262 | |
| 1263 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1264 | "qcom,%s-lpm-sup", vreg_name); |
| 1265 | if (of_get_property(np, prop_name, NULL)) |
| 1266 | vreg->lpm_sup = true; |
| 1267 | |
| 1268 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1269 | "qcom,%s-voltage-level", vreg_name); |
| 1270 | prop = of_get_property(np, prop_name, &len); |
| 1271 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 1272 | dev_warn(dev, "%s %s property\n", |
| 1273 | prop ? "invalid format" : "no", prop_name); |
| 1274 | } else { |
| 1275 | vreg->low_vol_level = be32_to_cpup(&prop[0]); |
| 1276 | vreg->high_vol_level = be32_to_cpup(&prop[1]); |
| 1277 | } |
| 1278 | |
| 1279 | snprintf(prop_name, MAX_PROP_SIZE, |
| 1280 | "qcom,%s-current-level", vreg_name); |
| 1281 | prop = of_get_property(np, prop_name, &len); |
| 1282 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 1283 | dev_warn(dev, "%s %s property\n", |
| 1284 | prop ? "invalid format" : "no", prop_name); |
| 1285 | } else { |
| 1286 | vreg->lpm_uA = be32_to_cpup(&prop[0]); |
| 1287 | vreg->hpm_uA = be32_to_cpup(&prop[1]); |
| 1288 | } |
| 1289 | |
| 1290 | *vreg_data = vreg; |
| 1291 | dev_dbg(dev, "%s: %s %s vol=[%d %d]uV, curr=[%d %d]uA\n", |
| 1292 | vreg->name, vreg->is_always_on ? "always_on," : "", |
| 1293 | vreg->lpm_sup ? "lpm_sup," : "", vreg->low_vol_level, |
| 1294 | vreg->high_vol_level, vreg->lpm_uA, vreg->hpm_uA); |
| 1295 | |
| 1296 | return ret; |
| 1297 | } |
| 1298 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1299 | static int sdhci_msm_parse_pinctrl_info(struct device *dev, |
| 1300 | struct sdhci_msm_pltfm_data *pdata) |
| 1301 | { |
| 1302 | struct sdhci_pinctrl_data *pctrl_data; |
| 1303 | struct pinctrl *pctrl; |
| 1304 | int ret = 0; |
| 1305 | |
| 1306 | /* Try to obtain pinctrl handle */ |
| 1307 | pctrl = devm_pinctrl_get(dev); |
| 1308 | if (IS_ERR(pctrl)) { |
| 1309 | ret = PTR_ERR(pctrl); |
| 1310 | goto out; |
| 1311 | } |
| 1312 | pctrl_data = devm_kzalloc(dev, sizeof(*pctrl_data), GFP_KERNEL); |
| 1313 | if (!pctrl_data) { |
| 1314 | dev_err(dev, "No memory for sdhci_pinctrl_data\n"); |
| 1315 | ret = -ENOMEM; |
| 1316 | goto out; |
| 1317 | } |
| 1318 | pctrl_data->pctrl = pctrl; |
| 1319 | /* Look-up and keep the states handy to be used later */ |
| 1320 | pctrl_data->pins_active = pinctrl_lookup_state( |
| 1321 | pctrl_data->pctrl, "active"); |
| 1322 | if (IS_ERR(pctrl_data->pins_active)) { |
| 1323 | ret = PTR_ERR(pctrl_data->pins_active); |
| 1324 | dev_err(dev, "Could not get active pinstates, err:%d\n", ret); |
| 1325 | goto out; |
| 1326 | } |
| 1327 | pctrl_data->pins_sleep = pinctrl_lookup_state( |
| 1328 | pctrl_data->pctrl, "sleep"); |
| 1329 | if (IS_ERR(pctrl_data->pins_sleep)) { |
| 1330 | ret = PTR_ERR(pctrl_data->pins_sleep); |
| 1331 | dev_err(dev, "Could not get sleep pinstates, err:%d\n", ret); |
| 1332 | goto out; |
| 1333 | } |
| 1334 | pdata->pctrl_data = pctrl_data; |
| 1335 | out: |
| 1336 | return ret; |
| 1337 | } |
| 1338 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1339 | #define GPIO_NAME_MAX_LEN 32 |
| 1340 | static int sdhci_msm_dt_parse_gpio_info(struct device *dev, |
| 1341 | struct sdhci_msm_pltfm_data *pdata) |
| 1342 | { |
| 1343 | int ret = 0, cnt, i; |
| 1344 | struct sdhci_msm_pin_data *pin_data; |
| 1345 | struct device_node *np = dev->of_node; |
| 1346 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1347 | ret = sdhci_msm_parse_pinctrl_info(dev, pdata); |
| 1348 | if (!ret) { |
| 1349 | goto out; |
| 1350 | } else if (ret == -EPROBE_DEFER) { |
| 1351 | dev_err(dev, "Pinctrl framework not registered, err:%d\n", ret); |
| 1352 | goto out; |
| 1353 | } else { |
| 1354 | dev_err(dev, "Parsing Pinctrl failed with %d, falling back on GPIO lib\n", |
| 1355 | ret); |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 1356 | ret = 0; |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 1357 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1358 | pin_data = devm_kzalloc(dev, sizeof(*pin_data), GFP_KERNEL); |
| 1359 | if (!pin_data) { |
| 1360 | dev_err(dev, "No memory for pin_data\n"); |
| 1361 | ret = -ENOMEM; |
| 1362 | goto out; |
| 1363 | } |
| 1364 | |
| 1365 | cnt = of_gpio_count(np); |
| 1366 | if (cnt > 0) { |
| 1367 | pin_data->gpio_data = devm_kzalloc(dev, |
| 1368 | sizeof(struct sdhci_msm_gpio_data), GFP_KERNEL); |
| 1369 | if (!pin_data->gpio_data) { |
| 1370 | dev_err(dev, "No memory for gpio_data\n"); |
| 1371 | ret = -ENOMEM; |
| 1372 | goto out; |
| 1373 | } |
| 1374 | pin_data->gpio_data->size = cnt; |
| 1375 | pin_data->gpio_data->gpio = devm_kzalloc(dev, cnt * |
| 1376 | sizeof(struct sdhci_msm_gpio), GFP_KERNEL); |
| 1377 | |
| 1378 | if (!pin_data->gpio_data->gpio) { |
| 1379 | dev_err(dev, "No memory for gpio\n"); |
| 1380 | ret = -ENOMEM; |
| 1381 | goto out; |
| 1382 | } |
| 1383 | |
| 1384 | for (i = 0; i < cnt; i++) { |
| 1385 | const char *name = NULL; |
| 1386 | char result[GPIO_NAME_MAX_LEN]; |
| 1387 | pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i); |
| 1388 | of_property_read_string_index(np, |
| 1389 | "qcom,gpio-names", i, &name); |
| 1390 | |
| 1391 | snprintf(result, GPIO_NAME_MAX_LEN, "%s-%s", |
| 1392 | dev_name(dev), name ? name : "?"); |
| 1393 | pin_data->gpio_data->gpio[i].name = result; |
| 1394 | dev_dbg(dev, "%s: gpio[%s] = %d\n", __func__, |
| 1395 | pin_data->gpio_data->gpio[i].name, |
| 1396 | pin_data->gpio_data->gpio[i].no); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1397 | } |
| 1398 | } |
Sahitya Tummala | 1cd7e07 | 2014-02-14 13:19:01 +0530 | [diff] [blame] | 1399 | pdata->pin_data = pin_data; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1400 | out: |
| 1401 | if (ret) |
| 1402 | dev_err(dev, "%s failed with err %d\n", __func__, ret); |
| 1403 | return ret; |
| 1404 | } |
| 1405 | |
| 1406 | /* Parse platform data */ |
| 1407 | static struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev) |
| 1408 | { |
| 1409 | struct sdhci_msm_pltfm_data *pdata = NULL; |
| 1410 | struct device_node *np = dev->of_node; |
| 1411 | u32 bus_width = 0; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 1412 | u32 cpu_dma_latency; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1413 | int len, i; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1414 | int clk_table_len; |
| 1415 | u32 *clk_table = NULL; |
Sujit Reddy Thumma | 1958d3d | 2013-06-03 09:54:32 +0530 | [diff] [blame] | 1416 | enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1417 | |
| 1418 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 1419 | if (!pdata) { |
| 1420 | dev_err(dev, "failed to allocate memory for platform data\n"); |
| 1421 | goto out; |
| 1422 | } |
| 1423 | |
Sujit Reddy Thumma | 1958d3d | 2013-06-03 09:54:32 +0530 | [diff] [blame] | 1424 | pdata->status_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags); |
| 1425 | if (gpio_is_valid(pdata->status_gpio) & !(flags & OF_GPIO_ACTIVE_LOW)) |
| 1426 | pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 1427 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1428 | of_property_read_u32(np, "qcom,bus-width", &bus_width); |
| 1429 | if (bus_width == 8) |
| 1430 | pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA; |
| 1431 | else if (bus_width == 4) |
| 1432 | pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA; |
| 1433 | else { |
| 1434 | dev_notice(dev, "invalid bus-width, default to 1-bit mode\n"); |
| 1435 | pdata->mmc_bus_width = 0; |
| 1436 | } |
| 1437 | |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 1438 | if (!of_property_read_u32(np, "qcom,cpu-dma-latency-us", |
| 1439 | &cpu_dma_latency)) |
| 1440 | pdata->cpu_dma_latency_us = cpu_dma_latency; |
Asutosh Das | 598a4d4 | 2014-02-05 16:38:23 +0530 | [diff] [blame] | 1441 | else |
| 1442 | pdata->cpu_dma_latency_us = MSM_MMC_DEFAULT_CPU_DMA_LATENCY; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1443 | if (sdhci_msm_dt_get_array(dev, "qcom,clk-rates", |
| 1444 | &clk_table, &clk_table_len, 0)) { |
| 1445 | dev_err(dev, "failed parsing supported clock rates\n"); |
| 1446 | goto out; |
| 1447 | } |
| 1448 | if (!clk_table || !clk_table_len) { |
| 1449 | dev_err(dev, "Invalid clock table\n"); |
| 1450 | goto out; |
| 1451 | } |
| 1452 | pdata->sup_clk_table = clk_table; |
| 1453 | pdata->sup_clk_cnt = clk_table_len; |
| 1454 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1455 | pdata->vreg_data = devm_kzalloc(dev, sizeof(struct |
| 1456 | sdhci_msm_slot_reg_data), |
| 1457 | GFP_KERNEL); |
| 1458 | if (!pdata->vreg_data) { |
| 1459 | dev_err(dev, "failed to allocate memory for vreg data\n"); |
| 1460 | goto out; |
| 1461 | } |
| 1462 | |
| 1463 | if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data, |
| 1464 | "vdd")) { |
| 1465 | dev_err(dev, "failed parsing vdd data\n"); |
| 1466 | goto out; |
| 1467 | } |
| 1468 | if (sdhci_msm_dt_parse_vreg_info(dev, |
| 1469 | &pdata->vreg_data->vdd_io_data, |
| 1470 | "vdd-io")) { |
| 1471 | dev_err(dev, "failed parsing vdd-io data\n"); |
| 1472 | goto out; |
| 1473 | } |
| 1474 | |
| 1475 | if (sdhci_msm_dt_parse_gpio_info(dev, pdata)) { |
| 1476 | dev_err(dev, "failed parsing gpio data\n"); |
| 1477 | goto out; |
| 1478 | } |
| 1479 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1480 | len = of_property_count_strings(np, "qcom,bus-speed-mode"); |
| 1481 | |
| 1482 | for (i = 0; i < len; i++) { |
| 1483 | const char *name = NULL; |
| 1484 | |
| 1485 | of_property_read_string_index(np, |
| 1486 | "qcom,bus-speed-mode", i, &name); |
| 1487 | if (!name) |
| 1488 | continue; |
| 1489 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 1490 | if (!strncmp(name, "HS400_1p8v", sizeof("HS400_1p8v"))) |
| 1491 | pdata->caps2 |= MMC_CAP2_HS400_1_8V; |
| 1492 | else if (!strncmp(name, "HS400_1p2v", sizeof("HS400_1p2v"))) |
| 1493 | pdata->caps2 |= MMC_CAP2_HS400_1_2V; |
| 1494 | else if (!strncmp(name, "HS200_1p8v", sizeof("HS200_1p8v"))) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1495 | pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR; |
| 1496 | else if (!strncmp(name, "HS200_1p2v", sizeof("HS200_1p2v"))) |
| 1497 | pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR; |
| 1498 | else if (!strncmp(name, "DDR_1p8v", sizeof("DDR_1p8v"))) |
| 1499 | pdata->caps |= MMC_CAP_1_8V_DDR |
| 1500 | | MMC_CAP_UHS_DDR50; |
| 1501 | else if (!strncmp(name, "DDR_1p2v", sizeof("DDR_1p2v"))) |
| 1502 | pdata->caps |= MMC_CAP_1_2V_DDR |
| 1503 | | MMC_CAP_UHS_DDR50; |
| 1504 | } |
| 1505 | |
| 1506 | if (of_get_property(np, "qcom,nonremovable", NULL)) |
| 1507 | pdata->nonremovable = true; |
| 1508 | |
| 1509 | return pdata; |
| 1510 | out: |
| 1511 | return NULL; |
| 1512 | } |
| 1513 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1514 | /* Returns required bandwidth in Bytes per Sec */ |
| 1515 | static unsigned int sdhci_get_bw_required(struct sdhci_host *host, |
| 1516 | struct mmc_ios *ios) |
| 1517 | { |
Sahitya Tummala | 2886c92 | 2013-04-03 18:03:31 +0530 | [diff] [blame] | 1518 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1519 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1520 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1521 | unsigned int bw; |
| 1522 | |
Sahitya Tummala | 2886c92 | 2013-04-03 18:03:31 +0530 | [diff] [blame] | 1523 | bw = msm_host->clk_rate; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1524 | /* |
| 1525 | * For DDR mode, SDCC controller clock will be at |
| 1526 | * the double rate than the actual clock that goes to card. |
| 1527 | */ |
| 1528 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1529 | bw /= 2; |
| 1530 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1531 | bw /= 8; |
| 1532 | |
| 1533 | return bw; |
| 1534 | } |
| 1535 | |
| 1536 | static int sdhci_msm_bus_get_vote_for_bw(struct sdhci_msm_host *host, |
| 1537 | unsigned int bw) |
| 1538 | { |
| 1539 | unsigned int *table = host->pdata->voting_data->bw_vecs; |
| 1540 | unsigned int size = host->pdata->voting_data->bw_vecs_size; |
| 1541 | int i; |
| 1542 | |
| 1543 | if (host->msm_bus_vote.is_max_bw_needed && bw) |
| 1544 | return host->msm_bus_vote.max_bw_vote; |
| 1545 | |
| 1546 | for (i = 0; i < size; i++) { |
| 1547 | if (bw <= table[i]) |
| 1548 | break; |
| 1549 | } |
| 1550 | |
| 1551 | if (i && (i == size)) |
| 1552 | i--; |
| 1553 | |
| 1554 | return i; |
| 1555 | } |
| 1556 | |
| 1557 | /* |
| 1558 | * This function must be called with host lock acquired. |
| 1559 | * Caller of this function should also ensure that msm bus client |
| 1560 | * handle is not null. |
| 1561 | */ |
| 1562 | static inline int sdhci_msm_bus_set_vote(struct sdhci_msm_host *msm_host, |
| 1563 | int vote, |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1564 | unsigned long *flags) |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1565 | { |
| 1566 | struct sdhci_host *host = platform_get_drvdata(msm_host->pdev); |
| 1567 | int rc = 0; |
| 1568 | |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1569 | BUG_ON(!flags); |
| 1570 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1571 | if (vote != msm_host->msm_bus_vote.curr_vote) { |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1572 | spin_unlock_irqrestore(&host->lock, *flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1573 | rc = msm_bus_scale_client_update_request( |
| 1574 | msm_host->msm_bus_vote.client_handle, vote); |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1575 | spin_lock_irqsave(&host->lock, *flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1576 | if (rc) { |
| 1577 | pr_err("%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n", |
| 1578 | mmc_hostname(host->mmc), |
| 1579 | msm_host->msm_bus_vote.client_handle, vote, rc); |
| 1580 | goto out; |
| 1581 | } |
| 1582 | msm_host->msm_bus_vote.curr_vote = vote; |
| 1583 | } |
| 1584 | out: |
| 1585 | return rc; |
| 1586 | } |
| 1587 | |
| 1588 | /* |
| 1589 | * Internal work. Work to set 0 bandwidth for msm bus. |
| 1590 | */ |
| 1591 | static void sdhci_msm_bus_work(struct work_struct *work) |
| 1592 | { |
| 1593 | struct sdhci_msm_host *msm_host; |
| 1594 | struct sdhci_host *host; |
| 1595 | unsigned long flags; |
| 1596 | |
| 1597 | msm_host = container_of(work, struct sdhci_msm_host, |
| 1598 | msm_bus_vote.vote_work.work); |
| 1599 | host = platform_get_drvdata(msm_host->pdev); |
| 1600 | |
| 1601 | if (!msm_host->msm_bus_vote.client_handle) |
| 1602 | return; |
| 1603 | |
| 1604 | spin_lock_irqsave(&host->lock, flags); |
| 1605 | /* don't vote for 0 bandwidth if any request is in progress */ |
| 1606 | if (!host->mrq) { |
| 1607 | sdhci_msm_bus_set_vote(msm_host, |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1608 | msm_host->msm_bus_vote.min_bw_vote, &flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1609 | } else |
| 1610 | pr_warning("%s: %s: Transfer in progress. skipping bus voting to 0 bandwidth\n", |
| 1611 | mmc_hostname(host->mmc), __func__); |
| 1612 | spin_unlock_irqrestore(&host->lock, flags); |
| 1613 | } |
| 1614 | |
| 1615 | /* |
| 1616 | * This function cancels any scheduled delayed work and sets the bus |
| 1617 | * vote based on bw (bandwidth) argument. |
| 1618 | */ |
| 1619 | static void sdhci_msm_bus_cancel_work_and_set_vote(struct sdhci_host *host, |
| 1620 | unsigned int bw) |
| 1621 | { |
| 1622 | int vote; |
| 1623 | unsigned long flags; |
| 1624 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1625 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1626 | |
| 1627 | cancel_delayed_work_sync(&msm_host->msm_bus_vote.vote_work); |
| 1628 | spin_lock_irqsave(&host->lock, flags); |
| 1629 | vote = sdhci_msm_bus_get_vote_for_bw(msm_host, bw); |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1630 | sdhci_msm_bus_set_vote(msm_host, vote, &flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1631 | spin_unlock_irqrestore(&host->lock, flags); |
| 1632 | } |
| 1633 | |
| 1634 | #define MSM_MMC_BUS_VOTING_DELAY 200 /* msecs */ |
| 1635 | |
| 1636 | /* This function queues a work which will set the bandwidth requiement to 0 */ |
| 1637 | static void sdhci_msm_bus_queue_work(struct sdhci_host *host) |
| 1638 | { |
| 1639 | unsigned long flags; |
| 1640 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1641 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1642 | |
| 1643 | spin_lock_irqsave(&host->lock, flags); |
| 1644 | if (msm_host->msm_bus_vote.min_bw_vote != |
| 1645 | msm_host->msm_bus_vote.curr_vote) |
| 1646 | queue_delayed_work(system_wq, |
| 1647 | &msm_host->msm_bus_vote.vote_work, |
| 1648 | msecs_to_jiffies(MSM_MMC_BUS_VOTING_DELAY)); |
| 1649 | spin_unlock_irqrestore(&host->lock, flags); |
| 1650 | } |
| 1651 | |
| 1652 | static int sdhci_msm_bus_register(struct sdhci_msm_host *host, |
| 1653 | struct platform_device *pdev) |
| 1654 | { |
| 1655 | int rc = 0; |
| 1656 | struct msm_bus_scale_pdata *bus_pdata; |
| 1657 | |
| 1658 | struct sdhci_msm_bus_voting_data *data; |
| 1659 | struct device *dev = &pdev->dev; |
| 1660 | |
| 1661 | data = devm_kzalloc(dev, |
| 1662 | sizeof(struct sdhci_msm_bus_voting_data), GFP_KERNEL); |
| 1663 | if (!data) { |
| 1664 | dev_err(&pdev->dev, |
| 1665 | "%s: failed to allocate memory\n", __func__); |
| 1666 | rc = -ENOMEM; |
| 1667 | goto out; |
| 1668 | } |
| 1669 | data->bus_pdata = msm_bus_cl_get_pdata(pdev); |
| 1670 | if (data->bus_pdata) { |
| 1671 | rc = sdhci_msm_dt_get_array(dev, "qcom,bus-bw-vectors-bps", |
| 1672 | &data->bw_vecs, &data->bw_vecs_size, 0); |
| 1673 | if (rc) { |
| 1674 | dev_err(&pdev->dev, |
| 1675 | "%s: Failed to get bus-bw-vectors-bps\n", |
| 1676 | __func__); |
| 1677 | goto out; |
| 1678 | } |
| 1679 | host->pdata->voting_data = data; |
| 1680 | } |
| 1681 | if (host->pdata->voting_data && |
| 1682 | host->pdata->voting_data->bus_pdata && |
| 1683 | host->pdata->voting_data->bw_vecs && |
| 1684 | host->pdata->voting_data->bw_vecs_size) { |
| 1685 | |
| 1686 | bus_pdata = host->pdata->voting_data->bus_pdata; |
| 1687 | host->msm_bus_vote.client_handle = |
| 1688 | msm_bus_scale_register_client(bus_pdata); |
| 1689 | if (!host->msm_bus_vote.client_handle) { |
| 1690 | dev_err(&pdev->dev, "msm_bus_scale_register_client()\n"); |
| 1691 | rc = -EFAULT; |
| 1692 | goto out; |
| 1693 | } |
| 1694 | /* cache the vote index for minimum and maximum bandwidth */ |
| 1695 | host->msm_bus_vote.min_bw_vote = |
| 1696 | sdhci_msm_bus_get_vote_for_bw(host, 0); |
| 1697 | host->msm_bus_vote.max_bw_vote = |
| 1698 | sdhci_msm_bus_get_vote_for_bw(host, UINT_MAX); |
| 1699 | } else { |
| 1700 | devm_kfree(dev, data); |
| 1701 | } |
| 1702 | |
| 1703 | out: |
| 1704 | return rc; |
| 1705 | } |
| 1706 | |
| 1707 | static void sdhci_msm_bus_unregister(struct sdhci_msm_host *host) |
| 1708 | { |
| 1709 | if (host->msm_bus_vote.client_handle) |
| 1710 | msm_bus_scale_unregister_client( |
| 1711 | host->msm_bus_vote.client_handle); |
| 1712 | } |
| 1713 | |
| 1714 | static void sdhci_msm_bus_voting(struct sdhci_host *host, u32 enable) |
| 1715 | { |
| 1716 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1717 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1718 | struct mmc_ios *ios = &host->mmc->ios; |
| 1719 | unsigned int bw; |
| 1720 | |
| 1721 | if (!msm_host->msm_bus_vote.client_handle) |
| 1722 | return; |
| 1723 | |
| 1724 | bw = sdhci_get_bw_required(host, ios); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1725 | if (enable) { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1726 | sdhci_msm_bus_cancel_work_and_set_vote(host, bw); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1727 | } else { |
| 1728 | /* |
| 1729 | * If clock gating is enabled, then remove the vote |
| 1730 | * immediately because clocks will be disabled only |
| 1731 | * after SDHCI_MSM_MMC_CLK_GATE_DELAY and thus no |
| 1732 | * additional delay is required to remove the bus vote. |
| 1733 | */ |
| 1734 | #ifdef CONFIG_MMC_CLKGATE |
| 1735 | if (host->mmc->clkgate_delay) |
| 1736 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 1737 | else |
| 1738 | #endif |
| 1739 | sdhci_msm_bus_queue_work(host); |
| 1740 | } |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1741 | } |
| 1742 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1743 | /* Regulator utility functions */ |
| 1744 | static int sdhci_msm_vreg_init_reg(struct device *dev, |
| 1745 | struct sdhci_msm_reg_data *vreg) |
| 1746 | { |
| 1747 | int ret = 0; |
| 1748 | |
| 1749 | /* check if regulator is already initialized? */ |
| 1750 | if (vreg->reg) |
| 1751 | goto out; |
| 1752 | |
| 1753 | /* Get the regulator handle */ |
| 1754 | vreg->reg = devm_regulator_get(dev, vreg->name); |
| 1755 | if (IS_ERR(vreg->reg)) { |
| 1756 | ret = PTR_ERR(vreg->reg); |
| 1757 | pr_err("%s: devm_regulator_get(%s) failed. ret=%d\n", |
| 1758 | __func__, vreg->name, ret); |
| 1759 | goto out; |
| 1760 | } |
| 1761 | |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1762 | if (regulator_count_voltages(vreg->reg) > 0) { |
| 1763 | vreg->set_voltage_sup = true; |
| 1764 | /* sanity check */ |
| 1765 | if (!vreg->high_vol_level || !vreg->hpm_uA) { |
| 1766 | pr_err("%s: %s invalid constraints specified\n", |
| 1767 | __func__, vreg->name); |
| 1768 | ret = -EINVAL; |
| 1769 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1770 | } |
| 1771 | |
| 1772 | out: |
| 1773 | return ret; |
| 1774 | } |
| 1775 | |
| 1776 | static void sdhci_msm_vreg_deinit_reg(struct sdhci_msm_reg_data *vreg) |
| 1777 | { |
| 1778 | if (vreg->reg) |
| 1779 | devm_regulator_put(vreg->reg); |
| 1780 | } |
| 1781 | |
| 1782 | static int sdhci_msm_vreg_set_optimum_mode(struct sdhci_msm_reg_data |
| 1783 | *vreg, int uA_load) |
| 1784 | { |
| 1785 | int ret = 0; |
| 1786 | |
| 1787 | /* |
| 1788 | * regulators that do not support regulator_set_voltage also |
| 1789 | * do not support regulator_set_optimum_mode |
| 1790 | */ |
| 1791 | if (vreg->set_voltage_sup) { |
| 1792 | ret = regulator_set_load(vreg->reg, uA_load); |
| 1793 | if (ret < 0) |
| 1794 | pr_err("%s: regulator_set_load(reg=%s,uA_load=%d) failed. ret=%d\n", |
| 1795 | __func__, vreg->name, uA_load, ret); |
| 1796 | else |
| 1797 | /* |
| 1798 | * regulator_set_load() can return non zero |
| 1799 | * value even for success case. |
| 1800 | */ |
| 1801 | ret = 0; |
| 1802 | } |
| 1803 | return ret; |
| 1804 | } |
| 1805 | |
| 1806 | static int sdhci_msm_vreg_set_voltage(struct sdhci_msm_reg_data *vreg, |
| 1807 | int min_uV, int max_uV) |
| 1808 | { |
| 1809 | int ret = 0; |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1810 | if (vreg->set_voltage_sup) { |
| 1811 | ret = regulator_set_voltage(vreg->reg, min_uV, max_uV); |
| 1812 | if (ret) { |
| 1813 | pr_err("%s: regulator_set_voltage(%s)failed. min_uV=%d,max_uV=%d,ret=%d\n", |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1814 | __func__, vreg->name, min_uV, max_uV, ret); |
| 1815 | } |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1816 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1817 | |
| 1818 | return ret; |
| 1819 | } |
| 1820 | |
| 1821 | static int sdhci_msm_vreg_enable(struct sdhci_msm_reg_data *vreg) |
| 1822 | { |
| 1823 | int ret = 0; |
| 1824 | |
| 1825 | /* Put regulator in HPM (high power mode) */ |
| 1826 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, vreg->hpm_uA); |
| 1827 | if (ret < 0) |
| 1828 | return ret; |
| 1829 | |
| 1830 | if (!vreg->is_enabled) { |
| 1831 | /* Set voltage level */ |
| 1832 | ret = sdhci_msm_vreg_set_voltage(vreg, vreg->high_vol_level, |
| 1833 | vreg->high_vol_level); |
| 1834 | if (ret) |
| 1835 | return ret; |
| 1836 | } |
| 1837 | ret = regulator_enable(vreg->reg); |
| 1838 | if (ret) { |
| 1839 | pr_err("%s: regulator_enable(%s) failed. ret=%d\n", |
| 1840 | __func__, vreg->name, ret); |
| 1841 | return ret; |
| 1842 | } |
| 1843 | vreg->is_enabled = true; |
| 1844 | return ret; |
| 1845 | } |
| 1846 | |
| 1847 | static int sdhci_msm_vreg_disable(struct sdhci_msm_reg_data *vreg) |
| 1848 | { |
| 1849 | int ret = 0; |
| 1850 | |
| 1851 | /* Never disable regulator marked as always_on */ |
| 1852 | if (vreg->is_enabled && !vreg->is_always_on) { |
| 1853 | ret = regulator_disable(vreg->reg); |
| 1854 | if (ret) { |
| 1855 | pr_err("%s: regulator_disable(%s) failed. ret=%d\n", |
| 1856 | __func__, vreg->name, ret); |
| 1857 | goto out; |
| 1858 | } |
| 1859 | vreg->is_enabled = false; |
| 1860 | |
| 1861 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, 0); |
| 1862 | if (ret < 0) |
| 1863 | goto out; |
| 1864 | |
| 1865 | /* Set min. voltage level to 0 */ |
| 1866 | ret = sdhci_msm_vreg_set_voltage(vreg, 0, vreg->high_vol_level); |
| 1867 | if (ret) |
| 1868 | goto out; |
| 1869 | } else if (vreg->is_enabled && vreg->is_always_on) { |
| 1870 | if (vreg->lpm_sup) { |
| 1871 | /* Put always_on regulator in LPM (low power mode) */ |
| 1872 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, |
| 1873 | vreg->lpm_uA); |
| 1874 | if (ret < 0) |
| 1875 | goto out; |
| 1876 | } |
| 1877 | } |
| 1878 | out: |
| 1879 | return ret; |
| 1880 | } |
| 1881 | |
| 1882 | static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata, |
| 1883 | bool enable, bool is_init) |
| 1884 | { |
| 1885 | int ret = 0, i; |
| 1886 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 1887 | struct sdhci_msm_reg_data *vreg_table[2]; |
| 1888 | |
| 1889 | curr_slot = pdata->vreg_data; |
| 1890 | if (!curr_slot) { |
| 1891 | pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n", |
| 1892 | __func__); |
| 1893 | goto out; |
| 1894 | } |
| 1895 | |
| 1896 | vreg_table[0] = curr_slot->vdd_data; |
| 1897 | vreg_table[1] = curr_slot->vdd_io_data; |
| 1898 | |
| 1899 | for (i = 0; i < ARRAY_SIZE(vreg_table); i++) { |
| 1900 | if (vreg_table[i]) { |
| 1901 | if (enable) |
| 1902 | ret = sdhci_msm_vreg_enable(vreg_table[i]); |
| 1903 | else |
| 1904 | ret = sdhci_msm_vreg_disable(vreg_table[i]); |
| 1905 | if (ret) |
| 1906 | goto out; |
| 1907 | } |
| 1908 | } |
| 1909 | out: |
| 1910 | return ret; |
| 1911 | } |
| 1912 | |
| 1913 | /* |
| 1914 | * Reset vreg by ensuring it is off during probe. A call |
| 1915 | * to enable vreg is needed to balance disable vreg |
| 1916 | */ |
| 1917 | static int sdhci_msm_vreg_reset(struct sdhci_msm_pltfm_data *pdata) |
| 1918 | { |
| 1919 | int ret; |
| 1920 | |
| 1921 | ret = sdhci_msm_setup_vreg(pdata, 1, true); |
| 1922 | if (ret) |
| 1923 | return ret; |
| 1924 | ret = sdhci_msm_setup_vreg(pdata, 0, true); |
| 1925 | return ret; |
| 1926 | } |
| 1927 | |
| 1928 | /* This init function should be called only once for each SDHC slot */ |
| 1929 | static int sdhci_msm_vreg_init(struct device *dev, |
| 1930 | struct sdhci_msm_pltfm_data *pdata, |
| 1931 | bool is_init) |
| 1932 | { |
| 1933 | int ret = 0; |
| 1934 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 1935 | struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg; |
| 1936 | |
| 1937 | curr_slot = pdata->vreg_data; |
| 1938 | if (!curr_slot) |
| 1939 | goto out; |
| 1940 | |
| 1941 | curr_vdd_reg = curr_slot->vdd_data; |
| 1942 | curr_vdd_io_reg = curr_slot->vdd_io_data; |
| 1943 | |
| 1944 | if (!is_init) |
| 1945 | /* Deregister all regulators from regulator framework */ |
| 1946 | goto vdd_io_reg_deinit; |
| 1947 | |
| 1948 | /* |
| 1949 | * Get the regulator handle from voltage regulator framework |
| 1950 | * and then try to set the voltage level for the regulator |
| 1951 | */ |
| 1952 | if (curr_vdd_reg) { |
| 1953 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_reg); |
| 1954 | if (ret) |
| 1955 | goto out; |
| 1956 | } |
| 1957 | if (curr_vdd_io_reg) { |
| 1958 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_io_reg); |
| 1959 | if (ret) |
| 1960 | goto vdd_reg_deinit; |
| 1961 | } |
| 1962 | ret = sdhci_msm_vreg_reset(pdata); |
| 1963 | if (ret) |
| 1964 | dev_err(dev, "vreg reset failed (%d)\n", ret); |
| 1965 | goto out; |
| 1966 | |
| 1967 | vdd_io_reg_deinit: |
| 1968 | if (curr_vdd_io_reg) |
| 1969 | sdhci_msm_vreg_deinit_reg(curr_vdd_io_reg); |
| 1970 | vdd_reg_deinit: |
| 1971 | if (curr_vdd_reg) |
| 1972 | sdhci_msm_vreg_deinit_reg(curr_vdd_reg); |
| 1973 | out: |
| 1974 | return ret; |
| 1975 | } |
| 1976 | |
| 1977 | |
| 1978 | static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata, |
| 1979 | enum vdd_io_level level, |
| 1980 | unsigned int voltage_level) |
| 1981 | { |
| 1982 | int ret = 0; |
| 1983 | int set_level; |
| 1984 | struct sdhci_msm_reg_data *vdd_io_reg; |
| 1985 | |
| 1986 | if (!pdata->vreg_data) |
| 1987 | return ret; |
| 1988 | |
| 1989 | vdd_io_reg = pdata->vreg_data->vdd_io_data; |
| 1990 | if (vdd_io_reg && vdd_io_reg->is_enabled) { |
| 1991 | switch (level) { |
| 1992 | case VDD_IO_LOW: |
| 1993 | set_level = vdd_io_reg->low_vol_level; |
| 1994 | break; |
| 1995 | case VDD_IO_HIGH: |
| 1996 | set_level = vdd_io_reg->high_vol_level; |
| 1997 | break; |
| 1998 | case VDD_IO_SET_LEVEL: |
| 1999 | set_level = voltage_level; |
| 2000 | break; |
| 2001 | default: |
| 2002 | pr_err("%s: invalid argument level = %d", |
| 2003 | __func__, level); |
| 2004 | ret = -EINVAL; |
| 2005 | return ret; |
| 2006 | } |
| 2007 | ret = sdhci_msm_vreg_set_voltage(vdd_io_reg, set_level, |
| 2008 | set_level); |
| 2009 | } |
| 2010 | return ret; |
| 2011 | } |
| 2012 | |
| 2013 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) |
| 2014 | { |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2015 | struct sdhci_host *host = (struct sdhci_host *)data; |
| 2016 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2017 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2018 | u8 irq_status = 0; |
| 2019 | u8 irq_ack = 0; |
| 2020 | int ret = 0; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2021 | int pwr_state = 0, io_level = 0; |
| 2022 | unsigned long flags; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2023 | |
| 2024 | irq_status = readb_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 2025 | pr_debug("%s: Received IRQ(%d), status=0x%x\n", |
| 2026 | mmc_hostname(msm_host->mmc), irq, irq_status); |
| 2027 | |
| 2028 | /* Clear the interrupt */ |
| 2029 | writeb_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 2030 | /* |
| 2031 | * SDHC has core_mem and hc_mem device memory and these memory |
| 2032 | * addresses do not fall within 1KB region. Hence, any update to |
| 2033 | * core_mem address space would require an mb() to ensure this gets |
| 2034 | * completed before its next update to registers within hc_mem. |
| 2035 | */ |
| 2036 | mb(); |
| 2037 | |
| 2038 | /* Handle BUS ON/OFF*/ |
| 2039 | if (irq_status & CORE_PWRCTL_BUS_ON) { |
| 2040 | ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2041 | if (!ret) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2042 | ret = sdhci_msm_setup_pins(msm_host->pdata, true); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2043 | ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, |
| 2044 | VDD_IO_HIGH, 0); |
| 2045 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2046 | if (ret) |
| 2047 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 2048 | else |
| 2049 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2050 | |
| 2051 | pwr_state = REQ_BUS_ON; |
| 2052 | io_level = REQ_IO_HIGH; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2053 | } |
| 2054 | if (irq_status & CORE_PWRCTL_BUS_OFF) { |
| 2055 | ret = sdhci_msm_setup_vreg(msm_host->pdata, false, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2056 | if (!ret) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2057 | ret = sdhci_msm_setup_pins(msm_host->pdata, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2058 | ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, |
| 2059 | VDD_IO_LOW, 0); |
| 2060 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2061 | if (ret) |
| 2062 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 2063 | else |
| 2064 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2065 | |
| 2066 | pwr_state = REQ_BUS_OFF; |
| 2067 | io_level = REQ_IO_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2068 | } |
| 2069 | /* Handle IO LOW/HIGH */ |
| 2070 | if (irq_status & CORE_PWRCTL_IO_LOW) { |
| 2071 | /* Switch voltage Low */ |
| 2072 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0); |
| 2073 | if (ret) |
| 2074 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 2075 | else |
| 2076 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2077 | |
| 2078 | io_level = REQ_IO_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2079 | } |
| 2080 | if (irq_status & CORE_PWRCTL_IO_HIGH) { |
| 2081 | /* Switch voltage High */ |
| 2082 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0); |
| 2083 | if (ret) |
| 2084 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 2085 | else |
| 2086 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2087 | |
| 2088 | io_level = REQ_IO_HIGH; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2089 | } |
| 2090 | |
| 2091 | /* ACK status to the core */ |
| 2092 | writeb_relaxed(irq_ack, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 2093 | /* |
| 2094 | * SDHC has core_mem and hc_mem device memory and these memory |
| 2095 | * addresses do not fall within 1KB region. Hence, any update to |
| 2096 | * core_mem address space would require an mb() to ensure this gets |
| 2097 | * completed before its next update to registers within hc_mem. |
| 2098 | */ |
| 2099 | mb(); |
| 2100 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2101 | if (io_level & REQ_IO_HIGH) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2102 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 2103 | ~CORE_IO_PAD_PWR_SWITCH), |
| 2104 | host->ioaddr + CORE_VENDOR_SPEC); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2105 | else if (io_level & REQ_IO_LOW) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2106 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | |
| 2107 | CORE_IO_PAD_PWR_SWITCH), |
| 2108 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2109 | mb(); |
| 2110 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2111 | pr_debug("%s: Handled IRQ(%d), ret=%d, ack=0x%x\n", |
| 2112 | mmc_hostname(msm_host->mmc), irq, ret, irq_ack); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2113 | spin_lock_irqsave(&host->lock, flags); |
| 2114 | if (pwr_state) |
| 2115 | msm_host->curr_pwr_state = pwr_state; |
| 2116 | if (io_level) |
| 2117 | msm_host->curr_io_level = io_level; |
| 2118 | complete(&msm_host->pwr_irq_completion); |
| 2119 | spin_unlock_irqrestore(&host->lock, flags); |
| 2120 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2121 | return IRQ_HANDLED; |
| 2122 | } |
| 2123 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2124 | static ssize_t |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 2125 | show_polling(struct device *dev, struct device_attribute *attr, char *buf) |
| 2126 | { |
| 2127 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2128 | int poll; |
| 2129 | unsigned long flags; |
| 2130 | |
| 2131 | spin_lock_irqsave(&host->lock, flags); |
| 2132 | poll = !!(host->mmc->caps & MMC_CAP_NEEDS_POLL); |
| 2133 | spin_unlock_irqrestore(&host->lock, flags); |
| 2134 | |
| 2135 | return snprintf(buf, PAGE_SIZE, "%d\n", poll); |
| 2136 | } |
| 2137 | |
| 2138 | static ssize_t |
| 2139 | store_polling(struct device *dev, struct device_attribute *attr, |
| 2140 | const char *buf, size_t count) |
| 2141 | { |
| 2142 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2143 | int value; |
| 2144 | unsigned long flags; |
| 2145 | |
| 2146 | if (!kstrtou32(buf, 0, &value)) { |
| 2147 | spin_lock_irqsave(&host->lock, flags); |
| 2148 | if (value) { |
| 2149 | host->mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 2150 | mmc_detect_change(host->mmc, 0); |
| 2151 | } else { |
| 2152 | host->mmc->caps &= ~MMC_CAP_NEEDS_POLL; |
| 2153 | } |
| 2154 | spin_unlock_irqrestore(&host->lock, flags); |
| 2155 | } |
| 2156 | return count; |
| 2157 | } |
| 2158 | |
| 2159 | static ssize_t |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2160 | show_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, |
| 2161 | char *buf) |
| 2162 | { |
| 2163 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2164 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2165 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2166 | |
| 2167 | return snprintf(buf, PAGE_SIZE, "%u\n", |
| 2168 | msm_host->msm_bus_vote.is_max_bw_needed); |
| 2169 | } |
| 2170 | |
| 2171 | static ssize_t |
| 2172 | store_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, |
| 2173 | const char *buf, size_t count) |
| 2174 | { |
| 2175 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 2176 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2177 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2178 | uint32_t value; |
| 2179 | unsigned long flags; |
| 2180 | |
| 2181 | if (!kstrtou32(buf, 0, &value)) { |
| 2182 | spin_lock_irqsave(&host->lock, flags); |
| 2183 | msm_host->msm_bus_vote.is_max_bw_needed = !!value; |
| 2184 | spin_unlock_irqrestore(&host->lock, flags); |
| 2185 | } |
| 2186 | return count; |
| 2187 | } |
| 2188 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2189 | static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2190 | { |
| 2191 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2192 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2193 | unsigned long flags; |
| 2194 | bool done = false; |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 2195 | u32 io_sig_sts; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2196 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2197 | spin_lock_irqsave(&host->lock, flags); |
| 2198 | pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", |
| 2199 | mmc_hostname(host->mmc), __func__, req_type, |
| 2200 | msm_host->curr_pwr_state, msm_host->curr_io_level); |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 2201 | io_sig_sts = readl_relaxed(msm_host->core_mem + CORE_GENERICS); |
| 2202 | /* |
| 2203 | * The IRQ for request type IO High/Low will be generated when - |
| 2204 | * 1. SWITCHABLE_SIGNALLING_VOL is enabled in HW. |
| 2205 | * 2. If 1 is true and when there is a state change in 1.8V enable |
| 2206 | * bit (bit 3) of SDHCI_HOST_CONTROL2 register. The reset state of |
| 2207 | * that bit is 0 which indicates 3.3V IO voltage. So, when MMC core |
| 2208 | * layer tries to set it to 3.3V before card detection happens, the |
| 2209 | * IRQ doesn't get triggered as there is no state change in this bit. |
| 2210 | * The driver already handles this case by changing the IO voltage |
| 2211 | * level to high as part of controller power up sequence. Hence, check |
| 2212 | * for host->pwr to handle a case where IO voltage high request is |
| 2213 | * issued even before controller power up. |
| 2214 | */ |
| 2215 | if (req_type & (REQ_IO_HIGH | REQ_IO_LOW)) { |
| 2216 | if (!(io_sig_sts & SWITCHABLE_SIGNALLING_VOL) || |
| 2217 | ((req_type & REQ_IO_HIGH) && !host->pwr)) { |
| 2218 | pr_debug("%s: do not wait for power IRQ that never comes\n", |
| 2219 | mmc_hostname(host->mmc)); |
| 2220 | spin_unlock_irqrestore(&host->lock, flags); |
| 2221 | return; |
| 2222 | } |
| 2223 | } |
| 2224 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2225 | if ((req_type & msm_host->curr_pwr_state) || |
| 2226 | (req_type & msm_host->curr_io_level)) |
| 2227 | done = true; |
| 2228 | spin_unlock_irqrestore(&host->lock, flags); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2229 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2230 | /* |
| 2231 | * This is needed here to hanlde a case where IRQ gets |
| 2232 | * triggered even before this function is called so that |
| 2233 | * x->done counter of completion gets reset. Otherwise, |
| 2234 | * next call to wait_for_completion returns immediately |
| 2235 | * without actually waiting for the IRQ to be handled. |
| 2236 | */ |
| 2237 | if (done) |
| 2238 | init_completion(&msm_host->pwr_irq_completion); |
| 2239 | else |
| 2240 | wait_for_completion(&msm_host->pwr_irq_completion); |
| 2241 | |
| 2242 | pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), |
| 2243 | __func__, req_type); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2244 | } |
| 2245 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2246 | static void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable) |
| 2247 | { |
| 2248 | if (enable) |
| 2249 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 2250 | CORE_DLL_CONFIG) | CORE_CDR_EN), |
| 2251 | host->ioaddr + CORE_DLL_CONFIG); |
| 2252 | else |
| 2253 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 2254 | CORE_DLL_CONFIG) & ~CORE_CDR_EN), |
| 2255 | host->ioaddr + CORE_DLL_CONFIG); |
| 2256 | } |
| 2257 | |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 2258 | static unsigned int sdhci_msm_max_segs(void) |
| 2259 | { |
| 2260 | return SDHCI_MSM_MAX_SEGMENTS; |
| 2261 | } |
| 2262 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2263 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2264 | { |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2265 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2266 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2267 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2268 | return msm_host->pdata->sup_clk_table[0]; |
| 2269 | } |
| 2270 | |
| 2271 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
| 2272 | { |
| 2273 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2274 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2275 | int max_clk_index = msm_host->pdata->sup_clk_cnt; |
| 2276 | |
| 2277 | return msm_host->pdata->sup_clk_table[max_clk_index - 1]; |
| 2278 | } |
| 2279 | |
| 2280 | static unsigned int sdhci_msm_get_sup_clk_rate(struct sdhci_host *host, |
| 2281 | u32 req_clk) |
| 2282 | { |
| 2283 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2284 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2285 | unsigned int sel_clk = -1; |
| 2286 | unsigned char cnt; |
| 2287 | |
| 2288 | if (req_clk < sdhci_msm_get_min_clock(host)) { |
| 2289 | sel_clk = sdhci_msm_get_min_clock(host); |
| 2290 | return sel_clk; |
| 2291 | } |
| 2292 | |
| 2293 | for (cnt = 0; cnt < msm_host->pdata->sup_clk_cnt; cnt++) { |
| 2294 | if (msm_host->pdata->sup_clk_table[cnt] > req_clk) { |
| 2295 | break; |
| 2296 | } else if (msm_host->pdata->sup_clk_table[cnt] == req_clk) { |
| 2297 | sel_clk = msm_host->pdata->sup_clk_table[cnt]; |
| 2298 | break; |
| 2299 | } else { |
| 2300 | sel_clk = msm_host->pdata->sup_clk_table[cnt]; |
| 2301 | } |
| 2302 | } |
| 2303 | return sel_clk; |
| 2304 | } |
| 2305 | |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2306 | static int sdhci_msm_enable_controller_clock(struct sdhci_host *host) |
| 2307 | { |
| 2308 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2309 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2310 | int rc = 0; |
| 2311 | |
| 2312 | if (atomic_read(&msm_host->controller_clock)) |
| 2313 | return 0; |
| 2314 | |
| 2315 | sdhci_msm_bus_voting(host, 1); |
| 2316 | |
| 2317 | if (!IS_ERR(msm_host->pclk)) { |
| 2318 | rc = clk_prepare_enable(msm_host->pclk); |
| 2319 | if (rc) { |
| 2320 | pr_err("%s: %s: failed to enable the pclk with error %d\n", |
| 2321 | mmc_hostname(host->mmc), __func__, rc); |
| 2322 | goto remove_vote; |
| 2323 | } |
| 2324 | } |
| 2325 | |
| 2326 | rc = clk_prepare_enable(msm_host->clk); |
| 2327 | if (rc) { |
| 2328 | pr_err("%s: %s: failed to enable the host-clk with error %d\n", |
| 2329 | mmc_hostname(host->mmc), __func__, rc); |
| 2330 | goto disable_pclk; |
| 2331 | } |
| 2332 | |
| 2333 | atomic_set(&msm_host->controller_clock, 1); |
| 2334 | pr_debug("%s: %s: enabled controller clock\n", |
| 2335 | mmc_hostname(host->mmc), __func__); |
| 2336 | goto out; |
| 2337 | |
| 2338 | disable_pclk: |
| 2339 | if (!IS_ERR(msm_host->pclk)) |
| 2340 | clk_disable_unprepare(msm_host->pclk); |
| 2341 | remove_vote: |
| 2342 | if (msm_host->msm_bus_vote.client_handle) |
| 2343 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 2344 | out: |
| 2345 | return rc; |
| 2346 | } |
| 2347 | |
| 2348 | |
| 2349 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2350 | static int sdhci_msm_prepare_clocks(struct sdhci_host *host, bool enable) |
| 2351 | { |
| 2352 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2353 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2354 | int rc = 0; |
| 2355 | |
| 2356 | if (enable && !atomic_read(&msm_host->clks_on)) { |
| 2357 | pr_debug("%s: request to enable clocks\n", |
| 2358 | mmc_hostname(host->mmc)); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2359 | |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2360 | /* |
| 2361 | * The bus-width or the clock rate might have changed |
| 2362 | * after controller clocks are enbaled, update bus vote |
| 2363 | * in such case. |
| 2364 | */ |
| 2365 | if (atomic_read(&msm_host->controller_clock)) |
| 2366 | sdhci_msm_bus_voting(host, 1); |
| 2367 | |
| 2368 | rc = sdhci_msm_enable_controller_clock(host); |
| 2369 | if (rc) |
| 2370 | goto remove_vote; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2371 | |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2372 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 2373 | rc = clk_prepare_enable(msm_host->bus_clk); |
| 2374 | if (rc) { |
| 2375 | pr_err("%s: %s: failed to enable the bus-clock with error %d\n", |
| 2376 | mmc_hostname(host->mmc), __func__, rc); |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2377 | goto disable_controller_clk; |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2378 | } |
| 2379 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2380 | if (!IS_ERR(msm_host->ff_clk)) { |
| 2381 | rc = clk_prepare_enable(msm_host->ff_clk); |
| 2382 | if (rc) { |
| 2383 | pr_err("%s: %s: failed to enable the ff_clk with error %d\n", |
| 2384 | mmc_hostname(host->mmc), __func__, rc); |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2385 | goto disable_bus_clk; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2386 | } |
| 2387 | } |
| 2388 | if (!IS_ERR(msm_host->sleep_clk)) { |
| 2389 | rc = clk_prepare_enable(msm_host->sleep_clk); |
| 2390 | if (rc) { |
| 2391 | pr_err("%s: %s: failed to enable the sleep_clk with error %d\n", |
| 2392 | mmc_hostname(host->mmc), __func__, rc); |
| 2393 | goto disable_ff_clk; |
| 2394 | } |
| 2395 | } |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2396 | mb(); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2397 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2398 | } else if (!enable && atomic_read(&msm_host->clks_on)) { |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2399 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
| 2400 | mb(); |
Sahitya Tummala | dc18298 | 2013-08-20 15:32:09 +0530 | [diff] [blame] | 2401 | /* |
| 2402 | * During 1.8V signal switching the clock source must |
| 2403 | * still be ON as it requires accessing SDHC |
| 2404 | * registers (SDHCi host control2 register bit 3 must |
| 2405 | * be written and polled after stopping the SDCLK). |
| 2406 | */ |
| 2407 | if (host->mmc->card_clock_off) |
| 2408 | return 0; |
| 2409 | pr_debug("%s: request to disable clocks\n", |
| 2410 | mmc_hostname(host->mmc)); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2411 | if (!IS_ERR_OR_NULL(msm_host->sleep_clk)) |
| 2412 | clk_disable_unprepare(msm_host->sleep_clk); |
| 2413 | if (!IS_ERR_OR_NULL(msm_host->ff_clk)) |
| 2414 | clk_disable_unprepare(msm_host->ff_clk); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2415 | clk_disable_unprepare(msm_host->clk); |
| 2416 | if (!IS_ERR(msm_host->pclk)) |
| 2417 | clk_disable_unprepare(msm_host->pclk); |
| 2418 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 2419 | clk_disable_unprepare(msm_host->bus_clk); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2420 | |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2421 | atomic_set(&msm_host->controller_clock, 0); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2422 | sdhci_msm_bus_voting(host, 0); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2423 | } |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2424 | atomic_set(&msm_host->clks_on, enable); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2425 | goto out; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2426 | disable_ff_clk: |
| 2427 | if (!IS_ERR_OR_NULL(msm_host->ff_clk)) |
| 2428 | clk_disable_unprepare(msm_host->ff_clk); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2429 | disable_bus_clk: |
| 2430 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 2431 | clk_disable_unprepare(msm_host->bus_clk); |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2432 | disable_controller_clk: |
| 2433 | if (!IS_ERR_OR_NULL(msm_host->clk)) |
| 2434 | clk_disable_unprepare(msm_host->clk); |
| 2435 | if (!IS_ERR_OR_NULL(msm_host->pclk)) |
| 2436 | clk_disable_unprepare(msm_host->pclk); |
| 2437 | atomic_set(&msm_host->controller_clock, 0); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2438 | remove_vote: |
| 2439 | if (msm_host->msm_bus_vote.client_handle) |
| 2440 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2441 | out: |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2442 | return rc; |
| 2443 | } |
| 2444 | |
| 2445 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) |
| 2446 | { |
| 2447 | int rc; |
| 2448 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2449 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2450 | struct mmc_ios curr_ios = host->mmc->ios; |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2451 | u32 sup_clock, ddr_clock, dll_lock; |
Sahitya Tummala | 043744a | 2013-06-24 09:55:33 +0530 | [diff] [blame] | 2452 | bool curr_pwrsave; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2453 | |
| 2454 | if (!clock) { |
Sujit Reddy Thumma | bf1aecc | 2014-01-10 10:58:54 +0530 | [diff] [blame] | 2455 | /* |
| 2456 | * disable pwrsave to ensure clock is not auto-gated until |
| 2457 | * the rate is >400KHz (initialization complete). |
| 2458 | */ |
| 2459 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 2460 | ~CORE_CLK_PWRSAVE, host->ioaddr + CORE_VENDOR_SPEC); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2461 | sdhci_msm_prepare_clocks(host, false); |
| 2462 | host->clock = clock; |
| 2463 | goto out; |
| 2464 | } |
| 2465 | |
| 2466 | rc = sdhci_msm_prepare_clocks(host, true); |
| 2467 | if (rc) |
| 2468 | goto out; |
| 2469 | |
Sahitya Tummala | 043744a | 2013-06-24 09:55:33 +0530 | [diff] [blame] | 2470 | curr_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 2471 | CORE_CLK_PWRSAVE); |
Sahitya Tummala | e000b24 | 2013-08-29 16:21:08 +0530 | [diff] [blame] | 2472 | if ((clock > 400000) && |
Sahitya Tummala | 043744a | 2013-06-24 09:55:33 +0530 | [diff] [blame] | 2473 | !curr_pwrsave && mmc_host_may_gate_card(host->mmc->card)) |
| 2474 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2475 | | CORE_CLK_PWRSAVE, |
| 2476 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2477 | /* |
| 2478 | * Disable pwrsave for a newly added card if doesn't allow clock |
| 2479 | * gating. |
| 2480 | */ |
| 2481 | else if (curr_pwrsave && !mmc_host_may_gate_card(host->mmc->card)) |
| 2482 | writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2483 | & ~CORE_CLK_PWRSAVE, |
| 2484 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2485 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2486 | sup_clock = sdhci_msm_get_sup_clk_rate(host, clock); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2487 | if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || |
| 2488 | (curr_ios.timing == MMC_TIMING_MMC_HS400)) { |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2489 | /* |
| 2490 | * The SDHC requires internal clock frequency to be double the |
| 2491 | * actual clock that will be set for DDR mode. The controller |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2492 | * uses the faster clock(100/400MHz) for some of its parts and |
| 2493 | * send the actual required clock (50/200MHz) to the card. |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2494 | */ |
| 2495 | ddr_clock = clock * 2; |
| 2496 | sup_clock = sdhci_msm_get_sup_clk_rate(host, |
| 2497 | ddr_clock); |
| 2498 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2499 | |
| 2500 | /* |
| 2501 | * In general all timing modes are controlled via UHS mode select in |
| 2502 | * Host Control2 register. eMMC specific HS200/HS400 doesn't have |
| 2503 | * their respective modes defined here, hence we use these values. |
| 2504 | * |
| 2505 | * HS200 - SDR104 (Since they both are equivalent in functionality) |
| 2506 | * HS400 - This involves multiple configurations |
| 2507 | * Initially SDR104 - when tuning is required as HS200 |
| 2508 | * Then when switching to DDR @ 400MHz (HS400) we use |
| 2509 | * the vendor specific HC_SELECT_IN to control the mode. |
| 2510 | * |
| 2511 | * In addition to controlling the modes we also need to select the |
| 2512 | * correct input clock for DLL depending on the mode. |
| 2513 | * |
| 2514 | * HS400 - divided clock (free running MCLK/2) |
| 2515 | * All other modes - default (free running MCLK) |
| 2516 | */ |
| 2517 | if (curr_ios.timing == MMC_TIMING_MMC_HS400) { |
| 2518 | /* Select the divided clock (free running MCLK/2) */ |
| 2519 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2520 | & ~CORE_HC_MCLK_SEL_MASK) |
| 2521 | | CORE_HC_MCLK_SEL_HS400), |
| 2522 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2523 | /* |
| 2524 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC |
| 2525 | * register |
| 2526 | */ |
| 2527 | if (msm_host->tuning_done && !msm_host->calibration_done) { |
| 2528 | /* |
| 2529 | * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN |
| 2530 | * field in VENDOR_SPEC_FUNC |
| 2531 | */ |
| 2532 | writel_relaxed((readl_relaxed(host->ioaddr + \ |
| 2533 | CORE_VENDOR_SPEC) |
| 2534 | | CORE_HC_SELECT_IN_HS400 |
| 2535 | | CORE_HC_SELECT_IN_EN), |
| 2536 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2537 | } |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2538 | if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) { |
| 2539 | /* |
| 2540 | * Poll on DLL_LOCK and DDR_DLL_LOCK bits in |
| 2541 | * CORE_DLL_STATUS to be set. This should get set |
| 2542 | * with in 15 us at 200 MHz. |
| 2543 | */ |
| 2544 | rc = readl_poll_timeout(host->ioaddr + CORE_DLL_STATUS, |
| 2545 | dll_lock, (dll_lock & (CORE_DLL_LOCK | |
| 2546 | CORE_DDR_DLL_LOCK)), 10, 1000); |
| 2547 | if (rc == -ETIMEDOUT) |
| 2548 | pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", |
| 2549 | mmc_hostname(host->mmc), |
| 2550 | dll_lock); |
| 2551 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2552 | } else { |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2553 | if (!msm_host->use_cdclp533) |
| 2554 | /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */ |
| 2555 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 2556 | CORE_VENDOR_SPEC3) & ~CORE_PWRSAVE_DLL), |
| 2557 | host->ioaddr + CORE_VENDOR_SPEC3); |
| 2558 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2559 | /* Select the default clock (free running MCLK) */ |
| 2560 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2561 | & ~CORE_HC_MCLK_SEL_MASK) |
| 2562 | | CORE_HC_MCLK_SEL_DFLT), |
| 2563 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2564 | |
| 2565 | /* |
| 2566 | * Disable HC_SELECT_IN to be able to use the UHS mode select |
| 2567 | * configuration from Host Control2 register for all other |
| 2568 | * modes. |
| 2569 | * |
| 2570 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field |
| 2571 | * in VENDOR_SPEC_FUNC |
| 2572 | */ |
| 2573 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 2574 | & ~CORE_HC_SELECT_IN_EN |
| 2575 | & ~CORE_HC_SELECT_IN_MASK), |
| 2576 | host->ioaddr + CORE_VENDOR_SPEC); |
| 2577 | } |
| 2578 | mb(); |
| 2579 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2580 | if (sup_clock != msm_host->clk_rate) { |
| 2581 | pr_debug("%s: %s: setting clk rate to %u\n", |
| 2582 | mmc_hostname(host->mmc), __func__, sup_clock); |
| 2583 | rc = clk_set_rate(msm_host->clk, sup_clock); |
| 2584 | if (rc) { |
| 2585 | pr_err("%s: %s: Failed to set rate %u for host-clk : %d\n", |
| 2586 | mmc_hostname(host->mmc), __func__, |
| 2587 | sup_clock, rc); |
| 2588 | goto out; |
| 2589 | } |
| 2590 | msm_host->clk_rate = sup_clock; |
| 2591 | host->clock = clock; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2592 | /* |
| 2593 | * Update the bus vote in case of frequency change due to |
| 2594 | * clock scaling. |
| 2595 | */ |
| 2596 | sdhci_msm_bus_voting(host, 1); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2597 | } |
| 2598 | out: |
| 2599 | sdhci_set_clock(host, clock); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2600 | } |
| 2601 | |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2602 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
| 2603 | unsigned int uhs) |
| 2604 | { |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2605 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2606 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2607 | u16 ctrl_2; |
| 2608 | |
| 2609 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2610 | /* Select Bus Speed Mode for host */ |
| 2611 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2612 | if (uhs == MMC_TIMING_MMC_HS400) |
| 2613 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2614 | else if (uhs == MMC_TIMING_MMC_HS200) |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2615 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2616 | else if (uhs == MMC_TIMING_UHS_SDR12) |
| 2617 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 2618 | else if (uhs == MMC_TIMING_UHS_SDR25) |
| 2619 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 2620 | else if (uhs == MMC_TIMING_UHS_SDR50) |
| 2621 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 2622 | else if (uhs == MMC_TIMING_UHS_SDR104) |
| 2623 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2624 | else if (uhs == MMC_TIMING_UHS_DDR50) |
| 2625 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2626 | /* |
| 2627 | * When clock frquency is less than 100MHz, the feedback clock must be |
| 2628 | * provided and DLL must not be used so that tuning can be skipped. To |
| 2629 | * provide feedback clock, the mode selection can be any value less |
| 2630 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. |
| 2631 | */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2632 | if (host->clock <= CORE_FREQ_100MHZ) { |
| 2633 | if ((uhs == MMC_TIMING_MMC_HS400) || |
| 2634 | (uhs == MMC_TIMING_MMC_HS200) || |
| 2635 | (uhs == MMC_TIMING_UHS_SDR104)) |
| 2636 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2637 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2638 | /* |
| 2639 | * Make sure DLL is disabled when not required |
| 2640 | * |
| 2641 | * Write 1 to DLL_RST bit of DLL_CONFIG register |
| 2642 | */ |
| 2643 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 2644 | | CORE_DLL_RST), |
| 2645 | host->ioaddr + CORE_DLL_CONFIG); |
| 2646 | |
| 2647 | /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ |
| 2648 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 2649 | | CORE_DLL_PDN), |
| 2650 | host->ioaddr + CORE_DLL_CONFIG); |
| 2651 | mb(); |
| 2652 | |
| 2653 | /* |
| 2654 | * The DLL needs to be restored and CDCLP533 recalibrated |
| 2655 | * when the clock frequency is set back to 400MHz. |
| 2656 | */ |
| 2657 | msm_host->calibration_done = false; |
| 2658 | } |
| 2659 | |
| 2660 | pr_debug("%s: %s-clock:%u uhs mode:%u ctrl_2:0x%x\n", |
| 2661 | mmc_hostname(host->mmc), __func__, host->clock, uhs, ctrl_2); |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2662 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 2663 | |
| 2664 | } |
| 2665 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 2666 | #define MAX_TEST_BUS 20 |
| 2667 | |
| 2668 | void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) |
| 2669 | { |
| 2670 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2671 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2672 | int tbsel, tbsel2; |
| 2673 | int i, index = 0; |
| 2674 | u32 test_bus_val = 0; |
| 2675 | u32 debug_reg[MAX_TEST_BUS] = {0}; |
| 2676 | |
| 2677 | pr_info("----------- VENDOR REGISTER DUMP -----------\n"); |
| 2678 | pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n", |
| 2679 | readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CNT), |
| 2680 | readl_relaxed(msm_host->core_mem + CORE_MCI_FIFO_CNT), |
| 2681 | readl_relaxed(msm_host->core_mem + CORE_MCI_STATUS)); |
| 2682 | pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n", |
| 2683 | readl_relaxed(host->ioaddr + CORE_DLL_CONFIG), |
| 2684 | readl_relaxed(host->ioaddr + CORE_DLL_STATUS), |
| 2685 | readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION)); |
| 2686 | pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n", |
| 2687 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC), |
| 2688 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0), |
| 2689 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1)); |
| 2690 | |
| 2691 | /* |
| 2692 | * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits |
| 2693 | * of CORE_TESTBUS_CONFIG register. |
| 2694 | * |
| 2695 | * To select test bus 0 to 7 use tbsel and to select any test bus |
| 2696 | * above 7 use (tbsel2 | tbsel) to get the test bus number. For eg, |
| 2697 | * to select test bus 14, write 0x1E to CORE_TESTBUS_CONFIG register |
| 2698 | * i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110. |
| 2699 | */ |
| 2700 | for (tbsel2 = 0; tbsel2 < 3; tbsel2++) { |
| 2701 | for (tbsel = 0; tbsel < 8; tbsel++) { |
| 2702 | if (index >= MAX_TEST_BUS) |
| 2703 | break; |
| 2704 | test_bus_val = (tbsel2 << CORE_TESTBUS_SEL2_BIT) | |
| 2705 | tbsel | CORE_TESTBUS_ENA; |
| 2706 | writel_relaxed(test_bus_val, |
| 2707 | msm_host->core_mem + CORE_TESTBUS_CONFIG); |
| 2708 | debug_reg[index++] = readl_relaxed(msm_host->core_mem + |
| 2709 | CORE_SDCC_DEBUG_REG); |
| 2710 | } |
| 2711 | } |
| 2712 | for (i = 0; i < MAX_TEST_BUS; i = i + 4) |
| 2713 | pr_info(" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 2714 | i, i + 3, debug_reg[i], debug_reg[i+1], |
| 2715 | debug_reg[i+2], debug_reg[i+3]); |
| 2716 | /* Disable test bus */ |
| 2717 | writel_relaxed(~CORE_TESTBUS_ENA, msm_host->core_mem + |
| 2718 | CORE_TESTBUS_CONFIG); |
| 2719 | } |
| 2720 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2721 | static struct sdhci_ops sdhci_msm_ops = { |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2722 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2723 | .check_power_status = sdhci_msm_check_power_status, |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2724 | .platform_execute_tuning = sdhci_msm_execute_tuning, |
| 2725 | .toggle_cdr = sdhci_msm_toggle_cdr, |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 2726 | .get_max_segments = sdhci_msm_max_segs, |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2727 | .set_clock = sdhci_msm_set_clock, |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2728 | .get_min_clock = sdhci_msm_get_min_clock, |
| 2729 | .get_max_clock = sdhci_msm_get_max_clock, |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 2730 | .dump_vendor_regs = sdhci_msm_dump_vendor_regs, |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 2731 | .config_auto_tuning_cmd = sdhci_msm_config_auto_tuning_cmd, |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2732 | .enable_controller_clock = sdhci_msm_enable_controller_clock, |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2733 | }; |
| 2734 | |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2735 | static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, |
| 2736 | struct sdhci_host *host) |
| 2737 | { |
| 2738 | u32 version, caps; |
| 2739 | u16 minor; |
| 2740 | u8 major; |
| 2741 | |
| 2742 | version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); |
| 2743 | major = (version & CORE_VERSION_MAJOR_MASK) >> |
| 2744 | CORE_VERSION_MAJOR_SHIFT; |
| 2745 | minor = version & CORE_VERSION_TARGET_MASK; |
| 2746 | |
| 2747 | /* |
| 2748 | * Starting with SDCC 5 controller (core major version = 1) |
Pratibhasagar V | ada4799 | 2013-12-09 20:42:32 +0530 | [diff] [blame] | 2749 | * controller won't advertise 3.0v and 8-bit features except for |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2750 | * some targets. |
| 2751 | */ |
| 2752 | if (major >= 1 && minor != 0x11 && minor != 0x12) { |
| 2753 | caps = CORE_3_0V_SUPPORT; |
Pratibhasagar V | ada4799 | 2013-12-09 20:42:32 +0530 | [diff] [blame] | 2754 | if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA) |
| 2755 | caps |= CORE_8_BIT_SUPPORT; |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2756 | writel_relaxed( |
| 2757 | (readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) | |
| 2758 | caps), host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); |
| 2759 | } |
Krishna Konda | 2faa7bb | 2014-06-04 01:25:16 -0700 | [diff] [blame] | 2760 | |
| 2761 | /* |
| 2762 | * SDCC 5 controller with major version 1, minor version 0x34 and later |
| 2763 | * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. |
| 2764 | */ |
| 2765 | if ((major == 1) && (minor < 0x34)) |
| 2766 | msm_host->use_cdclp533 = true; |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2767 | } |
| 2768 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2769 | static int sdhci_msm_probe(struct platform_device *pdev) |
| 2770 | { |
| 2771 | struct sdhci_host *host; |
| 2772 | struct sdhci_pltfm_host *pltfm_host; |
| 2773 | struct sdhci_msm_host *msm_host; |
| 2774 | struct resource *core_memres = NULL; |
| 2775 | int ret = 0, pwr_irq = 0, dead = 0; |
Stephen Boyd | 8dce5c6 | 2013-04-24 14:19:46 -0700 | [diff] [blame] | 2776 | u16 host_version; |
Subhash Jadavani | 2813734 | 2013-05-14 17:46:43 +0530 | [diff] [blame] | 2777 | u32 pwr, irq_status, irq_ctl; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2778 | |
| 2779 | pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); |
| 2780 | msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), |
| 2781 | GFP_KERNEL); |
| 2782 | if (!msm_host) { |
| 2783 | ret = -ENOMEM; |
| 2784 | goto out; |
| 2785 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2786 | |
| 2787 | msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops; |
| 2788 | host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0); |
| 2789 | if (IS_ERR(host)) { |
| 2790 | ret = PTR_ERR(host); |
| 2791 | goto out; |
| 2792 | } |
| 2793 | |
| 2794 | pltfm_host = sdhci_priv(host); |
| 2795 | pltfm_host->priv = msm_host; |
| 2796 | msm_host->mmc = host->mmc; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2797 | msm_host->pdev = pdev; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2798 | |
| 2799 | /* Extract platform data */ |
| 2800 | if (pdev->dev.of_node) { |
Venkat Gopalakrishnan | 270580a | 2013-03-11 12:17:57 -0700 | [diff] [blame] | 2801 | ret = of_alias_get_id(pdev->dev.of_node, "sdhc"); |
| 2802 | if (ret < 0) { |
| 2803 | dev_err(&pdev->dev, "Failed to get slot index %d\n", |
| 2804 | ret); |
| 2805 | goto pltfm_free; |
| 2806 | } |
| 2807 | if (disable_slots & (1 << (ret - 1))) { |
| 2808 | dev_info(&pdev->dev, "%s: Slot %d disabled\n", __func__, |
| 2809 | ret); |
| 2810 | ret = -ENODEV; |
| 2811 | goto pltfm_free; |
| 2812 | } |
| 2813 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2814 | msm_host->pdata = sdhci_msm_populate_pdata(&pdev->dev); |
| 2815 | if (!msm_host->pdata) { |
| 2816 | dev_err(&pdev->dev, "DT parsing error\n"); |
| 2817 | goto pltfm_free; |
| 2818 | } |
| 2819 | } else { |
| 2820 | dev_err(&pdev->dev, "No device tree node\n"); |
| 2821 | goto pltfm_free; |
| 2822 | } |
| 2823 | |
| 2824 | /* Setup Clocks */ |
| 2825 | |
| 2826 | /* Setup SDCC bus voter clock. */ |
| 2827 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); |
| 2828 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 2829 | /* Vote for max. clk rate for max. performance */ |
| 2830 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); |
| 2831 | if (ret) |
| 2832 | goto pltfm_free; |
| 2833 | ret = clk_prepare_enable(msm_host->bus_clk); |
| 2834 | if (ret) |
| 2835 | goto pltfm_free; |
| 2836 | } |
| 2837 | |
| 2838 | /* Setup main peripheral bus clock */ |
| 2839 | msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); |
| 2840 | if (!IS_ERR(msm_host->pclk)) { |
| 2841 | ret = clk_prepare_enable(msm_host->pclk); |
| 2842 | if (ret) |
| 2843 | goto bus_clk_disable; |
| 2844 | } |
Asutosh Das | 9d7ee2f | 2013-11-08 12:33:47 +0530 | [diff] [blame] | 2845 | atomic_set(&msm_host->controller_clock, 1); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2846 | |
| 2847 | /* Setup SDC MMC clock */ |
| 2848 | msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); |
| 2849 | if (IS_ERR(msm_host->clk)) { |
| 2850 | ret = PTR_ERR(msm_host->clk); |
| 2851 | goto pclk_disable; |
| 2852 | } |
| 2853 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2854 | /* Set to the minimum supported clock frequency */ |
| 2855 | ret = clk_set_rate(msm_host->clk, sdhci_msm_get_min_clock(host)); |
| 2856 | if (ret) { |
| 2857 | dev_err(&pdev->dev, "MClk rate set failed (%d)\n", ret); |
Sahitya Tummala | 020ede0d | 2013-06-07 13:03:07 +0530 | [diff] [blame] | 2858 | goto pclk_disable; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2859 | } |
Sahitya Tummala | 020ede0d | 2013-06-07 13:03:07 +0530 | [diff] [blame] | 2860 | ret = clk_prepare_enable(msm_host->clk); |
| 2861 | if (ret) |
| 2862 | goto pclk_disable; |
| 2863 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2864 | msm_host->clk_rate = sdhci_msm_get_min_clock(host); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2865 | atomic_set(&msm_host->clks_on, 1); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2866 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2867 | /* Setup CDC calibration fixed feedback clock */ |
| 2868 | msm_host->ff_clk = devm_clk_get(&pdev->dev, "cal_clk"); |
| 2869 | if (!IS_ERR(msm_host->ff_clk)) { |
| 2870 | ret = clk_prepare_enable(msm_host->ff_clk); |
| 2871 | if (ret) |
| 2872 | goto clk_disable; |
| 2873 | } |
| 2874 | |
| 2875 | /* Setup CDC calibration sleep clock */ |
| 2876 | msm_host->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk"); |
| 2877 | if (!IS_ERR(msm_host->sleep_clk)) { |
| 2878 | ret = clk_prepare_enable(msm_host->sleep_clk); |
| 2879 | if (ret) |
| 2880 | goto ff_clk_disable; |
| 2881 | } |
| 2882 | |
Venkat Gopalakrishnan | 9e06963 | 2013-06-12 11:16:37 -0700 | [diff] [blame] | 2883 | msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; |
| 2884 | |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2885 | ret = sdhci_msm_bus_register(msm_host, pdev); |
| 2886 | if (ret) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2887 | goto sleep_clk_disable; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2888 | |
| 2889 | if (msm_host->msm_bus_vote.client_handle) |
| 2890 | INIT_DELAYED_WORK(&msm_host->msm_bus_vote.vote_work, |
| 2891 | sdhci_msm_bus_work); |
| 2892 | sdhci_msm_bus_voting(host, 1); |
| 2893 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2894 | /* Setup regulators */ |
| 2895 | ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true); |
| 2896 | if (ret) { |
| 2897 | dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2898 | goto bus_unregister; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2899 | } |
| 2900 | |
| 2901 | /* Reset the core and Enable SDHC mode */ |
| 2902 | core_memres = platform_get_resource_byname(pdev, |
| 2903 | IORESOURCE_MEM, "core_mem"); |
| 2904 | msm_host->core_mem = devm_ioremap(&pdev->dev, core_memres->start, |
| 2905 | resource_size(core_memres)); |
| 2906 | |
| 2907 | if (!msm_host->core_mem) { |
| 2908 | dev_err(&pdev->dev, "Failed to remap registers\n"); |
| 2909 | ret = -ENOMEM; |
| 2910 | goto vreg_deinit; |
| 2911 | } |
| 2912 | |
Stepan Moskovchenko | a4d0fa7 | 2013-09-13 22:19:33 -0700 | [diff] [blame] | 2913 | /* Unset HC_MODE_EN bit in HC_MODE register */ |
| 2914 | writel_relaxed(0, (msm_host->core_mem + CORE_HC_MODE)); |
| 2915 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2916 | /* Set SW_RST bit in POWER register (Offset 0x0) */ |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 2917 | writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | |
| 2918 | CORE_SW_RST, msm_host->core_mem + CORE_POWER); |
| 2919 | /* |
| 2920 | * SW reset can take upto 10HCLK + 15MCLK cycles. |
| 2921 | * Calculating based on min clk rates (hclk = 27MHz, |
| 2922 | * mclk = 400KHz) it comes to ~40us. Let's poll for |
| 2923 | * max. 1ms for reset completion. |
| 2924 | */ |
| 2925 | ret = readl_poll_timeout(msm_host->core_mem + CORE_POWER, |
Matt Wagantall | c7097a2 | 2014-04-29 15:48:15 -0700 | [diff] [blame] | 2926 | pwr, !(pwr & CORE_SW_RST), 10, 1000); |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 2927 | |
| 2928 | if (ret) { |
| 2929 | dev_err(&pdev->dev, "reset failed (%d)\n", ret); |
| 2930 | goto vreg_deinit; |
| 2931 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2932 | /* Set HC_MODE_EN bit in HC_MODE register */ |
| 2933 | writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |
| 2934 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 2935 | /* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */ |
| 2936 | writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_HC_MODE) | |
| 2937 | FF_CLK_SW_RST_DIS, msm_host->core_mem + CORE_HC_MODE); |
| 2938 | |
Pratibhasagar V | d8acb7c | 2013-11-11 01:32:21 +0530 | [diff] [blame] | 2939 | sdhci_set_default_hw_caps(msm_host, host); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2940 | /* |
Subhash Jadavani | 2813734 | 2013-05-14 17:46:43 +0530 | [diff] [blame] | 2941 | * CORE_SW_RST above may trigger power irq if previous status of PWRCTL |
| 2942 | * was either BUS_ON or IO_HIGH_V. So before we enable the power irq |
| 2943 | * interrupt in GIC (by registering the interrupt handler), we need to |
| 2944 | * ensure that any pending power irq interrupt status is acknowledged |
| 2945 | * otherwise power irq interrupt handler would be fired prematurely. |
| 2946 | */ |
| 2947 | irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 2948 | writel_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 2949 | irq_ctl = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL); |
| 2950 | if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) |
| 2951 | irq_ctl |= CORE_PWRCTL_BUS_SUCCESS; |
| 2952 | if (irq_status & (CORE_PWRCTL_IO_HIGH | CORE_PWRCTL_IO_LOW)) |
| 2953 | irq_ctl |= CORE_PWRCTL_IO_SUCCESS; |
| 2954 | writel_relaxed(irq_ctl, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 2955 | /* |
| 2956 | * Ensure that above writes are propogated before interrupt enablement |
| 2957 | * in GIC. |
| 2958 | */ |
| 2959 | mb(); |
| 2960 | |
| 2961 | /* |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2962 | * Following are the deviations from SDHC spec v3.0 - |
| 2963 | * 1. Card detection is handled using separate GPIO. |
| 2964 | * 2. Bus power control is handled by interacting with PMIC. |
| 2965 | */ |
| 2966 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
| 2967 | host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2968 | host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; |
| 2969 | host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK; |
Sahitya Tummala | 87d4394 | 2013-04-12 11:49:11 +0530 | [diff] [blame] | 2970 | host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD; |
Sahitya Tummala | 314162c | 2013-04-12 12:11:20 +0530 | [diff] [blame] | 2971 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE; |
Sahitya Tummala | 7c9780d | 2013-04-12 11:59:25 +0530 | [diff] [blame] | 2972 | host->quirks2 |= SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2973 | |
Sahitya Tummala | a5733ab5 | 2013-06-10 16:32:51 +0530 | [diff] [blame] | 2974 | if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK) |
| 2975 | host->quirks2 |= SDHCI_QUIRK2_DIVIDE_TOUT_BY_4; |
| 2976 | |
Stephen Boyd | 8dce5c6 | 2013-04-24 14:19:46 -0700 | [diff] [blame] | 2977 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 2978 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", |
| 2979 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> |
| 2980 | SDHCI_VENDOR_VER_SHIFT)); |
| 2981 | if (((host_version & SDHCI_VENDOR_VER_MASK) >> |
| 2982 | SDHCI_VENDOR_VER_SHIFT) == SDHCI_VER_100) { |
| 2983 | /* |
| 2984 | * Add 40us delay in interrupt handler when |
| 2985 | * operating at initialization frequency(400KHz). |
| 2986 | */ |
| 2987 | host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; |
| 2988 | /* |
| 2989 | * Set Software Reset for DAT line in Software |
| 2990 | * Reset Register (Bit 2). |
| 2991 | */ |
| 2992 | host->quirks2 |= SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT; |
| 2993 | } |
| 2994 | |
Asutosh Das | 214b966 | 2013-06-13 14:27:42 +0530 | [diff] [blame] | 2995 | host->quirks2 |= SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR; |
| 2996 | |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 2997 | /* Setup PWRCTL irq */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2998 | pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); |
| 2999 | if (pwr_irq < 0) { |
| 3000 | dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n", |
| 3001 | pwr_irq); |
| 3002 | goto vreg_deinit; |
| 3003 | } |
| 3004 | ret = devm_request_threaded_irq(&pdev->dev, pwr_irq, NULL, |
| 3005 | sdhci_msm_pwr_irq, IRQF_ONESHOT, |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 3006 | dev_name(&pdev->dev), host); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3007 | if (ret) { |
| 3008 | dev_err(&pdev->dev, "Request threaded irq(%d) failed (%d)\n", |
| 3009 | pwr_irq, ret); |
| 3010 | goto vreg_deinit; |
| 3011 | } |
| 3012 | |
| 3013 | /* Enable pwr irq interrupts */ |
| 3014 | writel_relaxed(INT_MASK, (msm_host->core_mem + CORE_PWRCTL_MASK)); |
| 3015 | |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 3016 | #ifdef CONFIG_MMC_CLKGATE |
| 3017 | /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */ |
| 3018 | msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY; |
| 3019 | #endif |
| 3020 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3021 | /* Set host capabilities */ |
| 3022 | msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; |
| 3023 | msm_host->mmc->caps |= msm_host->pdata->caps; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3024 | msm_host->mmc->caps2 |= msm_host->pdata->caps2; |
| 3025 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR; |
| 3026 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR_CONTROL; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 3027 | msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE; |
Subhash Jadavani | 6d472b2 | 2013-05-29 15:52:10 +0530 | [diff] [blame] | 3028 | msm_host->mmc->caps2 |= MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE; |
Asutosh Das | bea115d | 2013-06-24 18:20:45 +0530 | [diff] [blame] | 3029 | msm_host->mmc->pm_caps |= MMC_PM_KEEP_POWER; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3030 | |
| 3031 | if (msm_host->pdata->nonremovable) |
| 3032 | msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
| 3033 | |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 3034 | host->cpu_dma_latency_us = msm_host->pdata->cpu_dma_latency_us; |
| 3035 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 3036 | init_completion(&msm_host->pwr_irq_completion); |
| 3037 | |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3038 | if (gpio_is_valid(msm_host->pdata->status_gpio)) { |
Sahitya Tummala | 6ddabb4 | 2014-06-05 13:26:55 +0530 | [diff] [blame] | 3039 | /* |
| 3040 | * Set up the card detect GPIO in active configuration before |
| 3041 | * configuring it as an IRQ. Otherwise, it can be in some |
| 3042 | * weird/inconsistent state resulting in flood of interrupts. |
| 3043 | */ |
| 3044 | sdhci_msm_setup_pins(msm_host->pdata, true); |
| 3045 | |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3046 | ret = mmc_gpio_request_cd(msm_host->mmc, |
| 3047 | msm_host->pdata->status_gpio, 0); |
| 3048 | if (ret) { |
| 3049 | dev_err(&pdev->dev, "%s: Failed to request card detection IRQ %d\n", |
| 3050 | __func__, ret); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 3051 | goto vreg_deinit; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3052 | } |
| 3053 | } |
| 3054 | |
Krishna Konda | 7feab35 | 2013-09-17 23:55:40 -0700 | [diff] [blame] | 3055 | if ((sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) && |
| 3056 | (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(64)))) { |
| 3057 | host->dma_mask = DMA_BIT_MASK(64); |
| 3058 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; |
| 3059 | } else if (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(32))) { |
Sahitya Tummala | eaa2186 | 2013-03-20 19:34:59 +0530 | [diff] [blame] | 3060 | host->dma_mask = DMA_BIT_MASK(32); |
| 3061 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; |
| 3062 | } else { |
| 3063 | dev_err(&pdev->dev, "%s: Failed to set dma mask\n", __func__); |
| 3064 | } |
| 3065 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3066 | ret = sdhci_add_host(host); |
| 3067 | if (ret) { |
| 3068 | dev_err(&pdev->dev, "Add host failed (%d)\n", ret); |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3069 | goto vreg_deinit; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3070 | } |
| 3071 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 3072 | msm_host->msm_bus_vote.max_bus_bw.show = show_sdhci_max_bus_bw; |
| 3073 | msm_host->msm_bus_vote.max_bus_bw.store = store_sdhci_max_bus_bw; |
| 3074 | sysfs_attr_init(&msm_host->msm_bus_vote.max_bus_bw.attr); |
| 3075 | msm_host->msm_bus_vote.max_bus_bw.attr.name = "max_bus_bw"; |
| 3076 | msm_host->msm_bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR; |
| 3077 | ret = device_create_file(&pdev->dev, |
| 3078 | &msm_host->msm_bus_vote.max_bus_bw); |
| 3079 | if (ret) |
| 3080 | goto remove_host; |
| 3081 | |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 3082 | if (!gpio_is_valid(msm_host->pdata->status_gpio)) { |
| 3083 | msm_host->polling.show = show_polling; |
| 3084 | msm_host->polling.store = store_polling; |
| 3085 | sysfs_attr_init(&msm_host->polling.attr); |
| 3086 | msm_host->polling.attr.name = "polling"; |
| 3087 | msm_host->polling.attr.mode = S_IRUGO | S_IWUSR; |
| 3088 | ret = device_create_file(&pdev->dev, &msm_host->polling); |
| 3089 | if (ret) |
| 3090 | goto remove_max_bus_bw_file; |
| 3091 | } |
Asutosh Das | e5e9ca6 | 2013-07-30 19:08:36 +0530 | [diff] [blame] | 3092 | |
| 3093 | msm_host->auto_cmd21_attr.show = show_auto_cmd21; |
| 3094 | msm_host->auto_cmd21_attr.store = store_auto_cmd21; |
| 3095 | sysfs_attr_init(&msm_host->auto_cmd21_attr.attr); |
| 3096 | msm_host->auto_cmd21_attr.attr.name = "enable_auto_cmd21"; |
| 3097 | msm_host->auto_cmd21_attr.attr.mode = S_IRUGO | S_IWUSR; |
| 3098 | ret = device_create_file(&pdev->dev, &msm_host->auto_cmd21_attr); |
| 3099 | if (ret) { |
| 3100 | pr_err("%s: %s: failed creating auto-cmd21 attr: %d\n", |
| 3101 | mmc_hostname(host->mmc), __func__, ret); |
| 3102 | device_remove_file(&pdev->dev, &msm_host->auto_cmd21_attr); |
| 3103 | } |
| 3104 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3105 | /* Successful initialization */ |
| 3106 | goto out; |
| 3107 | |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 3108 | remove_max_bus_bw_file: |
| 3109 | device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3110 | remove_host: |
| 3111 | dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
| 3112 | sdhci_remove_host(host, dead); |
| 3113 | vreg_deinit: |
| 3114 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 3115 | bus_unregister: |
| 3116 | if (msm_host->msm_bus_vote.client_handle) |
| 3117 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 3118 | sdhci_msm_bus_unregister(msm_host); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame] | 3119 | sleep_clk_disable: |
| 3120 | if (!IS_ERR(msm_host->sleep_clk)) |
| 3121 | clk_disable_unprepare(msm_host->sleep_clk); |
| 3122 | ff_clk_disable: |
| 3123 | if (!IS_ERR(msm_host->ff_clk)) |
| 3124 | clk_disable_unprepare(msm_host->ff_clk); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3125 | clk_disable: |
| 3126 | if (!IS_ERR(msm_host->clk)) |
| 3127 | clk_disable_unprepare(msm_host->clk); |
| 3128 | pclk_disable: |
| 3129 | if (!IS_ERR(msm_host->pclk)) |
| 3130 | clk_disable_unprepare(msm_host->pclk); |
| 3131 | bus_clk_disable: |
| 3132 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 3133 | clk_disable_unprepare(msm_host->bus_clk); |
| 3134 | pltfm_free: |
| 3135 | sdhci_pltfm_free(pdev); |
| 3136 | out: |
| 3137 | pr_debug("%s: Exit %s\n", dev_name(&pdev->dev), __func__); |
| 3138 | return ret; |
| 3139 | } |
| 3140 | |
| 3141 | static int sdhci_msm_remove(struct platform_device *pdev) |
| 3142 | { |
| 3143 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 3144 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 3145 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 3146 | struct sdhci_msm_pltfm_data *pdata = msm_host->pdata; |
| 3147 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
| 3148 | 0xffffffff); |
| 3149 | |
| 3150 | pr_debug("%s: %s\n", dev_name(&pdev->dev), __func__); |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 3151 | if (!gpio_is_valid(msm_host->pdata->status_gpio)) |
| 3152 | device_remove_file(&pdev->dev, &msm_host->polling); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 3153 | device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3154 | sdhci_remove_host(host, dead); |
| 3155 | sdhci_pltfm_free(pdev); |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 3156 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3157 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 3158 | |
Pratibhasagar V | 9acf264 | 2013-11-21 21:07:21 +0530 | [diff] [blame] | 3159 | sdhci_msm_setup_pins(pdata, true); |
| 3160 | sdhci_msm_setup_pins(pdata, false); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 3161 | |
| 3162 | if (msm_host->msm_bus_vote.client_handle) { |
| 3163 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 3164 | sdhci_msm_bus_unregister(msm_host); |
| 3165 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 3166 | return 0; |
| 3167 | } |
| 3168 | |
| 3169 | static const struct of_device_id sdhci_msm_dt_match[] = { |
| 3170 | {.compatible = "qcom,sdhci-msm"}, |
| 3171 | }; |
| 3172 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); |
| 3173 | |
| 3174 | static struct platform_driver sdhci_msm_driver = { |
| 3175 | .probe = sdhci_msm_probe, |
| 3176 | .remove = sdhci_msm_remove, |
| 3177 | .driver = { |
| 3178 | .name = "sdhci_msm", |
| 3179 | .owner = THIS_MODULE, |
| 3180 | .of_match_table = sdhci_msm_dt_match, |
| 3181 | }, |
| 3182 | }; |
| 3183 | |
| 3184 | module_platform_driver(sdhci_msm_driver); |
| 3185 | |
| 3186 | MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Secure Digital Host Controller Interface driver"); |
| 3187 | MODULE_LICENSE("GPL v2"); |