Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 1 | /* |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 3 | * |
| 4 | * Based on the TI DAVINCI I2C adapter driver. |
| 5 | * |
| 6 | * Copyright (C) 2006 Texas Instruments. |
| 7 | * Copyright (C) 2007 MontaVista Software Inc. |
| 8 | * Copyright (C) 2009 Provigent Ltd. |
| 9 | * |
| 10 | * ---------------------------------------------------------------------------- |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * ---------------------------------------------------------------------------- |
| 26 | * |
| 27 | */ |
| 28 | #include <linux/kernel.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/i2c.h> |
| 32 | #include <linux/clk.h> |
| 33 | #include <linux/errno.h> |
| 34 | #include <linux/sched.h> |
| 35 | #include <linux/err.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/platform_device.h> |
| 38 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 39 | #include <linux/slab.h> |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 40 | #include <linux/swab.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * Registers offset |
| 44 | */ |
| 45 | #define DW_IC_CON 0x0 |
| 46 | #define DW_IC_TAR 0x4 |
| 47 | #define DW_IC_DATA_CMD 0x10 |
| 48 | #define DW_IC_SS_SCL_HCNT 0x14 |
| 49 | #define DW_IC_SS_SCL_LCNT 0x18 |
| 50 | #define DW_IC_FS_SCL_HCNT 0x1c |
| 51 | #define DW_IC_FS_SCL_LCNT 0x20 |
| 52 | #define DW_IC_INTR_STAT 0x2c |
| 53 | #define DW_IC_INTR_MASK 0x30 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 54 | #define DW_IC_RAW_INTR_STAT 0x34 |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 55 | #define DW_IC_RX_TL 0x38 |
| 56 | #define DW_IC_TX_TL 0x3c |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 57 | #define DW_IC_CLR_INTR 0x40 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 58 | #define DW_IC_CLR_RX_UNDER 0x44 |
| 59 | #define DW_IC_CLR_RX_OVER 0x48 |
| 60 | #define DW_IC_CLR_TX_OVER 0x4c |
| 61 | #define DW_IC_CLR_RD_REQ 0x50 |
| 62 | #define DW_IC_CLR_TX_ABRT 0x54 |
| 63 | #define DW_IC_CLR_RX_DONE 0x58 |
| 64 | #define DW_IC_CLR_ACTIVITY 0x5c |
| 65 | #define DW_IC_CLR_STOP_DET 0x60 |
| 66 | #define DW_IC_CLR_START_DET 0x64 |
| 67 | #define DW_IC_CLR_GEN_CALL 0x68 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 68 | #define DW_IC_ENABLE 0x6c |
| 69 | #define DW_IC_STATUS 0x70 |
| 70 | #define DW_IC_TXFLR 0x74 |
| 71 | #define DW_IC_RXFLR 0x78 |
| 72 | #define DW_IC_COMP_PARAM_1 0xf4 |
Jean-Hugues Deschenes | 4ff895b | 2011-10-06 11:26:26 -0700 | [diff] [blame] | 73 | #define DW_IC_COMP_TYPE 0xfc |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 74 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
| 75 | |
| 76 | #define DW_IC_CON_MASTER 0x1 |
| 77 | #define DW_IC_CON_SPEED_STD 0x2 |
| 78 | #define DW_IC_CON_SPEED_FAST 0x4 |
| 79 | #define DW_IC_CON_10BITADDR_MASTER 0x10 |
| 80 | #define DW_IC_CON_RESTART_EN 0x20 |
| 81 | #define DW_IC_CON_SLAVE_DISABLE 0x40 |
| 82 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 83 | #define DW_IC_INTR_RX_UNDER 0x001 |
| 84 | #define DW_IC_INTR_RX_OVER 0x002 |
| 85 | #define DW_IC_INTR_RX_FULL 0x004 |
| 86 | #define DW_IC_INTR_TX_OVER 0x008 |
| 87 | #define DW_IC_INTR_TX_EMPTY 0x010 |
| 88 | #define DW_IC_INTR_RD_REQ 0x020 |
| 89 | #define DW_IC_INTR_TX_ABRT 0x040 |
| 90 | #define DW_IC_INTR_RX_DONE 0x080 |
| 91 | #define DW_IC_INTR_ACTIVITY 0x100 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 92 | #define DW_IC_INTR_STOP_DET 0x200 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 93 | #define DW_IC_INTR_START_DET 0x400 |
| 94 | #define DW_IC_INTR_GEN_CALL 0x800 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 95 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 96 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
| 97 | DW_IC_INTR_TX_EMPTY | \ |
| 98 | DW_IC_INTR_TX_ABRT | \ |
| 99 | DW_IC_INTR_STOP_DET) |
| 100 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 101 | #define DW_IC_STATUS_ACTIVITY 0x1 |
| 102 | |
| 103 | #define DW_IC_ERR_TX_ABRT 0x1 |
| 104 | |
| 105 | /* |
| 106 | * status codes |
| 107 | */ |
| 108 | #define STATUS_IDLE 0x0 |
| 109 | #define STATUS_WRITE_IN_PROGRESS 0x1 |
| 110 | #define STATUS_READ_IN_PROGRESS 0x2 |
| 111 | |
| 112 | #define TIMEOUT 20 /* ms */ |
| 113 | |
| 114 | /* |
| 115 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register |
| 116 | * |
| 117 | * only expected abort codes are listed here |
| 118 | * refer to the datasheet for the full list |
| 119 | */ |
| 120 | #define ABRT_7B_ADDR_NOACK 0 |
| 121 | #define ABRT_10ADDR1_NOACK 1 |
| 122 | #define ABRT_10ADDR2_NOACK 2 |
| 123 | #define ABRT_TXDATA_NOACK 3 |
| 124 | #define ABRT_GCALL_NOACK 4 |
| 125 | #define ABRT_GCALL_READ 5 |
| 126 | #define ABRT_SBYTE_ACKDET 7 |
| 127 | #define ABRT_SBYTE_NORSTRT 9 |
| 128 | #define ABRT_10B_RD_NORSTRT 10 |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 129 | #define ABRT_MASTER_DIS 11 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 130 | #define ARB_LOST 12 |
| 131 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 132 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
| 133 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) |
| 134 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) |
| 135 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) |
| 136 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) |
| 137 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) |
| 138 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) |
| 139 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) |
| 140 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) |
| 141 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) |
| 142 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) |
| 143 | |
| 144 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ |
| 145 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ |
| 146 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ |
| 147 | DW_IC_TX_ABRT_TXDATA_NOACK | \ |
| 148 | DW_IC_TX_ABRT_GCALL_NOACK) |
| 149 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 150 | static char *abort_sources[] = { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 151 | [ABRT_7B_ADDR_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 152 | "slave address not acknowledged (7bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 153 | [ABRT_10ADDR1_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 154 | "first address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 155 | [ABRT_10ADDR2_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 156 | "second address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 157 | [ABRT_TXDATA_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 158 | "data not acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 159 | [ABRT_GCALL_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 160 | "no acknowledgement for a general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 161 | [ABRT_GCALL_READ] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 162 | "read after general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 163 | [ABRT_SBYTE_ACKDET] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 164 | "start byte acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 165 | [ABRT_SBYTE_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 166 | "trying to send start byte when restart is disabled", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 167 | [ABRT_10B_RD_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 168 | "trying to read when restart is disabled (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 169 | [ABRT_MASTER_DIS] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 170 | "trying to use disabled adapter", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 171 | [ARB_LOST] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 172 | "lost arbitration", |
| 173 | }; |
| 174 | |
| 175 | /** |
| 176 | * struct dw_i2c_dev - private i2c-designware data |
| 177 | * @dev: driver model device node |
| 178 | * @base: IO registers pointer |
| 179 | * @cmd_complete: tx completion indicator |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 180 | * @lock: protect this struct and IO registers |
| 181 | * @clk: input reference clock |
| 182 | * @cmd_err: run time hadware error code |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 183 | * @msgs: points to an array of messages currently being transferred |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 184 | * @msgs_num: the number of elements in msgs |
| 185 | * @msg_write_idx: the element index of the current tx message in the msgs |
| 186 | * array |
| 187 | * @tx_buf_len: the length of the current tx buffer |
| 188 | * @tx_buf: the current tx buffer |
| 189 | * @msg_read_idx: the element index of the current rx message in the msgs |
| 190 | * array |
| 191 | * @rx_buf_len: the length of the current rx buffer |
| 192 | * @rx_buf: the current rx buffer |
| 193 | * @msg_err: error status of the current transfer |
| 194 | * @status: i2c master status, one of STATUS_* |
| 195 | * @abort_source: copy of the TX_ABRT_SOURCE register |
| 196 | * @irq: interrupt number for the i2c master |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 197 | * @swab: true if the instantiated IP is of different endianess |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 198 | * @adapter: i2c subsystem adapter node |
| 199 | * @tx_fifo_depth: depth of the hardware tx fifo |
| 200 | * @rx_fifo_depth: depth of the hardware rx fifo |
| 201 | */ |
| 202 | struct dw_i2c_dev { |
| 203 | struct device *dev; |
| 204 | void __iomem *base; |
| 205 | struct completion cmd_complete; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 206 | struct mutex lock; |
| 207 | struct clk *clk; |
| 208 | int cmd_err; |
| 209 | struct i2c_msg *msgs; |
| 210 | int msgs_num; |
| 211 | int msg_write_idx; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 212 | u32 tx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 213 | u8 *tx_buf; |
| 214 | int msg_read_idx; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 215 | u32 rx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 216 | u8 *rx_buf; |
| 217 | int msg_err; |
| 218 | unsigned int status; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 219 | u32 abort_source; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 220 | int irq; |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 221 | int swab; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 222 | struct i2c_adapter adapter; |
| 223 | unsigned int tx_fifo_depth; |
| 224 | unsigned int rx_fifo_depth; |
| 225 | }; |
| 226 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 227 | static u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
| 228 | { |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 229 | u32 value = readl(dev->base + offset); |
| 230 | |
| 231 | if (dev->swab) |
| 232 | return swab32(value); |
| 233 | else |
| 234 | return value; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 235 | } |
| 236 | |
| 237 | static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
| 238 | { |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 239 | if (dev->swab) |
| 240 | b = swab32(b); |
| 241 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 242 | writel(b, dev->base + offset); |
| 243 | } |
| 244 | |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 245 | static u32 |
| 246 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
| 247 | { |
| 248 | /* |
| 249 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
| 250 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
| 251 | * will result in violation of the tHD;STA spec. |
| 252 | */ |
| 253 | if (cond) |
| 254 | /* |
| 255 | * Conditional expression: |
| 256 | * |
| 257 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
| 258 | * |
| 259 | * This is based on the DW manuals, and represents an ideal |
| 260 | * configuration. The resulting I2C bus speed will be |
| 261 | * faster than any of the others. |
| 262 | * |
| 263 | * If your hardware is free from tHD;STA issue, try this one. |
| 264 | */ |
| 265 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; |
| 266 | else |
| 267 | /* |
| 268 | * Conditional expression: |
| 269 | * |
| 270 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
| 271 | * |
| 272 | * This is just experimental rule; the tHD;STA period turned |
| 273 | * out to be proportinal to (_HCNT + 3). With this setting, |
| 274 | * we could meet both tHIGH and tHD;STA timing specs. |
| 275 | * |
| 276 | * If unsure, you'd better to take this alternative. |
| 277 | * |
| 278 | * The reason why we need to take into account "tf" here, |
| 279 | * is the same as described in i2c_dw_scl_lcnt(). |
| 280 | */ |
| 281 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; |
| 282 | } |
| 283 | |
| 284 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
| 285 | { |
| 286 | /* |
| 287 | * Conditional expression: |
| 288 | * |
| 289 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
| 290 | * |
| 291 | * DW I2C core starts counting the SCL CNTs for the LOW period |
| 292 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
| 293 | * In order to meet the tLOW timing spec, we need to take into |
| 294 | * account the fall time of SCL signal (tf). Default tf value |
| 295 | * should be 0.3 us, for safety. |
| 296 | */ |
| 297 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; |
| 298 | } |
| 299 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 300 | /** |
| 301 | * i2c_dw_init() - initialize the designware i2c master hardware |
| 302 | * @dev: device private data |
| 303 | * |
| 304 | * This functions configures and enables the I2C master. |
| 305 | * This function is called during I2C init function, and in case of timeout at |
| 306 | * run time. |
| 307 | */ |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame^] | 308 | static int i2c_dw_init(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 309 | { |
| 310 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 311 | u32 ic_con, hcnt, lcnt; |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame^] | 312 | u32 reg; |
| 313 | |
| 314 | /* Configure register endianess access */ |
| 315 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
| 316 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { |
| 317 | dev->swab = 1; |
| 318 | reg = DW_IC_COMP_TYPE_VALUE; |
| 319 | } |
| 320 | |
| 321 | if (reg != DW_IC_COMP_TYPE_VALUE) { |
| 322 | dev_err(dev->dev, "Unknown Synopsys component type: " |
| 323 | "0x%08x\n", reg); |
| 324 | return -ENODEV; |
| 325 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 326 | |
| 327 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 328 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 329 | |
| 330 | /* set standard and fast speed deviders for high/low periods */ |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 331 | |
| 332 | /* Standard-mode */ |
| 333 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 334 | 40, /* tHD;STA = tHIGH = 4.0 us */ |
| 335 | 3, /* tf = 0.3 us */ |
| 336 | 0, /* 0: DW default, 1: Ideal */ |
| 337 | 0); /* No offset */ |
| 338 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 339 | 47, /* tLOW = 4.7 us */ |
| 340 | 3, /* tf = 0.3 us */ |
| 341 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 342 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
| 343 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 344 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
| 345 | |
| 346 | /* Fast-mode */ |
| 347 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 348 | 6, /* tHD;STA = tHIGH = 0.6 us */ |
| 349 | 3, /* tf = 0.3 us */ |
| 350 | 0, /* 0: DW default, 1: Ideal */ |
| 351 | 0); /* No offset */ |
| 352 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 353 | 13, /* tLOW = 1.3 us */ |
| 354 | 3, /* tf = 0.3 us */ |
| 355 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 356 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
| 357 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 358 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 359 | |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 360 | /* Configure Tx/Rx FIFO threshold levels */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 361 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
| 362 | dw_writel(dev, 0, DW_IC_RX_TL); |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 363 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 364 | /* configure the i2c master */ |
| 365 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | |
| 366 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 367 | dw_writel(dev, ic_con, DW_IC_CON); |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame^] | 368 | return 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | /* |
| 372 | * Waiting for bus not busy |
| 373 | */ |
| 374 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
| 375 | { |
| 376 | int timeout = TIMEOUT; |
| 377 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 378 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 379 | if (timeout <= 0) { |
| 380 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
| 381 | return -ETIMEDOUT; |
| 382 | } |
| 383 | timeout--; |
| 384 | mdelay(1); |
| 385 | } |
| 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 390 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
| 391 | { |
| 392 | struct i2c_msg *msgs = dev->msgs; |
| 393 | u32 ic_con; |
| 394 | |
| 395 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 396 | dw_writel(dev, 0, DW_IC_ENABLE); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 397 | |
| 398 | /* set the slave (target) address */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 399 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 400 | |
| 401 | /* if the slave address is ten bit address, enable 10BITADDR */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 402 | ic_con = dw_readl(dev, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 403 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
| 404 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
| 405 | else |
| 406 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 407 | dw_writel(dev, ic_con, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 408 | |
| 409 | /* Enable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 410 | dw_writel(dev, 1, DW_IC_ENABLE); |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 411 | |
| 412 | /* Enable interrupts */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 413 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 414 | } |
| 415 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 416 | /* |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 417 | * Initiate (and continue) low level master read/write transaction. |
| 418 | * This function is only called from i2c_dw_isr, and pumping i2c_msg |
| 419 | * messages into the tx buffer. Even if the size of i2c_msg data is |
| 420 | * longer than the size of the tx buffer, it handles everything. |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 421 | */ |
| 422 | static void |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 423 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 424 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 425 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 426 | u32 intr_mask; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 427 | int tx_limit, rx_limit; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 428 | u32 addr = msgs[dev->msg_write_idx].addr; |
| 429 | u32 buf_len = dev->tx_buf_len; |
Justin P. Mattock | 6993248 | 2011-07-26 23:06:29 -0700 | [diff] [blame] | 430 | u8 *buf = dev->tx_buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 431 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 432 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 433 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 434 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 435 | /* |
| 436 | * if target address has changed, we need to |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 437 | * reprogram the target address in the i2c |
| 438 | * adapter when we are done with this transfer |
| 439 | */ |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 440 | if (msgs[dev->msg_write_idx].addr != addr) { |
| 441 | dev_err(dev->dev, |
| 442 | "%s: invalid target address\n", __func__); |
| 443 | dev->msg_err = -EINVAL; |
| 444 | break; |
| 445 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 446 | |
| 447 | if (msgs[dev->msg_write_idx].len == 0) { |
| 448 | dev_err(dev->dev, |
| 449 | "%s: invalid message length\n", __func__); |
| 450 | dev->msg_err = -EINVAL; |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 451 | break; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 452 | } |
| 453 | |
| 454 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 455 | /* new i2c_msg */ |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 456 | buf = msgs[dev->msg_write_idx].buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 457 | buf_len = msgs[dev->msg_write_idx].len; |
| 458 | } |
| 459 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 460 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
| 461 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 462 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 463 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
| 464 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 465 | dw_writel(dev, 0x100, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 466 | rx_limit--; |
| 467 | } else |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 468 | dw_writel(dev, *buf++, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 469 | tx_limit--; buf_len--; |
| 470 | } |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 471 | |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 472 | dev->tx_buf = buf; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 473 | dev->tx_buf_len = buf_len; |
| 474 | |
| 475 | if (buf_len > 0) { |
| 476 | /* more bytes to be written */ |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 477 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
| 478 | break; |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 479 | } else |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 480 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 481 | } |
| 482 | |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 483 | /* |
| 484 | * If i2c_msg index search is completed, we don't need TX_EMPTY |
| 485 | * interrupt any more. |
| 486 | */ |
| 487 | if (dev->msg_write_idx == dev->msgs_num) |
| 488 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; |
| 489 | |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 490 | if (dev->msg_err) |
| 491 | intr_mask = 0; |
| 492 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 493 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | static void |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 497 | i2c_dw_read(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 498 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 499 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 500 | int rx_valid; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 501 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 502 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 503 | u32 len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 504 | u8 *buf; |
| 505 | |
| 506 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) |
| 507 | continue; |
| 508 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 509 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
| 510 | len = msgs[dev->msg_read_idx].len; |
| 511 | buf = msgs[dev->msg_read_idx].buf; |
| 512 | } else { |
| 513 | len = dev->rx_buf_len; |
| 514 | buf = dev->rx_buf; |
| 515 | } |
| 516 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 517 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 518 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 519 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 520 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 521 | |
| 522 | if (len > 0) { |
| 523 | dev->status |= STATUS_READ_IN_PROGRESS; |
| 524 | dev->rx_buf_len = len; |
| 525 | dev->rx_buf = buf; |
| 526 | return; |
| 527 | } else |
| 528 | dev->status &= ~STATUS_READ_IN_PROGRESS; |
| 529 | } |
| 530 | } |
| 531 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 532 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
| 533 | { |
| 534 | unsigned long abort_source = dev->abort_source; |
| 535 | int i; |
| 536 | |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 537 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 538 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 539 | dev_dbg(dev->dev, |
| 540 | "%s: %s\n", __func__, abort_sources[i]); |
| 541 | return -EREMOTEIO; |
| 542 | } |
| 543 | |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 544 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 545 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
| 546 | |
| 547 | if (abort_source & DW_IC_TX_ARB_LOST) |
| 548 | return -EAGAIN; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 549 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
| 550 | return -EINVAL; /* wrong msgs[] data */ |
| 551 | else |
| 552 | return -EIO; |
| 553 | } |
| 554 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 555 | /* |
| 556 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
| 557 | */ |
| 558 | static int |
| 559 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
| 560 | { |
| 561 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 562 | int ret; |
| 563 | |
| 564 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
| 565 | |
| 566 | mutex_lock(&dev->lock); |
| 567 | |
| 568 | INIT_COMPLETION(dev->cmd_complete); |
| 569 | dev->msgs = msgs; |
| 570 | dev->msgs_num = num; |
| 571 | dev->cmd_err = 0; |
| 572 | dev->msg_write_idx = 0; |
| 573 | dev->msg_read_idx = 0; |
| 574 | dev->msg_err = 0; |
| 575 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 576 | dev->abort_source = 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 577 | |
| 578 | ret = i2c_dw_wait_bus_not_busy(dev); |
| 579 | if (ret < 0) |
| 580 | goto done; |
| 581 | |
| 582 | /* start the transfers */ |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 583 | i2c_dw_xfer_init(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 584 | |
| 585 | /* wait for tx to complete */ |
| 586 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); |
| 587 | if (ret == 0) { |
| 588 | dev_err(dev->dev, "controller timed out\n"); |
| 589 | i2c_dw_init(dev); |
| 590 | ret = -ETIMEDOUT; |
| 591 | goto done; |
| 592 | } else if (ret < 0) |
| 593 | goto done; |
| 594 | |
| 595 | if (dev->msg_err) { |
| 596 | ret = dev->msg_err; |
| 597 | goto done; |
| 598 | } |
| 599 | |
| 600 | /* no error */ |
| 601 | if (likely(!dev->cmd_err)) { |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 602 | /* Disable the adapter */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 603 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 604 | ret = num; |
| 605 | goto done; |
| 606 | } |
| 607 | |
| 608 | /* We have an error */ |
| 609 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 610 | ret = i2c_dw_handle_tx_abort(dev); |
| 611 | goto done; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 612 | } |
| 613 | ret = -EIO; |
| 614 | |
| 615 | done: |
| 616 | mutex_unlock(&dev->lock); |
| 617 | |
| 618 | return ret; |
| 619 | } |
| 620 | |
| 621 | static u32 i2c_dw_func(struct i2c_adapter *adap) |
| 622 | { |
Shinya Kuribayashi | 52d7e43 | 2009-11-06 21:50:02 +0900 | [diff] [blame] | 623 | return I2C_FUNC_I2C | |
| 624 | I2C_FUNC_10BIT_ADDR | |
| 625 | I2C_FUNC_SMBUS_BYTE | |
| 626 | I2C_FUNC_SMBUS_BYTE_DATA | |
| 627 | I2C_FUNC_SMBUS_WORD_DATA | |
| 628 | I2C_FUNC_SMBUS_I2C_BLOCK; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 629 | } |
| 630 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 631 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
| 632 | { |
| 633 | u32 stat; |
| 634 | |
| 635 | /* |
| 636 | * The IC_INTR_STAT register just indicates "enabled" interrupts. |
| 637 | * Ths unmasked raw version of interrupt status bits are available |
| 638 | * in the IC_RAW_INTR_STAT register. |
| 639 | * |
| 640 | * That is, |
| 641 | * stat = readl(IC_INTR_STAT); |
| 642 | * equals to, |
| 643 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); |
| 644 | * |
| 645 | * The raw version might be useful for debugging purposes. |
| 646 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 647 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 648 | |
| 649 | /* |
| 650 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
| 651 | * you'll miss some interrupts, triggered during the period from |
| 652 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). |
| 653 | * |
| 654 | * Instead, use the separately-prepared IC_CLR_* registers. |
| 655 | */ |
| 656 | if (stat & DW_IC_INTR_RX_UNDER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 657 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 658 | if (stat & DW_IC_INTR_RX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 659 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 660 | if (stat & DW_IC_INTR_TX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 661 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 662 | if (stat & DW_IC_INTR_RD_REQ) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 663 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 664 | if (stat & DW_IC_INTR_TX_ABRT) { |
| 665 | /* |
| 666 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
| 667 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
| 668 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 669 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
| 670 | dw_readl(dev, DW_IC_CLR_TX_ABRT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 671 | } |
| 672 | if (stat & DW_IC_INTR_RX_DONE) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 673 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 674 | if (stat & DW_IC_INTR_ACTIVITY) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 675 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 676 | if (stat & DW_IC_INTR_STOP_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 677 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 678 | if (stat & DW_IC_INTR_START_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 679 | dw_readl(dev, DW_IC_CLR_START_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 680 | if (stat & DW_IC_INTR_GEN_CALL) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 681 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 682 | |
| 683 | return stat; |
| 684 | } |
| 685 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 686 | /* |
| 687 | * Interrupt service routine. This gets called whenever an I2C interrupt |
| 688 | * occurs. |
| 689 | */ |
| 690 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
| 691 | { |
| 692 | struct dw_i2c_dev *dev = dev_id; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 693 | u32 stat; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 694 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 695 | stat = i2c_dw_read_clear_intrbits(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 696 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 697 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 698 | if (stat & DW_IC_INTR_TX_ABRT) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 699 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
| 700 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 701 | |
| 702 | /* |
| 703 | * Anytime TX_ABRT is set, the contents of the tx/rx |
| 704 | * buffers are flushed. Make sure to skip them. |
| 705 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 706 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 707 | goto tx_aborted; |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 708 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 709 | |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 710 | if (stat & DW_IC_INTR_RX_FULL) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 711 | i2c_dw_read(dev); |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 712 | |
| 713 | if (stat & DW_IC_INTR_TX_EMPTY) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 714 | i2c_dw_xfer_msg(dev); |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 715 | |
| 716 | /* |
| 717 | * No need to modify or disable the interrupt mask here. |
| 718 | * i2c_dw_xfer_msg() will take care of it according to |
| 719 | * the current transmit status. |
| 720 | */ |
| 721 | |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 722 | tx_aborted: |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 723 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 724 | complete(&dev->cmd_complete); |
| 725 | |
| 726 | return IRQ_HANDLED; |
| 727 | } |
| 728 | |
| 729 | static struct i2c_algorithm i2c_dw_algo = { |
| 730 | .master_xfer = i2c_dw_xfer, |
| 731 | .functionality = i2c_dw_func, |
| 732 | }; |
| 733 | |
| 734 | static int __devinit dw_i2c_probe(struct platform_device *pdev) |
| 735 | { |
| 736 | struct dw_i2c_dev *dev; |
| 737 | struct i2c_adapter *adap; |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 738 | struct resource *mem, *ioarea; |
| 739 | int irq, r; |
Jean-Hugues Deschenes | 4ff895b | 2011-10-06 11:26:26 -0700 | [diff] [blame] | 740 | u32 reg; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 741 | |
| 742 | /* NOTE: driver uses the static register mapping */ |
| 743 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 744 | if (!mem) { |
| 745 | dev_err(&pdev->dev, "no mem resource?\n"); |
| 746 | return -EINVAL; |
| 747 | } |
| 748 | |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 749 | irq = platform_get_irq(pdev, 0); |
| 750 | if (irq < 0) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 751 | dev_err(&pdev->dev, "no irq resource?\n"); |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 752 | return irq; /* -ENXIO */ |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 753 | } |
| 754 | |
| 755 | ioarea = request_mem_region(mem->start, resource_size(mem), |
| 756 | pdev->name); |
| 757 | if (!ioarea) { |
| 758 | dev_err(&pdev->dev, "I2C region already claimed\n"); |
| 759 | return -EBUSY; |
| 760 | } |
| 761 | |
| 762 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); |
| 763 | if (!dev) { |
| 764 | r = -ENOMEM; |
| 765 | goto err_release_region; |
| 766 | } |
| 767 | |
| 768 | init_completion(&dev->cmd_complete); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 769 | mutex_init(&dev->lock); |
| 770 | dev->dev = get_device(&pdev->dev); |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 771 | dev->irq = irq; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 772 | platform_set_drvdata(pdev, dev); |
| 773 | |
| 774 | dev->clk = clk_get(&pdev->dev, NULL); |
| 775 | if (IS_ERR(dev->clk)) { |
| 776 | r = -ENODEV; |
| 777 | goto err_free_mem; |
| 778 | } |
| 779 | clk_enable(dev->clk); |
| 780 | |
| 781 | dev->base = ioremap(mem->start, resource_size(mem)); |
| 782 | if (dev->base == NULL) { |
| 783 | dev_err(&pdev->dev, "failure mapping io resources\n"); |
| 784 | r = -EBUSY; |
| 785 | goto err_unuse_clocks; |
| 786 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 787 | |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame^] | 788 | r = i2c_dw_init(dev); |
| 789 | if (r) |
| 790 | goto err_unuse_clocks; |
Jean-Hugues Deschenes | 4ff895b | 2011-10-06 11:26:26 -0700 | [diff] [blame] | 791 | |
| 792 | reg = dw_readl(dev, DW_IC_COMP_PARAM_1); |
| 793 | dev->tx_fifo_depth = ((reg >> 16) & 0xff) + 1; |
| 794 | dev->rx_fifo_depth = ((reg >> 8) & 0xff) + 1; |
| 795 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 796 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 797 | dw_writel(dev, 0, DW_IC_INTR_MASK); /* disable IRQ */ |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 798 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 799 | if (r) { |
| 800 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); |
| 801 | goto err_iounmap; |
| 802 | } |
| 803 | |
| 804 | adap = &dev->adapter; |
| 805 | i2c_set_adapdata(adap, dev); |
| 806 | adap->owner = THIS_MODULE; |
| 807 | adap->class = I2C_CLASS_HWMON; |
| 808 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", |
| 809 | sizeof(adap->name)); |
| 810 | adap->algo = &i2c_dw_algo; |
| 811 | adap->dev.parent = &pdev->dev; |
| 812 | |
| 813 | adap->nr = pdev->id; |
| 814 | r = i2c_add_numbered_adapter(adap); |
| 815 | if (r) { |
| 816 | dev_err(&pdev->dev, "failure adding adapter\n"); |
| 817 | goto err_free_irq; |
| 818 | } |
| 819 | |
| 820 | return 0; |
| 821 | |
| 822 | err_free_irq: |
| 823 | free_irq(dev->irq, dev); |
| 824 | err_iounmap: |
| 825 | iounmap(dev->base); |
| 826 | err_unuse_clocks: |
| 827 | clk_disable(dev->clk); |
| 828 | clk_put(dev->clk); |
| 829 | dev->clk = NULL; |
| 830 | err_free_mem: |
| 831 | platform_set_drvdata(pdev, NULL); |
| 832 | put_device(&pdev->dev); |
| 833 | kfree(dev); |
| 834 | err_release_region: |
| 835 | release_mem_region(mem->start, resource_size(mem)); |
| 836 | |
| 837 | return r; |
| 838 | } |
| 839 | |
| 840 | static int __devexit dw_i2c_remove(struct platform_device *pdev) |
| 841 | { |
| 842 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); |
| 843 | struct resource *mem; |
| 844 | |
| 845 | platform_set_drvdata(pdev, NULL); |
| 846 | i2c_del_adapter(&dev->adapter); |
| 847 | put_device(&pdev->dev); |
| 848 | |
| 849 | clk_disable(dev->clk); |
| 850 | clk_put(dev->clk); |
| 851 | dev->clk = NULL; |
| 852 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 853 | dw_writel(dev, 0, DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 854 | free_irq(dev->irq, dev); |
| 855 | kfree(dev); |
| 856 | |
| 857 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 858 | release_mem_region(mem->start, resource_size(mem)); |
| 859 | return 0; |
| 860 | } |
| 861 | |
| 862 | /* work with hotplug and coldplug */ |
| 863 | MODULE_ALIAS("platform:i2c_designware"); |
| 864 | |
| 865 | static struct platform_driver dw_i2c_driver = { |
| 866 | .remove = __devexit_p(dw_i2c_remove), |
| 867 | .driver = { |
| 868 | .name = "i2c_designware", |
| 869 | .owner = THIS_MODULE, |
| 870 | }, |
| 871 | }; |
| 872 | |
| 873 | static int __init dw_i2c_init_driver(void) |
| 874 | { |
| 875 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); |
| 876 | } |
| 877 | module_init(dw_i2c_init_driver); |
| 878 | |
| 879 | static void __exit dw_i2c_exit_driver(void) |
| 880 | { |
| 881 | platform_driver_unregister(&dw_i2c_driver); |
| 882 | } |
| 883 | module_exit(dw_i2c_exit_driver); |
| 884 | |
| 885 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); |
| 886 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); |
| 887 | MODULE_LICENSE("GPL"); |