Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc.h> |
| 32 | #include <drm/drm_crtc_helper.h> |
| 33 | #include <drm/drm_edid.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "i915_drv.h" |
| 37 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 38 | /* Here's the desired hotplug mode */ |
| 39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
| 40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
| 41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
| 42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
| 43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
| 44 | ADPA_CRT_HOTPLUG_ENABLE) |
| 45 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 46 | struct intel_crt { |
| 47 | struct intel_encoder base; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 48 | bool force_hotplug_required; |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 49 | u32 adpa_reg; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
| 53 | { |
| 54 | return container_of(intel_attached_encoder(connector), |
| 55 | struct intel_crt, base); |
| 56 | } |
| 57 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 58 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 59 | { |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 60 | return container_of(encoder, struct intel_crt, base); |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 61 | } |
| 62 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 63 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
| 64 | enum pipe *pipe) |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 65 | { |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 66 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 67 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 68 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 69 | u32 tmp; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 70 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 71 | tmp = I915_READ(crt->adpa_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 72 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 73 | if (!(tmp & ADPA_DAC_ENABLE)) |
| 74 | return false; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 75 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 76 | if (HAS_PCH_CPT(dev)) |
| 77 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 78 | else |
| 79 | *pipe = PORT_TO_PIPE(tmp); |
| 80 | |
| 81 | return true; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 84 | static void intel_disable_crt(struct intel_encoder *encoder) |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 85 | { |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 86 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 87 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 88 | u32 temp; |
| 89 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 90 | temp = I915_READ(crt->adpa_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 91 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
ling.ma@intel.com | febc769 | 2009-06-25 11:55:57 +0800 | [diff] [blame] | 92 | temp &= ~ADPA_DAC_ENABLE; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 93 | I915_WRITE(crt->adpa_reg, temp); |
| 94 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 95 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 96 | static void intel_enable_crt(struct intel_encoder *encoder) |
| 97 | { |
| 98 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 99 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 100 | u32 temp; |
| 101 | |
| 102 | temp = I915_READ(crt->adpa_reg); |
| 103 | temp |= ADPA_DAC_ENABLE; |
| 104 | I915_WRITE(crt->adpa_reg, temp); |
| 105 | } |
| 106 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 107 | /* Note: The caller is required to filter out dpms modes not supported by the |
| 108 | * platform. */ |
| 109 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 110 | { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 111 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 112 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 113 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 114 | u32 temp; |
| 115 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 116 | temp = I915_READ(crt->adpa_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 117 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
| 118 | temp &= ~ADPA_DAC_ENABLE; |
Jesse Barnes | bd9e841 | 2012-06-15 11:55:18 -0700 | [diff] [blame] | 119 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 120 | switch (mode) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 121 | case DRM_MODE_DPMS_ON: |
| 122 | temp |= ADPA_DAC_ENABLE; |
| 123 | break; |
| 124 | case DRM_MODE_DPMS_STANDBY: |
| 125 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
| 126 | break; |
| 127 | case DRM_MODE_DPMS_SUSPEND: |
| 128 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 129 | break; |
| 130 | case DRM_MODE_DPMS_OFF: |
| 131 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
| 132 | break; |
| 133 | } |
| 134 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 135 | I915_WRITE(crt->adpa_reg, temp); |
| 136 | } |
| 137 | |
| 138 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
| 139 | { |
| 140 | struct drm_device *dev = connector->dev; |
| 141 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
| 142 | struct drm_crtc *crtc; |
| 143 | int old_dpms; |
| 144 | |
| 145 | /* PCH platforms and VLV only support on/off. */ |
Jani Nikula | 4a8dece | 2012-11-05 13:51:51 +0200 | [diff] [blame^] | 146 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 147 | mode = DRM_MODE_DPMS_OFF; |
| 148 | |
| 149 | if (mode == connector->dpms) |
| 150 | return; |
| 151 | |
| 152 | old_dpms = connector->dpms; |
| 153 | connector->dpms = mode; |
| 154 | |
| 155 | /* Only need to change hw state when actually enabled */ |
| 156 | crtc = encoder->base.crtc; |
| 157 | if (!crtc) { |
| 158 | encoder->connectors_active = false; |
| 159 | return; |
| 160 | } |
| 161 | |
| 162 | /* We need the pipe to run for anything but OFF. */ |
| 163 | if (mode == DRM_MODE_DPMS_OFF) |
| 164 | encoder->connectors_active = false; |
| 165 | else |
| 166 | encoder->connectors_active = true; |
| 167 | |
| 168 | if (mode < old_dpms) { |
| 169 | /* From off to on, enable the pipe first. */ |
| 170 | intel_crtc_update_dpms(crtc); |
| 171 | |
| 172 | intel_crt_set_dpms(encoder, mode); |
| 173 | } else { |
| 174 | intel_crt_set_dpms(encoder, mode); |
| 175 | |
| 176 | intel_crtc_update_dpms(crtc); |
| 177 | } |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 178 | |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 179 | intel_modeset_check_state(connector->dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | static int intel_crt_mode_valid(struct drm_connector *connector, |
| 183 | struct drm_display_mode *mode) |
| 184 | { |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 185 | struct drm_device *dev = connector->dev; |
| 186 | |
| 187 | int max_clock = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 188 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 189 | return MODE_NO_DBLESCAN; |
| 190 | |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 191 | if (mode->clock < 25000) |
| 192 | return MODE_CLOCK_LOW; |
| 193 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 194 | if (IS_GEN2(dev)) |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 195 | max_clock = 350000; |
| 196 | else |
| 197 | max_clock = 400000; |
| 198 | if (mode->clock > max_clock) |
| 199 | return MODE_CLOCK_HIGH; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 200 | |
| 201 | return MODE_OK; |
| 202 | } |
| 203 | |
| 204 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 205 | const struct drm_display_mode *mode, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 206 | struct drm_display_mode *adjusted_mode) |
| 207 | { |
| 208 | return true; |
| 209 | } |
| 210 | |
| 211 | static void intel_crt_mode_set(struct drm_encoder *encoder, |
| 212 | struct drm_display_mode *mode, |
| 213 | struct drm_display_mode *adjusted_mode) |
| 214 | { |
| 215 | |
| 216 | struct drm_device *dev = encoder->dev; |
| 217 | struct drm_crtc *crtc = encoder->crtc; |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 218 | struct intel_crt *crt = |
| 219 | intel_encoder_to_crt(to_intel_encoder(encoder)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | 6478d41 | 2012-10-14 16:33:11 +0200 | [diff] [blame] | 222 | u32 adpa; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 223 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 224 | adpa = ADPA_HOTPLUG_BITS; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 225 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 226 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
| 227 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 228 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
| 229 | |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 230 | /* For CPT allow 3 pipe config, for others just use A or B */ |
| 231 | if (HAS_PCH_CPT(dev)) |
| 232 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| 233 | else if (intel_crtc->pipe == 0) |
| 234 | adpa |= ADPA_PIPE_A_SELECT; |
| 235 | else |
| 236 | adpa |= ADPA_PIPE_B_SELECT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 237 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 238 | if (!HAS_PCH_SPLIT(dev)) |
| 239 | I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); |
| 240 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 241 | I915_WRITE(crt->adpa_reg, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 242 | } |
| 243 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 244 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 245 | { |
| 246 | struct drm_device *dev = connector->dev; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 247 | struct intel_crt *crt = intel_attached_crt(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 248 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 249 | u32 adpa; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 250 | bool ret; |
| 251 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 252 | /* The first time through, trigger an explicit detection cycle */ |
| 253 | if (crt->force_hotplug_required) { |
| 254 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
| 255 | u32 save_adpa; |
Zhenyu Wang | 67941da | 2009-07-24 01:00:33 +0800 | [diff] [blame] | 256 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 257 | crt->force_hotplug_required = 0; |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 258 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 259 | save_adpa = adpa = I915_READ(PCH_ADPA); |
| 260 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 261 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 262 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 263 | if (turn_off_dac) |
| 264 | adpa &= ~ADPA_DAC_ENABLE; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 265 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 266 | I915_WRITE(PCH_ADPA, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 267 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 268 | if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
| 269 | 1000)) |
| 270 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 271 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 272 | if (turn_off_dac) { |
| 273 | I915_WRITE(PCH_ADPA, save_adpa); |
| 274 | POSTING_READ(PCH_ADPA); |
| 275 | } |
Zhenyu Wang | a4a6b90 | 2010-04-07 16:15:55 +0800 | [diff] [blame] | 276 | } |
| 277 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 278 | /* Check the status to see if both blue and green are on now */ |
| 279 | adpa = I915_READ(PCH_ADPA); |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 280 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 281 | ret = true; |
| 282 | else |
| 283 | ret = false; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 284 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 285 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 286 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 287 | } |
| 288 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 289 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
| 290 | { |
| 291 | struct drm_device *dev = connector->dev; |
| 292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 293 | u32 adpa; |
| 294 | bool ret; |
| 295 | u32 save_adpa; |
| 296 | |
| 297 | save_adpa = adpa = I915_READ(ADPA); |
| 298 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
| 299 | |
| 300 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 301 | |
| 302 | I915_WRITE(ADPA, adpa); |
| 303 | |
| 304 | if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
| 305 | 1000)) { |
| 306 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
| 307 | I915_WRITE(ADPA, save_adpa); |
| 308 | } |
| 309 | |
| 310 | /* Check the status to see if both blue and green are on now */ |
| 311 | adpa = I915_READ(ADPA); |
| 312 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
| 313 | ret = true; |
| 314 | else |
| 315 | ret = false; |
| 316 | |
| 317 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
| 318 | |
| 319 | /* FIXME: debug force function and remove */ |
| 320 | ret = true; |
| 321 | |
| 322 | return ret; |
| 323 | } |
| 324 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 325 | /** |
| 326 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
| 327 | * |
| 328 | * Not for i915G/i915GM |
| 329 | * |
| 330 | * \return true if CRT is connected. |
| 331 | * \return false if CRT is disconnected. |
| 332 | */ |
| 333 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
| 334 | { |
| 335 | struct drm_device *dev = connector->dev; |
| 336 | struct drm_i915_private *dev_priv = dev->dev_private; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 337 | u32 hotplug_en, orig, stat; |
| 338 | bool ret = false; |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 339 | int i, tries = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 340 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 341 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 342 | return intel_ironlake_crt_detect_hotplug(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 343 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 344 | if (IS_VALLEYVIEW(dev)) |
| 345 | return valleyview_crt_detect_hotplug(connector); |
| 346 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 347 | /* |
| 348 | * On 4 series desktop, CRT detect sequence need to be done twice |
| 349 | * to get a reliable result. |
| 350 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 351 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 352 | if (IS_G4X(dev) && !IS_GM45(dev)) |
| 353 | tries = 2; |
| 354 | else |
| 355 | tries = 1; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 356 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 357 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 358 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 359 | for (i = 0; i < tries ; i++) { |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 360 | /* turn on the FORCE_DETECT */ |
| 361 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 362 | /* wait for FORCE_DETECT to go off */ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 363 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
| 364 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 365 | 1000)) |
Chris Wilson | 7907731 | 2010-09-12 19:58:04 +0100 | [diff] [blame] | 366 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 367 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 368 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 369 | stat = I915_READ(PORT_HOTPLUG_STAT); |
| 370 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
| 371 | ret = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 372 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 373 | /* clear the interrupt we just generated, if any */ |
| 374 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
| 375 | |
| 376 | /* and put the bits back */ |
| 377 | I915_WRITE(PORT_HOTPLUG_EN, orig); |
| 378 | |
| 379 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 380 | } |
| 381 | |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 382 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
| 383 | struct i2c_adapter *i2c) |
| 384 | { |
| 385 | struct edid *edid; |
| 386 | |
| 387 | edid = drm_get_edid(connector, i2c); |
| 388 | |
| 389 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
| 390 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
| 391 | intel_gmbus_force_bit(i2c, true); |
| 392 | edid = drm_get_edid(connector, i2c); |
| 393 | intel_gmbus_force_bit(i2c, false); |
| 394 | } |
| 395 | |
| 396 | return edid; |
| 397 | } |
| 398 | |
| 399 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
| 400 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
| 401 | struct i2c_adapter *adapter) |
| 402 | { |
| 403 | struct edid *edid; |
| 404 | |
| 405 | edid = intel_crt_get_edid(connector, adapter); |
| 406 | if (!edid) |
| 407 | return 0; |
| 408 | |
| 409 | return intel_connector_update_modes(connector, edid); |
| 410 | } |
| 411 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 412 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 413 | { |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 414 | struct intel_crt *crt = intel_attached_crt(connector); |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 415 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 416 | struct edid *edid; |
| 417 | struct i2c_adapter *i2c; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 418 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 419 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 420 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 421 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 422 | edid = intel_crt_get_edid(connector, i2c); |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 423 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 424 | if (edid) { |
| 425 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
| 426 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 427 | /* |
| 428 | * This may be a DVI-I connector with a shared DDC |
| 429 | * link between analog and digital outputs, so we |
| 430 | * have to check the EDID input spec of the attached device. |
| 431 | */ |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 432 | if (!is_digital) { |
| 433 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
| 434 | return true; |
| 435 | } |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 436 | |
| 437 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
| 438 | } else { |
| 439 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 440 | } |
| 441 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 442 | kfree(edid); |
| 443 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 444 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 445 | } |
| 446 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 447 | static enum drm_connector_status |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 448 | intel_crt_load_detect(struct intel_crt *crt) |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 449 | { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 450 | struct drm_device *dev = crt->base.base.dev; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 451 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 452 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 453 | uint32_t save_bclrpat; |
| 454 | uint32_t save_vtotal; |
| 455 | uint32_t vtotal, vactive; |
| 456 | uint32_t vsample; |
| 457 | uint32_t vblank, vblank_start, vblank_end; |
| 458 | uint32_t dsl; |
| 459 | uint32_t bclrpat_reg; |
| 460 | uint32_t vtotal_reg; |
| 461 | uint32_t vblank_reg; |
| 462 | uint32_t vsync_reg; |
| 463 | uint32_t pipeconf_reg; |
| 464 | uint32_t pipe_dsl_reg; |
| 465 | uint8_t st00; |
| 466 | enum drm_connector_status status; |
| 467 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 468 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
| 469 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 470 | bclrpat_reg = BCLRPAT(pipe); |
| 471 | vtotal_reg = VTOTAL(pipe); |
| 472 | vblank_reg = VBLANK(pipe); |
| 473 | vsync_reg = VSYNC(pipe); |
| 474 | pipeconf_reg = PIPECONF(pipe); |
| 475 | pipe_dsl_reg = PIPEDSL(pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 476 | |
| 477 | save_bclrpat = I915_READ(bclrpat_reg); |
| 478 | save_vtotal = I915_READ(vtotal_reg); |
| 479 | vblank = I915_READ(vblank_reg); |
| 480 | |
| 481 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
| 482 | vactive = (save_vtotal & 0x7ff) + 1; |
| 483 | |
| 484 | vblank_start = (vblank & 0xfff) + 1; |
| 485 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
| 486 | |
| 487 | /* Set the border color to purple. */ |
| 488 | I915_WRITE(bclrpat_reg, 0x500050); |
| 489 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 490 | if (!IS_GEN2(dev)) { |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 491 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
| 492 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
Chris Wilson | 19c55da | 2010-08-09 14:50:53 +0100 | [diff] [blame] | 493 | POSTING_READ(pipeconf_reg); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 494 | /* Wait for next Vblank to substitue |
| 495 | * border color for Color info */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 496 | intel_wait_for_vblank(dev, pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 497 | st00 = I915_READ8(VGA_MSR_WRITE); |
| 498 | status = ((st00 & (1 << 4)) != 0) ? |
| 499 | connector_status_connected : |
| 500 | connector_status_disconnected; |
| 501 | |
| 502 | I915_WRITE(pipeconf_reg, pipeconf); |
| 503 | } else { |
| 504 | bool restore_vblank = false; |
| 505 | int count, detect; |
| 506 | |
| 507 | /* |
| 508 | * If there isn't any border, add some. |
| 509 | * Yes, this will flicker |
| 510 | */ |
| 511 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
| 512 | uint32_t vsync = I915_READ(vsync_reg); |
| 513 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
| 514 | |
| 515 | vblank_start = vsync_start; |
| 516 | I915_WRITE(vblank_reg, |
| 517 | (vblank_start - 1) | |
| 518 | ((vblank_end - 1) << 16)); |
| 519 | restore_vblank = true; |
| 520 | } |
| 521 | /* sample in the vertical border, selecting the larger one */ |
| 522 | if (vblank_start - vactive >= vtotal - vblank_end) |
| 523 | vsample = (vblank_start + vactive) >> 1; |
| 524 | else |
| 525 | vsample = (vtotal + vblank_end) >> 1; |
| 526 | |
| 527 | /* |
| 528 | * Wait for the border to be displayed |
| 529 | */ |
| 530 | while (I915_READ(pipe_dsl_reg) >= vactive) |
| 531 | ; |
| 532 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
| 533 | ; |
| 534 | /* |
| 535 | * Watch ST00 for an entire scanline |
| 536 | */ |
| 537 | detect = 0; |
| 538 | count = 0; |
| 539 | do { |
| 540 | count++; |
| 541 | /* Read the ST00 VGA status register */ |
| 542 | st00 = I915_READ8(VGA_MSR_WRITE); |
| 543 | if (st00 & (1 << 4)) |
| 544 | detect++; |
| 545 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
| 546 | |
| 547 | /* restore vblank if necessary */ |
| 548 | if (restore_vblank) |
| 549 | I915_WRITE(vblank_reg, vblank); |
| 550 | /* |
| 551 | * If more than 3/4 of the scanline detected a monitor, |
| 552 | * then it is assumed to be present. This works even on i830, |
| 553 | * where there isn't any way to force the border color across |
| 554 | * the screen |
| 555 | */ |
| 556 | status = detect * 4 > count * 3 ? |
| 557 | connector_status_connected : |
| 558 | connector_status_disconnected; |
| 559 | } |
| 560 | |
| 561 | /* Restore previous settings */ |
| 562 | I915_WRITE(bclrpat_reg, save_bclrpat); |
| 563 | |
| 564 | return status; |
| 565 | } |
| 566 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 567 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 568 | intel_crt_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 569 | { |
| 570 | struct drm_device *dev = connector->dev; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 571 | struct intel_crt *crt = intel_attached_crt(connector); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 572 | enum drm_connector_status status; |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 573 | struct intel_load_detect_pipe tmp; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 574 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 575 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 576 | /* We can not rely on the HPD pin always being correctly wired |
| 577 | * up, for example many KVM do not pass it through, and so |
| 578 | * only trust an assertion that the monitor is connected. |
| 579 | */ |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 580 | if (intel_crt_detect_hotplug(connector)) { |
| 581 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 582 | return connector_status_connected; |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 583 | } else |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 584 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 585 | } |
| 586 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 587 | if (intel_crt_detect_ddc(connector)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 588 | return connector_status_connected; |
| 589 | |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 590 | /* Load detection is broken on HPD capable machines. Whoever wants a |
| 591 | * broken monitor (without edid) to work behind a broken kvm (that fails |
| 592 | * to have the right resistors for HP detection) needs to fix this up. |
| 593 | * For now just bail out. */ |
| 594 | if (I915_HAS_HOTPLUG(dev)) |
| 595 | return connector_status_disconnected; |
| 596 | |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 597 | if (!force) |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 598 | return connector->status; |
| 599 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 600 | /* for pre-945g platforms use load detect */ |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 601 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 602 | if (intel_crt_detect_ddc(connector)) |
| 603 | status = connector_status_connected; |
| 604 | else |
| 605 | status = intel_crt_load_detect(crt); |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 606 | intel_release_load_detect_pipe(connector, &tmp); |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 607 | } else |
| 608 | status = connector_status_unknown; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 609 | |
| 610 | return status; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 611 | } |
| 612 | |
| 613 | static void intel_crt_destroy(struct drm_connector *connector) |
| 614 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 615 | drm_sysfs_connector_remove(connector); |
| 616 | drm_connector_cleanup(connector); |
| 617 | kfree(connector); |
| 618 | } |
| 619 | |
| 620 | static int intel_crt_get_modes(struct drm_connector *connector) |
| 621 | { |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 622 | struct drm_device *dev = connector->dev; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 623 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 624 | int ret; |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 625 | struct i2c_adapter *i2c; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 626 | |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 627 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 628 | ret = intel_crt_ddc_get_modes(connector, i2c); |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 629 | if (ret || !IS_G4X(dev)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 630 | return ret; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 631 | |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 632 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 633 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 634 | return intel_crt_ddc_get_modes(connector, i2c); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static int intel_crt_set_property(struct drm_connector *connector, |
| 638 | struct drm_property *property, |
| 639 | uint64_t value) |
| 640 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 641 | return 0; |
| 642 | } |
| 643 | |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 644 | static void intel_crt_reset(struct drm_connector *connector) |
| 645 | { |
| 646 | struct drm_device *dev = connector->dev; |
| 647 | struct intel_crt *crt = intel_attached_crt(connector); |
| 648 | |
| 649 | if (HAS_PCH_SPLIT(dev)) |
| 650 | crt->force_hotplug_required = 1; |
| 651 | } |
| 652 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 653 | /* |
| 654 | * Routines for controlling stuff on the analog port |
| 655 | */ |
| 656 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 657 | static const struct drm_encoder_helper_funcs crt_encoder_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 658 | .mode_fixup = intel_crt_mode_fixup, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 659 | .mode_set = intel_crt_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame] | 660 | .disable = intel_encoder_noop, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | }; |
| 662 | |
| 663 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 664 | .reset = intel_crt_reset, |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 665 | .dpms = intel_crt_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 666 | .detect = intel_crt_detect, |
| 667 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 668 | .destroy = intel_crt_destroy, |
| 669 | .set_property = intel_crt_set_property, |
| 670 | }; |
| 671 | |
| 672 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
| 673 | .mode_valid = intel_crt_mode_valid, |
| 674 | .get_modes = intel_crt_get_modes, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 675 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 676 | }; |
| 677 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 678 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 679 | .destroy = intel_encoder_destroy, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 680 | }; |
| 681 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 682 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
| 683 | { |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 684 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 685 | return 1; |
| 686 | } |
| 687 | |
| 688 | static const struct dmi_system_id intel_no_crt[] = { |
| 689 | { |
| 690 | .callback = intel_no_crt_dmi_callback, |
| 691 | .ident = "ACER ZGB", |
| 692 | .matches = { |
| 693 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
| 694 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
| 695 | }, |
| 696 | }, |
| 697 | { } |
| 698 | }; |
| 699 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 700 | void intel_crt_init(struct drm_device *dev) |
| 701 | { |
| 702 | struct drm_connector *connector; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 703 | struct intel_crt *crt; |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 704 | struct intel_connector *intel_connector; |
David Müller (ELSOFT AG) | db54501 | 2009-08-29 08:54:45 +0200 | [diff] [blame] | 705 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 706 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 707 | /* Skip machines without VGA that falsely report hotplug events */ |
| 708 | if (dmi_check_system(intel_no_crt)) |
| 709 | return; |
| 710 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 711 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
| 712 | if (!crt) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 713 | return; |
| 714 | |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 715 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 716 | if (!intel_connector) { |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 717 | kfree(crt); |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 718 | return; |
| 719 | } |
| 720 | |
| 721 | connector = &intel_connector->base; |
| 722 | drm_connector_init(dev, &intel_connector->base, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 723 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
| 724 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 725 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 726 | DRM_MODE_ENCODER_DAC); |
| 727 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 728 | intel_connector_attach_encoder(intel_connector, &crt->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 729 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 730 | crt->base.type = INTEL_OUTPUT_ANALOG; |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 731 | crt->base.cloneable = true; |
Daniel Vetter | 7f6658e | 2012-10-21 23:26:29 +0200 | [diff] [blame] | 732 | if (IS_HASWELL(dev) || IS_I830(dev)) |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 733 | crt->base.crtc_mask = (1 << 0); |
| 734 | else |
Keith Packard | 0826874 | 2012-08-13 21:34:45 -0700 | [diff] [blame] | 735 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 736 | |
Daniel Vetter | dbb0257 | 2012-01-28 14:49:23 +0100 | [diff] [blame] | 737 | if (IS_GEN2(dev)) |
| 738 | connector->interlace_allowed = 0; |
| 739 | else |
| 740 | connector->interlace_allowed = 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | connector->doublescan_allowed = 0; |
| 742 | |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 743 | if (HAS_PCH_SPLIT(dev)) |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 744 | crt->adpa_reg = PCH_ADPA; |
| 745 | else if (IS_VALLEYVIEW(dev)) |
| 746 | crt->adpa_reg = VLV_ADPA; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 747 | else |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 748 | crt->adpa_reg = ADPA; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 749 | |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 750 | crt->base.disable = intel_disable_crt; |
| 751 | crt->base.enable = intel_enable_crt; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 752 | crt->base.get_hw_state = intel_crt_get_hw_state; |
| 753 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 754 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 755 | drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 756 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
| 757 | |
| 758 | drm_sysfs_connector_add(connector); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 759 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 760 | if (I915_HAS_HOTPLUG(dev)) |
| 761 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 762 | else |
| 763 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 764 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 765 | /* |
| 766 | * Configure the automatic hotplug detection stuff |
| 767 | */ |
| 768 | crt->force_hotplug_required = 0; |
| 769 | if (HAS_PCH_SPLIT(dev)) { |
| 770 | u32 adpa; |
| 771 | |
| 772 | adpa = I915_READ(PCH_ADPA); |
| 773 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
| 774 | adpa |= ADPA_HOTPLUG_BITS; |
| 775 | I915_WRITE(PCH_ADPA, adpa); |
| 776 | POSTING_READ(PCH_ADPA); |
| 777 | |
| 778 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); |
| 779 | crt->force_hotplug_required = 1; |
| 780 | } |
| 781 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 782 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 783 | } |