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Auke Kokbc7f75f2007-09-17 12:30:59 -07001/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
Bruce Allanf5e261e2012-01-01 16:00:03 +00004 Copyright(c) 1999 - 2012 Intel Corporation.
Auke Kokbc7f75f2007-09-17 12:30:59 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/delay.h>
30
31#include "e1000.h"
32
33static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36static s32 e1000_wait_autoneg(struct e1000_hw *hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -070037static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
Bruce Allan2b6b1682011-05-13 07:20:09 +000039 u16 *data, bool read, bool page_set);
Bruce Allana4f58f52009-06-02 11:29:18 +000040static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
Auke Kokbc7f75f2007-09-17 12:30:59 -070043
44/* Cable length tables */
Bruce Allan64806412010-12-11 05:53:42 +000045static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
Bruce Allaneb656d42009-12-01 15:47:02 +000047#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
Auke Kokbc7f75f2007-09-17 12:30:59 -070049
Bruce Allan64806412010-12-11 05:53:42 +000050static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
58 124};
Auke Kokbc7f75f2007-09-17 12:30:59 -070059#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
Alejandro Martinez Ruizc00acf42007-10-18 10:16:33 +020060 ARRAY_SIZE(e1000_igp_2_cable_length_table)
Auke Kokbc7f75f2007-09-17 12:30:59 -070061
Bruce Allana4f58f52009-06-02 11:29:18 +000062#define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64#define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
68
69#define HV_INTC_FC_PAGE_START 768
70#define I82578_ADDR_REG 29
71#define I82577_ADDR_REG 16
72#define I82577_CFG_REG 22
73#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
75#define I82577_CTRL_REG 23
Bruce Allana4f58f52009-06-02 11:29:18 +000076
77/* 82577 specific PHY registers */
78#define I82577_PHY_CTRL_2 18
79#define I82577_PHY_STATUS_2 26
80#define I82577_PHY_DIAG_STATUS 31
81
82/* I82577 PHY Status 2 */
83#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84#define I82577_PHY_STATUS2_MDIX 0x0800
85#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
87
88/* I82577 PHY Control 2 */
89#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
91
92/* I82577 PHY Diagnostics Status */
93#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
95
96/* BM PHY Copper Specific Control 1 */
97#define BM_CS_CTRL1 16
98
Bruce Allana4f58f52009-06-02 11:29:18 +000099#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
102
Auke Kokbc7f75f2007-09-17 12:30:59 -0700103/**
104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
106 *
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return 0, otherwise
109 * return E1000_BLK_PHY_RESET (12).
110 **/
111s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
112{
113 u32 manc;
114
115 manc = er32(MANC);
116
117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
118 E1000_BLK_PHY_RESET : 0;
119}
120
121/**
122 * e1000e_get_phy_id - Retrieve the PHY ID and revision
123 * @hw: pointer to the HW structure
124 *
125 * Reads the PHY registers and stores the PHY ID and possibly the PHY
126 * revision in the hardware structure.
127 **/
128s32 e1000e_get_phy_id(struct e1000_hw *hw)
129{
130 struct e1000_phy_info *phy = &hw->phy;
Bruce Allana4f58f52009-06-02 11:29:18 +0000131 s32 ret_val = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700132 u16 phy_id;
Bruce Allana4f58f52009-06-02 11:29:18 +0000133 u16 retry_count = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700134
Bruce Allan668018d2012-01-31 07:02:56 +0000135 if (!phy->ops.read_reg)
Bruce Allan5015e532012-02-08 02:55:56 +0000136 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700137
Bruce Allana4f58f52009-06-02 11:29:18 +0000138 while (retry_count < 2) {
139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
140 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000141 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700142
Bruce Allana4f58f52009-06-02 11:29:18 +0000143 phy->id = (u32)(phy_id << 16);
144 udelay(20);
145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
146 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000147 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700148
Bruce Allana4f58f52009-06-02 11:29:18 +0000149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
151
152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
Bruce Allan5015e532012-02-08 02:55:56 +0000153 return 0;
Bruce Allana4f58f52009-06-02 11:29:18 +0000154
Bruce Allana4f58f52009-06-02 11:29:18 +0000155 retry_count++;
156 }
Bruce Allan5015e532012-02-08 02:55:56 +0000157
158 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700159}
160
161/**
162 * e1000e_phy_reset_dsp - Reset PHY DSP
163 * @hw: pointer to the HW structure
164 *
165 * Reset the digital signal processor.
166 **/
167s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
168{
169 s32 ret_val;
170
171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
172 if (ret_val)
173 return ret_val;
174
175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
176}
177
178/**
David Graham2d9498f2008-04-23 11:09:14 -0700179 * e1000e_read_phy_reg_mdic - Read MDI control register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700180 * @hw: pointer to the HW structure
181 * @offset: register offset to be read
182 * @data: pointer to the read data
183 *
Auke Kok489815c2008-02-21 15:11:07 -0800184 * Reads the MDI control register in the PHY at offset and stores the
Auke Kokbc7f75f2007-09-17 12:30:59 -0700185 * information read to data.
186 **/
David Graham2d9498f2008-04-23 11:09:14 -0700187s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700188{
189 struct e1000_phy_info *phy = &hw->phy;
190 u32 i, mdic = 0;
191
192 if (offset > MAX_PHY_REG_ADDRESS) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000193 e_dbg("PHY Address %d is out of range\n", offset);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700194 return -E1000_ERR_PARAM;
195 }
196
Bruce Allanad680762008-03-28 09:15:03 -0700197 /*
198 * Set up Op-code, Phy Address, and register offset in the MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -0700199 * Control register. The MAC will take care of interfacing with the
200 * PHY to retrieve the desired data.
201 */
202 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_READ));
205
206 ew32(MDIC, mdic);
207
Bruce Allanad680762008-03-28 09:15:03 -0700208 /*
209 * Poll the ready bit to see if the MDI read completed
210 * Increasing the time out as testing showed failures with
211 * the lower time out
212 */
David Graham2d9498f2008-04-23 11:09:14 -0700213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700214 udelay(50);
215 mdic = er32(MDIC);
216 if (mdic & E1000_MDIC_READY)
217 break;
218 }
219 if (!(mdic & E1000_MDIC_READY)) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000220 e_dbg("MDI Read did not complete\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700221 return -E1000_ERR_PHY;
222 }
223 if (mdic & E1000_MDIC_ERROR) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000224 e_dbg("MDI Error\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700225 return -E1000_ERR_PHY;
226 }
227 *data = (u16) mdic;
228
Bruce Allan664dc872010-11-24 06:01:46 +0000229 /*
230 * Allow some time after each MDIC transaction to avoid
231 * reading duplicate data in the next MDIC transaction.
232 */
233 if (hw->mac.type == e1000_pch2lan)
234 udelay(100);
235
Auke Kokbc7f75f2007-09-17 12:30:59 -0700236 return 0;
237}
238
239/**
David Graham2d9498f2008-04-23 11:09:14 -0700240 * e1000e_write_phy_reg_mdic - Write MDI control register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700241 * @hw: pointer to the HW structure
242 * @offset: register offset to write to
243 * @data: data to write to register at offset
244 *
245 * Writes data to MDI control register in the PHY at offset.
246 **/
David Graham2d9498f2008-04-23 11:09:14 -0700247s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700248{
249 struct e1000_phy_info *phy = &hw->phy;
250 u32 i, mdic = 0;
251
252 if (offset > MAX_PHY_REG_ADDRESS) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000253 e_dbg("PHY Address %d is out of range\n", offset);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700254 return -E1000_ERR_PARAM;
255 }
256
Bruce Allanad680762008-03-28 09:15:03 -0700257 /*
258 * Set up Op-code, Phy Address, and register offset in the MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -0700259 * Control register. The MAC will take care of interfacing with the
260 * PHY to retrieve the desired data.
261 */
262 mdic = (((u32)data) |
263 (offset << E1000_MDIC_REG_SHIFT) |
264 (phy->addr << E1000_MDIC_PHY_SHIFT) |
265 (E1000_MDIC_OP_WRITE));
266
267 ew32(MDIC, mdic);
268
David Graham2d9498f2008-04-23 11:09:14 -0700269 /*
270 * Poll the ready bit to see if the MDI read completed
271 * Increasing the time out as testing showed failures with
272 * the lower time out
273 */
274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
275 udelay(50);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700276 mdic = er32(MDIC);
277 if (mdic & E1000_MDIC_READY)
278 break;
279 }
280 if (!(mdic & E1000_MDIC_READY)) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000281 e_dbg("MDI Write did not complete\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700282 return -E1000_ERR_PHY;
283 }
David Graham2d9498f2008-04-23 11:09:14 -0700284 if (mdic & E1000_MDIC_ERROR) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000285 e_dbg("MDI Error\n");
David Graham2d9498f2008-04-23 11:09:14 -0700286 return -E1000_ERR_PHY;
287 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700288
Bruce Allan664dc872010-11-24 06:01:46 +0000289 /*
290 * Allow some time after each MDIC transaction to avoid
291 * reading duplicate data in the next MDIC transaction.
292 */
293 if (hw->mac.type == e1000_pch2lan)
294 udelay(100);
295
Auke Kokbc7f75f2007-09-17 12:30:59 -0700296 return 0;
297}
298
299/**
300 * e1000e_read_phy_reg_m88 - Read m88 PHY register
301 * @hw: pointer to the HW structure
302 * @offset: register offset to be read
303 * @data: pointer to the read data
304 *
305 * Acquires semaphore, if necessary, then reads the PHY register at offset
306 * and storing the retrieved information in data. Release any acquired
307 * semaphores before exiting.
308 **/
309s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
310{
311 s32 ret_val;
312
Bruce Allan94d81862009-11-20 23:25:26 +0000313 ret_val = hw->phy.ops.acquire(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700314 if (ret_val)
315 return ret_val;
316
David Graham2d9498f2008-04-23 11:09:14 -0700317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
318 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700319
Bruce Allan94d81862009-11-20 23:25:26 +0000320 hw->phy.ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700321
322 return ret_val;
323}
324
325/**
326 * e1000e_write_phy_reg_m88 - Write m88 PHY register
327 * @hw: pointer to the HW structure
328 * @offset: register offset to write to
329 * @data: data to write at register offset
330 *
331 * Acquires semaphore, if necessary, then writes the data to PHY register
332 * at the offset. Release any acquired semaphores before exiting.
333 **/
334s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
335{
336 s32 ret_val;
337
Bruce Allan94d81862009-11-20 23:25:26 +0000338 ret_val = hw->phy.ops.acquire(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700339 if (ret_val)
340 return ret_val;
341
David Graham2d9498f2008-04-23 11:09:14 -0700342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
343 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700344
Bruce Allan94d81862009-11-20 23:25:26 +0000345 hw->phy.ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700346
347 return ret_val;
348}
349
350/**
Bruce Allan2b6b1682011-05-13 07:20:09 +0000351 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
352 * @hw: pointer to the HW structure
353 * @page: page to set (shifted left when necessary)
354 *
355 * Sets PHY page required for PHY register access. Assumes semaphore is
356 * already acquired. Note, this function sets phy.addr to 1 so the caller
357 * must set it appropriately (if necessary) after this function returns.
358 **/
359s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
360{
361 e_dbg("Setting page 0x%x\n", page);
362
363 hw->phy.addr = 1;
364
365 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
366}
367
368/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000369 * __e1000e_read_phy_reg_igp - Read igp PHY register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700370 * @hw: pointer to the HW structure
371 * @offset: register offset to be read
372 * @data: pointer to the read data
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000373 * @locked: semaphore has already been acquired or not
Auke Kokbc7f75f2007-09-17 12:30:59 -0700374 *
375 * Acquires semaphore, if necessary, then reads the PHY register at offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000376 * and stores the retrieved information in data. Release any acquired
Auke Kokbc7f75f2007-09-17 12:30:59 -0700377 * semaphores before exiting.
378 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000379static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
380 bool locked)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700381{
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000382 s32 ret_val = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700383
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000384 if (!locked) {
Bruce Allan668018d2012-01-31 07:02:56 +0000385 if (!hw->phy.ops.acquire)
Bruce Allan5015e532012-02-08 02:55:56 +0000386 return 0;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000387
Bruce Allan94d81862009-11-20 23:25:26 +0000388 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000389 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000390 return ret_val;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000391 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700392
Bruce Allan5015e532012-02-08 02:55:56 +0000393 if (offset > MAX_PHY_MULTI_PAGE_REG)
David Graham2d9498f2008-04-23 11:09:14 -0700394 ret_val = e1000e_write_phy_reg_mdic(hw,
395 IGP01E1000_PHY_PAGE_SELECT,
396 (u16)offset);
Bruce Allan5015e532012-02-08 02:55:56 +0000397 if (!ret_val)
398 ret_val = e1000e_read_phy_reg_mdic(hw,
399 MAX_PHY_REG_ADDRESS & offset,
400 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000401 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000402 hw->phy.ops.release(hw);
Bruce Allan5015e532012-02-08 02:55:56 +0000403
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000404 return ret_val;
405}
Auke Kokbc7f75f2007-09-17 12:30:59 -0700406
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000407/**
408 * e1000e_read_phy_reg_igp - Read igp PHY register
409 * @hw: pointer to the HW structure
410 * @offset: register offset to be read
411 * @data: pointer to the read data
412 *
413 * Acquires semaphore then reads the PHY register at offset and stores the
414 * retrieved information in data.
415 * Release the acquired semaphore before exiting.
416 **/
417s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
418{
419 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
420}
421
422/**
423 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
424 * @hw: pointer to the HW structure
425 * @offset: register offset to be read
426 * @data: pointer to the read data
427 *
428 * Reads the PHY register at offset and stores the retrieved information
429 * in data. Assumes semaphore already acquired.
430 **/
431s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
432{
433 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
434}
435
436/**
437 * e1000e_write_phy_reg_igp - Write igp PHY register
438 * @hw: pointer to the HW structure
439 * @offset: register offset to write to
440 * @data: data to write at register offset
441 * @locked: semaphore has already been acquired or not
442 *
443 * Acquires semaphore, if necessary, then writes the data to PHY register
444 * at the offset. Release any acquired semaphores before exiting.
445 **/
446static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
447 bool locked)
448{
449 s32 ret_val = 0;
450
451 if (!locked) {
Bruce Allan668018d2012-01-31 07:02:56 +0000452 if (!hw->phy.ops.acquire)
Bruce Allan5015e532012-02-08 02:55:56 +0000453 return 0;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000454
Bruce Allan94d81862009-11-20 23:25:26 +0000455 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000456 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000457 return ret_val;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000458 }
459
Bruce Allan5015e532012-02-08 02:55:56 +0000460 if (offset > MAX_PHY_MULTI_PAGE_REG)
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000461 ret_val = e1000e_write_phy_reg_mdic(hw,
462 IGP01E1000_PHY_PAGE_SELECT,
463 (u16)offset);
Bruce Allan5015e532012-02-08 02:55:56 +0000464 if (!ret_val)
465 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
466 offset,
467 data);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000468 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000469 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000470
Auke Kokbc7f75f2007-09-17 12:30:59 -0700471 return ret_val;
472}
473
474/**
475 * e1000e_write_phy_reg_igp - Write igp PHY register
476 * @hw: pointer to the HW structure
477 * @offset: register offset to write to
478 * @data: data to write at register offset
479 *
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000480 * Acquires semaphore then writes the data to PHY register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700481 * at the offset. Release any acquired semaphores before exiting.
482 **/
483s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
484{
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000485 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700486}
487
488/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000489 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
490 * @hw: pointer to the HW structure
491 * @offset: register offset to write to
492 * @data: data to write at register offset
493 *
494 * Writes the data to PHY register at the offset.
495 * Assumes semaphore already acquired.
496 **/
497s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
498{
499 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
500}
501
502/**
503 * __e1000_read_kmrn_reg - Read kumeran register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700504 * @hw: pointer to the HW structure
505 * @offset: register offset to be read
506 * @data: pointer to the read data
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000507 * @locked: semaphore has already been acquired or not
Auke Kokbc7f75f2007-09-17 12:30:59 -0700508 *
509 * Acquires semaphore, if necessary. Then reads the PHY register at offset
510 * using the kumeran interface. The information retrieved is stored in data.
511 * Release any acquired semaphores before exiting.
512 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000513static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
514 bool locked)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700515{
516 u32 kmrnctrlsta;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700517
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000518 if (!locked) {
Bruce Allan5015e532012-02-08 02:55:56 +0000519 s32 ret_val = 0;
520
Bruce Allan668018d2012-01-31 07:02:56 +0000521 if (!hw->phy.ops.acquire)
Bruce Allan5015e532012-02-08 02:55:56 +0000522 return 0;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000523
Bruce Allan94d81862009-11-20 23:25:26 +0000524 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000525 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000526 return ret_val;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000527 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700528
529 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
530 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
531 ew32(KMRNCTRLSTA, kmrnctrlsta);
Jesse Brandeburg945a5152011-07-20 00:56:21 +0000532 e1e_flush();
Auke Kokbc7f75f2007-09-17 12:30:59 -0700533
534 udelay(2);
535
536 kmrnctrlsta = er32(KMRNCTRLSTA);
537 *data = (u16)kmrnctrlsta;
538
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000539 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000540 hw->phy.ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700541
Bruce Allan5015e532012-02-08 02:55:56 +0000542 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700543}
544
545/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000546 * e1000e_read_kmrn_reg - Read kumeran register
547 * @hw: pointer to the HW structure
548 * @offset: register offset to be read
549 * @data: pointer to the read data
550 *
551 * Acquires semaphore then reads the PHY register at offset using the
552 * kumeran interface. The information retrieved is stored in data.
553 * Release the acquired semaphore before exiting.
554 **/
555s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
556{
557 return __e1000_read_kmrn_reg(hw, offset, data, false);
558}
559
560/**
Bruce Allan1d5846b2009-10-29 13:46:05 +0000561 * e1000e_read_kmrn_reg_locked - Read kumeran register
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000562 * @hw: pointer to the HW structure
563 * @offset: register offset to be read
564 * @data: pointer to the read data
565 *
566 * Reads the PHY register at offset using the kumeran interface. The
567 * information retrieved is stored in data.
568 * Assumes semaphore already acquired.
569 **/
Bruce Allan1d5846b2009-10-29 13:46:05 +0000570s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000571{
572 return __e1000_read_kmrn_reg(hw, offset, data, true);
573}
574
575/**
576 * __e1000_write_kmrn_reg - Write kumeran register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700577 * @hw: pointer to the HW structure
578 * @offset: register offset to write to
579 * @data: data to write at register offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000580 * @locked: semaphore has already been acquired or not
Auke Kokbc7f75f2007-09-17 12:30:59 -0700581 *
582 * Acquires semaphore, if necessary. Then write the data to PHY register
583 * at the offset using the kumeran interface. Release any acquired semaphores
584 * before exiting.
585 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000586static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
587 bool locked)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700588{
589 u32 kmrnctrlsta;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700590
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000591 if (!locked) {
Bruce Allan5015e532012-02-08 02:55:56 +0000592 s32 ret_val = 0;
593
Bruce Allan668018d2012-01-31 07:02:56 +0000594 if (!hw->phy.ops.acquire)
Bruce Allan5015e532012-02-08 02:55:56 +0000595 return 0;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000596
Bruce Allan94d81862009-11-20 23:25:26 +0000597 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000598 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000599 return ret_val;
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000600 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700601
602 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
603 E1000_KMRNCTRLSTA_OFFSET) | data;
604 ew32(KMRNCTRLSTA, kmrnctrlsta);
Jesse Brandeburg945a5152011-07-20 00:56:21 +0000605 e1e_flush();
Auke Kokbc7f75f2007-09-17 12:30:59 -0700606
607 udelay(2);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700608
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000609 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +0000610 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000611
Bruce Allan5015e532012-02-08 02:55:56 +0000612 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700613}
614
615/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000616 * e1000e_write_kmrn_reg - Write kumeran register
617 * @hw: pointer to the HW structure
618 * @offset: register offset to write to
619 * @data: data to write at register offset
620 *
621 * Acquires semaphore then writes the data to the PHY register at the offset
622 * using the kumeran interface. Release the acquired semaphore before exiting.
623 **/
624s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
625{
626 return __e1000_write_kmrn_reg(hw, offset, data, false);
627}
628
629/**
Bruce Allan1d5846b2009-10-29 13:46:05 +0000630 * e1000e_write_kmrn_reg_locked - Write kumeran register
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000631 * @hw: pointer to the HW structure
632 * @offset: register offset to write to
633 * @data: data to write at register offset
634 *
635 * Write the data to PHY register at the offset using the kumeran interface.
636 * Assumes semaphore already acquired.
637 **/
Bruce Allan1d5846b2009-10-29 13:46:05 +0000638s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
Bruce Allan5ccdcec2009-10-26 11:24:02 +0000639{
640 return __e1000_write_kmrn_reg(hw, offset, data, true);
641}
642
643/**
Bruce Allana4f58f52009-06-02 11:29:18 +0000644 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
645 * @hw: pointer to the HW structure
646 *
647 * Sets up Carrier-sense on Transmit and downshift values.
648 **/
649s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
650{
Bruce Allana4f58f52009-06-02 11:29:18 +0000651 s32 ret_val;
652 u16 phy_data;
653
Bruce Allanaf667a22010-12-31 06:10:01 +0000654 /* Enable CRS on Tx. This must be set for half-duplex operation. */
Bruce Allan482fed82011-01-06 14:29:49 +0000655 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000656 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +0000657 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +0000658
659 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
660
661 /* Enable downshift */
662 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
663
Bruce Allan5015e532012-02-08 02:55:56 +0000664 return e1e_wphy(hw, I82577_CFG_REG, phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000665}
666
667/**
Auke Kokbc7f75f2007-09-17 12:30:59 -0700668 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
669 * @hw: pointer to the HW structure
670 *
671 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
672 * and downshift values are set also.
673 **/
674s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
675{
676 struct e1000_phy_info *phy = &hw->phy;
677 s32 ret_val;
678 u16 phy_data;
679
Bruce Allanad680762008-03-28 09:15:03 -0700680 /* Enable CRS on Tx. This must be set for half-duplex operation. */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700681 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
682 if (ret_val)
683 return ret_val;
684
Bruce Allana4f58f52009-06-02 11:29:18 +0000685 /* For BM PHY this bit is downshift enable */
686 if (phy->type != e1000_phy_bm)
David Graham2d9498f2008-04-23 11:09:14 -0700687 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700688
Bruce Allanad680762008-03-28 09:15:03 -0700689 /*
690 * Options:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700691 * MDI/MDI-X = 0 (default)
692 * 0 - Auto for all speeds
693 * 1 - MDI mode
694 * 2 - MDI-X mode
695 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
696 */
697 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
698
699 switch (phy->mdix) {
700 case 1:
701 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
702 break;
703 case 2:
704 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
705 break;
706 case 3:
707 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
708 break;
709 case 0:
710 default:
711 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
712 break;
713 }
714
Bruce Allanad680762008-03-28 09:15:03 -0700715 /*
716 * Options:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700717 * disable_polarity_correction = 0 (default)
718 * Automatic Correction for Reversed Cable Polarity
719 * 0 - Disabled
720 * 1 - Enabled
721 */
722 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
723 if (phy->disable_polarity_correction == 1)
724 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
725
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700726 /* Enable downshift on BM (disabled by default) */
727 if (phy->type == e1000_phy_bm)
728 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
729
Auke Kokbc7f75f2007-09-17 12:30:59 -0700730 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
731 if (ret_val)
732 return ret_val;
733
Bruce Allan4662e822008-08-26 18:37:06 -0700734 if ((phy->type == e1000_phy_m88) &&
735 (phy->revision < E1000_REVISION_4) &&
736 (phy->id != BME1000_E_PHY_ID_R2)) {
Bruce Allanad680762008-03-28 09:15:03 -0700737 /*
738 * Force TX_CLK in the Extended PHY Specific Control Register
Auke Kokbc7f75f2007-09-17 12:30:59 -0700739 * to 25MHz clock.
740 */
741 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
742 if (ret_val)
743 return ret_val;
744
745 phy_data |= M88E1000_EPSCR_TX_CLK_25;
746
747 if ((phy->revision == 2) &&
748 (phy->id == M88E1111_I_PHY_ID)) {
749 /* 82573L PHY - set the downshift counter to 5x. */
750 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
751 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
752 } else {
753 /* Configure Master and Slave downshift values */
754 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
755 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
756 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
757 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
758 }
759 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
760 if (ret_val)
761 return ret_val;
762 }
763
Bruce Allan4662e822008-08-26 18:37:06 -0700764 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
765 /* Set PHY page 0, register 29 to 0x0003 */
766 ret_val = e1e_wphy(hw, 29, 0x0003);
767 if (ret_val)
768 return ret_val;
769
770 /* Set PHY page 0, register 30 to 0x0000 */
771 ret_val = e1e_wphy(hw, 30, 0x0000);
772 if (ret_val)
773 return ret_val;
774 }
775
Auke Kokbc7f75f2007-09-17 12:30:59 -0700776 /* Commit the changes. */
777 ret_val = e1000e_commit_phy(hw);
Bruce Allana4f58f52009-06-02 11:29:18 +0000778 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000779 e_dbg("Error committing the PHY changes\n");
Bruce Allana4f58f52009-06-02 11:29:18 +0000780 return ret_val;
781 }
Auke Kokbc7f75f2007-09-17 12:30:59 -0700782
Bruce Allana4f58f52009-06-02 11:29:18 +0000783 if (phy->type == e1000_phy_82578) {
Bruce Allan482fed82011-01-06 14:29:49 +0000784 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000785 if (ret_val)
786 return ret_val;
787
788 /* 82578 PHY - set the downshift count to 1x. */
789 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
790 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
Bruce Allan482fed82011-01-06 14:29:49 +0000791 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +0000792 if (ret_val)
793 return ret_val;
794 }
795
796 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700797}
798
799/**
800 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
801 * @hw: pointer to the HW structure
802 *
803 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
804 * igp PHY's.
805 **/
806s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
807{
808 struct e1000_phy_info *phy = &hw->phy;
809 s32 ret_val;
810 u16 data;
811
812 ret_val = e1000_phy_hw_reset(hw);
813 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000814 e_dbg("Error resetting the PHY.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700815 return ret_val;
816 }
817
David Graham2d9498f2008-04-23 11:09:14 -0700818 /*
819 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
820 * timeout issues when LFS is enabled.
821 */
822 msleep(100);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700823
824 /* disable lplu d0 during driver init */
Bruce Allan564ea9b2009-11-20 23:26:44 +0000825 ret_val = e1000_set_d0_lplu_state(hw, false);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700826 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000827 e_dbg("Error Disabling LPLU D0\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700828 return ret_val;
829 }
830 /* Configure mdi-mdix settings */
831 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
832 if (ret_val)
833 return ret_val;
834
835 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
836
837 switch (phy->mdix) {
838 case 1:
839 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
840 break;
841 case 2:
842 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
843 break;
844 case 0:
845 default:
846 data |= IGP01E1000_PSCR_AUTO_MDIX;
847 break;
848 }
849 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
850 if (ret_val)
851 return ret_val;
852
853 /* set auto-master slave resolution settings */
854 if (hw->mac.autoneg) {
Bruce Allanad680762008-03-28 09:15:03 -0700855 /*
856 * when autonegotiation advertisement is only 1000Mbps then we
Auke Kokbc7f75f2007-09-17 12:30:59 -0700857 * should disable SmartSpeed and enable Auto MasterSlave
Bruce Allanad680762008-03-28 09:15:03 -0700858 * resolution as hardware default.
859 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700860 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
861 /* Disable SmartSpeed */
862 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700863 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700864 if (ret_val)
865 return ret_val;
866
867 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
868 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700869 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700870 if (ret_val)
871 return ret_val;
872
873 /* Set auto Master/Slave resolution process */
874 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
875 if (ret_val)
876 return ret_val;
877
878 data &= ~CR_1000T_MS_ENABLE;
879 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
880 if (ret_val)
881 return ret_val;
882 }
883
884 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
885 if (ret_val)
886 return ret_val;
887
888 /* load defaults for future use */
889 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
890 ((data & CR_1000T_MS_VALUE) ?
891 e1000_ms_force_master :
892 e1000_ms_force_slave) :
893 e1000_ms_auto;
894
895 switch (phy->ms_type) {
896 case e1000_ms_force_master:
897 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
898 break;
899 case e1000_ms_force_slave:
900 data |= CR_1000T_MS_ENABLE;
901 data &= ~(CR_1000T_MS_VALUE);
902 break;
903 case e1000_ms_auto:
904 data &= ~CR_1000T_MS_ENABLE;
905 default:
906 break;
907 }
908 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
909 }
910
911 return ret_val;
912}
913
914/**
915 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
916 * @hw: pointer to the HW structure
917 *
918 * Reads the MII auto-neg advertisement register and/or the 1000T control
919 * register and if the PHY is already setup for auto-negotiation, then
920 * return successful. Otherwise, setup advertisement and flow control to
921 * the appropriate values for the wanted auto-negotiation.
922 **/
923static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
924{
925 struct e1000_phy_info *phy = &hw->phy;
926 s32 ret_val;
927 u16 mii_autoneg_adv_reg;
928 u16 mii_1000t_ctrl_reg = 0;
929
930 phy->autoneg_advertised &= phy->autoneg_mask;
931
932 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
933 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
934 if (ret_val)
935 return ret_val;
936
937 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
938 /* Read the MII 1000Base-T Control Register (Address 9). */
939 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
940 if (ret_val)
941 return ret_val;
942 }
943
Bruce Allanad680762008-03-28 09:15:03 -0700944 /*
945 * Need to parse both autoneg_advertised and fc and set up
Auke Kokbc7f75f2007-09-17 12:30:59 -0700946 * the appropriate PHY registers. First we will parse for
947 * autoneg_advertised software override. Since we can advertise
948 * a plethora of combinations, we need to check each bit
949 * individually.
950 */
951
Bruce Allanad680762008-03-28 09:15:03 -0700952 /*
953 * First we clear all the 10/100 mb speed bits in the Auto-Neg
Auke Kokbc7f75f2007-09-17 12:30:59 -0700954 * Advertisement Register (Address 4) and the 1000 mb speed bits in
955 * the 1000Base-T Control Register (Address 9).
956 */
957 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
958 NWAY_AR_100TX_HD_CAPS |
959 NWAY_AR_10T_FD_CAPS |
960 NWAY_AR_10T_HD_CAPS);
961 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
962
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000963 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700964
965 /* Do we want to advertise 10 Mb Half Duplex? */
966 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000967 e_dbg("Advertise 10mb Half duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700968 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
969 }
970
971 /* Do we want to advertise 10 Mb Full Duplex? */
972 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000973 e_dbg("Advertise 10mb Full duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700974 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
975 }
976
977 /* Do we want to advertise 100 Mb Half Duplex? */
978 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000979 e_dbg("Advertise 100mb Half duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700980 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
981 }
982
983 /* Do we want to advertise 100 Mb Full Duplex? */
984 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000985 e_dbg("Advertise 100mb Full duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700986 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
987 }
988
989 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
990 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000991 e_dbg("Advertise 1000mb Half duplex request denied!\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700992
993 /* Do we want to advertise 1000 Mb Full Duplex? */
994 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +0000995 e_dbg("Advertise 1000mb Full duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -0700996 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
997 }
998
Bruce Allanad680762008-03-28 09:15:03 -0700999 /*
1000 * Check for a software override of the flow control settings, and
Auke Kokbc7f75f2007-09-17 12:30:59 -07001001 * setup the PHY advertisement registers accordingly. If
1002 * auto-negotiation is enabled, then software will have to set the
1003 * "PAUSE" bits to the correct value in the Auto-Negotiation
1004 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1005 * negotiation.
1006 *
1007 * The possible values of the "fc" parameter are:
1008 * 0: Flow control is completely disabled
1009 * 1: Rx flow control is enabled (we can receive pause frames
1010 * but not send pause frames).
1011 * 2: Tx flow control is enabled (we can send pause frames
1012 * but we do not support receiving pause frames).
Bruce Allanad680762008-03-28 09:15:03 -07001013 * 3: Both Rx and Tx flow control (symmetric) are enabled.
Auke Kokbc7f75f2007-09-17 12:30:59 -07001014 * other: No software override. The flow control configuration
1015 * in the EEPROM is used.
1016 */
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08001017 switch (hw->fc.current_mode) {
Auke Kokbc7f75f2007-09-17 12:30:59 -07001018 case e1000_fc_none:
Bruce Allanad680762008-03-28 09:15:03 -07001019 /*
1020 * Flow control (Rx & Tx) is completely disabled by a
Auke Kokbc7f75f2007-09-17 12:30:59 -07001021 * software over-ride.
1022 */
1023 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1024 break;
1025 case e1000_fc_rx_pause:
Bruce Allanad680762008-03-28 09:15:03 -07001026 /*
1027 * Rx Flow control is enabled, and Tx Flow control is
Auke Kokbc7f75f2007-09-17 12:30:59 -07001028 * disabled, by a software over-ride.
Bruce Allanad680762008-03-28 09:15:03 -07001029 *
1030 * Since there really isn't a way to advertise that we are
1031 * capable of Rx Pause ONLY, we will advertise that we
1032 * support both symmetric and asymmetric Rx PAUSE. Later
Auke Kokbc7f75f2007-09-17 12:30:59 -07001033 * (in e1000e_config_fc_after_link_up) we will disable the
1034 * hw's ability to send PAUSE frames.
1035 */
1036 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1037 break;
1038 case e1000_fc_tx_pause:
Bruce Allanad680762008-03-28 09:15:03 -07001039 /*
1040 * Tx Flow control is enabled, and Rx Flow control is
Auke Kokbc7f75f2007-09-17 12:30:59 -07001041 * disabled, by a software over-ride.
1042 */
1043 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1044 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1045 break;
1046 case e1000_fc_full:
Bruce Allanad680762008-03-28 09:15:03 -07001047 /*
1048 * Flow control (both Rx and Tx) is enabled by a software
Auke Kokbc7f75f2007-09-17 12:30:59 -07001049 * over-ride.
1050 */
1051 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1052 break;
1053 default:
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001054 e_dbg("Flow control param set incorrectly\n");
Bruce Allan7eb61d82012-02-08 02:55:03 +00001055 return -E1000_ERR_CONFIG;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001056 }
1057
1058 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1059 if (ret_val)
1060 return ret_val;
1061
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001062 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001063
Bruce Allanb1cdfea2010-12-11 05:53:47 +00001064 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
Auke Kokbc7f75f2007-09-17 12:30:59 -07001065 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001066
1067 return ret_val;
1068}
1069
1070/**
1071 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1072 * @hw: pointer to the HW structure
1073 *
1074 * Performs initial bounds checking on autoneg advertisement parameter, then
1075 * configure to advertise the full capability. Setup the PHY to autoneg
1076 * and restart the negotiation process between the link partner. If
Bruce Allanad680762008-03-28 09:15:03 -07001077 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
Auke Kokbc7f75f2007-09-17 12:30:59 -07001078 **/
1079static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1080{
1081 struct e1000_phy_info *phy = &hw->phy;
1082 s32 ret_val;
1083 u16 phy_ctrl;
1084
Bruce Allanad680762008-03-28 09:15:03 -07001085 /*
1086 * Perform some bounds checking on the autoneg advertisement
Auke Kokbc7f75f2007-09-17 12:30:59 -07001087 * parameter.
1088 */
1089 phy->autoneg_advertised &= phy->autoneg_mask;
1090
Bruce Allanad680762008-03-28 09:15:03 -07001091 /*
1092 * If autoneg_advertised is zero, we assume it was not defaulted
Auke Kokbc7f75f2007-09-17 12:30:59 -07001093 * by the calling code so we set to advertise full capability.
1094 */
1095 if (phy->autoneg_advertised == 0)
1096 phy->autoneg_advertised = phy->autoneg_mask;
1097
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001098 e_dbg("Reconfiguring auto-neg advertisement params\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001099 ret_val = e1000_phy_setup_autoneg(hw);
1100 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001101 e_dbg("Error Setting up Auto-Negotiation\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001102 return ret_val;
1103 }
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001104 e_dbg("Restarting Auto-Neg\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001105
Bruce Allanad680762008-03-28 09:15:03 -07001106 /*
1107 * Restart auto-negotiation by setting the Auto Neg Enable bit and
Auke Kokbc7f75f2007-09-17 12:30:59 -07001108 * the Auto Neg Restart bit in the PHY control register.
1109 */
1110 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1111 if (ret_val)
1112 return ret_val;
1113
1114 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1115 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1116 if (ret_val)
1117 return ret_val;
1118
Bruce Allanad680762008-03-28 09:15:03 -07001119 /*
1120 * Does the user want to wait for Auto-Neg to complete here, or
Auke Kokbc7f75f2007-09-17 12:30:59 -07001121 * check at a later time (for example, callback routine).
1122 */
Jeff Kirsher318a94d2008-03-28 09:15:16 -07001123 if (phy->autoneg_wait_to_complete) {
Auke Kokbc7f75f2007-09-17 12:30:59 -07001124 ret_val = e1000_wait_autoneg(hw);
1125 if (ret_val) {
Bruce Allan434f1392011-12-16 00:46:54 +00001126 e_dbg("Error while waiting for autoneg to complete\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001127 return ret_val;
1128 }
1129 }
1130
Bruce Allanf92518d2012-02-01 11:16:42 +00001131 hw->mac.get_link_status = true;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001132
1133 return ret_val;
1134}
1135
1136/**
1137 * e1000e_setup_copper_link - Configure copper link settings
1138 * @hw: pointer to the HW structure
1139 *
1140 * Calls the appropriate function to configure the link for auto-neg or forced
1141 * speed and duplex. Then we check for link, once link is established calls
1142 * to configure collision distance and flow control are called. If link is
1143 * not established, we return -E1000_ERR_PHY (-2).
1144 **/
1145s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1146{
1147 s32 ret_val;
1148 bool link;
1149
1150 if (hw->mac.autoneg) {
Bruce Allanad680762008-03-28 09:15:03 -07001151 /*
1152 * Setup autoneg and flow control advertisement and perform
1153 * autonegotiation.
1154 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001155 ret_val = e1000_copper_link_autoneg(hw);
1156 if (ret_val)
1157 return ret_val;
1158 } else {
Bruce Allanad680762008-03-28 09:15:03 -07001159 /*
1160 * PHY will be set to 10H, 10F, 100H or 100F
1161 * depending on user settings.
1162 */
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001163 e_dbg("Forcing Speed and Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001164 ret_val = e1000_phy_force_speed_duplex(hw);
1165 if (ret_val) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001166 e_dbg("Error Forcing Speed and Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001167 return ret_val;
1168 }
1169 }
1170
Bruce Allanad680762008-03-28 09:15:03 -07001171 /*
1172 * Check link status. Wait up to 100 microseconds for link to become
Auke Kokbc7f75f2007-09-17 12:30:59 -07001173 * valid.
1174 */
1175 ret_val = e1000e_phy_has_link_generic(hw,
1176 COPPER_LINK_UP_LIMIT,
1177 10,
1178 &link);
1179 if (ret_val)
1180 return ret_val;
1181
1182 if (link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001183 e_dbg("Valid link established!!!\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001184 e1000e_config_collision_dist(hw);
1185 ret_val = e1000e_config_fc_after_link_up(hw);
1186 } else {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001187 e_dbg("Unable to establish link!!!\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001188 }
1189
1190 return ret_val;
1191}
1192
1193/**
1194 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1195 * @hw: pointer to the HW structure
1196 *
1197 * Calls the PHY setup function to force speed and duplex. Clears the
1198 * auto-crossover to force MDI manually. Waits for link and returns
1199 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1200 **/
1201s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1202{
1203 struct e1000_phy_info *phy = &hw->phy;
1204 s32 ret_val;
1205 u16 phy_data;
1206 bool link;
1207
1208 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1209 if (ret_val)
1210 return ret_val;
1211
1212 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1213
1214 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1215 if (ret_val)
1216 return ret_val;
1217
Bruce Allanad680762008-03-28 09:15:03 -07001218 /*
1219 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -07001220 * forced whenever speed and duplex are forced.
1221 */
1222 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1223 if (ret_val)
1224 return ret_val;
1225
1226 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1227 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1228
1229 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1230 if (ret_val)
1231 return ret_val;
1232
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001233 e_dbg("IGP PSCR: %X\n", phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001234
1235 udelay(1);
1236
Jeff Kirsher318a94d2008-03-28 09:15:16 -07001237 if (phy->autoneg_wait_to_complete) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001238 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001239
1240 ret_val = e1000e_phy_has_link_generic(hw,
1241 PHY_FORCE_LIMIT,
1242 100000,
1243 &link);
1244 if (ret_val)
1245 return ret_val;
1246
1247 if (!link)
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001248 e_dbg("Link taking longer than expected.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001249
1250 /* Try once more */
1251 ret_val = e1000e_phy_has_link_generic(hw,
1252 PHY_FORCE_LIMIT,
1253 100000,
1254 &link);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001255 }
1256
1257 return ret_val;
1258}
1259
1260/**
1261 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1262 * @hw: pointer to the HW structure
1263 *
1264 * Calls the PHY setup function to force speed and duplex. Clears the
1265 * auto-crossover to force MDI manually. Resets the PHY to commit the
1266 * changes. If time expires while waiting for link up, we reset the DSP.
Bruce Allanad680762008-03-28 09:15:03 -07001267 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
Auke Kokbc7f75f2007-09-17 12:30:59 -07001268 * successful completion, else return corresponding error code.
1269 **/
1270s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1271{
1272 struct e1000_phy_info *phy = &hw->phy;
1273 s32 ret_val;
1274 u16 phy_data;
1275 bool link;
1276
Bruce Allanad680762008-03-28 09:15:03 -07001277 /*
1278 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
Auke Kokbc7f75f2007-09-17 12:30:59 -07001279 * forced whenever speed and duplex are forced.
1280 */
1281 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1282 if (ret_val)
1283 return ret_val;
1284
1285 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1286 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1287 if (ret_val)
1288 return ret_val;
1289
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001290 e_dbg("M88E1000 PSCR: %X\n", phy_data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001291
1292 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1293 if (ret_val)
1294 return ret_val;
1295
1296 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1297
Auke Kokbc7f75f2007-09-17 12:30:59 -07001298 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1299 if (ret_val)
1300 return ret_val;
1301
Bruce Allan5aa49c82008-11-21 16:49:53 -08001302 /* Reset the phy to commit changes. */
1303 ret_val = e1000e_commit_phy(hw);
1304 if (ret_val)
1305 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001306
Jeff Kirsher318a94d2008-03-28 09:15:16 -07001307 if (phy->autoneg_wait_to_complete) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001308 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001309
1310 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1311 100000, &link);
1312 if (ret_val)
1313 return ret_val;
1314
1315 if (!link) {
Bruce Allan0be84012009-12-02 17:03:18 +00001316 if (hw->phy.type != e1000_phy_m88) {
1317 e_dbg("Link taking longer than expected.\n");
1318 } else {
1319 /*
1320 * We didn't get link.
1321 * Reset the DSP and cross our fingers.
1322 */
Bruce Allan482fed82011-01-06 14:29:49 +00001323 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1324 0x001d);
Bruce Allan0be84012009-12-02 17:03:18 +00001325 if (ret_val)
1326 return ret_val;
1327 ret_val = e1000e_phy_reset_dsp(hw);
1328 if (ret_val)
1329 return ret_val;
1330 }
Auke Kokbc7f75f2007-09-17 12:30:59 -07001331 }
1332
1333 /* Try once more */
1334 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1335 100000, &link);
1336 if (ret_val)
1337 return ret_val;
1338 }
1339
Bruce Allan0be84012009-12-02 17:03:18 +00001340 if (hw->phy.type != e1000_phy_m88)
1341 return 0;
1342
Auke Kokbc7f75f2007-09-17 12:30:59 -07001343 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1344 if (ret_val)
1345 return ret_val;
1346
Bruce Allanad680762008-03-28 09:15:03 -07001347 /*
1348 * Resetting the phy means we need to re-force TX_CLK in the
Auke Kokbc7f75f2007-09-17 12:30:59 -07001349 * Extended PHY Specific Control Register to 25MHz clock from
1350 * the reset value of 2.5MHz.
1351 */
1352 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1353 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1354 if (ret_val)
1355 return ret_val;
1356
Bruce Allanad680762008-03-28 09:15:03 -07001357 /*
1358 * In addition, we must re-enable CRS on Tx for both half and full
Auke Kokbc7f75f2007-09-17 12:30:59 -07001359 * duplex.
1360 */
1361 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1362 if (ret_val)
1363 return ret_val;
1364
1365 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1366 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1367
1368 return ret_val;
1369}
1370
1371/**
Bruce Allan0be84012009-12-02 17:03:18 +00001372 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1373 * @hw: pointer to the HW structure
1374 *
1375 * Forces the speed and duplex settings of the PHY.
1376 * This is a function pointer entry point only called by
1377 * PHY setup routines.
1378 **/
1379s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1380{
1381 struct e1000_phy_info *phy = &hw->phy;
1382 s32 ret_val;
1383 u16 data;
1384 bool link;
1385
1386 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1387 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001388 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00001389
1390 e1000e_phy_force_speed_duplex_setup(hw, &data);
1391
1392 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1393 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001394 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00001395
1396 /* Disable MDI-X support for 10/100 */
1397 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1398 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001399 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00001400
1401 data &= ~IFE_PMC_AUTO_MDIX;
1402 data &= ~IFE_PMC_FORCE_MDIX;
1403
1404 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1405 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001406 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00001407
1408 e_dbg("IFE PMC: %X\n", data);
1409
1410 udelay(1);
1411
1412 if (phy->autoneg_wait_to_complete) {
1413 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1414
1415 ret_val = e1000e_phy_has_link_generic(hw,
1416 PHY_FORCE_LIMIT,
1417 100000,
1418 &link);
1419 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001420 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00001421
1422 if (!link)
1423 e_dbg("Link taking longer than expected.\n");
1424
1425 /* Try once more */
1426 ret_val = e1000e_phy_has_link_generic(hw,
1427 PHY_FORCE_LIMIT,
1428 100000,
1429 &link);
1430 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001431 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00001432 }
1433
Bruce Allan5015e532012-02-08 02:55:56 +00001434 return 0;
Bruce Allan0be84012009-12-02 17:03:18 +00001435}
1436
1437/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001438 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1439 * @hw: pointer to the HW structure
1440 * @phy_ctrl: pointer to current value of PHY_CONTROL
1441 *
1442 * Forces speed and duplex on the PHY by doing the following: disable flow
1443 * control, force speed/duplex on the MAC, disable auto speed detection,
1444 * disable auto-negotiation, configure duplex, configure speed, configure
1445 * the collision distance, write configuration to CTRL register. The
1446 * caller must write to the PHY_CONTROL register for these settings to
1447 * take affect.
1448 **/
1449void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1450{
1451 struct e1000_mac_info *mac = &hw->mac;
1452 u32 ctrl;
1453
1454 /* Turn off flow control when forcing speed/duplex */
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08001455 hw->fc.current_mode = e1000_fc_none;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001456
1457 /* Force speed/duplex on the mac */
1458 ctrl = er32(CTRL);
1459 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1460 ctrl &= ~E1000_CTRL_SPD_SEL;
1461
1462 /* Disable Auto Speed Detection */
1463 ctrl &= ~E1000_CTRL_ASDE;
1464
1465 /* Disable autoneg on the phy */
1466 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1467
1468 /* Forcing Full or Half Duplex? */
1469 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1470 ctrl &= ~E1000_CTRL_FD;
1471 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001472 e_dbg("Half Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001473 } else {
1474 ctrl |= E1000_CTRL_FD;
1475 *phy_ctrl |= MII_CR_FULL_DUPLEX;
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001476 e_dbg("Full Duplex\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001477 }
1478
1479 /* Forcing 10mb or 100mb? */
1480 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1481 ctrl |= E1000_CTRL_SPD_100;
1482 *phy_ctrl |= MII_CR_SPEED_100;
1483 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001484 e_dbg("Forcing 100mb\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001485 } else {
1486 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1487 *phy_ctrl |= MII_CR_SPEED_10;
1488 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001489 e_dbg("Forcing 10mb\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001490 }
1491
1492 e1000e_config_collision_dist(hw);
1493
1494 ew32(CTRL, ctrl);
1495}
1496
1497/**
1498 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1499 * @hw: pointer to the HW structure
1500 * @active: boolean used to enable/disable lplu
1501 *
1502 * Success returns 0, Failure returns 1
1503 *
1504 * The low power link up (lplu) state is set to the power management level D3
1505 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1506 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1507 * is used during Dx states where the power conservation is most important.
1508 * During driver activity, SmartSpeed should be enabled so performance is
1509 * maintained.
1510 **/
1511s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1512{
1513 struct e1000_phy_info *phy = &hw->phy;
1514 s32 ret_val;
1515 u16 data;
1516
1517 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1518 if (ret_val)
1519 return ret_val;
1520
1521 if (!active) {
1522 data &= ~IGP02E1000_PM_D3_LPLU;
David Graham2d9498f2008-04-23 11:09:14 -07001523 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001524 if (ret_val)
1525 return ret_val;
Bruce Allanad680762008-03-28 09:15:03 -07001526 /*
1527 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
Auke Kokbc7f75f2007-09-17 12:30:59 -07001528 * during Dx states where the power conservation is most
1529 * important. During driver activity we should enable
Bruce Allanad680762008-03-28 09:15:03 -07001530 * SmartSpeed, so performance is maintained.
1531 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001532 if (phy->smart_speed == e1000_smart_speed_on) {
1533 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001534 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001535 if (ret_val)
1536 return ret_val;
1537
1538 data |= IGP01E1000_PSCFR_SMART_SPEED;
1539 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001540 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001541 if (ret_val)
1542 return ret_val;
1543 } else if (phy->smart_speed == e1000_smart_speed_off) {
1544 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001545 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001546 if (ret_val)
1547 return ret_val;
1548
1549 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1550 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -07001551 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001552 if (ret_val)
1553 return ret_val;
1554 }
1555 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1556 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1557 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1558 data |= IGP02E1000_PM_D3_LPLU;
1559 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1560 if (ret_val)
1561 return ret_val;
1562
1563 /* When LPLU is enabled, we should disable SmartSpeed */
1564 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1565 if (ret_val)
1566 return ret_val;
1567
1568 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1569 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1570 }
1571
1572 return ret_val;
1573}
1574
1575/**
Auke Kok489815c2008-02-21 15:11:07 -08001576 * e1000e_check_downshift - Checks whether a downshift in speed occurred
Auke Kokbc7f75f2007-09-17 12:30:59 -07001577 * @hw: pointer to the HW structure
1578 *
1579 * Success returns 0, Failure returns 1
1580 *
1581 * A downshift is detected by querying the PHY link health.
1582 **/
1583s32 e1000e_check_downshift(struct e1000_hw *hw)
1584{
1585 struct e1000_phy_info *phy = &hw->phy;
1586 s32 ret_val;
1587 u16 phy_data, offset, mask;
1588
1589 switch (phy->type) {
1590 case e1000_phy_m88:
1591 case e1000_phy_gg82563:
Bruce Allan07f025e2009-12-01 15:53:48 +00001592 case e1000_phy_bm:
Bruce Allana4f58f52009-06-02 11:29:18 +00001593 case e1000_phy_82578:
Auke Kokbc7f75f2007-09-17 12:30:59 -07001594 offset = M88E1000_PHY_SPEC_STATUS;
1595 mask = M88E1000_PSSR_DOWNSHIFT;
1596 break;
1597 case e1000_phy_igp_2:
1598 case e1000_phy_igp_3:
1599 offset = IGP01E1000_PHY_LINK_HEALTH;
1600 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1601 break;
1602 default:
1603 /* speed downshift not supported */
Bruce Allan564ea9b2009-11-20 23:26:44 +00001604 phy->speed_downgraded = false;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001605 return 0;
1606 }
1607
1608 ret_val = e1e_rphy(hw, offset, &phy_data);
1609
1610 if (!ret_val)
1611 phy->speed_downgraded = (phy_data & mask);
1612
1613 return ret_val;
1614}
1615
1616/**
1617 * e1000_check_polarity_m88 - Checks the polarity.
1618 * @hw: pointer to the HW structure
1619 *
1620 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1621 *
1622 * Polarity is determined based on the PHY specific status register.
1623 **/
Bruce Allan0be84012009-12-02 17:03:18 +00001624s32 e1000_check_polarity_m88(struct e1000_hw *hw)
Auke Kokbc7f75f2007-09-17 12:30:59 -07001625{
1626 struct e1000_phy_info *phy = &hw->phy;
1627 s32 ret_val;
1628 u16 data;
1629
1630 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1631
1632 if (!ret_val)
1633 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1634 ? e1000_rev_polarity_reversed
1635 : e1000_rev_polarity_normal;
1636
1637 return ret_val;
1638}
1639
1640/**
1641 * e1000_check_polarity_igp - Checks the polarity.
1642 * @hw: pointer to the HW structure
1643 *
1644 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1645 *
1646 * Polarity is determined based on the PHY port status register, and the
1647 * current speed (since there is no polarity at 100Mbps).
1648 **/
Bruce Allan0be84012009-12-02 17:03:18 +00001649s32 e1000_check_polarity_igp(struct e1000_hw *hw)
Auke Kokbc7f75f2007-09-17 12:30:59 -07001650{
1651 struct e1000_phy_info *phy = &hw->phy;
1652 s32 ret_val;
1653 u16 data, offset, mask;
1654
Bruce Allanad680762008-03-28 09:15:03 -07001655 /*
1656 * Polarity is determined based on the speed of
1657 * our connection.
1658 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001659 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1660 if (ret_val)
1661 return ret_val;
1662
1663 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1664 IGP01E1000_PSSR_SPEED_1000MBPS) {
1665 offset = IGP01E1000_PHY_PCS_INIT_REG;
1666 mask = IGP01E1000_PHY_POLARITY_MASK;
1667 } else {
Bruce Allanad680762008-03-28 09:15:03 -07001668 /*
1669 * This really only applies to 10Mbps since
Auke Kokbc7f75f2007-09-17 12:30:59 -07001670 * there is no polarity for 100Mbps (always 0).
1671 */
1672 offset = IGP01E1000_PHY_PORT_STATUS;
1673 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1674 }
1675
1676 ret_val = e1e_rphy(hw, offset, &data);
1677
1678 if (!ret_val)
1679 phy->cable_polarity = (data & mask)
1680 ? e1000_rev_polarity_reversed
1681 : e1000_rev_polarity_normal;
1682
1683 return ret_val;
1684}
1685
1686/**
Bruce Allan0be84012009-12-02 17:03:18 +00001687 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1688 * @hw: pointer to the HW structure
1689 *
1690 * Polarity is determined on the polarity reversal feature being enabled.
1691 **/
1692s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1693{
1694 struct e1000_phy_info *phy = &hw->phy;
1695 s32 ret_val;
1696 u16 phy_data, offset, mask;
1697
1698 /*
1699 * Polarity is determined based on the reversal feature being enabled.
1700 */
1701 if (phy->polarity_correction) {
1702 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1703 mask = IFE_PESC_POLARITY_REVERSED;
1704 } else {
1705 offset = IFE_PHY_SPECIAL_CONTROL;
1706 mask = IFE_PSC_FORCE_POLARITY;
1707 }
1708
1709 ret_val = e1e_rphy(hw, offset, &phy_data);
1710
1711 if (!ret_val)
1712 phy->cable_polarity = (phy_data & mask)
1713 ? e1000_rev_polarity_reversed
1714 : e1000_rev_polarity_normal;
1715
1716 return ret_val;
1717}
1718
1719/**
Bruce Allanad680762008-03-28 09:15:03 -07001720 * e1000_wait_autoneg - Wait for auto-neg completion
Auke Kokbc7f75f2007-09-17 12:30:59 -07001721 * @hw: pointer to the HW structure
1722 *
1723 * Waits for auto-negotiation to complete or for the auto-negotiation time
1724 * limit to expire, which ever happens first.
1725 **/
1726static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1727{
1728 s32 ret_val = 0;
1729 u16 i, phy_status;
1730
1731 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1732 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1733 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1734 if (ret_val)
1735 break;
1736 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1737 if (ret_val)
1738 break;
1739 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1740 break;
1741 msleep(100);
1742 }
1743
Bruce Allanad680762008-03-28 09:15:03 -07001744 /*
1745 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
Auke Kokbc7f75f2007-09-17 12:30:59 -07001746 * has completed.
1747 */
1748 return ret_val;
1749}
1750
1751/**
1752 * e1000e_phy_has_link_generic - Polls PHY for link
1753 * @hw: pointer to the HW structure
1754 * @iterations: number of times to poll for link
1755 * @usec_interval: delay between polling attempts
1756 * @success: pointer to whether polling was successful or not
1757 *
1758 * Polls the PHY status register for link, 'iterations' number of times.
1759 **/
1760s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1761 u32 usec_interval, bool *success)
1762{
1763 s32 ret_val = 0;
1764 u16 i, phy_status;
1765
1766 for (i = 0; i < iterations; i++) {
Bruce Allanad680762008-03-28 09:15:03 -07001767 /*
1768 * Some PHYs require the PHY_STATUS register to be read
Auke Kokbc7f75f2007-09-17 12:30:59 -07001769 * twice due to the link bit being sticky. No harm doing
1770 * it across the board.
1771 */
1772 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1773 if (ret_val)
Bruce Allan906e8d92009-07-01 13:28:50 +00001774 /*
1775 * If the first read fails, another entity may have
1776 * ownership of the resources, wait and try again to
1777 * see if they have relinquished the resources yet.
1778 */
1779 udelay(usec_interval);
Auke Kokbc7f75f2007-09-17 12:30:59 -07001780 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1781 if (ret_val)
1782 break;
1783 if (phy_status & MII_SR_LINK_STATUS)
1784 break;
1785 if (usec_interval >= 1000)
1786 mdelay(usec_interval/1000);
1787 else
1788 udelay(usec_interval);
1789 }
1790
1791 *success = (i < iterations);
1792
1793 return ret_val;
1794}
1795
1796/**
1797 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1798 * @hw: pointer to the HW structure
1799 *
1800 * Reads the PHY specific status register to retrieve the cable length
1801 * information. The cable length is determined by averaging the minimum and
1802 * maximum values to get the "average" cable length. The m88 PHY has four
1803 * possible cable length values, which are:
1804 * Register Value Cable Length
1805 * 0 < 50 meters
1806 * 1 50 - 80 meters
1807 * 2 80 - 110 meters
1808 * 3 110 - 140 meters
1809 * 4 > 140 meters
1810 **/
1811s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1812{
1813 struct e1000_phy_info *phy = &hw->phy;
1814 s32 ret_val;
1815 u16 phy_data, index;
1816
1817 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1818 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00001819 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001820
1821 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
Bruce Allaneb656d42009-12-01 15:47:02 +00001822 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
Bruce Allan5015e532012-02-08 02:55:56 +00001823
1824 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1825 return -E1000_ERR_PHY;
Bruce Allaneb656d42009-12-01 15:47:02 +00001826
Auke Kokbc7f75f2007-09-17 12:30:59 -07001827 phy->min_cable_length = e1000_m88_cable_length_table[index];
Bruce Allaneb656d42009-12-01 15:47:02 +00001828 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
Auke Kokbc7f75f2007-09-17 12:30:59 -07001829
1830 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1831
Bruce Allan5015e532012-02-08 02:55:56 +00001832 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001833}
1834
1835/**
1836 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1837 * @hw: pointer to the HW structure
1838 *
1839 * The automatic gain control (agc) normalizes the amplitude of the
1840 * received signal, adjusting for the attenuation produced by the
Auke Kok489815c2008-02-21 15:11:07 -08001841 * cable. By reading the AGC registers, which represent the
Bruce Allan5ff5b662009-12-01 15:51:11 +00001842 * combination of coarse and fine gain value, the value can be put
Auke Kokbc7f75f2007-09-17 12:30:59 -07001843 * into a lookup table to obtain the approximate cable length
1844 * for each channel.
1845 **/
1846s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1847{
1848 struct e1000_phy_info *phy = &hw->phy;
1849 s32 ret_val;
1850 u16 phy_data, i, agc_value = 0;
1851 u16 cur_agc_index, max_agc_index = 0;
1852 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
Jeff Kirsher66744502010-12-01 19:59:50 +00001853 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1854 IGP02E1000_PHY_AGC_A,
1855 IGP02E1000_PHY_AGC_B,
1856 IGP02E1000_PHY_AGC_C,
1857 IGP02E1000_PHY_AGC_D
1858 };
Auke Kokbc7f75f2007-09-17 12:30:59 -07001859
1860 /* Read the AGC registers for all channels */
1861 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1862 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1863 if (ret_val)
1864 return ret_val;
1865
Bruce Allanad680762008-03-28 09:15:03 -07001866 /*
1867 * Getting bits 15:9, which represent the combination of
Bruce Allan5ff5b662009-12-01 15:51:11 +00001868 * coarse and fine gain values. The result is a number
Auke Kokbc7f75f2007-09-17 12:30:59 -07001869 * that can be put into the lookup table to obtain the
Bruce Allanad680762008-03-28 09:15:03 -07001870 * approximate cable length.
1871 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001872 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1873 IGP02E1000_AGC_LENGTH_MASK;
1874
1875 /* Array index bound check. */
1876 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1877 (cur_agc_index == 0))
1878 return -E1000_ERR_PHY;
1879
1880 /* Remove min & max AGC values from calculation. */
1881 if (e1000_igp_2_cable_length_table[min_agc_index] >
1882 e1000_igp_2_cable_length_table[cur_agc_index])
1883 min_agc_index = cur_agc_index;
1884 if (e1000_igp_2_cable_length_table[max_agc_index] <
1885 e1000_igp_2_cable_length_table[cur_agc_index])
1886 max_agc_index = cur_agc_index;
1887
1888 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1889 }
1890
1891 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1892 e1000_igp_2_cable_length_table[max_agc_index]);
1893 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1894
1895 /* Calculate cable length with the error range of +/- 10 meters. */
1896 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1897 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1898 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1899
1900 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1901
Bruce Allan82607252012-02-08 02:55:09 +00001902 return 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001903}
1904
1905/**
1906 * e1000e_get_phy_info_m88 - Retrieve PHY information
1907 * @hw: pointer to the HW structure
1908 *
1909 * Valid for only copper links. Read the PHY status register (sticky read)
1910 * to verify that link is up. Read the PHY special control register to
1911 * determine the polarity and 10base-T extended distance. Read the PHY
1912 * special status register to determine MDI/MDIx and current speed. If
1913 * speed is 1000, then determine cable length, local and remote receiver.
1914 **/
1915s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1916{
1917 struct e1000_phy_info *phy = &hw->phy;
1918 s32 ret_val;
1919 u16 phy_data;
1920 bool link;
1921
Bruce Allan0be84012009-12-02 17:03:18 +00001922 if (phy->media_type != e1000_media_type_copper) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001923 e_dbg("Phy info is only valid for copper media\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001924 return -E1000_ERR_CONFIG;
1925 }
1926
1927 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1928 if (ret_val)
1929 return ret_val;
1930
1931 if (!link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00001932 e_dbg("Phy info is only valid if link is up\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001933 return -E1000_ERR_CONFIG;
1934 }
1935
1936 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1937 if (ret_val)
1938 return ret_val;
1939
1940 phy->polarity_correction = (phy_data &
1941 M88E1000_PSCR_POLARITY_REVERSAL);
1942
1943 ret_val = e1000_check_polarity_m88(hw);
1944 if (ret_val)
1945 return ret_val;
1946
1947 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1948 if (ret_val)
1949 return ret_val;
1950
1951 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1952
1953 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1954 ret_val = e1000_get_cable_length(hw);
1955 if (ret_val)
1956 return ret_val;
1957
1958 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1959 if (ret_val)
1960 return ret_val;
1961
1962 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1963 ? e1000_1000t_rx_status_ok
1964 : e1000_1000t_rx_status_not_ok;
1965
1966 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1967 ? e1000_1000t_rx_status_ok
1968 : e1000_1000t_rx_status_not_ok;
1969 } else {
1970 /* Set values to "undefined" */
1971 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1972 phy->local_rx = e1000_1000t_rx_status_undefined;
1973 phy->remote_rx = e1000_1000t_rx_status_undefined;
1974 }
1975
1976 return ret_val;
1977}
1978
1979/**
1980 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1981 * @hw: pointer to the HW structure
1982 *
1983 * Read PHY status to determine if link is up. If link is up, then
1984 * set/determine 10base-T extended distance and polarity correction. Read
1985 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1986 * determine on the cable length, local and remote receiver.
1987 **/
1988s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1989{
1990 struct e1000_phy_info *phy = &hw->phy;
1991 s32 ret_val;
1992 u16 data;
1993 bool link;
1994
1995 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1996 if (ret_val)
1997 return ret_val;
1998
1999 if (!link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00002000 e_dbg("Phy info is only valid if link is up\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07002001 return -E1000_ERR_CONFIG;
2002 }
2003
Bruce Allan564ea9b2009-11-20 23:26:44 +00002004 phy->polarity_correction = true;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002005
2006 ret_val = e1000_check_polarity_igp(hw);
2007 if (ret_val)
2008 return ret_val;
2009
2010 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2011 if (ret_val)
2012 return ret_val;
2013
2014 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2015
2016 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2017 IGP01E1000_PSSR_SPEED_1000MBPS) {
2018 ret_val = e1000_get_cable_length(hw);
2019 if (ret_val)
2020 return ret_val;
2021
2022 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2023 if (ret_val)
2024 return ret_val;
2025
2026 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2027 ? e1000_1000t_rx_status_ok
2028 : e1000_1000t_rx_status_not_ok;
2029
2030 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2031 ? e1000_1000t_rx_status_ok
2032 : e1000_1000t_rx_status_not_ok;
2033 } else {
2034 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2035 phy->local_rx = e1000_1000t_rx_status_undefined;
2036 phy->remote_rx = e1000_1000t_rx_status_undefined;
2037 }
2038
2039 return ret_val;
2040}
2041
2042/**
Bruce Allan0be84012009-12-02 17:03:18 +00002043 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2044 * @hw: pointer to the HW structure
2045 *
2046 * Populates "phy" structure with various feature states.
2047 **/
2048s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2049{
2050 struct e1000_phy_info *phy = &hw->phy;
2051 s32 ret_val;
2052 u16 data;
2053 bool link;
2054
2055 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2056 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00002057 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00002058
2059 if (!link) {
2060 e_dbg("Phy info is only valid if link is up\n");
Bruce Allan5015e532012-02-08 02:55:56 +00002061 return -E1000_ERR_CONFIG;
Bruce Allan0be84012009-12-02 17:03:18 +00002062 }
2063
2064 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2065 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00002066 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00002067 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2068 ? false : true;
2069
2070 if (phy->polarity_correction) {
2071 ret_val = e1000_check_polarity_ife(hw);
2072 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00002073 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00002074 } else {
2075 /* Polarity is forced */
2076 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2077 ? e1000_rev_polarity_reversed
2078 : e1000_rev_polarity_normal;
2079 }
2080
2081 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2082 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00002083 return ret_val;
Bruce Allan0be84012009-12-02 17:03:18 +00002084
2085 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2086
2087 /* The following parameters are undefined for 10/100 operation. */
2088 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2089 phy->local_rx = e1000_1000t_rx_status_undefined;
2090 phy->remote_rx = e1000_1000t_rx_status_undefined;
2091
Bruce Allan5015e532012-02-08 02:55:56 +00002092 return 0;
Bruce Allan0be84012009-12-02 17:03:18 +00002093}
2094
2095/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07002096 * e1000e_phy_sw_reset - PHY software reset
2097 * @hw: pointer to the HW structure
2098 *
2099 * Does a software reset of the PHY by reading the PHY control register and
2100 * setting/write the control register reset bit to the PHY.
2101 **/
2102s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2103{
2104 s32 ret_val;
2105 u16 phy_ctrl;
2106
2107 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2108 if (ret_val)
2109 return ret_val;
2110
2111 phy_ctrl |= MII_CR_RESET;
2112 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2113 if (ret_val)
2114 return ret_val;
2115
2116 udelay(1);
2117
2118 return ret_val;
2119}
2120
2121/**
2122 * e1000e_phy_hw_reset_generic - PHY hardware reset
2123 * @hw: pointer to the HW structure
2124 *
2125 * Verify the reset block is not blocking us from resetting. Acquire
2126 * semaphore (if necessary) and read/set/write the device control reset
2127 * bit in the PHY. Wait the appropriate delay time for the device to
Auke Kok489815c2008-02-21 15:11:07 -08002128 * reset and release the semaphore (if necessary).
Auke Kokbc7f75f2007-09-17 12:30:59 -07002129 **/
2130s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2131{
2132 struct e1000_phy_info *phy = &hw->phy;
2133 s32 ret_val;
2134 u32 ctrl;
2135
2136 ret_val = e1000_check_reset_block(hw);
2137 if (ret_val)
2138 return 0;
2139
Bruce Allan94d81862009-11-20 23:25:26 +00002140 ret_val = phy->ops.acquire(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002141 if (ret_val)
2142 return ret_val;
2143
2144 ctrl = er32(CTRL);
2145 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2146 e1e_flush();
2147
2148 udelay(phy->reset_delay_us);
2149
2150 ew32(CTRL, ctrl);
2151 e1e_flush();
2152
2153 udelay(150);
2154
Bruce Allan94d81862009-11-20 23:25:26 +00002155 phy->ops.release(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002156
2157 return e1000_get_phy_cfg_done(hw);
2158}
2159
2160/**
2161 * e1000e_get_cfg_done - Generic configuration done
2162 * @hw: pointer to the HW structure
2163 *
2164 * Generic function to wait 10 milli-seconds for configuration to complete
2165 * and return success.
2166 **/
2167s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2168{
2169 mdelay(10);
2170 return 0;
2171}
2172
Bruce Allanf4187b52008-08-26 18:36:50 -07002173/**
2174 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2175 * @hw: pointer to the HW structure
2176 *
2177 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2178 **/
2179s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2180{
Bruce Allan3bb99fe2009-11-20 23:25:07 +00002181 e_dbg("Running IGP 3 PHY init script\n");
Bruce Allanf4187b52008-08-26 18:36:50 -07002182
2183 /* PHY init IGP 3 */
2184 /* Enable rise/fall, 10-mode work in class-A */
2185 e1e_wphy(hw, 0x2F5B, 0x9018);
2186 /* Remove all caps from Replica path filter */
2187 e1e_wphy(hw, 0x2F52, 0x0000);
2188 /* Bias trimming for ADC, AFE and Driver (Default) */
2189 e1e_wphy(hw, 0x2FB1, 0x8B24);
2190 /* Increase Hybrid poly bias */
2191 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2192 /* Add 4% to Tx amplitude in Gig mode */
2193 e1e_wphy(hw, 0x2010, 0x10B0);
2194 /* Disable trimming (TTT) */
2195 e1e_wphy(hw, 0x2011, 0x0000);
2196 /* Poly DC correction to 94.6% + 2% for all channels */
2197 e1e_wphy(hw, 0x20DD, 0x249A);
2198 /* ABS DC correction to 95.9% */
2199 e1e_wphy(hw, 0x20DE, 0x00D3);
2200 /* BG temp curve trim */
2201 e1e_wphy(hw, 0x28B4, 0x04CE);
2202 /* Increasing ADC OPAMP stage 1 currents to max */
2203 e1e_wphy(hw, 0x2F70, 0x29E4);
2204 /* Force 1000 ( required for enabling PHY regs configuration) */
2205 e1e_wphy(hw, 0x0000, 0x0140);
2206 /* Set upd_freq to 6 */
2207 e1e_wphy(hw, 0x1F30, 0x1606);
2208 /* Disable NPDFE */
2209 e1e_wphy(hw, 0x1F31, 0xB814);
2210 /* Disable adaptive fixed FFE (Default) */
2211 e1e_wphy(hw, 0x1F35, 0x002A);
2212 /* Enable FFE hysteresis */
2213 e1e_wphy(hw, 0x1F3E, 0x0067);
2214 /* Fixed FFE for short cable lengths */
2215 e1e_wphy(hw, 0x1F54, 0x0065);
2216 /* Fixed FFE for medium cable lengths */
2217 e1e_wphy(hw, 0x1F55, 0x002A);
2218 /* Fixed FFE for long cable lengths */
2219 e1e_wphy(hw, 0x1F56, 0x002A);
2220 /* Enable Adaptive Clip Threshold */
2221 e1e_wphy(hw, 0x1F72, 0x3FB0);
2222 /* AHT reset limit to 1 */
2223 e1e_wphy(hw, 0x1F76, 0xC0FF);
2224 /* Set AHT master delay to 127 msec */
2225 e1e_wphy(hw, 0x1F77, 0x1DEC);
2226 /* Set scan bits for AHT */
2227 e1e_wphy(hw, 0x1F78, 0xF9EF);
2228 /* Set AHT Preset bits */
2229 e1e_wphy(hw, 0x1F79, 0x0210);
2230 /* Change integ_factor of channel A to 3 */
2231 e1e_wphy(hw, 0x1895, 0x0003);
2232 /* Change prop_factor of channels BCD to 8 */
2233 e1e_wphy(hw, 0x1796, 0x0008);
2234 /* Change cg_icount + enable integbp for channels BCD */
2235 e1e_wphy(hw, 0x1798, 0xD008);
2236 /*
2237 * Change cg_icount + enable integbp + change prop_factor_master
2238 * to 8 for channel A
2239 */
2240 e1e_wphy(hw, 0x1898, 0xD918);
2241 /* Disable AHT in Slave mode on channel A */
2242 e1e_wphy(hw, 0x187A, 0x0800);
2243 /*
2244 * Enable LPLU and disable AN to 1000 in non-D0a states,
2245 * Enable SPD+B2B
2246 */
2247 e1e_wphy(hw, 0x0019, 0x008D);
2248 /* Enable restart AN on an1000_dis change */
2249 e1e_wphy(hw, 0x001B, 0x2080);
2250 /* Enable wh_fifo read clock in 10/100 modes */
2251 e1e_wphy(hw, 0x0014, 0x0045);
2252 /* Restart AN, Speed selection is 1000 */
2253 e1e_wphy(hw, 0x0000, 0x1340);
2254
2255 return 0;
2256}
2257
Auke Kokbc7f75f2007-09-17 12:30:59 -07002258/* Internal function pointers */
2259
2260/**
2261 * e1000_get_phy_cfg_done - Generic PHY configuration done
2262 * @hw: pointer to the HW structure
2263 *
2264 * Return success if silicon family did not implement a family specific
2265 * get_cfg_done function.
2266 **/
2267static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2268{
2269 if (hw->phy.ops.get_cfg_done)
2270 return hw->phy.ops.get_cfg_done(hw);
2271
2272 return 0;
2273}
2274
2275/**
2276 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2277 * @hw: pointer to the HW structure
2278 *
2279 * When the silicon family has not implemented a forced speed/duplex
2280 * function for the PHY, simply return 0.
2281 **/
2282static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2283{
2284 if (hw->phy.ops.force_speed_duplex)
2285 return hw->phy.ops.force_speed_duplex(hw);
2286
2287 return 0;
2288}
2289
2290/**
2291 * e1000e_get_phy_type_from_id - Get PHY type from id
2292 * @phy_id: phy_id read from the phy
2293 *
2294 * Returns the phy type from the id.
2295 **/
2296enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2297{
2298 enum e1000_phy_type phy_type = e1000_phy_unknown;
2299
2300 switch (phy_id) {
2301 case M88E1000_I_PHY_ID:
2302 case M88E1000_E_PHY_ID:
2303 case M88E1111_I_PHY_ID:
2304 case M88E1011_I_PHY_ID:
2305 phy_type = e1000_phy_m88;
2306 break;
2307 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2308 phy_type = e1000_phy_igp_2;
2309 break;
2310 case GG82563_E_PHY_ID:
2311 phy_type = e1000_phy_gg82563;
2312 break;
2313 case IGP03E1000_E_PHY_ID:
2314 phy_type = e1000_phy_igp_3;
2315 break;
2316 case IFE_E_PHY_ID:
2317 case IFE_PLUS_E_PHY_ID:
2318 case IFE_C_E_PHY_ID:
2319 phy_type = e1000_phy_ife;
2320 break;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002321 case BME1000_E_PHY_ID:
2322 case BME1000_E_PHY_ID_R2:
2323 phy_type = e1000_phy_bm;
2324 break;
Bruce Allana4f58f52009-06-02 11:29:18 +00002325 case I82578_E_PHY_ID:
2326 phy_type = e1000_phy_82578;
2327 break;
2328 case I82577_E_PHY_ID:
2329 phy_type = e1000_phy_82577;
2330 break;
Bruce Alland3738bb2010-06-16 13:27:28 +00002331 case I82579_E_PHY_ID:
2332 phy_type = e1000_phy_82579;
2333 break;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002334 default:
2335 phy_type = e1000_phy_unknown;
2336 break;
2337 }
2338 return phy_type;
2339}
2340
2341/**
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002342 * e1000e_determine_phy_address - Determines PHY address.
2343 * @hw: pointer to the HW structure
2344 *
2345 * This uses a trial and error method to loop through possible PHY
2346 * addresses. It tests each by reading the PHY ID registers and
2347 * checking for a match.
2348 **/
2349s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2350{
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002351 u32 phy_addr = 0;
2352 u32 i;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002353 enum e1000_phy_type phy_type = e1000_phy_unknown;
2354
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002355 hw->phy.id = phy_type;
2356
2357 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2358 hw->phy.addr = phy_addr;
2359 i = 0;
2360
2361 do {
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002362 e1000e_get_phy_id(hw);
2363 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2364
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002365 /*
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002366 * If phy_type is valid, break - we found our
2367 * PHY address
2368 */
Bruce Allan5015e532012-02-08 02:55:56 +00002369 if (phy_type != e1000_phy_unknown)
2370 return 0;
2371
Bruce Allan1bba4382011-03-19 00:27:20 +00002372 usleep_range(1000, 2000);
Bruce Allan5eb6f3c2009-12-02 17:02:43 +00002373 i++;
2374 } while (i < 10);
2375 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002376
Bruce Allan5015e532012-02-08 02:55:56 +00002377 return -E1000_ERR_PHY_TYPE;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002378}
2379
2380/**
2381 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2382 * @page: page to access
2383 *
2384 * Returns the phy address for the page requested.
2385 **/
2386static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2387{
2388 u32 phy_addr = 2;
2389
2390 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2391 phy_addr = 1;
2392
2393 return phy_addr;
2394}
2395
2396/**
2397 * e1000e_write_phy_reg_bm - Write BM PHY register
2398 * @hw: pointer to the HW structure
2399 * @offset: register offset to write to
2400 * @data: data to write at register offset
2401 *
2402 * Acquires semaphore, if necessary, then writes the data to PHY register
2403 * at the offset. Release any acquired semaphores before exiting.
2404 **/
2405s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2406{
2407 s32 ret_val;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002408 u32 page = offset >> IGP_PAGE_SHIFT;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002409
Bruce Allan94d81862009-11-20 23:25:26 +00002410 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002411 if (ret_val)
2412 return ret_val;
2413
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002414 /* Page 800 works differently than the rest so it has its own func */
2415 if (page == BM_WUC_PAGE) {
2416 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002417 false, false);
Bruce Allan75ce1532012-02-08 02:54:48 +00002418 goto release;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002419 }
2420
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002421 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2422
2423 if (offset > MAX_PHY_MULTI_PAGE_REG) {
Bruce Allan90da0662011-01-06 07:02:53 +00002424 u32 page_shift, page_select;
2425
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002426 /*
2427 * Page select is register 31 for phy address 1 and 22 for
2428 * phy address 2 and 3. Page select is shifted only for
2429 * phy address 1.
2430 */
2431 if (hw->phy.addr == 1) {
2432 page_shift = IGP_PAGE_SHIFT;
2433 page_select = IGP01E1000_PHY_PAGE_SELECT;
2434 } else {
2435 page_shift = 0;
2436 page_select = BM_PHY_PAGE_SELECT;
2437 }
2438
2439 /* Page is shifted left, PHY expects (page x 32) */
2440 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2441 (page << page_shift));
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002442 if (ret_val)
Bruce Allan75ce1532012-02-08 02:54:48 +00002443 goto release;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002444 }
2445
2446 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2447 data);
2448
Bruce Allan75ce1532012-02-08 02:54:48 +00002449release:
Bruce Allan94d81862009-11-20 23:25:26 +00002450 hw->phy.ops.release(hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002451 return ret_val;
2452}
2453
2454/**
2455 * e1000e_read_phy_reg_bm - Read BM PHY register
2456 * @hw: pointer to the HW structure
2457 * @offset: register offset to be read
2458 * @data: pointer to the read data
2459 *
2460 * Acquires semaphore, if necessary, then reads the PHY register at offset
2461 * and storing the retrieved information in data. Release any acquired
2462 * semaphores before exiting.
2463 **/
2464s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2465{
2466 s32 ret_val;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002467 u32 page = offset >> IGP_PAGE_SHIFT;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002468
Bruce Allan94d81862009-11-20 23:25:26 +00002469 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002470 if (ret_val)
2471 return ret_val;
2472
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002473 /* Page 800 works differently than the rest so it has its own func */
2474 if (page == BM_WUC_PAGE) {
2475 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002476 true, false);
Bruce Allan75ce1532012-02-08 02:54:48 +00002477 goto release;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002478 }
2479
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002480 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2481
2482 if (offset > MAX_PHY_MULTI_PAGE_REG) {
Bruce Allan90da0662011-01-06 07:02:53 +00002483 u32 page_shift, page_select;
2484
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002485 /*
2486 * Page select is register 31 for phy address 1 and 22 for
2487 * phy address 2 and 3. Page select is shifted only for
2488 * phy address 1.
2489 */
2490 if (hw->phy.addr == 1) {
2491 page_shift = IGP_PAGE_SHIFT;
2492 page_select = IGP01E1000_PHY_PAGE_SELECT;
2493 } else {
2494 page_shift = 0;
2495 page_select = BM_PHY_PAGE_SELECT;
2496 }
2497
2498 /* Page is shifted left, PHY expects (page x 32) */
2499 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2500 (page << page_shift));
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002501 if (ret_val)
Bruce Allan75ce1532012-02-08 02:54:48 +00002502 goto release;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002503 }
2504
2505 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2506 data);
Bruce Allan75ce1532012-02-08 02:54:48 +00002507release:
Bruce Allan94d81862009-11-20 23:25:26 +00002508 hw->phy.ops.release(hw);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002509 return ret_val;
2510}
2511
2512/**
Bruce Allan4662e822008-08-26 18:37:06 -07002513 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2514 * @hw: pointer to the HW structure
2515 * @offset: register offset to be read
2516 * @data: pointer to the read data
2517 *
2518 * Acquires semaphore, if necessary, then reads the PHY register at offset
2519 * and storing the retrieved information in data. Release any acquired
2520 * semaphores before exiting.
2521 **/
2522s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2523{
2524 s32 ret_val;
2525 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2526
Bruce Allan94d81862009-11-20 23:25:26 +00002527 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002528 if (ret_val)
2529 return ret_val;
2530
Bruce Allan4662e822008-08-26 18:37:06 -07002531 /* Page 800 works differently than the rest so it has its own func */
2532 if (page == BM_WUC_PAGE) {
2533 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002534 true, false);
Bruce Allan75ce1532012-02-08 02:54:48 +00002535 goto release;
Bruce Allan4662e822008-08-26 18:37:06 -07002536 }
2537
Bruce Allan4662e822008-08-26 18:37:06 -07002538 hw->phy.addr = 1;
2539
2540 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2541
2542 /* Page is shifted left, PHY expects (page x 32) */
2543 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2544 page);
2545
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002546 if (ret_val)
Bruce Allan75ce1532012-02-08 02:54:48 +00002547 goto release;
Bruce Allan4662e822008-08-26 18:37:06 -07002548 }
2549
2550 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2551 data);
Bruce Allan75ce1532012-02-08 02:54:48 +00002552release:
Bruce Allan94d81862009-11-20 23:25:26 +00002553 hw->phy.ops.release(hw);
Bruce Allan4662e822008-08-26 18:37:06 -07002554 return ret_val;
2555}
2556
2557/**
2558 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2559 * @hw: pointer to the HW structure
2560 * @offset: register offset to write to
2561 * @data: data to write at register offset
2562 *
2563 * Acquires semaphore, if necessary, then writes the data to PHY register
2564 * at the offset. Release any acquired semaphores before exiting.
2565 **/
2566s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2567{
2568 s32 ret_val;
2569 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2570
Bruce Allan94d81862009-11-20 23:25:26 +00002571 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002572 if (ret_val)
2573 return ret_val;
2574
Bruce Allan4662e822008-08-26 18:37:06 -07002575 /* Page 800 works differently than the rest so it has its own func */
2576 if (page == BM_WUC_PAGE) {
2577 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002578 false, false);
Bruce Allan75ce1532012-02-08 02:54:48 +00002579 goto release;
Bruce Allan4662e822008-08-26 18:37:06 -07002580 }
2581
Bruce Allan4662e822008-08-26 18:37:06 -07002582 hw->phy.addr = 1;
2583
2584 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2585 /* Page is shifted left, PHY expects (page x 32) */
2586 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2587 page);
2588
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002589 if (ret_val)
Bruce Allan75ce1532012-02-08 02:54:48 +00002590 goto release;
Bruce Allan4662e822008-08-26 18:37:06 -07002591 }
2592
2593 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2594 data);
2595
Bruce Allan75ce1532012-02-08 02:54:48 +00002596release:
Bruce Allan94d81862009-11-20 23:25:26 +00002597 hw->phy.ops.release(hw);
Bruce Allan4662e822008-08-26 18:37:06 -07002598 return ret_val;
2599}
2600
2601/**
Bruce Allan2b6b1682011-05-13 07:20:09 +00002602 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2603 * @hw: pointer to the HW structure
2604 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2605 *
2606 * Assumes semaphore already acquired and phy_reg points to a valid memory
2607 * address to store contents of the BM_WUC_ENABLE_REG register.
2608 **/
2609s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2610{
2611 s32 ret_val;
2612 u16 temp;
2613
2614 /* All page select, port ctrl and wakeup registers use phy address 1 */
2615 hw->phy.addr = 1;
2616
2617 /* Select Port Control Registers page */
2618 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2619 if (ret_val) {
2620 e_dbg("Could not set Port Control page\n");
Bruce Allan5015e532012-02-08 02:55:56 +00002621 return ret_val;
Bruce Allan2b6b1682011-05-13 07:20:09 +00002622 }
2623
2624 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2625 if (ret_val) {
2626 e_dbg("Could not read PHY register %d.%d\n",
2627 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
Bruce Allan5015e532012-02-08 02:55:56 +00002628 return ret_val;
Bruce Allan2b6b1682011-05-13 07:20:09 +00002629 }
2630
2631 /*
2632 * Enable both PHY wakeup mode and Wakeup register page writes.
2633 * Prevent a power state change by disabling ME and Host PHY wakeup.
2634 */
2635 temp = *phy_reg;
2636 temp |= BM_WUC_ENABLE_BIT;
2637 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2638
2639 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2640 if (ret_val) {
2641 e_dbg("Could not write PHY register %d.%d\n",
2642 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
Bruce Allan5015e532012-02-08 02:55:56 +00002643 return ret_val;
Bruce Allan2b6b1682011-05-13 07:20:09 +00002644 }
2645
Bruce Allan5015e532012-02-08 02:55:56 +00002646 /*
2647 * Select Host Wakeup Registers page - caller now able to write
2648 * registers on the Wakeup registers page
2649 */
2650 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
Bruce Allan2b6b1682011-05-13 07:20:09 +00002651}
2652
2653/**
2654 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2655 * @hw: pointer to the HW structure
2656 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2657 *
2658 * Restore BM_WUC_ENABLE_REG to its original value.
2659 *
2660 * Assumes semaphore already acquired and *phy_reg is the contents of the
2661 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2662 * caller.
2663 **/
2664s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2665{
2666 s32 ret_val = 0;
2667
2668 /* Select Port Control Registers page */
2669 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2670 if (ret_val) {
2671 e_dbg("Could not set Port Control page\n");
Bruce Allan5015e532012-02-08 02:55:56 +00002672 return ret_val;
Bruce Allan2b6b1682011-05-13 07:20:09 +00002673 }
2674
2675 /* Restore 769.17 to its original value */
2676 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2677 if (ret_val)
2678 e_dbg("Could not restore PHY register %d.%d\n",
2679 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
Bruce Allan5015e532012-02-08 02:55:56 +00002680
Bruce Allan2b6b1682011-05-13 07:20:09 +00002681 return ret_val;
2682}
2683
2684/**
2685 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002686 * @hw: pointer to the HW structure
2687 * @offset: register offset to be read or written
2688 * @data: pointer to the data to read or write
2689 * @read: determines if operation is read or write
Bruce Allan2b6b1682011-05-13 07:20:09 +00002690 * @page_set: BM_WUC_PAGE already set and access enabled
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002691 *
Bruce Allan2b6b1682011-05-13 07:20:09 +00002692 * Read the PHY register at offset and store the retrieved information in
2693 * data, or write data to PHY register at offset. Note the procedure to
2694 * access the PHY wakeup registers is different than reading the other PHY
2695 * registers. It works as such:
2696 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002697 * 2) Set page to 800 for host (801 if we were manageability)
2698 * 3) Write the address using the address opcode (0x11)
2699 * 4) Read or write the data using the data opcode (0x12)
Bruce Allan2b6b1682011-05-13 07:20:09 +00002700 * 5) Restore 769.17.2 to its original value
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002701 *
Bruce Allan2b6b1682011-05-13 07:20:09 +00002702 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2703 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2704 *
2705 * Assumes semaphore is already acquired. When page_set==true, assumes
2706 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2707 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002708 **/
2709static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002710 u16 *data, bool read, bool page_set)
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002711{
2712 s32 ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00002713 u16 reg = BM_PHY_REG_NUM(offset);
Bruce Allan2b6b1682011-05-13 07:20:09 +00002714 u16 page = BM_PHY_REG_PAGE(offset);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002715 u16 phy_reg = 0;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002716
Bruce Allan2b6b1682011-05-13 07:20:09 +00002717 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
Bruce Allana4f58f52009-06-02 11:29:18 +00002718 if ((hw->mac.type == e1000_pchlan) &&
Bruce Allan2b6b1682011-05-13 07:20:09 +00002719 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2720 e_dbg("Attempting to access page %d while gig enabled.\n",
2721 page);
Bruce Allana4f58f52009-06-02 11:29:18 +00002722
Bruce Allan2b6b1682011-05-13 07:20:09 +00002723 if (!page_set) {
2724 /* Enable access to PHY wakeup registers */
2725 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2726 if (ret_val) {
2727 e_dbg("Could not enable PHY wakeup reg access\n");
Bruce Allan5015e532012-02-08 02:55:56 +00002728 return ret_val;
Bruce Allan2b6b1682011-05-13 07:20:09 +00002729 }
Bruce Allan9b71b412009-12-01 15:53:07 +00002730 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002731
Bruce Allan2b6b1682011-05-13 07:20:09 +00002732 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002733
Bruce Allan2b6b1682011-05-13 07:20:09 +00002734 /* Write the Wakeup register page offset value using opcode 0x11 */
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002735 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
Bruce Allan9b71b412009-12-01 15:53:07 +00002736 if (ret_val) {
Bruce Allan2b6b1682011-05-13 07:20:09 +00002737 e_dbg("Could not write address opcode to page %d\n", page);
Bruce Allan5015e532012-02-08 02:55:56 +00002738 return ret_val;
Bruce Allan9b71b412009-12-01 15:53:07 +00002739 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002740
2741 if (read) {
Bruce Allan2b6b1682011-05-13 07:20:09 +00002742 /* Read the Wakeup register page value using opcode 0x12 */
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002743 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2744 data);
2745 } else {
Bruce Allan2b6b1682011-05-13 07:20:09 +00002746 /* Write the Wakeup register page value using opcode 0x12 */
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002747 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2748 *data);
2749 }
2750
Bruce Allan9b71b412009-12-01 15:53:07 +00002751 if (ret_val) {
Bruce Allan2b6b1682011-05-13 07:20:09 +00002752 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
Bruce Allan5015e532012-02-08 02:55:56 +00002753 return ret_val;
Bruce Allan9b71b412009-12-01 15:53:07 +00002754 }
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002755
Bruce Allan2b6b1682011-05-13 07:20:09 +00002756 if (!page_set)
2757 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002758
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002759 return ret_val;
2760}
2761
2762/**
Bruce Allan17f208d2009-12-01 15:47:22 +00002763 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2764 * @hw: pointer to the HW structure
2765 *
2766 * In the case of a PHY power down to save power, or to turn off link during a
2767 * driver unload, or wake on lan is not enabled, restore the link to previous
2768 * settings.
2769 **/
2770void e1000_power_up_phy_copper(struct e1000_hw *hw)
2771{
2772 u16 mii_reg = 0;
2773
2774 /* The PHY will retain its settings across a power down/up cycle */
2775 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2776 mii_reg &= ~MII_CR_POWER_DOWN;
2777 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2778}
2779
2780/**
2781 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2782 * @hw: pointer to the HW structure
2783 *
2784 * In the case of a PHY power down to save power, or to turn off link during a
2785 * driver unload, or wake on lan is not enabled, restore the link to previous
2786 * settings.
2787 **/
2788void e1000_power_down_phy_copper(struct e1000_hw *hw)
2789{
2790 u16 mii_reg = 0;
2791
2792 /* The PHY will retain its settings across a power down/up cycle */
2793 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2794 mii_reg |= MII_CR_POWER_DOWN;
2795 e1e_wphy(hw, PHY_CONTROL, mii_reg);
Bruce Allan1bba4382011-03-19 00:27:20 +00002796 usleep_range(1000, 2000);
Bruce Allan17f208d2009-12-01 15:47:22 +00002797}
2798
2799/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07002800 * e1000e_commit_phy - Soft PHY reset
2801 * @hw: pointer to the HW structure
2802 *
2803 * Performs a soft PHY reset on those that apply. This is a function pointer
2804 * entry point called by drivers.
2805 **/
2806s32 e1000e_commit_phy(struct e1000_hw *hw)
2807{
Bruce Allan94d81862009-11-20 23:25:26 +00002808 if (hw->phy.ops.commit)
2809 return hw->phy.ops.commit(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002810
2811 return 0;
2812}
2813
2814/**
2815 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2816 * @hw: pointer to the HW structure
2817 * @active: boolean used to enable/disable lplu
2818 *
2819 * Success returns 0, Failure returns 1
2820 *
2821 * The low power link up (lplu) state is set to the power management level D0
2822 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2823 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2824 * is used during Dx states where the power conservation is most important.
2825 * During driver activity, SmartSpeed should be enabled so performance is
2826 * maintained. This is a function pointer entry point called by drivers.
2827 **/
2828static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2829{
2830 if (hw->phy.ops.set_d0_lplu_state)
2831 return hw->phy.ops.set_d0_lplu_state(hw, active);
2832
2833 return 0;
2834}
Bruce Allana4f58f52009-06-02 11:29:18 +00002835
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002836/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002837 * __e1000_read_phy_reg_hv - Read HV PHY register
Bruce Allana4f58f52009-06-02 11:29:18 +00002838 * @hw: pointer to the HW structure
2839 * @offset: register offset to be read
2840 * @data: pointer to the read data
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002841 * @locked: semaphore has already been acquired or not
Bruce Allana4f58f52009-06-02 11:29:18 +00002842 *
2843 * Acquires semaphore, if necessary, then reads the PHY register at offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002844 * and stores the retrieved information in data. Release any acquired
Bruce Allana4f58f52009-06-02 11:29:18 +00002845 * semaphore before exiting.
2846 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002847static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002848 bool locked, bool page_set)
Bruce Allana4f58f52009-06-02 11:29:18 +00002849{
2850 s32 ret_val;
2851 u16 page = BM_PHY_REG_PAGE(offset);
2852 u16 reg = BM_PHY_REG_NUM(offset);
Bruce Allan2b6b1682011-05-13 07:20:09 +00002853 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
Bruce Allana4f58f52009-06-02 11:29:18 +00002854
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002855 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +00002856 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002857 if (ret_val)
2858 return ret_val;
2859 }
2860
Bruce Allana4f58f52009-06-02 11:29:18 +00002861 /* Page 800 works differently than the rest so it has its own func */
2862 if (page == BM_WUC_PAGE) {
Bruce Allan2b6b1682011-05-13 07:20:09 +00002863 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2864 true, page_set);
Bruce Allana4f58f52009-06-02 11:29:18 +00002865 goto out;
2866 }
2867
2868 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2869 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2870 data, true);
2871 goto out;
2872 }
2873
Bruce Allan2b6b1682011-05-13 07:20:09 +00002874 if (!page_set) {
2875 if (page == HV_INTC_FC_PAGE_START)
2876 page = 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00002877
Bruce Allan2b6b1682011-05-13 07:20:09 +00002878 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2879 /* Page is shifted left, PHY expects (page x 32) */
2880 ret_val = e1000_set_page_igp(hw,
2881 (page << IGP_PAGE_SHIFT));
Bruce Allana4f58f52009-06-02 11:29:18 +00002882
Bruce Allan2b6b1682011-05-13 07:20:09 +00002883 hw->phy.addr = phy_addr;
Bruce Allana4f58f52009-06-02 11:29:18 +00002884
Bruce Allan2b6b1682011-05-13 07:20:09 +00002885 if (ret_val)
2886 goto out;
2887 }
Bruce Allana4f58f52009-06-02 11:29:18 +00002888 }
2889
Bruce Allan2b6b1682011-05-13 07:20:09 +00002890 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2891 page << IGP_PAGE_SHIFT, reg);
2892
Bruce Allana4f58f52009-06-02 11:29:18 +00002893 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2894 data);
Bruce Allana4f58f52009-06-02 11:29:18 +00002895out:
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002896 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +00002897 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002898
Bruce Allana4f58f52009-06-02 11:29:18 +00002899 return ret_val;
2900}
2901
2902/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002903 * e1000_read_phy_reg_hv - Read HV PHY register
2904 * @hw: pointer to the HW structure
2905 * @offset: register offset to be read
2906 * @data: pointer to the read data
2907 *
2908 * Acquires semaphore then reads the PHY register at offset and stores
2909 * the retrieved information in data. Release the acquired semaphore
2910 * before exiting.
2911 **/
2912s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2913{
Bruce Allan2b6b1682011-05-13 07:20:09 +00002914 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002915}
2916
2917/**
2918 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2919 * @hw: pointer to the HW structure
2920 * @offset: register offset to be read
2921 * @data: pointer to the read data
2922 *
2923 * Reads the PHY register at offset and stores the retrieved information
2924 * in data. Assumes semaphore already acquired.
2925 **/
2926s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2927{
Bruce Allan2b6b1682011-05-13 07:20:09 +00002928 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2929}
2930
2931/**
2932 * e1000_read_phy_reg_page_hv - Read HV PHY register
2933 * @hw: pointer to the HW structure
2934 * @offset: register offset to write to
2935 * @data: data to write at register offset
2936 *
2937 * Reads the PHY register at offset and stores the retrieved information
2938 * in data. Assumes semaphore already acquired and page already set.
2939 **/
2940s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2941{
2942 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002943}
2944
2945/**
2946 * __e1000_write_phy_reg_hv - Write HV PHY register
Bruce Allana4f58f52009-06-02 11:29:18 +00002947 * @hw: pointer to the HW structure
2948 * @offset: register offset to write to
2949 * @data: data to write at register offset
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002950 * @locked: semaphore has already been acquired or not
Bruce Allana4f58f52009-06-02 11:29:18 +00002951 *
2952 * Acquires semaphore, if necessary, then writes the data to PHY register
2953 * at the offset. Release any acquired semaphores before exiting.
2954 **/
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002955static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
Bruce Allan2b6b1682011-05-13 07:20:09 +00002956 bool locked, bool page_set)
Bruce Allana4f58f52009-06-02 11:29:18 +00002957{
2958 s32 ret_val;
2959 u16 page = BM_PHY_REG_PAGE(offset);
2960 u16 reg = BM_PHY_REG_NUM(offset);
Bruce Allan2b6b1682011-05-13 07:20:09 +00002961 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
Bruce Allana4f58f52009-06-02 11:29:18 +00002962
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002963 if (!locked) {
Bruce Allan94d81862009-11-20 23:25:26 +00002964 ret_val = hw->phy.ops.acquire(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00002965 if (ret_val)
2966 return ret_val;
2967 }
2968
Bruce Allana4f58f52009-06-02 11:29:18 +00002969 /* Page 800 works differently than the rest so it has its own func */
2970 if (page == BM_WUC_PAGE) {
Bruce Allan2b6b1682011-05-13 07:20:09 +00002971 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2972 false, page_set);
Bruce Allana4f58f52009-06-02 11:29:18 +00002973 goto out;
2974 }
2975
2976 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2977 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2978 &data, false);
2979 goto out;
2980 }
2981
Bruce Allan2b6b1682011-05-13 07:20:09 +00002982 if (!page_set) {
2983 if (page == HV_INTC_FC_PAGE_START)
2984 page = 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00002985
Bruce Allan2b6b1682011-05-13 07:20:09 +00002986 /*
2987 * Workaround MDIO accesses being disabled after entering IEEE
2988 * Power Down (when bit 11 of the PHY Control register is set)
2989 */
2990 if ((hw->phy.type == e1000_phy_82578) &&
2991 (hw->phy.revision >= 1) &&
2992 (hw->phy.addr == 2) &&
2993 ((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) {
2994 u16 data2 = 0x7EFF;
2995 ret_val = e1000_access_phy_debug_regs_hv(hw,
2996 (1 << 6) | 0x3,
2997 &data2, false);
2998 if (ret_val)
2999 goto out;
3000 }
Bruce Allana4f58f52009-06-02 11:29:18 +00003001
Bruce Allan2b6b1682011-05-13 07:20:09 +00003002 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3003 /* Page is shifted left, PHY expects (page x 32) */
3004 ret_val = e1000_set_page_igp(hw,
3005 (page << IGP_PAGE_SHIFT));
3006
3007 hw->phy.addr = phy_addr;
3008
3009 if (ret_val)
3010 goto out;
3011 }
Bruce Allana4f58f52009-06-02 11:29:18 +00003012 }
3013
Bruce Allan2b6b1682011-05-13 07:20:09 +00003014 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3015 page << IGP_PAGE_SHIFT, reg);
Bruce Allana4f58f52009-06-02 11:29:18 +00003016
3017 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3018 data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003019
3020out:
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003021 if (!locked)
Bruce Allan94d81862009-11-20 23:25:26 +00003022 hw->phy.ops.release(hw);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003023
Bruce Allana4f58f52009-06-02 11:29:18 +00003024 return ret_val;
3025}
3026
3027/**
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003028 * e1000_write_phy_reg_hv - Write HV PHY register
3029 * @hw: pointer to the HW structure
3030 * @offset: register offset to write to
3031 * @data: data to write at register offset
3032 *
3033 * Acquires semaphore then writes the data to PHY register at the offset.
3034 * Release the acquired semaphores before exiting.
3035 **/
3036s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3037{
Bruce Allan2b6b1682011-05-13 07:20:09 +00003038 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003039}
3040
3041/**
3042 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3043 * @hw: pointer to the HW structure
3044 * @offset: register offset to write to
3045 * @data: data to write at register offset
3046 *
3047 * Writes the data to PHY register at the offset. Assumes semaphore
3048 * already acquired.
3049 **/
3050s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3051{
Bruce Allan2b6b1682011-05-13 07:20:09 +00003052 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3053}
3054
3055/**
3056 * e1000_write_phy_reg_page_hv - Write HV PHY register
3057 * @hw: pointer to the HW structure
3058 * @offset: register offset to write to
3059 * @data: data to write at register offset
3060 *
3061 * Writes the data to PHY register at the offset. Assumes semaphore
3062 * already acquired and page already set.
3063 **/
3064s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3065{
3066 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003067}
3068
3069/**
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04003070 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
Bruce Allana4f58f52009-06-02 11:29:18 +00003071 * @page: page to be accessed
3072 **/
3073static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3074{
3075 u32 phy_addr = 2;
3076
3077 if (page >= HV_INTC_FC_PAGE_START)
3078 phy_addr = 1;
3079
3080 return phy_addr;
3081}
3082
3083/**
3084 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3085 * @hw: pointer to the HW structure
3086 * @offset: register offset to be read or written
3087 * @data: pointer to the data to be read or written
Bruce Allan2b6b1682011-05-13 07:20:09 +00003088 * @read: determines if operation is read or write
Bruce Allana4f58f52009-06-02 11:29:18 +00003089 *
Bruce Allan5ccdcec2009-10-26 11:24:02 +00003090 * Reads the PHY register at offset and stores the retreived information
3091 * in data. Assumes semaphore already acquired. Note that the procedure
Bruce Allan2b6b1682011-05-13 07:20:09 +00003092 * to access these regs uses the address port and data port to read/write.
3093 * These accesses done with PHY address 2 and without using pages.
Bruce Allana4f58f52009-06-02 11:29:18 +00003094 **/
3095static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3096 u16 *data, bool read)
3097{
3098 s32 ret_val;
3099 u32 addr_reg = 0;
3100 u32 data_reg = 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00003101
3102 /* This takes care of the difference with desktop vs mobile phy */
3103 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3104 I82578_ADDR_REG : I82577_ADDR_REG;
3105 data_reg = addr_reg + 1;
3106
Bruce Allana4f58f52009-06-02 11:29:18 +00003107 /* All operations in this function are phy address 2 */
3108 hw->phy.addr = 2;
3109
3110 /* masking with 0x3F to remove the page from offset */
3111 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3112 if (ret_val) {
Bruce Allan2b6b1682011-05-13 07:20:09 +00003113 e_dbg("Could not write the Address Offset port register\n");
Bruce Allan5015e532012-02-08 02:55:56 +00003114 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003115 }
3116
3117 /* Read or write the data value next */
3118 if (read)
3119 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3120 else
3121 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3122
Bruce Allan5015e532012-02-08 02:55:56 +00003123 if (ret_val)
Bruce Allan2b6b1682011-05-13 07:20:09 +00003124 e_dbg("Could not access the Data port register\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003125
Bruce Allana4f58f52009-06-02 11:29:18 +00003126 return ret_val;
3127}
3128
3129/**
3130 * e1000_link_stall_workaround_hv - Si workaround
3131 * @hw: pointer to the HW structure
3132 *
3133 * This function works around a Si bug where the link partner can get
3134 * a link up indication before the PHY does. If small packets are sent
3135 * by the link partner they can be placed in the packet buffer without
3136 * being properly accounted for by the PHY and will stall preventing
3137 * further packets from being received. The workaround is to clear the
3138 * packet buffer after the PHY detects link up.
3139 **/
3140s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3141{
3142 s32 ret_val = 0;
3143 u16 data;
3144
3145 if (hw->phy.type != e1000_phy_82578)
Bruce Allan5015e532012-02-08 02:55:56 +00003146 return 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00003147
Bruce Allane65fa872009-07-01 13:27:31 +00003148 /* Do not apply workaround if in PHY loopback bit 14 set */
Bruce Allan482fed82011-01-06 14:29:49 +00003149 e1e_rphy(hw, PHY_CONTROL, &data);
Bruce Allane65fa872009-07-01 13:27:31 +00003150 if (data & PHY_CONTROL_LB)
Bruce Allan5015e532012-02-08 02:55:56 +00003151 return 0;
Bruce Allane65fa872009-07-01 13:27:31 +00003152
Bruce Allana4f58f52009-06-02 11:29:18 +00003153 /* check if link is up and at 1Gbps */
Bruce Allan482fed82011-01-06 14:29:49 +00003154 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003155 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003156 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003157
3158 data &= BM_CS_STATUS_LINK_UP |
3159 BM_CS_STATUS_RESOLVED |
3160 BM_CS_STATUS_SPEED_MASK;
3161
3162 if (data != (BM_CS_STATUS_LINK_UP |
3163 BM_CS_STATUS_RESOLVED |
3164 BM_CS_STATUS_SPEED_1000))
Bruce Allan5015e532012-02-08 02:55:56 +00003165 return 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00003166
3167 mdelay(200);
3168
3169 /* flush the packets in the fifo buffer */
Bruce Allan482fed82011-01-06 14:29:49 +00003170 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3171 HV_MUX_DATA_CTRL_FORCE_SPEED);
Bruce Allana4f58f52009-06-02 11:29:18 +00003172 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003173 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003174
Bruce Allan5015e532012-02-08 02:55:56 +00003175 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
Bruce Allana4f58f52009-06-02 11:29:18 +00003176}
3177
3178/**
3179 * e1000_check_polarity_82577 - Checks the polarity.
3180 * @hw: pointer to the HW structure
3181 *
3182 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3183 *
3184 * Polarity is determined based on the PHY specific status register.
3185 **/
3186s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3187{
3188 struct e1000_phy_info *phy = &hw->phy;
3189 s32 ret_val;
3190 u16 data;
3191
Bruce Allan482fed82011-01-06 14:29:49 +00003192 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003193
3194 if (!ret_val)
3195 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3196 ? e1000_rev_polarity_reversed
3197 : e1000_rev_polarity_normal;
3198
3199 return ret_val;
3200}
3201
3202/**
3203 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3204 * @hw: pointer to the HW structure
3205 *
Bruce Allaneab50ff2010-05-10 15:01:30 +00003206 * Calls the PHY setup function to force speed and duplex.
Bruce Allana4f58f52009-06-02 11:29:18 +00003207 **/
3208s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3209{
3210 struct e1000_phy_info *phy = &hw->phy;
3211 s32 ret_val;
3212 u16 phy_data;
3213 bool link;
3214
Bruce Allan482fed82011-01-06 14:29:49 +00003215 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003216 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003217 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003218
3219 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3220
Bruce Allan482fed82011-01-06 14:29:49 +00003221 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003222 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003223 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003224
Bruce Allana4f58f52009-06-02 11:29:18 +00003225 udelay(1);
3226
3227 if (phy->autoneg_wait_to_complete) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003228 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003229
3230 ret_val = e1000e_phy_has_link_generic(hw,
3231 PHY_FORCE_LIMIT,
3232 100000,
3233 &link);
3234 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003235 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003236
3237 if (!link)
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003238 e_dbg("Link taking longer than expected.\n");
Bruce Allana4f58f52009-06-02 11:29:18 +00003239
3240 /* Try once more */
3241 ret_val = e1000e_phy_has_link_generic(hw,
3242 PHY_FORCE_LIMIT,
3243 100000,
3244 &link);
Bruce Allana4f58f52009-06-02 11:29:18 +00003245 }
3246
Bruce Allana4f58f52009-06-02 11:29:18 +00003247 return ret_val;
3248}
3249
3250/**
3251 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3252 * @hw: pointer to the HW structure
3253 *
3254 * Read PHY status to determine if link is up. If link is up, then
3255 * set/determine 10base-T extended distance and polarity correction. Read
3256 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3257 * determine on the cable length, local and remote receiver.
3258 **/
3259s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3260{
3261 struct e1000_phy_info *phy = &hw->phy;
3262 s32 ret_val;
3263 u16 data;
3264 bool link;
3265
3266 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3267 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003268 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003269
3270 if (!link) {
Bruce Allan3bb99fe2009-11-20 23:25:07 +00003271 e_dbg("Phy info is only valid if link is up\n");
Bruce Allan5015e532012-02-08 02:55:56 +00003272 return -E1000_ERR_CONFIG;
Bruce Allana4f58f52009-06-02 11:29:18 +00003273 }
3274
3275 phy->polarity_correction = true;
3276
3277 ret_val = e1000_check_polarity_82577(hw);
3278 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003279 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003280
Bruce Allan482fed82011-01-06 14:29:49 +00003281 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003282 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003283 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003284
3285 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3286
3287 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3288 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3289 ret_val = hw->phy.ops.get_cable_length(hw);
3290 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003291 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003292
Bruce Allan482fed82011-01-06 14:29:49 +00003293 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003294 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003295 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003296
3297 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3298 ? e1000_1000t_rx_status_ok
3299 : e1000_1000t_rx_status_not_ok;
3300
3301 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3302 ? e1000_1000t_rx_status_ok
3303 : e1000_1000t_rx_status_not_ok;
3304 } else {
3305 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3306 phy->local_rx = e1000_1000t_rx_status_undefined;
3307 phy->remote_rx = e1000_1000t_rx_status_undefined;
3308 }
3309
Bruce Allan5015e532012-02-08 02:55:56 +00003310 return 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00003311}
3312
3313/**
3314 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3315 * @hw: pointer to the HW structure
3316 *
3317 * Reads the diagnostic status register and verifies result is valid before
3318 * placing it in the phy_cable_length field.
3319 **/
3320s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3321{
3322 struct e1000_phy_info *phy = &hw->phy;
3323 s32 ret_val;
3324 u16 phy_data, length;
3325
Bruce Allan482fed82011-01-06 14:29:49 +00003326 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
Bruce Allana4f58f52009-06-02 11:29:18 +00003327 if (ret_val)
Bruce Allan5015e532012-02-08 02:55:56 +00003328 return ret_val;
Bruce Allana4f58f52009-06-02 11:29:18 +00003329
3330 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3331 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3332
3333 if (length == E1000_CABLE_LENGTH_UNDEFINED)
Bruce Allan98086a92009-11-20 23:23:53 +00003334 ret_val = -E1000_ERR_PHY;
Bruce Allana4f58f52009-06-02 11:29:18 +00003335
3336 phy->cable_length = length;
3337
Bruce Allan5015e532012-02-08 02:55:56 +00003338 return 0;
Bruce Allana4f58f52009-06-02 11:29:18 +00003339}