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Felipe Balbi550a7372008-07-24 12:27:36 +03001/*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -07007 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
Felipe Balbi550a7372008-07-24 12:27:36 +03008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/errno.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030042#include <linux/list.h>
Maulik Mankad496dda72010-09-24 13:44:06 +030043#include <linux/dma-mapping.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030044
45#include "musb_core.h"
46#include "musb_host.h"
47
Felipe Balbi550a7372008-07-24 12:27:36 +030048/* MUSB HOST status 22-mar-2006
49 *
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
52 *
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
59 *
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
64 *
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
66 *
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -080067 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
68 * starvation ... nothing yet for TX, interrupt, or bulk.
Felipe Balbi550a7372008-07-24 12:27:36 +030069 *
70 * - Not tested with HNP, but some SRP paths seem to behave.
71 *
72 * NOTE 24-August-2006:
73 *
74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
75 * extra endpoint for periodic use enabling hub + keybd + mouse. That
76 * mostly works, except that with "usbnet" it's easy to trigger cases
77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
79 * although ARP RX wins. (That test was done with a full speed link.)
80 */
81
82
83/*
84 * NOTE on endpoint usage:
85 *
86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
Felipe Balbi550a7372008-07-24 12:27:36 +030088 * (Yes, bulk _could_ use more of the endpoints than that, and would even
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -080089 * benefit from it.)
Felipe Balbi550a7372008-07-24 12:27:36 +030090 *
91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
92 * So far that scheduling is both dumb and optimistic: the endpoint will be
93 * "claimed" until its software queue is no longer refilled. No multiplexing
94 * of transfers between endpoints, or anything clever.
95 */
96
Daniel Mack74c2e932013-04-10 21:55:45 +020097struct musb *hcd_to_musb(struct usb_hcd *hcd)
98{
99 return *(struct musb **) hcd->hcd_priv;
100}
101
Felipe Balbi550a7372008-07-24 12:27:36 +0300102
103static void musb_ep_program(struct musb *musb, u8 epnum,
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700104 struct urb *urb, int is_out,
105 u8 *buf, u32 offset, u32 len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300106
107/*
108 * Clear TX fifo. Needed to avoid BABBLE errors.
109 */
David Brownellc767c1c2008-09-11 11:53:23 +0300110static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
Felipe Balbi550a7372008-07-24 12:27:36 +0300111{
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300112 struct musb *musb = ep->musb;
Felipe Balbi550a7372008-07-24 12:27:36 +0300113 void __iomem *epio = ep->regs;
114 u16 csr;
David Brownellbb1c9ef2008-11-24 13:06:50 +0200115 u16 lastcsr = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300116 int retries = 1000;
117
118 csr = musb_readw(epio, MUSB_TXCSR);
119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
David Brownellbb1c9ef2008-11-24 13:06:50 +0200120 if (csr != lastcsr)
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300121 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
David Brownellbb1c9ef2008-11-24 13:06:50 +0200122 lastcsr = csr;
Daniel Mack2ccc6d32014-05-26 14:52:37 +0200123 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;
Felipe Balbi550a7372008-07-24 12:27:36 +0300124 musb_writew(epio, MUSB_TXCSR, csr);
125 csr = musb_readw(epio, MUSB_TXCSR);
David Brownellbb1c9ef2008-11-24 13:06:50 +0200126 if (WARN(retries-- < 1,
127 "Could not flush host TX%d fifo: csr: %04x\n",
128 ep->epnum, csr))
Felipe Balbi550a7372008-07-24 12:27:36 +0300129 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300130 mdelay(1);
131 }
132}
133
David Brownell78322c12009-03-26 17:38:30 -0700134static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
135{
136 void __iomem *epio = ep->regs;
137 u16 csr;
138 int retries = 5;
139
140 /* scrub any data left in the fifo */
141 do {
142 csr = musb_readw(epio, MUSB_TXCSR);
143 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
144 break;
145 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
146 csr = musb_readw(epio, MUSB_TXCSR);
147 udelay(10);
148 } while (--retries);
149
150 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
151 ep->epnum, csr);
152
153 /* and reset for the next transfer */
154 musb_writew(epio, MUSB_TXCSR, 0);
155}
156
Felipe Balbi550a7372008-07-24 12:27:36 +0300157/*
158 * Start transmit. Caller is responsible for locking shared resources.
159 * musb must be locked.
160 */
161static inline void musb_h_tx_start(struct musb_hw_ep *ep)
162{
163 u16 txcsr;
164
165 /* NOTE: no locks here; caller should lock and select EP */
166 if (ep->epnum) {
167 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
168 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
169 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
170 } else {
171 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
172 musb_writew(ep->regs, MUSB_CSR0, txcsr);
173 }
174
175}
176
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700177static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
Felipe Balbi550a7372008-07-24 12:27:36 +0300178{
179 u16 txcsr;
180
181 /* NOTE: no locks here; caller should lock and select EP */
182 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
183 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
Tony Lindgrenf8e9f34f2015-05-01 12:29:27 -0700184 if (is_cppi_enabled(ep->musb))
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700185 txcsr |= MUSB_TXCSR_DMAMODE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300186 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
187}
188
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700189static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
190{
191 if (is_in != 0 || ep->is_shared_fifo)
192 ep->in_qh = qh;
193 if (is_in == 0 || ep->is_shared_fifo)
194 ep->out_qh = qh;
195}
196
197static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
198{
199 return is_in ? ep->in_qh : ep->out_qh;
200}
201
Felipe Balbi550a7372008-07-24 12:27:36 +0300202/*
203 * Start the URB at the front of an endpoint's queue
204 * end must be claimed from the caller.
205 *
206 * Context: controller locked, irqs blocked
207 */
208static void
209musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
210{
211 u16 frame;
212 u32 len;
Felipe Balbi550a7372008-07-24 12:27:36 +0300213 void __iomem *mbase = musb->mregs;
214 struct urb *urb = next_urb(qh);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700215 void *buf = urb->transfer_buffer;
216 u32 offset = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300217 struct musb_hw_ep *hw_ep = qh->hw_ep;
218 unsigned pipe = urb->pipe;
219 u8 address = usb_pipedevice(pipe);
220 int epnum = hw_ep->epnum;
221
222 /* initialize software qh state */
223 qh->offset = 0;
224 qh->segsize = 0;
225
226 /* gather right source of data */
227 switch (qh->type) {
228 case USB_ENDPOINT_XFER_CONTROL:
229 /* control transfers always start with SETUP */
230 is_in = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300231 musb->ep0_stage = MUSB_EP0_START;
232 buf = urb->setup_packet;
233 len = 8;
234 break;
235 case USB_ENDPOINT_XFER_ISOC:
236 qh->iso_idx = 0;
237 qh->frame = 0;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700238 offset = urb->iso_frame_desc[0].offset;
Felipe Balbi550a7372008-07-24 12:27:36 +0300239 len = urb->iso_frame_desc[0].length;
240 break;
241 default: /* bulk, interrupt */
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -0800242 /* actual_length may be nonzero on retry paths */
243 buf = urb->transfer_buffer + urb->actual_length;
244 len = urb->transfer_buffer_length - urb->actual_length;
Felipe Balbi550a7372008-07-24 12:27:36 +0300245 }
246
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300247 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
Felipe Balbi550a7372008-07-24 12:27:36 +0300248 qh, urb, address, qh->epnum,
249 is_in ? "in" : "out",
250 ({char *s; switch (qh->type) {
251 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
252 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
253 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
254 default: s = "-intr"; break;
Joe Perches2b84f922013-10-08 16:01:37 -0700255 } s; }),
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700256 epnum, buf + offset, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300257
258 /* Configure endpoint */
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700259 musb_ep_set_qh(hw_ep, is_in, qh);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700260 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300261
262 /* transmit may have more work: start it when it is time */
263 if (is_in)
264 return;
265
266 /* determine if the time is right for a periodic transfer */
267 switch (qh->type) {
268 case USB_ENDPOINT_XFER_ISOC:
269 case USB_ENDPOINT_XFER_INT:
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300270 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
Felipe Balbi550a7372008-07-24 12:27:36 +0300271 frame = musb_readw(mbase, MUSB_FRAME);
272 /* FIXME this doesn't implement that scheduling policy ...
273 * or handle framecounter wrapping
274 */
Alan Stern8a1ea512013-05-29 13:21:01 -0400275 if (1) { /* Always assume URB_ISO_ASAP */
Felipe Balbi550a7372008-07-24 12:27:36 +0300276 /* REVISIT the SOF irq handler shouldn't duplicate
277 * this code; and we don't init urb->start_frame...
278 */
279 qh->frame = 0;
280 goto start;
281 } else {
282 qh->frame = urb->start_frame;
283 /* enable SOF interrupt so we can count down */
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300284 dev_dbg(musb->controller, "SOF for %d\n", epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +0300285#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
286 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
287#endif
288 }
289 break;
290 default:
291start:
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300292 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
Felipe Balbi550a7372008-07-24 12:27:36 +0300293 hw_ep->tx_channel ? "dma" : "pio");
294
295 if (!hw_ep->tx_channel)
296 musb_h_tx_start(hw_ep);
Tony Lindgrenf8e9f34f2015-05-01 12:29:27 -0700297 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700298 musb_h_tx_dma_start(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +0300299 }
300}
301
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700302/* Context: caller owns controller lock, IRQs are blocked */
303static void musb_giveback(struct musb *musb, struct urb *urb, int status)
Felipe Balbi550a7372008-07-24 12:27:36 +0300304__releases(musb->lock)
305__acquires(musb->lock)
306{
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300307 dev_dbg(musb->controller,
David Brownellbb1c9ef2008-11-24 13:06:50 +0200308 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
309 urb, urb->complete, status,
Felipe Balbi550a7372008-07-24 12:27:36 +0300310 usb_pipedevice(urb->pipe),
311 usb_pipeendpoint(urb->pipe),
312 usb_pipein(urb->pipe) ? "in" : "out",
313 urb->actual_length, urb->transfer_buffer_length
314 );
315
Daniel Mack8b125df2013-04-10 21:55:50 +0200316 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
Felipe Balbi550a7372008-07-24 12:27:36 +0300317 spin_unlock(&musb->lock);
Daniel Mack8b125df2013-04-10 21:55:50 +0200318 usb_hcd_giveback_urb(musb->hcd, urb, status);
Felipe Balbi550a7372008-07-24 12:27:36 +0300319 spin_lock(&musb->lock);
320}
321
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700322/* For bulk/interrupt endpoints only */
323static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
324 struct urb *urb)
Felipe Balbi550a7372008-07-24 12:27:36 +0300325{
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700326 void __iomem *epio = qh->hw_ep->regs;
Felipe Balbi550a7372008-07-24 12:27:36 +0300327 u16 csr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300328
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700329 /*
330 * FIXME: the current Mentor DMA code seems to have
Felipe Balbi550a7372008-07-24 12:27:36 +0300331 * problems getting toggle correct.
332 */
333
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700334 if (is_in)
335 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300336 else
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700337 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300338
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700339 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
Felipe Balbi550a7372008-07-24 12:27:36 +0300340}
341
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700342/*
343 * Advance this hardware endpoint's queue, completing the specified URB and
344 * advancing to either the next URB queued to that qh, or else invalidating
345 * that qh and advancing to the next qh scheduled after the current one.
346 *
347 * Context: caller owns controller lock, IRQs are blocked
348 */
349static void musb_advance_schedule(struct musb *musb, struct urb *urb,
350 struct musb_hw_ep *hw_ep, int is_in)
Felipe Balbi550a7372008-07-24 12:27:36 +0300351{
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700352 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
Felipe Balbi550a7372008-07-24 12:27:36 +0300353 struct musb_hw_ep *ep = qh->hw_ep;
Felipe Balbi550a7372008-07-24 12:27:36 +0300354 int ready = qh->is_ready;
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700355 int status;
356
357 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
Felipe Balbi550a7372008-07-24 12:27:36 +0300358
Felipe Balbi550a7372008-07-24 12:27:36 +0300359 /* save toggle eagerly, for paranoia */
360 switch (qh->type) {
361 case USB_ENDPOINT_XFER_BULK:
362 case USB_ENDPOINT_XFER_INT:
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700363 musb_save_toggle(qh, is_in, urb);
Felipe Balbi550a7372008-07-24 12:27:36 +0300364 break;
365 case USB_ENDPOINT_XFER_ISOC:
Sergei Shtylyov1fe975f2009-07-10 20:02:44 +0300366 if (status == 0 && urb->error_count)
Felipe Balbi550a7372008-07-24 12:27:36 +0300367 status = -EXDEV;
368 break;
369 }
370
Felipe Balbi550a7372008-07-24 12:27:36 +0300371 qh->is_ready = 0;
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700372 musb_giveback(musb, urb, status);
Felipe Balbi550a7372008-07-24 12:27:36 +0300373 qh->is_ready = ready;
374
375 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
376 * invalidate qh as soon as list_empty(&hep->urb_list)
377 */
378 if (list_empty(&qh->hep->urb_list)) {
379 struct list_head *head;
Ajay Kumar Gupta8c778db2012-06-21 17:18:12 +0530380 struct dma_controller *dma = musb->dma_controller;
Felipe Balbi550a7372008-07-24 12:27:36 +0300381
Ajay Kumar Gupta8c778db2012-06-21 17:18:12 +0530382 if (is_in) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300383 ep->rx_reinit = 1;
Ajay Kumar Gupta8c778db2012-06-21 17:18:12 +0530384 if (ep->rx_channel) {
385 dma->channel_release(ep->rx_channel);
386 ep->rx_channel = NULL;
387 }
388 } else {
Felipe Balbi550a7372008-07-24 12:27:36 +0300389 ep->tx_reinit = 1;
Ajay Kumar Gupta8c778db2012-06-21 17:18:12 +0530390 if (ep->tx_channel) {
391 dma->channel_release(ep->tx_channel);
392 ep->tx_channel = NULL;
393 }
394 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300395
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700396 /* Clobber old pointers to this qh */
397 musb_ep_set_qh(ep, is_in, NULL);
Felipe Balbi550a7372008-07-24 12:27:36 +0300398 qh->hep->hcpriv = NULL;
399
400 switch (qh->type) {
401
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +0200402 case USB_ENDPOINT_XFER_CONTROL:
403 case USB_ENDPOINT_XFER_BULK:
404 /* fifo policy for these lists, except that NAKing
405 * should rotate a qh to the end (for fairness).
406 */
407 if (qh->mux == 1) {
408 head = qh->ring.prev;
409 list_del(&qh->ring);
410 kfree(qh);
411 qh = first_qh(head);
412 break;
413 }
414
Felipe Balbi550a7372008-07-24 12:27:36 +0300415 case USB_ENDPOINT_XFER_ISOC:
416 case USB_ENDPOINT_XFER_INT:
417 /* this is where periodic bandwidth should be
418 * de-allocated if it's tracked and allocated;
419 * and where we'd update the schedule tree...
420 */
Felipe Balbi550a7372008-07-24 12:27:36 +0300421 kfree(qh);
422 qh = NULL;
423 break;
Felipe Balbi550a7372008-07-24 12:27:36 +0300424 }
425 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300426
Sergei Shtylyova2fd8142009-02-21 15:30:45 -0800427 if (qh != NULL && qh->is_ready) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300428 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
Felipe Balbi550a7372008-07-24 12:27:36 +0300430 musb_start_urb(musb, is_in, qh);
431 }
432}
433
David Brownellc767c1c2008-09-11 11:53:23 +0300434static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
Felipe Balbi550a7372008-07-24 12:27:36 +0300435{
436 /* we don't want fifo to fill itself again;
437 * ignore dma (various models),
438 * leave toggle alone (may not have been saved yet)
439 */
440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
441 csr &= ~(MUSB_RXCSR_H_REQPKT
442 | MUSB_RXCSR_H_AUTOREQ
443 | MUSB_RXCSR_AUTOCLEAR);
444
445 /* write 2x to allow double buffering */
446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448
449 /* flush writebuffer */
450 return musb_readw(hw_ep->regs, MUSB_RXCSR);
451}
452
453/*
454 * PIO RX for a packet (or part of it).
455 */
456static bool
457musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
458{
459 u16 rx_count;
460 u8 *buf;
461 u16 csr;
462 bool done = false;
463 u32 length;
464 int do_flush = 0;
465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
466 void __iomem *epio = hw_ep->regs;
467 struct musb_qh *qh = hw_ep->in_qh;
468 int pipe = urb->pipe;
469 void *buffer = urb->transfer_buffer;
470
471 /* musb_ep_select(mbase, epnum); */
472 rx_count = musb_readw(epio, MUSB_RXCOUNT);
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300473 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
Felipe Balbi550a7372008-07-24 12:27:36 +0300474 urb->transfer_buffer, qh->offset,
475 urb->transfer_buffer_length);
476
477 /* unload FIFO */
478 if (usb_pipeisoc(pipe)) {
479 int status = 0;
480 struct usb_iso_packet_descriptor *d;
481
482 if (iso_err) {
483 status = -EILSEQ;
484 urb->error_count++;
485 }
486
487 d = urb->iso_frame_desc + qh->iso_idx;
488 buf = buffer + d->offset;
489 length = d->length;
490 if (rx_count > length) {
491 if (status == 0) {
492 status = -EOVERFLOW;
493 urb->error_count++;
494 }
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300495 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
Felipe Balbi550a7372008-07-24 12:27:36 +0300496 do_flush = 1;
497 } else
498 length = rx_count;
499 urb->actual_length += length;
500 d->actual_length = length;
501
502 d->status = status;
503
504 /* see if we are done */
505 done = (++qh->iso_idx >= urb->number_of_packets);
506 } else {
507 /* non-isoch */
508 buf = buffer + qh->offset;
509 length = urb->transfer_buffer_length - qh->offset;
510 if (rx_count > length) {
511 if (urb->status == -EINPROGRESS)
512 urb->status = -EOVERFLOW;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300513 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
Felipe Balbi550a7372008-07-24 12:27:36 +0300514 do_flush = 1;
515 } else
516 length = rx_count;
517 urb->actual_length += length;
518 qh->offset += length;
519
520 /* see if we are done */
521 done = (urb->actual_length == urb->transfer_buffer_length)
522 || (rx_count < qh->maxpacket)
523 || (urb->status != -EINPROGRESS);
524 if (done
525 && (urb->status == -EINPROGRESS)
526 && (urb->transfer_flags & URB_SHORT_NOT_OK)
527 && (urb->actual_length
528 < urb->transfer_buffer_length))
529 urb->status = -EREMOTEIO;
530 }
531
532 musb_read_fifo(hw_ep, length, buf);
533
534 csr = musb_readw(epio, MUSB_RXCSR);
535 csr |= MUSB_RXCSR_H_WZC_BITS;
536 if (unlikely(do_flush))
537 musb_h_flush_rxfifo(hw_ep, csr);
538 else {
539 /* REVISIT this assumes AUTOCLEAR is never set */
540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
541 if (!done)
542 csr |= MUSB_RXCSR_H_REQPKT;
543 musb_writew(epio, MUSB_RXCSR, csr);
544 }
545
546 return done;
547}
548
549/* we don't always need to reinit a given side of an endpoint...
550 * when we do, use tx/rx reinit routine and then construct a new CSR
551 * to address data toggle, NYET, and DMA or PIO.
552 *
553 * it's possible that driver bugs (especially for DMA) or aborting a
554 * transfer might have left the endpoint busier than it should be.
555 * the busy/not-empty tests are basically paranoia.
556 */
557static void
Hans de Goede0cb74b32015-03-20 20:11:11 +0100558musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum)
Felipe Balbi550a7372008-07-24 12:27:36 +0300559{
Hans de Goede0cb74b32015-03-20 20:11:11 +0100560 struct musb_hw_ep *ep = musb->endpoints + epnum;
Felipe Balbi550a7372008-07-24 12:27:36 +0300561 u16 csr;
562
563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
564 * That always uses tx_reinit since ep0 repurposes TX register
565 * offsets; the initial SETUP packet is also a kind of OUT.
566 */
567
568 /* if programmed for Tx, put it in RX mode */
569 if (ep->is_shared_fifo) {
570 csr = musb_readw(ep->regs, MUSB_TXCSR);
571 if (csr & MUSB_TXCSR_MODE) {
572 musb_h_tx_flush_fifo(ep);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700573 csr = musb_readw(ep->regs, MUSB_TXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300574 musb_writew(ep->regs, MUSB_TXCSR,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700575 csr | MUSB_TXCSR_FRCDATATOG);
Felipe Balbi550a7372008-07-24 12:27:36 +0300576 }
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700577
578 /*
579 * Clear the MODE bit (and everything else) to enable Rx.
580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
581 */
582 if (csr & MUSB_TXCSR_DMAMODE)
583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
Felipe Balbi550a7372008-07-24 12:27:36 +0300584 musb_writew(ep->regs, MUSB_TXCSR, 0);
585
586 /* scrub all previous state, clearing toggle */
587 } else {
588 csr = musb_readw(ep->regs, MUSB_RXCSR);
589 if (csr & MUSB_RXCSR_RXPKTRDY)
590 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
591 musb_readw(ep->regs, MUSB_RXCOUNT));
592
593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
594 }
595
596 /* target addr and (for multipoint) hub addr/port */
597 if (musb->is_multipoint) {
Hans de Goede6cc2af62015-03-20 20:11:12 +0100598 musb_write_rxfunaddr(musb, epnum, qh->addr_reg);
599 musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg);
600 musb_write_rxhubport(musb, epnum, qh->h_port_reg);
Felipe Balbi550a7372008-07-24 12:27:36 +0300601 } else
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
603
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
Cliff Cai9f445cb2010-01-28 20:44:18 -0500608 /* Set RXMAXP with the FIFO size of the endpoint
609 * to disable double buffer mode.
610 */
Felipe Balbi06624812011-01-21 13:39:20 +0800611 if (musb->double_buffer_not_ok)
Cliff Cai9f445cb2010-01-28 20:44:18 -0500612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
613 else
614 musb_writew(ep->regs, MUSB_RXMAXP,
615 qh->maxpacket | ((qh->hb_mult - 1) << 11));
Felipe Balbi550a7372008-07-24 12:27:36 +0300616
617 ep->rx_reinit = 0;
618}
619
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700620static int musb_tx_dma_set_mode_mentor(struct dma_controller *dma,
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700621 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700622 struct urb *urb, u32 offset,
623 u32 *length, u8 *mode)
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700624{
625 struct dma_channel *channel = hw_ep->tx_channel;
626 void __iomem *epio = hw_ep->regs;
627 u16 pkt_size = qh->maxpacket;
628 u16 csr;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700629
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700630 if (*length > channel->max_len)
631 *length = channel->max_len;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700632
633 csr = musb_readw(epio, MUSB_TXCSR);
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700634 if (*length > pkt_size) {
635 *mode = 1;
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -0700636 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
637 /* autoset shouldn't be set in high bandwidth */
supriya karanthf2786282012-12-06 11:16:23 +0530638 /*
639 * Enable Autoset according to table
640 * below
641 * bulk_split hb_mult Autoset_Enable
642 * 0 1 Yes(Normal)
643 * 0 >1 No(High BW ISO)
644 * 1 1 Yes(HS bulk)
645 * 1 >1 Yes(FS bulk)
646 */
647 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
648 can_bulk_split(hw_ep->musb, qh->type)))
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -0700649 csr |= MUSB_TXCSR_AUTOSET;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700650 } else {
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700651 *mode = 0;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700652 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
653 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
654 }
655 channel->desired_mode = mode;
656 musb_writew(epio, MUSB_TXCSR, csr);
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700657
658 return 0;
659}
660
661static int musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma,
662 struct musb_hw_ep *hw_ep,
663 struct musb_qh *qh,
664 struct urb *urb,
665 u32 offset,
666 u32 *length,
667 u8 *mode)
668{
669 struct dma_channel *channel = hw_ep->tx_channel;
670
Tony Lindgrenf8e9f34f2015-05-01 12:29:27 -0700671 if (!is_cppi_enabled(hw_ep->musb) && !tusb_dma_omap(hw_ep->musb))
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700672 return -ENODEV;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700673
674 channel->actual_len = 0;
675
676 /*
677 * TX uses "RNDIS" mode automatically but needs help
678 * to identify the zero-length-final-packet case.
679 */
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700680 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
681
682 return 0;
683}
684
685static bool musb_tx_dma_program(struct dma_controller *dma,
686 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
687 struct urb *urb, u32 offset, u32 length)
688{
689 struct dma_channel *channel = hw_ep->tx_channel;
690 u16 pkt_size = qh->maxpacket;
691 u8 mode;
692 int res;
693
694 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb))
695 res = musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb,
696 offset, &length, &mode);
697 else
698 res = musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb,
699 offset, &length, &mode);
700 if (res)
701 return false;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700702
703 qh->segsize = length;
704
Santosh Shilimkar4c647332010-09-20 10:32:07 +0300705 /*
706 * Ensure the data reaches to main memory before starting
707 * DMA transfer
708 */
709 wmb();
710
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700711 if (!dma->channel_program(channel, pkt_size, mode,
712 urb->transfer_dma + offset, length)) {
Tony Lindgren754fe4a2015-05-01 12:29:32 -0700713 void __iomem *epio = hw_ep->regs;
714 u16 csr;
715
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700716 dma->channel_release(channel);
717 hw_ep->tx_channel = NULL;
718
719 csr = musb_readw(epio, MUSB_TXCSR);
720 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
721 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
722 return false;
723 }
724 return true;
725}
Felipe Balbi550a7372008-07-24 12:27:36 +0300726
727/*
728 * Program an HDRC endpoint as per the given URB
729 * Context: irqs blocked, controller lock held
730 */
731static void musb_ep_program(struct musb *musb, u8 epnum,
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700732 struct urb *urb, int is_out,
733 u8 *buf, u32 offset, u32 len)
Felipe Balbi550a7372008-07-24 12:27:36 +0300734{
735 struct dma_controller *dma_controller;
736 struct dma_channel *dma_channel;
737 u8 dma_ok;
738 void __iomem *mbase = musb->mregs;
739 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
740 void __iomem *epio = hw_ep->regs;
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700741 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
742 u16 packet_sz = qh->maxpacket;
Ajay Kumar Gupta31321222012-07-20 11:07:22 +0530743 u8 use_dma = 1;
744 u16 csr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300745
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300746 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
Felipe Balbi550a7372008-07-24 12:27:36 +0300747 "h_addr%02x h_port%02x bytes %d\n",
748 is_out ? "-->" : "<--",
749 epnum, urb, urb->dev->speed,
750 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
751 qh->h_addr_reg, qh->h_port_reg,
752 len);
753
754 musb_ep_select(mbase, epnum);
755
Ajay Kumar Gupta31321222012-07-20 11:07:22 +0530756 if (is_out && !len) {
757 use_dma = 0;
758 csr = musb_readw(epio, MUSB_TXCSR);
759 csr &= ~MUSB_TXCSR_DMAENAB;
760 musb_writew(epio, MUSB_TXCSR, csr);
761 hw_ep->tx_channel = NULL;
762 }
763
Felipe Balbi550a7372008-07-24 12:27:36 +0300764 /* candidate for DMA? */
765 dma_controller = musb->dma_controller;
Ajay Kumar Gupta31321222012-07-20 11:07:22 +0530766 if (use_dma && is_dma_capable() && epnum && dma_controller) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300767 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
768 if (!dma_channel) {
769 dma_channel = dma_controller->channel_alloc(
770 dma_controller, hw_ep, is_out);
771 if (is_out)
772 hw_ep->tx_channel = dma_channel;
773 else
774 hw_ep->rx_channel = dma_channel;
775 }
776 } else
777 dma_channel = NULL;
778
779 /* make sure we clear DMAEnab, autoSet bits from previous run */
780
781 /* OUT/transmit/EP0 or IN/receive? */
782 if (is_out) {
783 u16 csr;
784 u16 int_txe;
785 u16 load_count;
786
787 csr = musb_readw(epio, MUSB_TXCSR);
788
789 /* disable interrupt in case we flush */
Sebastian Andrzej Siewiorb18d26f2012-10-30 19:52:26 +0100790 int_txe = musb->intrtxe;
Felipe Balbi550a7372008-07-24 12:27:36 +0300791 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
792
793 /* general endpoint setup */
794 if (epnum) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300795 /* flush all old state, set default */
supriya karantha70b8442013-01-04 17:10:33 +0530796 /*
797 * We could be flushing valid
798 * packets in double buffering
799 * case
800 */
801 if (!hw_ep->tx_double_buffered)
802 musb_h_tx_flush_fifo(hw_ep);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700803
804 /*
805 * We must not clear the DMAMODE bit before or in
806 * the same cycle with the DMAENAB bit, so we clear
807 * the latter first...
808 */
Felipe Balbi550a7372008-07-24 12:27:36 +0300809 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700810 | MUSB_TXCSR_AUTOSET
811 | MUSB_TXCSR_DMAENAB
Felipe Balbi550a7372008-07-24 12:27:36 +0300812 | MUSB_TXCSR_FRCDATATOG
813 | MUSB_TXCSR_H_RXSTALL
814 | MUSB_TXCSR_H_ERROR
815 | MUSB_TXCSR_TXPKTRDY
816 );
817 csr |= MUSB_TXCSR_MODE;
818
supriya karantha70b8442013-01-04 17:10:33 +0530819 if (!hw_ep->tx_double_buffered) {
820 if (usb_gettoggle(urb->dev, qh->epnum, 1))
821 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
822 | MUSB_TXCSR_H_DATATOGGLE;
823 else
824 csr |= MUSB_TXCSR_CLRDATATOG;
825 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300826
Felipe Balbi550a7372008-07-24 12:27:36 +0300827 musb_writew(epio, MUSB_TXCSR, csr);
828 /* REVISIT may need to clear FLUSHFIFO ... */
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700829 csr &= ~MUSB_TXCSR_DMAMODE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300830 musb_writew(epio, MUSB_TXCSR, csr);
831 csr = musb_readw(epio, MUSB_TXCSR);
832 } else {
833 /* endpoint 0: just flush */
David Brownell78322c12009-03-26 17:38:30 -0700834 musb_h_ep0_flush_fifo(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +0300835 }
836
837 /* target addr and (for multipoint) hub addr/port */
838 if (musb->is_multipoint) {
Hans de Goede6cc2af62015-03-20 20:11:12 +0100839 musb_write_txfunaddr(musb, epnum, qh->addr_reg);
840 musb_write_txhubaddr(musb, epnum, qh->h_addr_reg);
841 musb_write_txhubport(musb, epnum, qh->h_port_reg);
Felipe Balbi550a7372008-07-24 12:27:36 +0300842/* FIXME if !epnum, do the same for RX ... */
843 } else
844 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
845
846 /* protocol/endpoint/interval/NAKlimit */
847 if (epnum) {
848 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
supriya karanthf2786282012-12-06 11:16:23 +0530849 if (musb->double_buffer_not_ok) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300850 musb_writew(epio, MUSB_TXMAXP,
Felipe Balbi06624812011-01-21 13:39:20 +0800851 hw_ep->max_packet_sz_tx);
supriya karanthf2786282012-12-06 11:16:23 +0530852 } else if (can_bulk_split(musb, qh->type)) {
853 qh->hb_mult = hw_ep->max_packet_sz_tx
854 / packet_sz;
Ajay Kumar Guptaccc080c2011-12-13 10:32:42 +0530855 musb_writew(epio, MUSB_TXMAXP, packet_sz
supriya karanthf2786282012-12-06 11:16:23 +0530856 | ((qh->hb_mult) - 1) << 11);
857 } else {
Felipe Balbi550a7372008-07-24 12:27:36 +0300858 musb_writew(epio, MUSB_TXMAXP,
Felipe Balbi06624812011-01-21 13:39:20 +0800859 qh->maxpacket |
860 ((qh->hb_mult - 1) << 11));
supriya karanthf2786282012-12-06 11:16:23 +0530861 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300862 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
863 } else {
864 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
865 if (musb->is_multipoint)
866 musb_writeb(epio, MUSB_TYPE0,
867 qh->type_reg);
868 }
869
870 if (can_bulk_split(musb, qh->type))
871 load_count = min((u32) hw_ep->max_packet_sz_tx,
872 len);
873 else
874 load_count = min((u32) packet_sz, len);
875
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700876 if (dma_channel && musb_tx_dma_program(dma_controller,
877 hw_ep, qh, urb, offset, len))
878 load_count = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300879
880 if (load_count) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300881 /* PIO to load FIFO */
882 qh->segsize = load_count;
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +0530883 if (!buf) {
884 sg_miter_start(&qh->sg_miter, urb->sg, 1,
885 SG_MITER_ATOMIC
886 | SG_MITER_FROM_SG);
887 if (!sg_miter_next(&qh->sg_miter)) {
888 dev_err(musb->controller,
889 "error: sg"
890 "list empty\n");
891 sg_miter_stop(&qh->sg_miter);
892 goto finish;
893 }
894 buf = qh->sg_miter.addr + urb->sg->offset +
895 urb->actual_length;
896 load_count = min_t(u32, load_count,
897 qh->sg_miter.length);
898 musb_write_fifo(hw_ep, load_count, buf);
899 qh->sg_miter.consumed = load_count;
900 sg_miter_stop(&qh->sg_miter);
901 } else
902 musb_write_fifo(hw_ep, load_count, buf);
Felipe Balbi550a7372008-07-24 12:27:36 +0300903 }
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +0530904finish:
Felipe Balbi550a7372008-07-24 12:27:36 +0300905 /* re-enable interrupt */
906 musb_writew(mbase, MUSB_INTRTXE, int_txe);
907
908 /* IN/receive */
909 } else {
910 u16 csr;
911
912 if (hw_ep->rx_reinit) {
Hans de Goede0cb74b32015-03-20 20:11:11 +0100913 musb_rx_reinit(musb, qh, epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +0300914
915 /* init new state: toggle and NYET, maybe DMA later */
916 if (usb_gettoggle(urb->dev, qh->epnum, 0))
917 csr = MUSB_RXCSR_H_WR_DATATOGGLE
918 | MUSB_RXCSR_H_DATATOGGLE;
919 else
920 csr = 0;
921 if (qh->type == USB_ENDPOINT_XFER_INT)
922 csr |= MUSB_RXCSR_DISNYET;
923
924 } else {
925 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
926
927 if (csr & (MUSB_RXCSR_RXPKTRDY
928 | MUSB_RXCSR_DMAENAB
929 | MUSB_RXCSR_H_REQPKT))
930 ERR("broken !rx_reinit, ep%d csr %04x\n",
931 hw_ep->epnum, csr);
932
933 /* scrub any stale state, leaving toggle alone */
934 csr &= MUSB_RXCSR_DISNYET;
935 }
936
937 /* kick things off */
938
Tony Lindgrenf8e9f34f2015-05-01 12:29:27 -0700939 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) {
Sergei Shtylyovc51e36d2011-05-07 19:44:13 +0400940 /* Candidate for DMA */
941 dma_channel->actual_len = 0L;
942 qh->segsize = len;
Felipe Balbi550a7372008-07-24 12:27:36 +0300943
Sergei Shtylyovc51e36d2011-05-07 19:44:13 +0400944 /* AUTOREQ is in a DMA register */
945 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
946 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300947
Sergei Shtylyovc51e36d2011-05-07 19:44:13 +0400948 /*
949 * Unless caller treats short RX transfers as
950 * errors, we dare not queue multiple transfers.
951 */
952 dma_ok = dma_controller->channel_program(dma_channel,
953 packet_sz, !(urb->transfer_flags &
954 URB_SHORT_NOT_OK),
955 urb->transfer_dma + offset,
956 qh->segsize);
957 if (!dma_ok) {
958 dma_controller->channel_release(dma_channel);
959 hw_ep->rx_channel = dma_channel = NULL;
960 } else
961 csr |= MUSB_RXCSR_DMAENAB;
Felipe Balbi550a7372008-07-24 12:27:36 +0300962 }
963
964 csr |= MUSB_RXCSR_H_REQPKT;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300965 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300966 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
967 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
968 }
969}
970
Ajay Kumar Guptaf2838622012-07-19 13:41:59 +0530971/* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
972 * the end; avoids starvation for other endpoints.
973 */
974static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
975 int is_in)
976{
977 struct dma_channel *dma;
978 struct urb *urb;
979 void __iomem *mbase = musb->mregs;
980 void __iomem *epio = ep->regs;
981 struct musb_qh *cur_qh, *next_qh;
982 u16 rx_csr, tx_csr;
983
984 musb_ep_select(mbase, ep->epnum);
985 if (is_in) {
986 dma = is_dma_capable() ? ep->rx_channel : NULL;
987
988 /* clear nak timeout bit */
989 rx_csr = musb_readw(epio, MUSB_RXCSR);
990 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
991 rx_csr &= ~MUSB_RXCSR_DATAERROR;
992 musb_writew(epio, MUSB_RXCSR, rx_csr);
993
994 cur_qh = first_qh(&musb->in_bulk);
995 } else {
996 dma = is_dma_capable() ? ep->tx_channel : NULL;
997
998 /* clear nak timeout bit */
999 tx_csr = musb_readw(epio, MUSB_TXCSR);
1000 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
1001 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
1002 musb_writew(epio, MUSB_TXCSR, tx_csr);
1003
1004 cur_qh = first_qh(&musb->out_bulk);
1005 }
1006 if (cur_qh) {
1007 urb = next_urb(cur_qh);
1008 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1009 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1010 musb->dma_controller->channel_abort(dma);
1011 urb->actual_length += dma->actual_len;
1012 dma->actual_len = 0L;
1013 }
1014 musb_save_toggle(cur_qh, is_in, urb);
1015
1016 if (is_in) {
1017 /* move cur_qh to end of queue */
1018 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1019
1020 /* get the next qh from musb->in_bulk */
1021 next_qh = first_qh(&musb->in_bulk);
1022
1023 /* set rx_reinit and schedule the next qh */
1024 ep->rx_reinit = 1;
1025 } else {
1026 /* move cur_qh to end of queue */
1027 list_move_tail(&cur_qh->ring, &musb->out_bulk);
1028
1029 /* get the next qh from musb->out_bulk */
1030 next_qh = first_qh(&musb->out_bulk);
1031
1032 /* set tx_reinit and schedule the next qh */
1033 ep->tx_reinit = 1;
1034 }
1035 musb_start_urb(musb, is_in, next_qh);
1036 }
1037}
Felipe Balbi550a7372008-07-24 12:27:36 +03001038
1039/*
1040 * Service the default endpoint (ep0) as host.
1041 * Return true until it's time to start the status stage.
1042 */
1043static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1044{
1045 bool more = false;
1046 u8 *fifo_dest = NULL;
1047 u16 fifo_count = 0;
1048 struct musb_hw_ep *hw_ep = musb->control_ep;
1049 struct musb_qh *qh = hw_ep->in_qh;
1050 struct usb_ctrlrequest *request;
1051
1052 switch (musb->ep0_stage) {
1053 case MUSB_EP0_IN:
1054 fifo_dest = urb->transfer_buffer + urb->actual_length;
Sergei Shtylyov3ecdb9a2009-02-21 15:31:23 -08001055 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1056 urb->actual_length);
Felipe Balbi550a7372008-07-24 12:27:36 +03001057 if (fifo_count < len)
1058 urb->status = -EOVERFLOW;
1059
1060 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1061
1062 urb->actual_length += fifo_count;
1063 if (len < qh->maxpacket) {
1064 /* always terminate on short read; it's
1065 * rarely reported as an error.
1066 */
1067 } else if (urb->actual_length <
1068 urb->transfer_buffer_length)
1069 more = true;
1070 break;
1071 case MUSB_EP0_START:
1072 request = (struct usb_ctrlrequest *) urb->setup_packet;
1073
1074 if (!request->wLength) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001075 dev_dbg(musb->controller, "start no-DATA\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03001076 break;
1077 } else if (request->bRequestType & USB_DIR_IN) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001078 dev_dbg(musb->controller, "start IN-DATA\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03001079 musb->ep0_stage = MUSB_EP0_IN;
1080 more = true;
1081 break;
1082 } else {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001083 dev_dbg(musb->controller, "start OUT-DATA\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03001084 musb->ep0_stage = MUSB_EP0_OUT;
1085 more = true;
1086 }
1087 /* FALLTHROUGH */
1088 case MUSB_EP0_OUT:
Sergei Shtylyov3ecdb9a2009-02-21 15:31:23 -08001089 fifo_count = min_t(size_t, qh->maxpacket,
1090 urb->transfer_buffer_length -
1091 urb->actual_length);
Felipe Balbi550a7372008-07-24 12:27:36 +03001092 if (fifo_count) {
1093 fifo_dest = (u8 *) (urb->transfer_buffer
1094 + urb->actual_length);
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001095 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
David Brownellbb1c9ef2008-11-24 13:06:50 +02001096 fifo_count,
1097 (fifo_count == 1) ? "" : "s",
1098 fifo_dest);
Felipe Balbi550a7372008-07-24 12:27:36 +03001099 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1100
1101 urb->actual_length += fifo_count;
1102 more = true;
1103 }
1104 break;
1105 default:
1106 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1107 break;
1108 }
1109
1110 return more;
1111}
1112
1113/*
1114 * Handle default endpoint interrupt as host. Only called in IRQ time
David Brownellc767c1c2008-09-11 11:53:23 +03001115 * from musb_interrupt().
Felipe Balbi550a7372008-07-24 12:27:36 +03001116 *
1117 * called with controller irqlocked
1118 */
1119irqreturn_t musb_h_ep0_irq(struct musb *musb)
1120{
1121 struct urb *urb;
1122 u16 csr, len;
1123 int status = 0;
1124 void __iomem *mbase = musb->mregs;
1125 struct musb_hw_ep *hw_ep = musb->control_ep;
1126 void __iomem *epio = hw_ep->regs;
1127 struct musb_qh *qh = hw_ep->in_qh;
1128 bool complete = false;
1129 irqreturn_t retval = IRQ_NONE;
1130
1131 /* ep0 only has one queue, "in" */
1132 urb = next_urb(qh);
1133
1134 musb_ep_select(mbase, 0);
1135 csr = musb_readw(epio, MUSB_CSR0);
1136 len = (csr & MUSB_CSR0_RXPKTRDY)
1137 ? musb_readb(epio, MUSB_COUNT0)
1138 : 0;
1139
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001140 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
Felipe Balbi550a7372008-07-24 12:27:36 +03001141 csr, qh, len, urb, musb->ep0_stage);
1142
1143 /* if we just did status stage, we are done */
1144 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1145 retval = IRQ_HANDLED;
1146 complete = true;
1147 }
1148
1149 /* prepare status */
1150 if (csr & MUSB_CSR0_H_RXSTALL) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001151 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03001152 status = -EPIPE;
1153
1154 } else if (csr & MUSB_CSR0_H_ERROR) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001155 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
Felipe Balbi550a7372008-07-24 12:27:36 +03001156 status = -EPROTO;
1157
1158 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001159 dev_dbg(musb->controller, "control NAK timeout\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03001160
1161 /* NOTE: this code path would be a good place to PAUSE a
1162 * control transfer, if another one is queued, so that
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001163 * ep0 is more likely to stay busy. That's already done
1164 * for bulk RX transfers.
Felipe Balbi550a7372008-07-24 12:27:36 +03001165 *
1166 * if (qh->ring.next != &musb->control), then
1167 * we have a candidate... NAKing is *NOT* an error
1168 */
1169 musb_writew(epio, MUSB_CSR0, 0);
1170 retval = IRQ_HANDLED;
1171 }
1172
1173 if (status) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001174 dev_dbg(musb->controller, "aborting\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03001175 retval = IRQ_HANDLED;
1176 if (urb)
1177 urb->status = status;
1178 complete = true;
1179
1180 /* use the proper sequence to abort the transfer */
1181 if (csr & MUSB_CSR0_H_REQPKT) {
1182 csr &= ~MUSB_CSR0_H_REQPKT;
1183 musb_writew(epio, MUSB_CSR0, csr);
1184 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1185 musb_writew(epio, MUSB_CSR0, csr);
1186 } else {
David Brownell78322c12009-03-26 17:38:30 -07001187 musb_h_ep0_flush_fifo(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +03001188 }
1189
1190 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1191
1192 /* clear it */
1193 musb_writew(epio, MUSB_CSR0, 0);
1194 }
1195
1196 if (unlikely(!urb)) {
1197 /* stop endpoint since we have no place for its data, this
1198 * SHOULD NEVER HAPPEN! */
1199 ERR("no URB for end 0\n");
1200
David Brownell78322c12009-03-26 17:38:30 -07001201 musb_h_ep0_flush_fifo(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +03001202 goto done;
1203 }
1204
1205 if (!complete) {
1206 /* call common logic and prepare response */
1207 if (musb_h_ep0_continue(musb, len, urb)) {
1208 /* more packets required */
1209 csr = (MUSB_EP0_IN == musb->ep0_stage)
1210 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1211 } else {
1212 /* data transfer complete; perform status phase */
1213 if (usb_pipeout(urb->pipe)
1214 || !urb->transfer_buffer_length)
1215 csr = MUSB_CSR0_H_STATUSPKT
1216 | MUSB_CSR0_H_REQPKT;
1217 else
1218 csr = MUSB_CSR0_H_STATUSPKT
1219 | MUSB_CSR0_TXPKTRDY;
1220
Ajay Kumar Gupta3c4653c2014-02-04 15:28:06 +02001221 /* disable ping token in status phase */
1222 csr |= MUSB_CSR0_H_DIS_PING;
1223
Felipe Balbi550a7372008-07-24 12:27:36 +03001224 /* flag status stage */
1225 musb->ep0_stage = MUSB_EP0_STATUS;
1226
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001227 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
Felipe Balbi550a7372008-07-24 12:27:36 +03001228
1229 }
1230 musb_writew(epio, MUSB_CSR0, csr);
1231 retval = IRQ_HANDLED;
1232 } else
1233 musb->ep0_stage = MUSB_EP0_IDLE;
1234
1235 /* call completion handler if done */
1236 if (complete)
1237 musb_advance_schedule(musb, urb, hw_ep, 1);
1238done:
1239 return retval;
1240}
1241
1242
1243#ifdef CONFIG_USB_INVENTRA_DMA
1244
1245/* Host side TX (OUT) using Mentor DMA works as follows:
1246 submit_urb ->
1247 - if queue was empty, Program Endpoint
1248 - ... which starts DMA to fifo in mode 1 or 0
1249
1250 DMA Isr (transfer complete) -> TxAvail()
1251 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1252 only in musb_cleanup_urb)
1253 - TxPktRdy has to be set in mode 0 or for
1254 short packets in mode 1.
1255*/
1256
1257#endif
1258
1259/* Service a Tx-Available or dma completion irq for the endpoint */
1260void musb_host_tx(struct musb *musb, u8 epnum)
1261{
1262 int pipe;
1263 bool done = false;
1264 u16 tx_csr;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001265 size_t length = 0;
1266 size_t offset = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +03001267 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1268 void __iomem *epio = hw_ep->regs;
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -07001269 struct musb_qh *qh = hw_ep->out_qh;
1270 struct urb *urb = next_urb(qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03001271 u32 status = 0;
1272 void __iomem *mbase = musb->mregs;
1273 struct dma_channel *dma;
T. S., Anil Kumarf8afbf7f2010-09-24 13:44:09 +03001274 bool transfer_pending = false;
Felipe Balbi550a7372008-07-24 12:27:36 +03001275
Felipe Balbi550a7372008-07-24 12:27:36 +03001276 musb_ep_select(mbase, epnum);
1277 tx_csr = musb_readw(epio, MUSB_TXCSR);
1278
1279 /* with CPPI, DMA sometimes triggers "extra" irqs */
1280 if (!urb) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001281 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001282 return;
Felipe Balbi550a7372008-07-24 12:27:36 +03001283 }
1284
1285 pipe = urb->pipe;
1286 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001287 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
Felipe Balbi550a7372008-07-24 12:27:36 +03001288 dma ? ", dma" : "");
1289
1290 /* check for errors */
1291 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1292 /* dma was disabled, fifo flushed */
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001293 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +03001294
1295 /* stall; record URB status */
1296 status = -EPIPE;
1297
1298 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1299 /* (NON-ISO) dma was disabled, fifo flushed */
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001300 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +03001301
1302 status = -ETIMEDOUT;
1303
1304 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
Ajay Kumar Guptaf2838622012-07-19 13:41:59 +05301305 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1306 && !list_is_singular(&musb->out_bulk)) {
1307 dev_dbg(musb->controller,
1308 "NAK timeout on TX%d ep\n", epnum);
1309 musb_bulk_nak_timeout(musb, hw_ep, 0);
1310 } else {
1311 dev_dbg(musb->controller,
1312 "TX end=%d device not responding\n", epnum);
1313 /* NOTE: this code path would be a good place to PAUSE a
1314 * transfer, if there's some other (nonperiodic) tx urb
1315 * that could use this fifo. (dma complicates it...)
1316 * That's already done for bulk RX transfers.
1317 *
1318 * if (bulk && qh->ring.next != &musb->out_bulk), then
1319 * we have a candidate... NAKing is *NOT* an error
1320 */
1321 musb_ep_select(mbase, epnum);
1322 musb_writew(epio, MUSB_TXCSR,
1323 MUSB_TXCSR_H_WZC_BITS
1324 | MUSB_TXCSR_TXPKTRDY);
1325 }
1326 return;
Felipe Balbi550a7372008-07-24 12:27:36 +03001327 }
1328
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301329done:
Felipe Balbi550a7372008-07-24 12:27:36 +03001330 if (status) {
1331 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1332 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
Daniel Mack9c547692014-05-26 14:52:35 +02001333 musb->dma_controller->channel_abort(dma);
Felipe Balbi550a7372008-07-24 12:27:36 +03001334 }
1335
1336 /* do the proper sequence to abort the transfer in the
1337 * usb core; the dma engine should already be stopped.
1338 */
1339 musb_h_tx_flush_fifo(hw_ep);
1340 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1341 | MUSB_TXCSR_DMAENAB
1342 | MUSB_TXCSR_H_ERROR
1343 | MUSB_TXCSR_H_RXSTALL
1344 | MUSB_TXCSR_H_NAKTIMEOUT
1345 );
1346
1347 musb_ep_select(mbase, epnum);
1348 musb_writew(epio, MUSB_TXCSR, tx_csr);
1349 /* REVISIT may need to clear FLUSHFIFO ... */
1350 musb_writew(epio, MUSB_TXCSR, tx_csr);
1351 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1352
1353 done = true;
1354 }
1355
1356 /* second cppi case */
1357 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001358 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001359 return;
Felipe Balbi550a7372008-07-24 12:27:36 +03001360 }
1361
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -07001362 if (is_dma_capable() && dma && !status) {
1363 /*
1364 * DMA has completed. But if we're using DMA mode 1 (multi
1365 * packet DMA), we need a terminal TXPKTRDY interrupt before
1366 * we can consider this transfer completed, lest we trash
1367 * its last packet when writing the next URB's data. So we
1368 * switch back to mode 0 to get that interrupt; we'll come
1369 * back here once it happens.
1370 */
1371 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1372 /*
1373 * We shouldn't clear DMAMODE with DMAENAB set; so
1374 * clear them in a safe order. That should be OK
1375 * once TXPKTRDY has been set (and I've never seen
1376 * it being 0 at this moment -- DMA interrupt latency
1377 * is significant) but if it hasn't been then we have
1378 * no choice but to stop being polite and ignore the
1379 * programmer's guide... :-)
1380 *
1381 * Note that we must write TXCSR with TXPKTRDY cleared
1382 * in order not to re-trigger the packet send (this bit
1383 * can't be cleared by CPU), and there's another caveat:
1384 * TXPKTRDY may be set shortly and then cleared in the
1385 * double-buffered FIFO mode, so we do an extra TXCSR
1386 * read for debouncing...
1387 */
1388 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1389 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1390 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1391 MUSB_TXCSR_TXPKTRDY);
1392 musb_writew(epio, MUSB_TXCSR,
1393 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1394 }
1395 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1396 MUSB_TXCSR_TXPKTRDY);
1397 musb_writew(epio, MUSB_TXCSR,
1398 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1399
1400 /*
1401 * There is no guarantee that we'll get an interrupt
1402 * after clearing DMAMODE as we might have done this
1403 * too late (after TXPKTRDY was cleared by controller).
1404 * Re-read TXCSR as we have spoiled its previous value.
1405 */
1406 tx_csr = musb_readw(epio, MUSB_TXCSR);
1407 }
1408
1409 /*
1410 * We may get here from a DMA completion or TXPKTRDY interrupt.
1411 * In any case, we must check the FIFO status here and bail out
1412 * only if the FIFO still has data -- that should prevent the
1413 * "missed" TXPKTRDY interrupts and deal with double-buffered
1414 * FIFO mode too...
1415 */
1416 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001417 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -07001418 "CSR %04x\n", tx_csr);
1419 return;
1420 }
1421 }
1422
Felipe Balbi550a7372008-07-24 12:27:36 +03001423 if (!status || dma || usb_pipeisoc(pipe)) {
1424 if (dma)
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001425 length = dma->actual_len;
Felipe Balbi550a7372008-07-24 12:27:36 +03001426 else
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001427 length = qh->segsize;
1428 qh->offset += length;
Felipe Balbi550a7372008-07-24 12:27:36 +03001429
1430 if (usb_pipeisoc(pipe)) {
1431 struct usb_iso_packet_descriptor *d;
1432
1433 d = urb->iso_frame_desc + qh->iso_idx;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001434 d->actual_length = length;
1435 d->status = status;
Felipe Balbi550a7372008-07-24 12:27:36 +03001436 if (++qh->iso_idx >= urb->number_of_packets) {
1437 done = true;
1438 } else {
1439 d++;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001440 offset = d->offset;
1441 length = d->length;
Felipe Balbi550a7372008-07-24 12:27:36 +03001442 }
T. S., Anil Kumarf8afbf7f2010-09-24 13:44:09 +03001443 } else if (dma && urb->transfer_buffer_length == qh->offset) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001444 done = true;
1445 } else {
1446 /* see if we need to send more data, or ZLP */
1447 if (qh->segsize < qh->maxpacket)
1448 done = true;
1449 else if (qh->offset == urb->transfer_buffer_length
1450 && !(urb->transfer_flags
1451 & URB_ZERO_PACKET))
1452 done = true;
1453 if (!done) {
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001454 offset = qh->offset;
1455 length = urb->transfer_buffer_length - offset;
T. S., Anil Kumarf8afbf7f2010-09-24 13:44:09 +03001456 transfer_pending = true;
Felipe Balbi550a7372008-07-24 12:27:36 +03001457 }
1458 }
1459 }
1460
1461 /* urb->status != -EINPROGRESS means request has been faulted,
1462 * so we must abort this transfer after cleanup
1463 */
1464 if (urb->status != -EINPROGRESS) {
1465 done = true;
1466 if (status == 0)
1467 status = urb->status;
1468 }
1469
1470 if (done) {
1471 /* set status */
1472 urb->status = status;
1473 urb->actual_length = qh->offset;
1474 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001475 return;
T. S., Anil Kumarf8afbf7f2010-09-24 13:44:09 +03001476 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001477 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
Ajay Kumar Guptadfeffa52009-11-17 15:22:55 +05301478 offset, length)) {
Tony Lindgrenf8e9f34f2015-05-01 12:29:27 -07001479 if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
Ajay Kumar Guptadfeffa52009-11-17 15:22:55 +05301480 musb_h_tx_dma_start(hw_ep);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001481 return;
Ajay Kumar Guptadfeffa52009-11-17 15:22:55 +05301482 }
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001483 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001484 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001485 return;
1486 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001487
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001488 /*
1489 * PIO: start next packet in this URB.
1490 *
1491 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1492 * (and presumably, FIFO is not half-full) we should write *two*
1493 * packets before updating TXCSR; other docs disagree...
1494 */
1495 if (length > qh->maxpacket)
1496 length = qh->maxpacket;
Maulik Mankad496dda72010-09-24 13:44:06 +03001497 /* Unmap the buffer so that CPU can use it */
Daniel Mack8b125df2013-04-10 21:55:50 +02001498 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301499
1500 /*
1501 * We need to map sg if the transfer_buffer is
1502 * NULL.
1503 */
1504 if (!urb->transfer_buffer)
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02001505 qh->use_sg = true;
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301506
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02001507 if (qh->use_sg) {
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301508 /* sg_miter_start is already done in musb_ep_program */
1509 if (!sg_miter_next(&qh->sg_miter)) {
1510 dev_err(musb->controller, "error: sg list empty\n");
1511 sg_miter_stop(&qh->sg_miter);
1512 status = -EINVAL;
1513 goto done;
1514 }
1515 urb->transfer_buffer = qh->sg_miter.addr;
1516 length = min_t(u32, length, qh->sg_miter.length);
1517 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1518 qh->sg_miter.consumed = length;
1519 sg_miter_stop(&qh->sg_miter);
1520 } else {
1521 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1522 }
1523
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001524 qh->segsize = length;
Felipe Balbi550a7372008-07-24 12:27:36 +03001525
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02001526 if (qh->use_sg) {
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301527 if (offset + length >= urb->transfer_buffer_length)
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02001528 qh->use_sg = false;
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301529 }
1530
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001531 musb_ep_select(mbase, epnum);
1532 musb_writew(epio, MUSB_TXCSR,
1533 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
Felipe Balbi550a7372008-07-24 12:27:36 +03001534}
1535
Tony Lindgren069a3fd2015-05-01 12:29:33 -07001536#ifdef CONFIG_USB_TI_CPPI41_DMA
1537/* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */
1538static int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1539 struct musb_hw_ep *hw_ep,
1540 struct musb_qh *qh,
1541 struct urb *urb,
1542 size_t len)
1543{
1544 struct dma_channel *channel = hw_ep->tx_channel;
1545 void __iomem *epio = hw_ep->regs;
1546 dma_addr_t *buf;
1547 u32 length, res;
1548 u16 val;
1549
1550 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset +
1551 (u32)urb->transfer_dma;
1552
1553 length = urb->iso_frame_desc[qh->iso_idx].length;
1554
1555 val = musb_readw(epio, MUSB_RXCSR);
1556 val |= MUSB_RXCSR_DMAENAB;
1557 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1558
1559 res = dma->channel_program(channel, qh->maxpacket, 0,
1560 (u32)buf, length);
1561
1562 return res;
1563}
1564#else
1565static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1566 struct musb_hw_ep *hw_ep,
1567 struct musb_qh *qh,
1568 struct urb *urb,
1569 size_t len)
1570{
1571 return false;
1572}
1573#endif
Felipe Balbi550a7372008-07-24 12:27:36 +03001574
Tony Lindgrencff84bd2015-05-01 12:29:35 -07001575#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1576 defined(CONFIG_USB_TI_CPPI41_DMA)
Felipe Balbi550a7372008-07-24 12:27:36 +03001577/* Host side RX (IN) using Mentor DMA works as follows:
1578 submit_urb ->
1579 - if queue was empty, ProgramEndpoint
1580 - first IN token is sent out (by setting ReqPkt)
1581 LinuxIsr -> RxReady()
1582 /\ => first packet is received
1583 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1584 | -> DMA Isr (transfer complete) -> RxReady()
1585 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1586 | - if urb not complete, send next IN token (ReqPkt)
1587 | | else complete urb.
1588 | |
1589 ---------------------------
1590 *
1591 * Nuances of mode 1:
1592 * For short packets, no ack (+RxPktRdy) is sent automatically
1593 * (even if AutoClear is ON)
1594 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1595 * automatically => major problem, as collecting the next packet becomes
1596 * difficult. Hence mode 1 is not used.
1597 *
1598 * REVISIT
1599 * All we care about at this driver level is that
1600 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1601 * (b) termination conditions are: short RX, or buffer full;
1602 * (c) fault modes include
1603 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1604 * (and that endpoint's dma queue stops immediately)
1605 * - overflow (full, PLUS more bytes in the terminal packet)
1606 *
1607 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1608 * thus be a great candidate for using mode 1 ... for all but the
1609 * last packet of one URB's transfer.
1610 */
Tony Lindgrencff84bd2015-05-01 12:29:35 -07001611static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1612 struct musb_hw_ep *hw_ep,
1613 struct musb_qh *qh,
1614 struct urb *urb,
1615 size_t len)
1616{
1617 struct dma_channel *channel = hw_ep->rx_channel;
1618 void __iomem *epio = hw_ep->regs;
1619 u16 val;
1620 int pipe;
1621 bool done;
Felipe Balbi550a7372008-07-24 12:27:36 +03001622
Tony Lindgrencff84bd2015-05-01 12:29:35 -07001623 pipe = urb->pipe;
1624
1625 if (usb_pipeisoc(pipe)) {
1626 struct usb_iso_packet_descriptor *d;
1627
1628 d = urb->iso_frame_desc + qh->iso_idx;
1629 d->actual_length = len;
1630
1631 /* even if there was an error, we did the dma
1632 * for iso_frame_desc->length
1633 */
1634 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1635 d->status = 0;
1636
1637 if (++qh->iso_idx >= urb->number_of_packets) {
1638 done = true;
1639 } else {
1640 /* REVISIT: Why ignore return value here? */
1641 if (musb_dma_cppi41(hw_ep->musb))
1642 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh,
1643 urb, len);
1644 done = false;
1645 }
1646
1647 } else {
1648 /* done if urb buffer is full or short packet is recd */
1649 done = (urb->actual_length + len >=
1650 urb->transfer_buffer_length
1651 || channel->actual_len < qh->maxpacket
1652 || channel->rx_packet_done);
1653 }
1654
1655 /* send IN token for next packet, without AUTOREQ */
1656 if (!done) {
1657 val = musb_readw(epio, MUSB_RXCSR);
1658 val |= MUSB_RXCSR_H_REQPKT;
1659 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1660 }
1661
1662 return done;
1663}
Tony Lindgrenac33cdb2015-05-01 12:29:37 -07001664
1665/* Disadvantage of using mode 1:
1666 * It's basically usable only for mass storage class; essentially all
1667 * other protocols also terminate transfers on short packets.
1668 *
1669 * Details:
1670 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1671 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1672 * to use the extra IN token to grab the last packet using mode 0, then
1673 * the problem is that you cannot be sure when the device will send the
1674 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1675 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1676 * transfer, while sometimes it is recd just a little late so that if you
1677 * try to configure for mode 0 soon after the mode 1 transfer is
1678 * completed, you will find rxcount 0. Okay, so you might think why not
1679 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1680 */
1681static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1682 struct musb_hw_ep *hw_ep,
1683 struct musb_qh *qh,
1684 struct urb *urb,
1685 size_t len,
1686 u8 iso_err)
1687{
1688 struct musb *musb = hw_ep->musb;
1689 void __iomem *epio = hw_ep->regs;
1690 struct dma_channel *channel = hw_ep->rx_channel;
1691 u16 rx_count, val;
1692 int length, pipe, done;
1693 dma_addr_t buf;
1694
1695 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1696 pipe = urb->pipe;
1697
1698 if (usb_pipeisoc(pipe)) {
1699 int d_status = 0;
1700 struct usb_iso_packet_descriptor *d;
1701
1702 d = urb->iso_frame_desc + qh->iso_idx;
1703
1704 if (iso_err) {
1705 d_status = -EILSEQ;
1706 urb->error_count++;
1707 }
1708 if (rx_count > d->length) {
1709 if (d_status == 0) {
1710 d_status = -EOVERFLOW;
1711 urb->error_count++;
1712 }
1713 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",
1714 rx_count, d->length);
1715
1716 length = d->length;
1717 } else
1718 length = rx_count;
1719 d->status = d_status;
1720 buf = urb->transfer_dma + d->offset;
1721 } else {
1722 length = rx_count;
1723 buf = urb->transfer_dma + urb->actual_length;
1724 }
1725
1726 channel->desired_mode = 0;
1727#ifdef USE_MODE1
1728 /* because of the issue below, mode 1 will
1729 * only rarely behave with correct semantics.
1730 */
1731 if ((urb->transfer_flags & URB_SHORT_NOT_OK)
1732 && (urb->transfer_buffer_length - urb->actual_length)
1733 > qh->maxpacket)
1734 channel->desired_mode = 1;
1735 if (rx_count < hw_ep->max_packet_sz_rx) {
1736 length = rx_count;
1737 channel->desired_mode = 0;
1738 } else {
1739 length = urb->transfer_buffer_length;
1740 }
1741#endif
1742
1743 /* See comments above on disadvantages of using mode 1 */
1744 val = musb_readw(epio, MUSB_RXCSR);
1745 val &= ~MUSB_RXCSR_H_REQPKT;
1746
1747 if (channel->desired_mode == 0)
1748 val &= ~MUSB_RXCSR_H_AUTOREQ;
1749 else
1750 val |= MUSB_RXCSR_H_AUTOREQ;
1751 val |= MUSB_RXCSR_DMAENAB;
1752
1753 /* autoclear shouldn't be set in high bandwidth */
1754 if (qh->hb_mult == 1)
1755 val |= MUSB_RXCSR_AUTOCLEAR;
1756
1757 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1758
1759 /* REVISIT if when actual_length != 0,
1760 * transfer_buffer_length needs to be
1761 * adjusted first...
1762 */
1763 done = dma->channel_program(channel, qh->maxpacket,
1764 channel->desired_mode,
1765 buf, length);
1766
1767 if (!done) {
1768 dma->channel_release(channel);
1769 hw_ep->rx_channel = NULL;
1770 channel = NULL;
1771 val = musb_readw(epio, MUSB_RXCSR);
1772 val &= ~(MUSB_RXCSR_DMAENAB
1773 | MUSB_RXCSR_H_AUTOREQ
1774 | MUSB_RXCSR_AUTOCLEAR);
1775 musb_writew(epio, MUSB_RXCSR, val);
1776 }
1777
1778 return done;
1779}
Tony Lindgrencff84bd2015-05-01 12:29:35 -07001780#else
1781static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1782 struct musb_hw_ep *hw_ep,
1783 struct musb_qh *qh,
1784 struct urb *urb,
1785 size_t len)
1786{
1787 return false;
1788}
Tony Lindgrenac33cdb2015-05-01 12:29:37 -07001789
1790static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1791 struct musb_hw_ep *hw_ep,
1792 struct musb_qh *qh,
1793 struct urb *urb,
1794 size_t len,
1795 u8 iso_err)
1796{
1797 return false;
1798}
Felipe Balbi550a7372008-07-24 12:27:36 +03001799#endif
1800
1801/*
1802 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1803 * and high-bandwidth IN transfer cases.
1804 */
1805void musb_host_rx(struct musb *musb, u8 epnum)
1806{
1807 struct urb *urb;
1808 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
Tony Lindgrencff84bd2015-05-01 12:29:35 -07001809 struct dma_controller *c = musb->dma_controller;
Felipe Balbi550a7372008-07-24 12:27:36 +03001810 void __iomem *epio = hw_ep->regs;
1811 struct musb_qh *qh = hw_ep->in_qh;
1812 size_t xfer_len;
1813 void __iomem *mbase = musb->mregs;
1814 int pipe;
1815 u16 rx_csr, val;
1816 bool iso_err = false;
1817 bool done = false;
1818 u32 status;
1819 struct dma_channel *dma;
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05301820 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
Felipe Balbi550a7372008-07-24 12:27:36 +03001821
1822 musb_ep_select(mbase, epnum);
1823
1824 urb = next_urb(qh);
1825 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1826 status = 0;
1827 xfer_len = 0;
1828
1829 rx_csr = musb_readw(epio, MUSB_RXCSR);
1830 val = rx_csr;
1831
1832 if (unlikely(!urb)) {
1833 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1834 * usbtest #11 (unlinks) triggers it regularly, sometimes
1835 * with fifo full. (Only with DMA??)
1836 */
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001837 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
Felipe Balbi550a7372008-07-24 12:27:36 +03001838 musb_readw(epio, MUSB_RXCOUNT));
1839 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1840 return;
1841 }
1842
1843 pipe = urb->pipe;
1844
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001845 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
Felipe Balbi550a7372008-07-24 12:27:36 +03001846 epnum, rx_csr, urb->actual_length,
1847 dma ? dma->actual_len : 0);
1848
1849 /* check for errors, concurrent stall & unlink is not really
1850 * handled yet! */
1851 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001852 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +03001853
1854 /* stall; record URB status */
1855 status = -EPIPE;
1856
1857 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001858 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +03001859
1860 status = -EPROTO;
1861 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1862
1863 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1864
1865 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001866 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001867
1868 /* NOTE: NAKing is *NOT* an error, so we want to
1869 * continue. Except ... if there's a request for
1870 * another QH, use that instead of starving it.
1871 *
1872 * Devices like Ethernet and serial adapters keep
1873 * reads posted at all times, which will starve
1874 * other devices without this logic.
1875 */
1876 if (usb_pipebulk(urb->pipe)
1877 && qh->mux == 1
1878 && !list_is_singular(&musb->in_bulk)) {
Ajay Kumar Guptaf2838622012-07-19 13:41:59 +05301879 musb_bulk_nak_timeout(musb, hw_ep, 1);
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001880 return;
1881 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001882 musb_ep_select(mbase, epnum);
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001883 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1884 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1885 musb_writew(epio, MUSB_RXCSR, rx_csr);
Felipe Balbi550a7372008-07-24 12:27:36 +03001886
1887 goto finish;
1888 } else {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001889 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
Felipe Balbi550a7372008-07-24 12:27:36 +03001890 /* packet error reported later */
1891 iso_err = true;
1892 }
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001893 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001894 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001895 epnum);
1896 status = -EPROTO;
Felipe Balbi550a7372008-07-24 12:27:36 +03001897 }
1898
1899 /* faults abort the transfer */
1900 if (status) {
1901 /* clean up dma and collect transfer count */
1902 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1903 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
Daniel Mack9c547692014-05-26 14:52:35 +02001904 musb->dma_controller->channel_abort(dma);
Felipe Balbi550a7372008-07-24 12:27:36 +03001905 xfer_len = dma->actual_len;
1906 }
1907 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1908 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1909 done = true;
1910 goto finish;
1911 }
1912
1913 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1914 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1915 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1916 goto finish;
1917 }
1918
1919 /* thorough shutdown for now ... given more precise fault handling
1920 * and better queueing support, we might keep a DMA pipeline going
1921 * while processing this irq for earlier completions.
1922 */
1923
1924 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
Tony Lindgren557d5432015-05-01 12:29:34 -07001925 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) &&
1926 (rx_csr & MUSB_RXCSR_H_REQPKT)) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001927 /* REVISIT this happened for a while on some short reads...
1928 * the cleanup still needs investigation... looks bad...
1929 * and also duplicates dma cleanup code above ... plus,
1930 * shouldn't this be the "half full" double buffer case?
1931 */
1932 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1933 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
Daniel Mack9c547692014-05-26 14:52:35 +02001934 musb->dma_controller->channel_abort(dma);
Felipe Balbi550a7372008-07-24 12:27:36 +03001935 xfer_len = dma->actual_len;
1936 done = true;
1937 }
1938
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03001939 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
Felipe Balbi550a7372008-07-24 12:27:36 +03001940 xfer_len, dma ? ", dma" : "");
1941 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1942
1943 musb_ep_select(mbase, epnum);
1944 musb_writew(epio, MUSB_RXCSR,
1945 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1946 }
Tony Lindgren557d5432015-05-01 12:29:34 -07001947
Felipe Balbi550a7372008-07-24 12:27:36 +03001948 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1949 xfer_len = dma->actual_len;
1950
1951 val &= ~(MUSB_RXCSR_DMAENAB
1952 | MUSB_RXCSR_H_AUTOREQ
1953 | MUSB_RXCSR_AUTOCLEAR
1954 | MUSB_RXCSR_RXPKTRDY);
1955 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1956
Tony Lindgrencff84bd2015-05-01 12:29:35 -07001957 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1958 musb_dma_cppi41(musb)) {
1959 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len);
1960 dev_dbg(hw_ep->musb->controller,
1961 "ep %d dma %s, rxcsr %04x, rxcount %d\n",
1962 epnum, done ? "off" : "reset",
1963 musb_readw(epio, MUSB_RXCSR),
1964 musb_readw(epio, MUSB_RXCOUNT));
1965 } else {
1966 done = true;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001967 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001968
Felipe Balbi550a7372008-07-24 12:27:36 +03001969 } else if (urb->status == -EINPROGRESS) {
1970 /* if no errors, be sure a packet is ready for unloading */
1971 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1972 status = -EPROTO;
1973 ERR("Rx interrupt with no errors or packet!\n");
1974
1975 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1976
1977/* SCRUB (RX) */
1978 /* do the proper sequence to abort the transfer */
1979 musb_ep_select(mbase, epnum);
1980 val &= ~MUSB_RXCSR_H_REQPKT;
1981 musb_writew(epio, MUSB_RXCSR, val);
1982 goto finish;
1983 }
1984
1985 /* we are expecting IN packets */
Tony Lindgrene530bb82015-05-01 12:29:36 -07001986 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1987 musb_dma_cppi41(musb)) && dma) {
Tony Lindgrenac33cdb2015-05-01 12:29:37 -07001988 dev_dbg(hw_ep->musb->controller,
1989 "RX%d count %d, buffer 0x%llx len %d/%d\n",
1990 epnum, musb_readw(epio, MUSB_RXCOUNT),
1991 (unsigned long long) urb->transfer_dma
1992 + urb->actual_length,
1993 qh->offset,
1994 urb->transfer_buffer_length);
Felipe Balbi550a7372008-07-24 12:27:36 +03001995
Tony Lindgrenac33cdb2015-05-01 12:29:37 -07001996 done = musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh,
1997 urb, xfer_len,
1998 iso_err);
1999 if (done)
2000 goto finish;
Felipe Balbi550a7372008-07-24 12:27:36 +03002001 else
Tony Lindgrenac33cdb2015-05-01 12:29:37 -07002002 dev_err(musb->controller, "error: rx_dma failed\n");
Felipe Balbi550a7372008-07-24 12:27:36 +03002003 }
Felipe Balbi550a7372008-07-24 12:27:36 +03002004
2005 if (!dma) {
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05302006 unsigned int received_len;
2007
Maulik Mankad496dda72010-09-24 13:44:06 +03002008 /* Unmap the buffer so that CPU can use it */
Daniel Mack8b125df2013-04-10 21:55:50 +02002009 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05302010
2011 /*
2012 * We need to map sg if the transfer_buffer is
2013 * NULL.
2014 */
2015 if (!urb->transfer_buffer) {
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02002016 qh->use_sg = true;
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05302017 sg_miter_start(&qh->sg_miter, urb->sg, 1,
2018 sg_flags);
2019 }
2020
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02002021 if (qh->use_sg) {
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05302022 if (!sg_miter_next(&qh->sg_miter)) {
2023 dev_err(musb->controller, "error: sg list empty\n");
2024 sg_miter_stop(&qh->sg_miter);
2025 status = -EINVAL;
2026 done = true;
2027 goto finish;
2028 }
2029 urb->transfer_buffer = qh->sg_miter.addr;
2030 received_len = urb->actual_length;
2031 qh->offset = 0x0;
2032 done = musb_host_packet_rx(musb, urb, epnum,
2033 iso_err);
2034 /* Calculate the number of bytes received */
2035 received_len = urb->actual_length -
2036 received_len;
2037 qh->sg_miter.consumed = received_len;
2038 sg_miter_stop(&qh->sg_miter);
2039 } else {
2040 done = musb_host_packet_rx(musb, urb,
2041 epnum, iso_err);
2042 }
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03002043 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
Felipe Balbi550a7372008-07-24 12:27:36 +03002044 }
2045 }
2046
Felipe Balbi550a7372008-07-24 12:27:36 +03002047finish:
2048 urb->actual_length += xfer_len;
2049 qh->offset += xfer_len;
2050 if (done) {
Virupax Sadashivpetimathed74df12013-04-24 08:38:48 +02002051 if (qh->use_sg)
2052 qh->use_sg = false;
Virupax Sadashivpetimath8e8a5512012-08-07 14:46:20 +05302053
Felipe Balbi550a7372008-07-24 12:27:36 +03002054 if (urb->status == -EINPROGRESS)
2055 urb->status = status;
2056 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
2057 }
2058}
2059
2060/* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
2061 * the software schedule associates multiple such nodes with a given
2062 * host side hardware endpoint + direction; scheduling may activate
2063 * that hardware endpoint.
2064 */
2065static int musb_schedule(
2066 struct musb *musb,
2067 struct musb_qh *qh,
2068 int is_in)
2069{
Rickard Strandqvisteac44dc2014-06-01 15:48:12 +02002070 int idle = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +03002071 int best_diff;
2072 int best_end, epnum;
2073 struct musb_hw_ep *hw_ep = NULL;
2074 struct list_head *head = NULL;
Swaminathan S5274dab2009-12-28 13:40:37 +02002075 u8 toggle;
2076 u8 txtype;
2077 struct urb *urb = next_urb(qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03002078
2079 /* use fixed hardware for control and bulk */
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002080 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002081 head = &musb->control;
2082 hw_ep = musb->control_ep;
Felipe Balbi550a7372008-07-24 12:27:36 +03002083 goto success;
2084 }
2085
2086 /* else, periodic transfers get muxed to other endpoints */
2087
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08002088 /*
2089 * We know this qh hasn't been scheduled, so all we need to do
Felipe Balbi550a7372008-07-24 12:27:36 +03002090 * is choose which hardware endpoint to put it on ...
2091 *
2092 * REVISIT what we really want here is a regular schedule tree
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08002093 * like e.g. OHCI uses.
Felipe Balbi550a7372008-07-24 12:27:36 +03002094 */
2095 best_diff = 4096;
2096 best_end = -1;
2097
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08002098 for (epnum = 1, hw_ep = musb->endpoints + 1;
2099 epnum < musb->nr_endpoints;
2100 epnum++, hw_ep++) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002101 int diff;
2102
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -07002103 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
Felipe Balbi550a7372008-07-24 12:27:36 +03002104 continue;
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08002105
Felipe Balbi550a7372008-07-24 12:27:36 +03002106 if (hw_ep == musb->bulk_ep)
2107 continue;
2108
2109 if (is_in)
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07002110 diff = hw_ep->max_packet_sz_rx;
Felipe Balbi550a7372008-07-24 12:27:36 +03002111 else
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07002112 diff = hw_ep->max_packet_sz_tx;
2113 diff -= (qh->maxpacket * qh->hb_mult);
Felipe Balbi550a7372008-07-24 12:27:36 +03002114
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002115 if (diff >= 0 && best_diff > diff) {
Swaminathan S5274dab2009-12-28 13:40:37 +02002116
2117 /*
2118 * Mentor controller has a bug in that if we schedule
2119 * a BULK Tx transfer on an endpoint that had earlier
2120 * handled ISOC then the BULK transfer has to start on
2121 * a zero toggle. If the BULK transfer starts on a 1
2122 * toggle then this transfer will fail as the mentor
2123 * controller starts the Bulk transfer on a 0 toggle
2124 * irrespective of the programming of the toggle bits
2125 * in the TXCSR register. Check for this condition
2126 * while allocating the EP for a Tx Bulk transfer. If
2127 * so skip this EP.
2128 */
2129 hw_ep = musb->endpoints + epnum;
2130 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2131 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2132 >> 4) & 0x3;
2133 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2134 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2135 continue;
2136
Felipe Balbi550a7372008-07-24 12:27:36 +03002137 best_diff = diff;
2138 best_end = epnum;
2139 }
2140 }
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002141 /* use bulk reserved ep1 if no other ep is free */
Felipe Balbiaa5cbbe2008-11-17 09:08:16 +02002142 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002143 hw_ep = musb->bulk_ep;
2144 if (is_in)
2145 head = &musb->in_bulk;
2146 else
2147 head = &musb->out_bulk;
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002148
Ajay Kumar Guptaf2838622012-07-19 13:41:59 +05302149 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
Rahul Bedarkar5ae477b2014-01-02 19:27:47 +05302150 * multiplexed. This scheme does not work in high speed to full
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002151 * speed scenario as NAK interrupts are not coming from a
2152 * full speed device connected to a high speed device.
2153 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2154 * 4 (8 frame or 8ms) for FS device.
2155 */
Ajay Kumar Guptaf2838622012-07-19 13:41:59 +05302156 if (qh->dev)
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002157 qh->intv_reg =
2158 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002159 goto success;
2160 } else if (best_end < 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002161 return -ENOSPC;
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002162 }
Felipe Balbi550a7372008-07-24 12:27:36 +03002163
2164 idle = 1;
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002165 qh->mux = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +03002166 hw_ep = musb->endpoints + best_end;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03002167 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
Felipe Balbi550a7372008-07-24 12:27:36 +03002168success:
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02002169 if (head) {
2170 idle = list_empty(head);
2171 list_add_tail(&qh->ring, head);
2172 qh->mux = 1;
2173 }
Felipe Balbi550a7372008-07-24 12:27:36 +03002174 qh->hw_ep = hw_ep;
2175 qh->hep->hcpriv = qh;
2176 if (idle)
2177 musb_start_urb(musb, is_in, qh);
2178 return 0;
2179}
2180
2181static int musb_urb_enqueue(
2182 struct usb_hcd *hcd,
2183 struct urb *urb,
2184 gfp_t mem_flags)
2185{
2186 unsigned long flags;
2187 struct musb *musb = hcd_to_musb(hcd);
2188 struct usb_host_endpoint *hep = urb->ep;
David Brownell74bb3502009-03-26 17:36:57 -07002189 struct musb_qh *qh;
Felipe Balbi550a7372008-07-24 12:27:36 +03002190 struct usb_endpoint_descriptor *epd = &hep->desc;
2191 int ret;
2192 unsigned type_reg;
2193 unsigned interval;
2194
2195 /* host role must be active */
2196 if (!is_host_active(musb) || !musb->is_active)
2197 return -ENODEV;
2198
2199 spin_lock_irqsave(&musb->lock, flags);
2200 ret = usb_hcd_link_urb_to_ep(hcd, urb);
David Brownell74bb3502009-03-26 17:36:57 -07002201 qh = ret ? NULL : hep->hcpriv;
2202 if (qh)
2203 urb->hcpriv = qh;
Felipe Balbi550a7372008-07-24 12:27:36 +03002204 spin_unlock_irqrestore(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002205
2206 /* DMA mapping was already done, if needed, and this urb is on
David Brownell74bb3502009-03-26 17:36:57 -07002207 * hep->urb_list now ... so we're done, unless hep wasn't yet
2208 * scheduled onto a live qh.
Felipe Balbi550a7372008-07-24 12:27:36 +03002209 *
2210 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2211 * disabled, testing for empty qh->ring and avoiding qh setup costs
2212 * except for the first urb queued after a config change.
2213 */
David Brownell74bb3502009-03-26 17:36:57 -07002214 if (qh || ret)
2215 return ret;
Felipe Balbi550a7372008-07-24 12:27:36 +03002216
2217 /* Allocate and initialize qh, minimizing the work done each time
2218 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2219 *
2220 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2221 * for bugs in other kernel code to break this driver...
2222 */
2223 qh = kzalloc(sizeof *qh, mem_flags);
2224 if (!qh) {
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03002225 spin_lock_irqsave(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002226 usb_hcd_unlink_urb_from_ep(hcd, urb);
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03002227 spin_unlock_irqrestore(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002228 return -ENOMEM;
2229 }
2230
2231 qh->hep = hep;
2232 qh->dev = urb->dev;
2233 INIT_LIST_HEAD(&qh->ring);
2234 qh->is_ready = 1;
2235
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07002236 qh->maxpacket = usb_endpoint_maxp(epd);
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07002237 qh->type = usb_endpoint_type(epd);
Felipe Balbi550a7372008-07-24 12:27:36 +03002238
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07002239 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2240 * Some musb cores don't support high bandwidth ISO transfers; and
2241 * we don't (yet!) support high bandwidth interrupt transfers.
2242 */
2243 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2244 if (qh->hb_mult > 1) {
2245 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2246
2247 if (ok)
2248 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2249 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2250 if (!ok) {
2251 ret = -EMSGSIZE;
2252 goto done;
2253 }
2254 qh->maxpacket &= 0x7ff;
Felipe Balbi550a7372008-07-24 12:27:36 +03002255 }
2256
Julia Lawall96bcd092009-01-24 17:57:24 -08002257 qh->epnum = usb_endpoint_num(epd);
Felipe Balbi550a7372008-07-24 12:27:36 +03002258
2259 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2260 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2261
2262 /* precompute rxtype/txtype/type0 register */
2263 type_reg = (qh->type << 4) | qh->epnum;
2264 switch (urb->dev->speed) {
2265 case USB_SPEED_LOW:
2266 type_reg |= 0xc0;
2267 break;
2268 case USB_SPEED_FULL:
2269 type_reg |= 0x80;
2270 break;
2271 default:
2272 type_reg |= 0x40;
2273 }
2274 qh->type_reg = type_reg;
2275
Sergei Shtylyov136733d2009-02-21 15:31:35 -08002276 /* Precompute RXINTERVAL/TXINTERVAL register */
Felipe Balbi550a7372008-07-24 12:27:36 +03002277 switch (qh->type) {
2278 case USB_ENDPOINT_XFER_INT:
Sergei Shtylyov136733d2009-02-21 15:31:35 -08002279 /*
2280 * Full/low speeds use the linear encoding,
2281 * high speed uses the logarithmic encoding.
2282 */
2283 if (urb->dev->speed <= USB_SPEED_FULL) {
2284 interval = max_t(u8, epd->bInterval, 1);
2285 break;
Felipe Balbi550a7372008-07-24 12:27:36 +03002286 }
2287 /* FALLTHROUGH */
2288 case USB_ENDPOINT_XFER_ISOC:
Sergei Shtylyov136733d2009-02-21 15:31:35 -08002289 /* ISO always uses logarithmic encoding */
2290 interval = min_t(u8, epd->bInterval, 16);
Felipe Balbi550a7372008-07-24 12:27:36 +03002291 break;
2292 default:
2293 /* REVISIT we actually want to use NAK limits, hinting to the
2294 * transfer scheduling logic to try some other qh, e.g. try
2295 * for 2 msec first:
2296 *
2297 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2298 *
2299 * The downside of disabling this is that transfer scheduling
2300 * gets VERY unfair for nonperiodic transfers; a misbehaving
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002301 * peripheral could make that hurt. That's perfectly normal
2302 * for reads from network or serial adapters ... so we have
2303 * partial NAKlimit support for bulk RX.
Felipe Balbi550a7372008-07-24 12:27:36 +03002304 *
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002305 * The upside of disabling it is simpler transfer scheduling.
Felipe Balbi550a7372008-07-24 12:27:36 +03002306 */
2307 interval = 0;
2308 }
2309 qh->intv_reg = interval;
2310
2311 /* precompute addressing for external hub/tt ports */
2312 if (musb->is_multipoint) {
2313 struct usb_device *parent = urb->dev->parent;
2314
2315 if (parent != hcd->self.root_hub) {
2316 qh->h_addr_reg = (u8) parent->devnum;
2317
2318 /* set up tt info if needed */
2319 if (urb->dev->tt) {
2320 qh->h_port_reg = (u8) urb->dev->ttport;
Ajay Kumar Guptaae5ad292008-09-11 11:53:20 +03002321 if (urb->dev->tt->hub)
2322 qh->h_addr_reg =
2323 (u8) urb->dev->tt->hub->devnum;
2324 if (urb->dev->tt->multi)
2325 qh->h_addr_reg |= 0x80;
Felipe Balbi550a7372008-07-24 12:27:36 +03002326 }
2327 }
2328 }
2329
2330 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2331 * until we get real dma queues (with an entry for each urb/buffer),
2332 * we only have work to do in the former case.
2333 */
2334 spin_lock_irqsave(&musb->lock, flags);
yuzheng ma30677792012-08-15 16:11:40 +08002335 if (hep->hcpriv || !next_urb(qh)) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002336 /* some concurrent activity submitted another urb to hep...
2337 * odd, rare, error prone, but legal.
2338 */
2339 kfree(qh);
Dan Carpenter714bc5e2010-03-25 13:14:27 +02002340 qh = NULL;
Felipe Balbi550a7372008-07-24 12:27:36 +03002341 ret = 0;
2342 } else
2343 ret = musb_schedule(musb, qh,
2344 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2345
2346 if (ret == 0) {
2347 urb->hcpriv = qh;
2348 /* FIXME set urb->start_frame for iso/intr, it's tested in
2349 * musb_start_urb(), but otherwise only konicawc cares ...
2350 */
2351 }
2352 spin_unlock_irqrestore(&musb->lock, flags);
2353
2354done:
2355 if (ret != 0) {
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03002356 spin_lock_irqsave(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002357 usb_hcd_unlink_urb_from_ep(hcd, urb);
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03002358 spin_unlock_irqrestore(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002359 kfree(qh);
2360 }
2361 return ret;
2362}
2363
2364
2365/*
2366 * abort a transfer that's at the head of a hardware queue.
2367 * called with controller locked, irqs blocked
2368 * that hardware queue advances to the next transfer, unless prevented
2369 */
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002370static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
Felipe Balbi550a7372008-07-24 12:27:36 +03002371{
2372 struct musb_hw_ep *ep = qh->hw_ep;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03002373 struct musb *musb = ep->musb;
Felipe Balbi550a7372008-07-24 12:27:36 +03002374 void __iomem *epio = ep->regs;
2375 unsigned hw_end = ep->epnum;
2376 void __iomem *regs = ep->musb->mregs;
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002377 int is_in = usb_pipein(urb->pipe);
Felipe Balbi550a7372008-07-24 12:27:36 +03002378 int status = 0;
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002379 u16 csr;
Felipe Balbi550a7372008-07-24 12:27:36 +03002380
2381 musb_ep_select(regs, hw_end);
2382
2383 if (is_dma_capable()) {
2384 struct dma_channel *dma;
2385
2386 dma = is_in ? ep->rx_channel : ep->tx_channel;
2387 if (dma) {
2388 status = ep->musb->dma_controller->channel_abort(dma);
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03002389 dev_dbg(musb->controller,
Felipe Balbi550a7372008-07-24 12:27:36 +03002390 "abort %cX%d DMA for urb %p --> %d\n",
2391 is_in ? 'R' : 'T', ep->epnum,
2392 urb, status);
2393 urb->actual_length += dma->actual_len;
2394 }
2395 }
2396
2397 /* turn off DMA requests, discard state, stop polling ... */
Ajay Kumar Gupta692933b2012-03-14 17:33:35 +05302398 if (ep->epnum && is_in) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002399 /* giveback saves bulk toggle */
2400 csr = musb_h_flush_rxfifo(ep, 0);
2401
2402 /* REVISIT we still get an irq; should likely clear the
2403 * endpoint's irq status here to avoid bogus irqs.
2404 * clearing that status is platform-specific...
2405 */
David Brownell78322c12009-03-26 17:38:30 -07002406 } else if (ep->epnum) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002407 musb_h_tx_flush_fifo(ep);
2408 csr = musb_readw(epio, MUSB_TXCSR);
2409 csr &= ~(MUSB_TXCSR_AUTOSET
2410 | MUSB_TXCSR_DMAENAB
2411 | MUSB_TXCSR_H_RXSTALL
2412 | MUSB_TXCSR_H_NAKTIMEOUT
2413 | MUSB_TXCSR_H_ERROR
2414 | MUSB_TXCSR_TXPKTRDY);
2415 musb_writew(epio, MUSB_TXCSR, csr);
2416 /* REVISIT may need to clear FLUSHFIFO ... */
2417 musb_writew(epio, MUSB_TXCSR, csr);
2418 /* flush cpu writebuffer */
2419 csr = musb_readw(epio, MUSB_TXCSR);
David Brownell78322c12009-03-26 17:38:30 -07002420 } else {
2421 musb_h_ep0_flush_fifo(ep);
Felipe Balbi550a7372008-07-24 12:27:36 +03002422 }
2423 if (status == 0)
2424 musb_advance_schedule(ep->musb, urb, ep, is_in);
2425 return status;
2426}
2427
2428static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2429{
2430 struct musb *musb = hcd_to_musb(hcd);
2431 struct musb_qh *qh;
Felipe Balbi550a7372008-07-24 12:27:36 +03002432 unsigned long flags;
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002433 int is_in = usb_pipein(urb->pipe);
Felipe Balbi550a7372008-07-24 12:27:36 +03002434 int ret;
2435
Felipe Balbi5c8a86e2011-05-11 12:44:08 +03002436 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
Felipe Balbi550a7372008-07-24 12:27:36 +03002437 usb_pipedevice(urb->pipe),
2438 usb_pipeendpoint(urb->pipe),
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002439 is_in ? "in" : "out");
Felipe Balbi550a7372008-07-24 12:27:36 +03002440
2441 spin_lock_irqsave(&musb->lock, flags);
2442 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2443 if (ret)
2444 goto done;
2445
2446 qh = urb->hcpriv;
2447 if (!qh)
2448 goto done;
2449
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002450 /*
2451 * Any URB not actively programmed into endpoint hardware can be
Sergei Shtylyova2fd8142009-02-21 15:30:45 -08002452 * immediately given back; that's any URB not at the head of an
Felipe Balbi550a7372008-07-24 12:27:36 +03002453 * endpoint queue, unless someday we get real DMA queues. And even
Sergei Shtylyova2fd8142009-02-21 15:30:45 -08002454 * if it's at the head, it might not be known to the hardware...
Felipe Balbi550a7372008-07-24 12:27:36 +03002455 *
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002456 * Otherwise abort current transfer, pending DMA, etc.; urb->status
Felipe Balbi550a7372008-07-24 12:27:36 +03002457 * has already been updated. This is a synchronous abort; it'd be
2458 * OK to hold off until after some IRQ, though.
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002459 *
2460 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
Felipe Balbi550a7372008-07-24 12:27:36 +03002461 */
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002462 if (!qh->is_ready
2463 || urb->urb_list.prev != &qh->hep->urb_list
2464 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002465 int ready = qh->is_ready;
2466
Felipe Balbi550a7372008-07-24 12:27:36 +03002467 qh->is_ready = 0;
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -07002468 musb_giveback(musb, urb, 0);
Felipe Balbi550a7372008-07-24 12:27:36 +03002469 qh->is_ready = ready;
Sergei Shtylyova2fd8142009-02-21 15:30:45 -08002470
2471 /* If nothing else (usually musb_giveback) is using it
2472 * and its URB list has emptied, recycle this qh.
2473 */
2474 if (ready && list_empty(&qh->hep->urb_list)) {
2475 qh->hep->hcpriv = NULL;
2476 list_del(&qh->ring);
2477 kfree(qh);
2478 }
Felipe Balbi550a7372008-07-24 12:27:36 +03002479 } else
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002480 ret = musb_cleanup_urb(urb, qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03002481done:
2482 spin_unlock_irqrestore(&musb->lock, flags);
2483 return ret;
2484}
2485
2486/* disable an endpoint */
2487static void
2488musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2489{
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002490 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
Felipe Balbi550a7372008-07-24 12:27:36 +03002491 unsigned long flags;
2492 struct musb *musb = hcd_to_musb(hcd);
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002493 struct musb_qh *qh;
2494 struct urb *urb;
Felipe Balbi550a7372008-07-24 12:27:36 +03002495
Felipe Balbi550a7372008-07-24 12:27:36 +03002496 spin_lock_irqsave(&musb->lock, flags);
2497
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002498 qh = hep->hcpriv;
2499 if (qh == NULL)
2500 goto exit;
2501
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002502 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
Felipe Balbi550a7372008-07-24 12:27:36 +03002503
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002504 /* Kick the first URB off the hardware, if needed */
Felipe Balbi550a7372008-07-24 12:27:36 +03002505 qh->is_ready = 0;
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002506 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002507 urb = next_urb(qh);
2508
2509 /* make software (then hardware) stop ASAP */
2510 if (!urb->unlinked)
2511 urb->status = -ESHUTDOWN;
2512
2513 /* cleanup */
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002514 musb_cleanup_urb(urb, qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03002515
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002516 /* Then nuke all the others ... and advance the
2517 * queue on hw_ep (e.g. bulk ring) when we're done.
2518 */
2519 while (!list_empty(&hep->urb_list)) {
2520 urb = next_urb(qh);
2521 urb->status = -ESHUTDOWN;
2522 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2523 }
2524 } else {
2525 /* Just empty the queue; the hardware is busy with
2526 * other transfers, and since !qh->is_ready nothing
2527 * will activate any of these as it advances.
2528 */
2529 while (!list_empty(&hep->urb_list))
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -07002530 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
Felipe Balbi550a7372008-07-24 12:27:36 +03002531
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002532 hep->hcpriv = NULL;
2533 list_del(&qh->ring);
2534 kfree(qh);
2535 }
2536exit:
Felipe Balbi550a7372008-07-24 12:27:36 +03002537 spin_unlock_irqrestore(&musb->lock, flags);
2538}
2539
2540static int musb_h_get_frame_number(struct usb_hcd *hcd)
2541{
2542 struct musb *musb = hcd_to_musb(hcd);
2543
2544 return musb_readw(musb->mregs, MUSB_FRAME);
2545}
2546
2547static int musb_h_start(struct usb_hcd *hcd)
2548{
2549 struct musb *musb = hcd_to_musb(hcd);
2550
2551 /* NOTE: musb_start() is called when the hub driver turns
2552 * on port power, or when (OTG) peripheral starts.
2553 */
2554 hcd->state = HC_STATE_RUNNING;
2555 musb->port1_status = 0;
2556 return 0;
2557}
2558
2559static void musb_h_stop(struct usb_hcd *hcd)
2560{
2561 musb_stop(hcd_to_musb(hcd));
2562 hcd->state = HC_STATE_HALT;
2563}
2564
2565static int musb_bus_suspend(struct usb_hcd *hcd)
2566{
2567 struct musb *musb = hcd_to_musb(hcd);
David Brownell89368d32009-07-01 03:36:16 -07002568 u8 devctl;
Felipe Balbi550a7372008-07-24 12:27:36 +03002569
Daniel Mack94f72132013-11-25 22:26:41 +01002570 musb_port_suspend(musb, true);
2571
David Brownell89368d32009-07-01 03:36:16 -07002572 if (!is_host_active(musb))
Felipe Balbi550a7372008-07-24 12:27:36 +03002573 return 0;
2574
Antoine Tenarte47d9252014-10-30 18:41:13 +01002575 switch (musb->xceiv->otg->state) {
David Brownell89368d32009-07-01 03:36:16 -07002576 case OTG_STATE_A_SUSPEND:
2577 return 0;
2578 case OTG_STATE_A_WAIT_VRISE:
2579 /* ID could be grounded even if there's no device
2580 * on the other end of the cable. NOTE that the
2581 * A_WAIT_VRISE timers are messy with MUSB...
2582 */
2583 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2584 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
Antoine Tenarte47d9252014-10-30 18:41:13 +01002585 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
David Brownell89368d32009-07-01 03:36:16 -07002586 break;
2587 default:
2588 break;
2589 }
2590
2591 if (musb->is_active) {
2592 WARNING("trying to suspend as %s while active\n",
Antoine Tenarte47d9252014-10-30 18:41:13 +01002593 usb_otg_state_string(musb->xceiv->otg->state));
Felipe Balbi550a7372008-07-24 12:27:36 +03002594 return -EBUSY;
2595 } else
2596 return 0;
2597}
2598
2599static int musb_bus_resume(struct usb_hcd *hcd)
2600{
Daniel Mack869c5972013-11-26 13:31:14 +01002601 struct musb *musb = hcd_to_musb(hcd);
2602
2603 if (musb->config &&
2604 musb->config->host_port_deassert_reset_at_resume)
2605 musb_port_reset(musb, false);
2606
Felipe Balbi550a7372008-07-24 12:27:36 +03002607 return 0;
2608}
2609
Ruslan Bilovol8408fd12013-03-29 19:15:21 +02002610#ifndef CONFIG_MUSB_PIO_ONLY
2611
2612#define MUSB_USB_DMA_ALIGN 4
2613
2614struct musb_temp_buffer {
2615 void *kmalloc_ptr;
2616 void *old_xfer_buffer;
2617 u8 data[0];
2618};
2619
2620static void musb_free_temp_buffer(struct urb *urb)
2621{
2622 enum dma_data_direction dir;
2623 struct musb_temp_buffer *temp;
Johan Hovoldd72348f2015-04-23 16:06:50 +02002624 size_t length;
Ruslan Bilovol8408fd12013-03-29 19:15:21 +02002625
2626 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2627 return;
2628
2629 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2630
2631 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2632 data);
2633
2634 if (dir == DMA_FROM_DEVICE) {
Johan Hovoldd72348f2015-04-23 16:06:50 +02002635 if (usb_pipeisoc(urb->pipe))
2636 length = urb->transfer_buffer_length;
2637 else
2638 length = urb->actual_length;
2639
2640 memcpy(temp->old_xfer_buffer, temp->data, length);
Ruslan Bilovol8408fd12013-03-29 19:15:21 +02002641 }
2642 urb->transfer_buffer = temp->old_xfer_buffer;
2643 kfree(temp->kmalloc_ptr);
2644
2645 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2646}
2647
2648static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2649{
2650 enum dma_data_direction dir;
2651 struct musb_temp_buffer *temp;
2652 void *kmalloc_ptr;
2653 size_t kmalloc_size;
2654
2655 if (urb->num_sgs || urb->sg ||
2656 urb->transfer_buffer_length == 0 ||
2657 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2658 return 0;
2659
2660 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2661
2662 /* Allocate a buffer with enough padding for alignment */
2663 kmalloc_size = urb->transfer_buffer_length +
2664 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2665
2666 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2667 if (!kmalloc_ptr)
2668 return -ENOMEM;
2669
2670 /* Position our struct temp_buffer such that data is aligned */
2671 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2672
2673
2674 temp->kmalloc_ptr = kmalloc_ptr;
2675 temp->old_xfer_buffer = urb->transfer_buffer;
2676 if (dir == DMA_TO_DEVICE)
2677 memcpy(temp->data, urb->transfer_buffer,
2678 urb->transfer_buffer_length);
2679 urb->transfer_buffer = temp->data;
2680
2681 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2682
2683 return 0;
2684}
2685
2686static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2687 gfp_t mem_flags)
2688{
2689 struct musb *musb = hcd_to_musb(hcd);
2690 int ret;
2691
2692 /*
2693 * The DMA engine in RTL1.8 and above cannot handle
2694 * DMA addresses that are not aligned to a 4 byte boundary.
2695 * For such engine implemented (un)map_urb_for_dma hooks.
2696 * Do not use these hooks for RTL<1.8
2697 */
2698 if (musb->hwvers < MUSB_HWVERS_1800)
2699 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2700
2701 ret = musb_alloc_temp_buffer(urb, mem_flags);
2702 if (ret)
2703 return ret;
2704
2705 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2706 if (ret)
2707 musb_free_temp_buffer(urb);
2708
2709 return ret;
2710}
2711
2712static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2713{
2714 struct musb *musb = hcd_to_musb(hcd);
2715
2716 usb_hcd_unmap_urb_for_dma(hcd, urb);
2717
2718 /* Do not use this hook for RTL<1.8 (see description above) */
2719 if (musb->hwvers < MUSB_HWVERS_1800)
2720 return;
2721
2722 musb_free_temp_buffer(urb);
2723}
2724#endif /* !CONFIG_MUSB_PIO_ONLY */
2725
Daniel Mack74c2e932013-04-10 21:55:45 +02002726static const struct hc_driver musb_hc_driver = {
Felipe Balbi550a7372008-07-24 12:27:36 +03002727 .description = "musb-hcd",
2728 .product_desc = "MUSB HDRC host driver",
Daniel Mack74c2e932013-04-10 21:55:45 +02002729 .hcd_priv_size = sizeof(struct musb *),
George Cherian20357722014-03-05 14:01:43 +05302730 .flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
Felipe Balbi550a7372008-07-24 12:27:36 +03002731
2732 /* not using irq handler or reset hooks from usbcore, since
2733 * those must be shared with peripheral code for OTG configs
2734 */
2735
2736 .start = musb_h_start,
2737 .stop = musb_h_stop,
2738
2739 .get_frame_number = musb_h_get_frame_number,
2740
2741 .urb_enqueue = musb_urb_enqueue,
2742 .urb_dequeue = musb_urb_dequeue,
2743 .endpoint_disable = musb_h_disable,
2744
Ruslan Bilovol8408fd12013-03-29 19:15:21 +02002745#ifndef CONFIG_MUSB_PIO_ONLY
2746 .map_urb_for_dma = musb_map_urb_for_dma,
2747 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2748#endif
2749
Felipe Balbi550a7372008-07-24 12:27:36 +03002750 .hub_status_data = musb_hub_status_data,
2751 .hub_control = musb_hub_control,
2752 .bus_suspend = musb_bus_suspend,
2753 .bus_resume = musb_bus_resume,
2754 /* .start_port_reset = NULL, */
2755 /* .hub_irq_enable = NULL, */
2756};
Daniel Mack0b3eba42013-04-10 21:55:42 +02002757
Daniel Mack74c2e932013-04-10 21:55:45 +02002758int musb_host_alloc(struct musb *musb)
2759{
2760 struct device *dev = musb->controller;
2761
2762 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2763 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2764 if (!musb->hcd)
2765 return -EINVAL;
2766
2767 *musb->hcd->hcd_priv = (unsigned long) musb;
2768 musb->hcd->self.uses_pio_for_control = 1;
2769 musb->hcd->uses_new_polling = 1;
2770 musb->hcd->has_tt = 1;
2771
2772 return 0;
2773}
2774
2775void musb_host_cleanup(struct musb *musb)
2776{
Sebastian Andrzej Siewior90474282013-08-20 18:35:44 +02002777 if (musb->port_mode == MUSB_PORT_MODE_GADGET)
2778 return;
Daniel Mack74c2e932013-04-10 21:55:45 +02002779 usb_remove_hcd(musb->hcd);
Daniel Mack74c2e932013-04-10 21:55:45 +02002780}
2781
2782void musb_host_free(struct musb *musb)
2783{
2784 usb_put_hcd(musb->hcd);
2785}
2786
Daniel Mack2cc65fe2013-04-10 21:55:47 +02002787int musb_host_setup(struct musb *musb, int power_budget)
2788{
2789 int ret;
2790 struct usb_hcd *hcd = musb->hcd;
2791
2792 MUSB_HST_MODE(musb);
2793 musb->xceiv->otg->default_a = 1;
Antoine Tenarte47d9252014-10-30 18:41:13 +01002794 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
Daniel Mack2cc65fe2013-04-10 21:55:47 +02002795
2796 otg_set_host(musb->xceiv->otg, &hcd->self);
2797 hcd->self.otg_port = 1;
2798 musb->xceiv->otg->host = &hcd->self;
2799 hcd->power_budget = 2 * (power_budget ? : 250);
2800
2801 ret = usb_add_hcd(hcd, 0, 0);
2802 if (ret < 0)
2803 return ret;
2804
Peter Chen3c9740a2013-11-05 10:46:02 +08002805 device_wakeup_enable(hcd->self.controller);
Daniel Mack2cc65fe2013-04-10 21:55:47 +02002806 return 0;
2807}
2808
Daniel Mack0b3eba42013-04-10 21:55:42 +02002809void musb_host_resume_root_hub(struct musb *musb)
2810{
Daniel Mack74c2e932013-04-10 21:55:45 +02002811 usb_hcd_resume_root_hub(musb->hcd);
Daniel Mack0b3eba42013-04-10 21:55:42 +02002812}
2813
2814void musb_host_poke_root_hub(struct musb *musb)
2815{
2816 MUSB_HST_MODE(musb);
Daniel Mack74c2e932013-04-10 21:55:45 +02002817 if (musb->hcd->status_urb)
2818 usb_hcd_poll_rh_status(musb->hcd);
Daniel Mack0b3eba42013-04-10 21:55:42 +02002819 else
Daniel Mack74c2e932013-04-10 21:55:45 +02002820 usb_hcd_resume_root_hub(musb->hcd);
Daniel Mack0b3eba42013-04-10 21:55:42 +02002821}