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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Terje Bergstromd43f81c2013-03-22 16:34:09 +02003 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Terje Bergstrom4231c6b2013-03-22 16:34:05 +020010#ifndef HOST1X_DRM_H
11#define HOST1X_DRM_H 1
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000012
Thierry Redinge1e90642013-09-24 13:59:01 +020013#include <uapi/drm/tegra_drm.h>
14#include <linux/host1x.h>
Thierry Redingfb36d0e2015-04-27 15:12:39 +020015#include <linux/of_gpio.h>
Thierry Redinge1e90642013-09-24 13:59:01 +020016
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000017#include <drm/drmP.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_edid.h>
20#include <drm/drm_fb_helper.h>
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000021#include <drm/drm_fixed.h>
22
Thierry Redingc134f012014-06-03 14:48:12 +020023#include "gem.h"
24
Stephen Warrenca480802013-11-06 16:20:54 -070025struct reset_control;
26
Arto Merilainende2ba662013-03-22 16:34:08 +020027struct tegra_fb {
28 struct drm_framebuffer base;
29 struct tegra_bo **planes;
30 unsigned int num_planes;
31};
32
Archit Tanejab110ef32015-10-27 13:40:59 +053033#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020034struct tegra_fbdev {
35 struct drm_fb_helper base;
36 struct tegra_fb *fb;
37};
Thierry Reding60c2f702013-10-31 13:28:50 +010038#endif
Arto Merilainende2ba662013-03-22 16:34:08 +020039
Thierry Reding386a2a72013-09-24 13:22:17 +020040struct tegra_drm {
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000041 struct drm_device *drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000042
Thierry Redingdf06b752014-06-26 21:41:53 +020043 struct iommu_domain *domain;
44 struct drm_mm mm;
45
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000046 struct mutex clients_lock;
47 struct list_head clients;
48
Archit Tanejab110ef32015-10-27 13:40:59 +053049#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020050 struct tegra_fbdev *fbdev;
Thierry Reding60c2f702013-10-31 13:28:50 +010051#endif
Thierry Redingd1f3e1e2014-07-11 08:29:14 +020052
53 unsigned int pitch_align;
Thierry Reding1503ca42014-11-24 17:41:23 +010054
55 struct {
56 struct drm_atomic_state *state;
57 struct work_struct work;
58 struct mutex lock;
59 } commit;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000060};
61
Thierry Reding53fa7f72013-09-24 15:35:40 +020062struct tegra_drm_client;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000063
Thierry Redingc88c3632013-09-26 16:08:22 +020064struct tegra_drm_context {
Thierry Reding53fa7f72013-09-24 15:35:40 +020065 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +020066 struct host1x_channel *channel;
67 struct list_head list;
68};
69
Thierry Reding53fa7f72013-09-24 15:35:40 +020070struct tegra_drm_client_ops {
71 int (*open_channel)(struct tegra_drm_client *client,
Thierry Redingc88c3632013-09-26 16:08:22 +020072 struct tegra_drm_context *context);
73 void (*close_channel)(struct tegra_drm_context *context);
Thierry Redingc40f0f12013-10-10 11:00:33 +020074 int (*is_addr_reg)(struct device *dev, u32 class, u32 offset);
Thierry Redingc88c3632013-09-26 16:08:22 +020075 int (*submit)(struct tegra_drm_context *context,
Terje Bergstromd43f81c2013-03-22 16:34:09 +020076 struct drm_tegra_submit *args, struct drm_device *drm,
77 struct drm_file *file);
78};
79
Thierry Redingc40f0f12013-10-10 11:00:33 +020080int tegra_drm_submit(struct tegra_drm_context *context,
81 struct drm_tegra_submit *args, struct drm_device *drm,
82 struct drm_file *file);
83
Thierry Reding53fa7f72013-09-24 15:35:40 +020084struct tegra_drm_client {
85 struct host1x_client base;
Thierry Reding776dc382013-10-14 14:43:22 +020086 struct list_head list;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000087
Thierry Reding53fa7f72013-09-24 15:35:40 +020088 const struct tegra_drm_client_ops *ops;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000089};
90
Thierry Reding53fa7f72013-09-24 15:35:40 +020091static inline struct tegra_drm_client *
Thierry Reding776dc382013-10-14 14:43:22 +020092host1x_to_drm_client(struct host1x_client *client)
Thierry Reding53fa7f72013-09-24 15:35:40 +020093{
94 return container_of(client, struct tegra_drm_client, base);
95}
96
Thierry Reding688c59a2014-04-16 09:54:21 +020097int tegra_drm_register_client(struct tegra_drm *tegra,
98 struct tegra_drm_client *client);
99int tegra_drm_unregister_client(struct tegra_drm *tegra,
100 struct tegra_drm_client *client);
Thierry Reding776dc382013-10-14 14:43:22 +0200101
Thierry Reding688c59a2014-04-16 09:54:21 +0200102int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm);
103int tegra_drm_exit(struct tegra_drm *tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000104
Thierry Reding8620fc62013-12-12 11:03:59 +0100105struct tegra_dc_soc_info;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000106struct tegra_output;
107
Thierry Reding791ddb12015-07-28 21:27:05 +0200108struct tegra_dc_stats {
109 unsigned long frames;
110 unsigned long vblank;
111 unsigned long underflow;
112 unsigned long overflow;
113};
114
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000115struct tegra_dc {
Thierry Reding776dc382013-10-14 14:43:22 +0200116 struct host1x_client client;
Thierry Reding42e9ce02015-01-28 14:43:05 +0100117 struct host1x_syncpt *syncpt;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000118 struct device *dev;
Thierry Redingd18d3032013-09-26 16:09:19 +0200119 spinlock_t lock;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000120
121 struct drm_crtc base;
Thierry Reding9c012702014-07-07 15:32:53 +0200122 int powergate;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000123 int pipe;
124
125 struct clk *clk;
Stephen Warrenca480802013-11-06 16:20:54 -0700126 struct reset_control *rst;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000127 void __iomem *regs;
128 int irq;
129
130 struct tegra_output *rgb;
131
Thierry Reding791ddb12015-07-28 21:27:05 +0200132 struct tegra_dc_stats stats;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000133 struct list_head list;
134
135 struct drm_info_list *debugfs_files;
136 struct drm_minor *minor;
137 struct dentry *debugfs;
Thierry Reding3c03c462012-11-28 12:00:18 +0100138
139 /* page-flip handling */
140 struct drm_pending_vblank_event *event;
Thierry Reding8620fc62013-12-12 11:03:59 +0100141
142 const struct tegra_dc_soc_info *soc;
Thierry Redingdf06b752014-06-26 21:41:53 +0200143
144 struct iommu_domain *domain;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000145};
146
Thierry Reding53fa7f72013-09-24 15:35:40 +0200147static inline struct tegra_dc *
Thierry Reding776dc382013-10-14 14:43:22 +0200148host1x_client_to_dc(struct host1x_client *client)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000149{
150 return container_of(client, struct tegra_dc, client);
151}
152
153static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
154{
Thierry Reding37826512013-11-08 12:30:37 +0100155 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000156}
157
Thierry Reding03a60562014-10-21 13:48:48 +0200158static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
159 unsigned long offset)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000160{
Thierry Reding03a60562014-10-21 13:48:48 +0200161 writel(value, dc->regs + (offset << 2));
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000162}
163
Thierry Reding03a60562014-10-21 13:48:48 +0200164static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000165{
Thierry Reding03a60562014-10-21 13:48:48 +0200166 return readl(dc->regs + (offset << 2));
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000167}
168
Thierry Redingf34bc782012-11-04 21:47:13 +0100169struct tegra_dc_window {
170 struct {
171 unsigned int x;
172 unsigned int y;
173 unsigned int w;
174 unsigned int h;
175 } src;
176 struct {
177 unsigned int x;
178 unsigned int y;
179 unsigned int w;
180 unsigned int h;
181 } dst;
182 unsigned int bits_per_pixel;
Thierry Redingf34bc782012-11-04 21:47:13 +0100183 unsigned int stride[2];
184 unsigned long base[3];
Thierry Redingdb7fbdf2013-10-07 09:47:58 +0200185 bool bottom_up;
Thierry Redingc134f012014-06-03 14:48:12 +0200186
187 struct tegra_bo_tiling tiling;
Thierry Reding8f604f82014-11-28 13:14:55 +0100188 u32 format;
189 u32 swap;
Thierry Redingf34bc782012-11-04 21:47:13 +0100190};
191
192/* from dc.c */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100193u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc);
Thierry Reding688c59a2014-04-16 09:54:21 +0200194void tegra_dc_enable_vblank(struct tegra_dc *dc);
195void tegra_dc_disable_vblank(struct tegra_dc *dc);
196void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
Thierry Reding62b9e062014-11-21 17:33:33 +0100197void tegra_dc_commit(struct tegra_dc *dc);
Thierry Redingca915b12014-12-08 16:14:45 +0100198int tegra_dc_state_setup_clock(struct tegra_dc *dc,
199 struct drm_crtc_state *crtc_state,
200 struct clk *clk, unsigned long pclk,
201 unsigned int div);
Thierry Redingf34bc782012-11-04 21:47:13 +0100202
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000203struct tegra_output {
204 struct device_node *of_node;
205 struct device *dev;
206
Thierry Reding9be7d862013-08-30 15:22:36 +0200207 struct drm_panel *panel;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000208 struct i2c_adapter *ddc;
209 const struct edid *edid;
210 unsigned int hpd_irq;
211 int hpd_gpio;
Thierry Redingfb36d0e2015-04-27 15:12:39 +0200212 enum of_gpio_flags hpd_gpio_flags;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000213
214 struct drm_encoder encoder;
215 struct drm_connector connector;
216};
217
218static inline struct tegra_output *encoder_to_output(struct drm_encoder *e)
219{
220 return container_of(e, struct tegra_output, encoder);
221}
222
223static inline struct tegra_output *connector_to_output(struct drm_connector *c)
224{
225 return container_of(c, struct tegra_output, connector);
226}
227
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000228/* from rgb.c */
Thierry Reding688c59a2014-04-16 09:54:21 +0200229int tegra_dc_rgb_probe(struct tegra_dc *dc);
230int tegra_dc_rgb_remove(struct tegra_dc *dc);
231int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
232int tegra_dc_rgb_exit(struct tegra_dc *dc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000233
234/* from output.c */
Thierry Reding688c59a2014-04-16 09:54:21 +0200235int tegra_output_probe(struct tegra_output *output);
Thierry Reding328ec692014-12-19 15:55:08 +0100236void tegra_output_remove(struct tegra_output *output);
Thierry Reding688c59a2014-04-16 09:54:21 +0200237int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
Thierry Reding328ec692014-12-19 15:55:08 +0100238void tegra_output_exit(struct tegra_output *output);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000239
Thierry Reding132085d2014-11-28 15:38:40 +0100240int tegra_output_connector_get_modes(struct drm_connector *connector);
241struct drm_encoder *
242tegra_output_connector_best_encoder(struct drm_connector *connector);
243enum drm_connector_status
244tegra_output_connector_detect(struct drm_connector *connector, bool force);
245void tegra_output_connector_destroy(struct drm_connector *connector);
246
247void tegra_output_encoder_destroy(struct drm_encoder *encoder);
248
Thierry Reding6b6b6042013-11-15 16:06:05 +0100249/* from dpaux.c */
Thierry Reding6b6b6042013-11-15 16:06:05 +0100250struct tegra_dpaux;
251struct drm_dp_link;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100252
253struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np);
254enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux);
255int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output);
256int tegra_dpaux_detach(struct tegra_dpaux *dpaux);
257int tegra_dpaux_enable(struct tegra_dpaux *dpaux);
258int tegra_dpaux_disable(struct tegra_dpaux *dpaux);
259int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding);
260int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
261 u8 pattern);
262
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000263/* from fb.c */
Arto Merilainende2ba662013-03-22 16:34:08 +0200264struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
265 unsigned int index);
Thierry Redingdb7fbdf2013-10-07 09:47:58 +0200266bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
Thierry Redingc134f012014-06-03 14:48:12 +0200267int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
268 struct tegra_bo_tiling *tiling);
Thierry Redingf9914212014-11-26 13:03:57 +0100269struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
270 struct drm_file *file,
Ville Syrjälä1eb83452015-11-11 19:11:29 +0200271 const struct drm_mode_fb_cmd2 *cmd);
Thierry Redinge2215322014-06-27 17:19:25 +0200272int tegra_drm_fb_prepare(struct drm_device *drm);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100273void tegra_drm_fb_free(struct drm_device *drm);
Thierry Reding688c59a2014-04-16 09:54:21 +0200274int tegra_drm_fb_init(struct drm_device *drm);
275void tegra_drm_fb_exit(struct drm_device *drm);
Archit Tanejab110ef32015-10-27 13:40:59 +0530276#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding688c59a2014-04-16 09:54:21 +0200277void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
Thierry Redingf9914212014-11-26 13:03:57 +0100278void tegra_fb_output_poll_changed(struct drm_device *drm);
Thierry Reding60c2f702013-10-31 13:28:50 +0100279#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000280
Thierry Reding776dc382013-10-14 14:43:22 +0200281extern struct platform_driver tegra_dc_driver;
Thierry Redingdec72732013-09-03 08:45:46 +0200282extern struct platform_driver tegra_dsi_driver;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100283extern struct platform_driver tegra_sor_driver;
Thierry Reding776dc382013-10-14 14:43:22 +0200284extern struct platform_driver tegra_hdmi_driver;
Thierry Reding6b6b6042013-11-15 16:06:05 +0100285extern struct platform_driver tegra_dpaux_driver;
Thierry Reding776dc382013-10-14 14:43:22 +0200286extern struct platform_driver tegra_gr2d_driver;
Thierry Reding5f60ed02013-02-28 08:08:01 +0100287extern struct platform_driver tegra_gr3d_driver;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000288
Terje Bergstrom4231c6b2013-03-22 16:34:05 +0200289#endif /* HOST1X_DRM_H */