Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * |
| 6 | * Rami Rosen <rosenr@marvell.com> |
| 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 15 | #include <linux/netdevice.h> |
| 16 | #include <linux/etherdevice.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/skbuff.h> |
| 19 | #include <linux/inetdevice.h> |
| 20 | #include <linux/mbus.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/interrupt.h> |
David S. Miller | 2d39d12 | 2014-08-25 20:21:55 -0700 | [diff] [blame] | 23 | #include <linux/if_vlan.h> |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 24 | #include <net/ip.h> |
| 25 | #include <net/ipv6.h> |
Thomas Petazzoni | c3f0dd3 | 2014-03-27 11:39:29 +0100 | [diff] [blame] | 26 | #include <linux/io.h> |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 27 | #include <net/tso.h> |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 28 | #include <linux/of.h> |
| 29 | #include <linux/of_irq.h> |
| 30 | #include <linux/of_mdio.h> |
| 31 | #include <linux/of_net.h> |
| 32 | #include <linux/of_address.h> |
| 33 | #include <linux/phy.h> |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 34 | #include <linux/clk.h> |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 35 | #include <linux/cpu.h> |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 36 | |
| 37 | /* Registers */ |
| 38 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) |
Marcin Wojtas | e5bdf68 | 2015-11-30 13:27:42 +0100 | [diff] [blame] | 39 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 40 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
| 41 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) |
| 42 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) |
| 43 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) |
| 44 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) |
| 45 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) |
| 46 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 |
| 47 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) |
| 48 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) |
| 49 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff |
| 50 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) |
| 51 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 |
| 52 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 |
| 53 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
| 54 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) |
| 55 | #define MVNETA_PHY_ADDR 0x2000 |
| 56 | #define MVNETA_PHY_ADDR_MASK 0x1f |
| 57 | #define MVNETA_MBUS_RETRY 0x2010 |
| 58 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 |
| 59 | #define MVNETA_UNIT_CONTROL 0x20B0 |
| 60 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) |
| 61 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) |
| 62 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) |
| 63 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) |
| 64 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 |
Marcin Wojtas | db6ba9a | 2015-11-30 13:27:41 +0100 | [diff] [blame] | 65 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 66 | #define MVNETA_PORT_CONFIG 0x2400 |
| 67 | #define MVNETA_UNI_PROMISC_MODE BIT(0) |
| 68 | #define MVNETA_DEF_RXQ(q) ((q) << 1) |
| 69 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) |
| 70 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) |
| 71 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) |
| 72 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) |
| 73 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) |
| 74 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) |
| 75 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ |
| 76 | MVNETA_DEF_RXQ_ARP(q) | \ |
| 77 | MVNETA_DEF_RXQ_TCP(q) | \ |
| 78 | MVNETA_DEF_RXQ_UDP(q) | \ |
| 79 | MVNETA_DEF_RXQ_BPDU(q) | \ |
| 80 | MVNETA_TX_UNSET_ERR_SUM | \ |
| 81 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) |
| 82 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 |
| 83 | #define MVNETA_MAC_ADDR_LOW 0x2414 |
| 84 | #define MVNETA_MAC_ADDR_HIGH 0x2418 |
| 85 | #define MVNETA_SDMA_CONFIG 0x241c |
| 86 | #define MVNETA_SDMA_BRST_SIZE_16 4 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 87 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
| 88 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) |
| 89 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) |
Thomas Petazzoni | 9ad8fef | 2013-07-29 15:21:28 +0200 | [diff] [blame] | 90 | #define MVNETA_DESC_SWAP BIT(6) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 91 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
| 92 | #define MVNETA_PORT_STATUS 0x2444 |
| 93 | #define MVNETA_TX_IN_PRGRS BIT(1) |
| 94 | #define MVNETA_TX_FIFO_EMPTY BIT(8) |
| 95 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 96 | #define MVNETA_SERDES_CFG 0x24A0 |
Arnaud Patard \(Rtp\) | 5445eaf | 2013-07-29 21:56:48 +0200 | [diff] [blame] | 97 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 98 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 99 | #define MVNETA_TYPE_PRIO 0x24bc |
| 100 | #define MVNETA_FORCE_UNI BIT(21) |
| 101 | #define MVNETA_TXQ_CMD_1 0x24e4 |
| 102 | #define MVNETA_TXQ_CMD 0x2448 |
| 103 | #define MVNETA_TXQ_DISABLE_SHIFT 8 |
| 104 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff |
Andrew Lunn | e483911 | 2015-10-22 18:37:36 +0100 | [diff] [blame] | 105 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
| 106 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 107 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
| 108 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 109 | #define MVNETA_ACC_MODE 0x2500 |
| 110 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
| 111 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff |
| 112 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 |
| 113 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
willy tarreau | 40ba35e | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 114 | |
| 115 | /* Exception Interrupt Port/Queue Cause register */ |
| 116 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 117 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 118 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
willy tarreau | 40ba35e | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 119 | |
| 120 | /* bits 0..7 = TXQ SENT, one bit per queue. |
| 121 | * bits 8..15 = RXQ OCCUP, one bit per queue. |
| 122 | * bits 16..23 = RXQ FREE, one bit per queue. |
| 123 | * bit 29 = OLD_REG_SUM, see old reg ? |
| 124 | * bit 30 = TX_ERR_SUM, one bit for 4 ports |
| 125 | * bit 31 = MISC_SUM, one bit for 4 ports |
| 126 | */ |
| 127 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) |
| 128 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) |
| 129 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) |
| 130 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 131 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
willy tarreau | 40ba35e | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 132 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 133 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
| 134 | #define MVNETA_INTR_OLD_MASK 0x25ac |
willy tarreau | 40ba35e | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 135 | |
| 136 | /* Data Path Port/Queue Cause Register */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 137 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
| 138 | #define MVNETA_INTR_MISC_MASK 0x25b4 |
willy tarreau | 40ba35e | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 139 | |
| 140 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) |
| 141 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) |
| 142 | #define MVNETA_CAUSE_PTP BIT(4) |
| 143 | |
| 144 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) |
| 145 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) |
| 146 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) |
| 147 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) |
| 148 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) |
| 149 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) |
| 150 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) |
| 151 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) |
| 152 | |
| 153 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 |
| 154 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) |
| 155 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) |
| 156 | |
| 157 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 |
| 158 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) |
| 159 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) |
| 160 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 161 | #define MVNETA_INTR_ENABLE 0x25b8 |
| 162 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 |
Marcin Wojtas | dc1aadf | 2015-11-30 13:27:43 +0100 | [diff] [blame] | 163 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
willy tarreau | 40ba35e | 2014-01-16 08:20:10 +0100 | [diff] [blame] | 164 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 165 | #define MVNETA_RXQ_CMD 0x2680 |
| 166 | #define MVNETA_RXQ_DISABLE_SHIFT 8 |
| 167 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff |
| 168 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) |
| 169 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) |
| 170 | #define MVNETA_GMAC_CTRL_0 0x2c00 |
| 171 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 |
| 172 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc |
| 173 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) |
| 174 | #define MVNETA_GMAC_CTRL_2 0x2c08 |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 175 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
Thomas Petazzoni | a79121d | 2014-03-26 00:25:41 +0100 | [diff] [blame] | 176 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 177 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
| 178 | #define MVNETA_GMAC2_PORT_RESET BIT(6) |
| 179 | #define MVNETA_GMAC_STATUS 0x2c10 |
| 180 | #define MVNETA_GMAC_LINK_UP BIT(0) |
| 181 | #define MVNETA_GMAC_SPEED_1000 BIT(1) |
| 182 | #define MVNETA_GMAC_SPEED_100 BIT(2) |
| 183 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) |
| 184 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) |
| 185 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) |
| 186 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) |
| 187 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) |
| 188 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c |
| 189 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) |
| 190 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 191 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 192 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
| 193 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) |
Thomas Petazzoni | 7140860 | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 194 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 195 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 196 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
Thomas Petazzoni | 7140860 | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 197 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
Andrew Lunn | e483911 | 2015-10-22 18:37:36 +0100 | [diff] [blame] | 198 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 199 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
| 200 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 |
| 201 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 |
| 202 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 |
| 203 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) |
| 204 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) |
| 205 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 |
| 206 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) |
| 207 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) |
| 208 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 |
| 209 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
| 210 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 |
| 211 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 |
| 212 | #define MVNETA_PORT_TX_RESET 0x3cf0 |
| 213 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) |
| 214 | #define MVNETA_TX_MTU 0x3e0c |
| 215 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 |
| 216 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff |
| 217 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) |
| 218 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff |
| 219 | |
| 220 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
| 221 | |
| 222 | /* Descriptor ring Macros */ |
| 223 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ |
| 224 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) |
| 225 | |
| 226 | /* Various constants */ |
| 227 | |
| 228 | /* Coalescing */ |
willy tarreau | aebea2b | 2014-12-02 08:13:04 +0100 | [diff] [blame] | 229 | #define MVNETA_TXDONE_COAL_PKTS 1 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 230 | #define MVNETA_RX_COAL_PKTS 32 |
| 231 | #define MVNETA_RX_COAL_USEC 100 |
| 232 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 233 | /* The two bytes Marvell header. Either contains a special value used |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 234 | * by Marvell switches when a specific hardware mode is enabled (not |
| 235 | * supported by this driver) or is filled automatically by zeroes on |
| 236 | * the RX side. Those two bytes being at the front of the Ethernet |
| 237 | * header, they allow to have the IP header aligned on a 4 bytes |
| 238 | * boundary automatically: the hardware skips those two bytes on its |
| 239 | * own. |
| 240 | */ |
| 241 | #define MVNETA_MH_SIZE 2 |
| 242 | |
| 243 | #define MVNETA_VLAN_TAG_LEN 4 |
| 244 | |
| 245 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 |
Marcin Wojtas | 9110ee0 | 2015-11-30 13:27:45 +0100 | [diff] [blame] | 246 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 247 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
| 248 | #define MVNETA_ACC_MODE_EXT 1 |
| 249 | |
| 250 | /* Timeout constants */ |
| 251 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 |
| 252 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 |
| 253 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 |
| 254 | |
| 255 | #define MVNETA_TX_MTU_MAX 0x3ffff |
| 256 | |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 257 | /* TSO header size */ |
| 258 | #define TSO_HEADER_SIZE 128 |
| 259 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 260 | /* Max number of Rx descriptors */ |
| 261 | #define MVNETA_MAX_RXD 128 |
| 262 | |
| 263 | /* Max number of Tx descriptors */ |
| 264 | #define MVNETA_MAX_TXD 532 |
| 265 | |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 266 | /* Max number of allowed TCP segments for software TSO */ |
| 267 | #define MVNETA_MAX_TSO_SEGS 100 |
| 268 | |
| 269 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) |
| 270 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 271 | /* descriptor aligned size */ |
| 272 | #define MVNETA_DESC_ALIGNED_SIZE 32 |
| 273 | |
| 274 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
| 275 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ |
| 276 | ETH_HLEN + ETH_FCS_LEN, \ |
| 277 | MVNETA_CPU_D_CACHE_LINE_SIZE) |
| 278 | |
Ezequiel Garcia | 2e3173a | 2014-05-30 13:40:07 -0300 | [diff] [blame] | 279 | #define IS_TSO_HEADER(txq, addr) \ |
| 280 | ((addr >= txq->tso_hdrs_phys) && \ |
| 281 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) |
| 282 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 283 | #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) |
| 284 | |
Russell King | 9b0cdef | 2015-10-22 18:37:30 +0100 | [diff] [blame] | 285 | struct mvneta_statistic { |
| 286 | unsigned short offset; |
| 287 | unsigned short type; |
| 288 | const char name[ETH_GSTRING_LEN]; |
| 289 | }; |
| 290 | |
| 291 | #define T_REG_32 32 |
| 292 | #define T_REG_64 64 |
| 293 | |
| 294 | static const struct mvneta_statistic mvneta_statistics[] = { |
| 295 | { 0x3000, T_REG_64, "good_octets_received", }, |
| 296 | { 0x3010, T_REG_32, "good_frames_received", }, |
| 297 | { 0x3008, T_REG_32, "bad_octets_received", }, |
| 298 | { 0x3014, T_REG_32, "bad_frames_received", }, |
| 299 | { 0x3018, T_REG_32, "broadcast_frames_received", }, |
| 300 | { 0x301c, T_REG_32, "multicast_frames_received", }, |
| 301 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, |
| 302 | { 0x3058, T_REG_32, "good_fc_received", }, |
| 303 | { 0x305c, T_REG_32, "bad_fc_received", }, |
| 304 | { 0x3060, T_REG_32, "undersize_received", }, |
| 305 | { 0x3064, T_REG_32, "fragments_received", }, |
| 306 | { 0x3068, T_REG_32, "oversize_received", }, |
| 307 | { 0x306c, T_REG_32, "jabber_received", }, |
| 308 | { 0x3070, T_REG_32, "mac_receive_error", }, |
| 309 | { 0x3074, T_REG_32, "bad_crc_event", }, |
| 310 | { 0x3078, T_REG_32, "collision", }, |
| 311 | { 0x307c, T_REG_32, "late_collision", }, |
| 312 | { 0x2484, T_REG_32, "rx_discard", }, |
| 313 | { 0x2488, T_REG_32, "rx_overrun", }, |
| 314 | { 0x3020, T_REG_32, "frames_64_octets", }, |
| 315 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, |
| 316 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, |
| 317 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, |
| 318 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, |
| 319 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, |
| 320 | { 0x3038, T_REG_64, "good_octets_sent", }, |
| 321 | { 0x3040, T_REG_32, "good_frames_sent", }, |
| 322 | { 0x3044, T_REG_32, "excessive_collision", }, |
| 323 | { 0x3048, T_REG_32, "multicast_frames_sent", }, |
| 324 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, |
| 325 | { 0x3054, T_REG_32, "fc_sent", }, |
| 326 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, |
| 327 | }; |
| 328 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 329 | struct mvneta_pcpu_stats { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 330 | struct u64_stats_sync syncp; |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 331 | u64 rx_packets; |
| 332 | u64 rx_bytes; |
| 333 | u64 tx_packets; |
| 334 | u64 tx_bytes; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 335 | }; |
| 336 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 337 | struct mvneta_pcpu_port { |
| 338 | /* Pointer to the shared port */ |
| 339 | struct mvneta_port *pp; |
| 340 | |
| 341 | /* Pointer to the CPU-local NAPI struct */ |
| 342 | struct napi_struct napi; |
| 343 | |
| 344 | /* Cause of the previous interrupt */ |
| 345 | u32 cause_rx_tx; |
| 346 | }; |
| 347 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 348 | struct mvneta_port { |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 349 | struct mvneta_pcpu_port __percpu *ports; |
| 350 | struct mvneta_pcpu_stats __percpu *stats; |
| 351 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 352 | int pkt_size; |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 353 | unsigned int frag_size; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 354 | void __iomem *base; |
| 355 | struct mvneta_rx_queue *rxqs; |
| 356 | struct mvneta_tx_queue *txqs; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 357 | struct net_device *dev; |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 358 | struct notifier_block cpu_notifier; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 359 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 360 | /* Core clock */ |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 361 | struct clk *clk; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 362 | u8 mcast_count[256]; |
| 363 | u16 tx_ring_size; |
| 364 | u16 rx_ring_size; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 365 | |
| 366 | struct mii_bus *mii_bus; |
| 367 | struct phy_device *phy_dev; |
| 368 | phy_interface_t phy_interface; |
| 369 | struct device_node *phy_node; |
| 370 | unsigned int link; |
| 371 | unsigned int duplex; |
| 372 | unsigned int speed; |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 373 | unsigned int tx_csum_limit; |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 374 | int use_inband_status:1; |
Russell King | 9b0cdef | 2015-10-22 18:37:30 +0100 | [diff] [blame] | 375 | |
| 376 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 377 | }; |
| 378 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 379 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 380 | * layout of the transmit and reception DMA descriptors, and their |
| 381 | * layout is therefore defined by the hardware design |
| 382 | */ |
Thomas Petazzoni | 6083ed4 | 2013-07-29 15:21:27 +0200 | [diff] [blame] | 383 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 384 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
| 385 | #define MVNETA_TX_IP_HLEN_SHIFT 8 |
| 386 | #define MVNETA_TX_L4_UDP BIT(16) |
| 387 | #define MVNETA_TX_L3_IP6 BIT(17) |
| 388 | #define MVNETA_TXD_IP_CSUM BIT(18) |
| 389 | #define MVNETA_TXD_Z_PAD BIT(19) |
| 390 | #define MVNETA_TXD_L_DESC BIT(20) |
| 391 | #define MVNETA_TXD_F_DESC BIT(21) |
| 392 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ |
| 393 | MVNETA_TXD_L_DESC | \ |
| 394 | MVNETA_TXD_F_DESC) |
| 395 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) |
| 396 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) |
| 397 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 398 | #define MVNETA_RXD_ERR_CRC 0x0 |
| 399 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
| 400 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) |
| 401 | #define MVNETA_RXD_ERR_LEN BIT(18) |
| 402 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) |
| 403 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) |
| 404 | #define MVNETA_RXD_L3_IP4 BIT(25) |
| 405 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) |
| 406 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) |
| 407 | |
Thomas Petazzoni | 9ad8fef | 2013-07-29 15:21:28 +0200 | [diff] [blame] | 408 | #if defined(__LITTLE_ENDIAN) |
Thomas Petazzoni | 6083ed4 | 2013-07-29 15:21:27 +0200 | [diff] [blame] | 409 | struct mvneta_tx_desc { |
| 410 | u32 command; /* Options used by HW for packet transmitting.*/ |
| 411 | u16 reserverd1; /* csum_l4 (for future use) */ |
| 412 | u16 data_size; /* Data size of transmitted packet in bytes */ |
| 413 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ |
| 414 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ |
| 415 | u32 reserved3[4]; /* Reserved - (for future use) */ |
| 416 | }; |
| 417 | |
| 418 | struct mvneta_rx_desc { |
| 419 | u32 status; /* Info about received packet */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 420 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
| 421 | u16 data_size; /* Size of received packet in bytes */ |
Thomas Petazzoni | 6083ed4 | 2013-07-29 15:21:27 +0200 | [diff] [blame] | 422 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 423 | u32 buf_phys_addr; /* Physical address of the buffer */ |
| 424 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ |
Thomas Petazzoni | 6083ed4 | 2013-07-29 15:21:27 +0200 | [diff] [blame] | 425 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 426 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
| 427 | u16 reserved3; /* prefetch_cmd, for future use */ |
| 428 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ |
Thomas Petazzoni | 6083ed4 | 2013-07-29 15:21:27 +0200 | [diff] [blame] | 429 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 430 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
| 431 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ |
| 432 | }; |
Thomas Petazzoni | 9ad8fef | 2013-07-29 15:21:28 +0200 | [diff] [blame] | 433 | #else |
| 434 | struct mvneta_tx_desc { |
| 435 | u16 data_size; /* Data size of transmitted packet in bytes */ |
| 436 | u16 reserverd1; /* csum_l4 (for future use) */ |
| 437 | u32 command; /* Options used by HW for packet transmitting.*/ |
| 438 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ |
| 439 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ |
| 440 | u32 reserved3[4]; /* Reserved - (for future use) */ |
| 441 | }; |
| 442 | |
| 443 | struct mvneta_rx_desc { |
| 444 | u16 data_size; /* Size of received packet in bytes */ |
| 445 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
| 446 | u32 status; /* Info about received packet */ |
| 447 | |
| 448 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ |
| 449 | u32 buf_phys_addr; /* Physical address of the buffer */ |
| 450 | |
| 451 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ |
| 452 | u16 reserved3; /* prefetch_cmd, for future use */ |
| 453 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
| 454 | |
| 455 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
| 456 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ |
| 457 | }; |
| 458 | #endif |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 459 | |
| 460 | struct mvneta_tx_queue { |
| 461 | /* Number of this TX queue, in the range 0-7 */ |
| 462 | u8 id; |
| 463 | |
| 464 | /* Number of TX DMA descriptors in the descriptor ring */ |
| 465 | int size; |
| 466 | |
| 467 | /* Number of currently used TX DMA descriptor in the |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 468 | * descriptor ring |
| 469 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 470 | int count; |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 471 | int tx_stop_threshold; |
| 472 | int tx_wake_threshold; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 473 | |
| 474 | /* Array of transmitted skb */ |
| 475 | struct sk_buff **tx_skb; |
| 476 | |
| 477 | /* Index of last TX DMA descriptor that was inserted */ |
| 478 | int txq_put_index; |
| 479 | |
| 480 | /* Index of the TX DMA descriptor to be cleaned up */ |
| 481 | int txq_get_index; |
| 482 | |
| 483 | u32 done_pkts_coal; |
| 484 | |
| 485 | /* Virtual address of the TX DMA descriptors array */ |
| 486 | struct mvneta_tx_desc *descs; |
| 487 | |
| 488 | /* DMA address of the TX DMA descriptors array */ |
| 489 | dma_addr_t descs_phys; |
| 490 | |
| 491 | /* Index of the last TX DMA descriptor */ |
| 492 | int last_desc; |
| 493 | |
| 494 | /* Index of the next TX DMA descriptor to process */ |
| 495 | int next_desc_to_proc; |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 496 | |
| 497 | /* DMA buffers for TSO headers */ |
| 498 | char *tso_hdrs; |
| 499 | |
| 500 | /* DMA address of TSO headers */ |
| 501 | dma_addr_t tso_hdrs_phys; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 502 | }; |
| 503 | |
| 504 | struct mvneta_rx_queue { |
| 505 | /* rx queue number, in the range 0-7 */ |
| 506 | u8 id; |
| 507 | |
| 508 | /* num of rx descriptors in the rx descriptor ring */ |
| 509 | int size; |
| 510 | |
| 511 | /* counter of times when mvneta_refill() failed */ |
| 512 | int missed; |
| 513 | |
| 514 | u32 pkts_coal; |
| 515 | u32 time_coal; |
| 516 | |
| 517 | /* Virtual address of the RX DMA descriptors array */ |
| 518 | struct mvneta_rx_desc *descs; |
| 519 | |
| 520 | /* DMA address of the RX DMA descriptors array */ |
| 521 | dma_addr_t descs_phys; |
| 522 | |
| 523 | /* Index of the last RX DMA descriptor */ |
| 524 | int last_desc; |
| 525 | |
| 526 | /* Index of the next RX DMA descriptor to process */ |
| 527 | int next_desc_to_proc; |
| 528 | }; |
| 529 | |
Ezequiel Garcia | edadb7f | 2014-05-22 20:07:01 -0300 | [diff] [blame] | 530 | /* The hardware supports eight (8) rx queues, but we are only allowing |
| 531 | * the first one to be used. Therefore, let's just allocate one queue. |
| 532 | */ |
Maxime Ripard | d893665 | 2015-09-25 18:09:37 +0200 | [diff] [blame] | 533 | static int rxq_number = 8; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 534 | static int txq_number = 8; |
| 535 | |
| 536 | static int rxq_def; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 537 | |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 538 | static int rx_copybreak __read_mostly = 256; |
| 539 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 540 | #define MVNETA_DRIVER_NAME "mvneta" |
| 541 | #define MVNETA_DRIVER_VERSION "1.0" |
| 542 | |
| 543 | /* Utility/helper methods */ |
| 544 | |
| 545 | /* Write helper method */ |
| 546 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) |
| 547 | { |
| 548 | writel(data, pp->base + offset); |
| 549 | } |
| 550 | |
| 551 | /* Read helper method */ |
| 552 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) |
| 553 | { |
| 554 | return readl(pp->base + offset); |
| 555 | } |
| 556 | |
| 557 | /* Increment txq get counter */ |
| 558 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) |
| 559 | { |
| 560 | txq->txq_get_index++; |
| 561 | if (txq->txq_get_index == txq->size) |
| 562 | txq->txq_get_index = 0; |
| 563 | } |
| 564 | |
| 565 | /* Increment txq put counter */ |
| 566 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) |
| 567 | { |
| 568 | txq->txq_put_index++; |
| 569 | if (txq->txq_put_index == txq->size) |
| 570 | txq->txq_put_index = 0; |
| 571 | } |
| 572 | |
| 573 | |
| 574 | /* Clear all MIB counters */ |
| 575 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) |
| 576 | { |
| 577 | int i; |
| 578 | u32 dummy; |
| 579 | |
| 580 | /* Perform dummy reads from MIB counters */ |
| 581 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) |
| 582 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); |
Andrew Lunn | e483911 | 2015-10-22 18:37:36 +0100 | [diff] [blame] | 583 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
| 584 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 585 | } |
| 586 | |
| 587 | /* Get System Network Statistics */ |
| 588 | struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, |
| 589 | struct rtnl_link_stats64 *stats) |
| 590 | { |
| 591 | struct mvneta_port *pp = netdev_priv(dev); |
| 592 | unsigned int start; |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 593 | int cpu; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 594 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 595 | for_each_possible_cpu(cpu) { |
| 596 | struct mvneta_pcpu_stats *cpu_stats; |
| 597 | u64 rx_packets; |
| 598 | u64 rx_bytes; |
| 599 | u64 tx_packets; |
| 600 | u64 tx_bytes; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 601 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 602 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
| 603 | do { |
Eric W. Biederman | 57a7744 | 2014-03-13 21:26:42 -0700 | [diff] [blame] | 604 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 605 | rx_packets = cpu_stats->rx_packets; |
| 606 | rx_bytes = cpu_stats->rx_bytes; |
| 607 | tx_packets = cpu_stats->tx_packets; |
| 608 | tx_bytes = cpu_stats->tx_bytes; |
Eric W. Biederman | 57a7744 | 2014-03-13 21:26:42 -0700 | [diff] [blame] | 609 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 610 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 611 | stats->rx_packets += rx_packets; |
| 612 | stats->rx_bytes += rx_bytes; |
| 613 | stats->tx_packets += tx_packets; |
| 614 | stats->tx_bytes += tx_bytes; |
| 615 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 616 | |
| 617 | stats->rx_errors = dev->stats.rx_errors; |
| 618 | stats->rx_dropped = dev->stats.rx_dropped; |
| 619 | |
| 620 | stats->tx_dropped = dev->stats.tx_dropped; |
| 621 | |
| 622 | return stats; |
| 623 | } |
| 624 | |
| 625 | /* Rx descriptors helper methods */ |
| 626 | |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 627 | /* Checks whether the RX descriptor having this status is both the first |
| 628 | * and the last descriptor for the RX packet. Each RX packet is currently |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 629 | * received through a single RX descriptor, so not having each RX |
| 630 | * descriptor with its first and last bits set is an error |
| 631 | */ |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 632 | static int mvneta_rxq_desc_is_first_last(u32 status) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 633 | { |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 634 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 635 | MVNETA_RXD_FIRST_LAST_DESC; |
| 636 | } |
| 637 | |
| 638 | /* Add number of descriptors ready to receive new packets */ |
| 639 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, |
| 640 | struct mvneta_rx_queue *rxq, |
| 641 | int ndescs) |
| 642 | { |
| 643 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 644 | * be added at once |
| 645 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 646 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
| 647 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), |
| 648 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << |
| 649 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); |
| 650 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; |
| 651 | } |
| 652 | |
| 653 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), |
| 654 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); |
| 655 | } |
| 656 | |
| 657 | /* Get number of RX descriptors occupied by received packets */ |
| 658 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, |
| 659 | struct mvneta_rx_queue *rxq) |
| 660 | { |
| 661 | u32 val; |
| 662 | |
| 663 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); |
| 664 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; |
| 665 | } |
| 666 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 667 | /* Update num of rx desc called upon return from rx path or |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 668 | * from mvneta_rxq_drop_pkts(). |
| 669 | */ |
| 670 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, |
| 671 | struct mvneta_rx_queue *rxq, |
| 672 | int rx_done, int rx_filled) |
| 673 | { |
| 674 | u32 val; |
| 675 | |
| 676 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { |
| 677 | val = rx_done | |
| 678 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); |
| 679 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); |
| 680 | return; |
| 681 | } |
| 682 | |
| 683 | /* Only 255 descriptors can be added at once */ |
| 684 | while ((rx_done > 0) || (rx_filled > 0)) { |
| 685 | if (rx_done <= 0xff) { |
| 686 | val = rx_done; |
| 687 | rx_done = 0; |
| 688 | } else { |
| 689 | val = 0xff; |
| 690 | rx_done -= 0xff; |
| 691 | } |
| 692 | if (rx_filled <= 0xff) { |
| 693 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; |
| 694 | rx_filled = 0; |
| 695 | } else { |
| 696 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; |
| 697 | rx_filled -= 0xff; |
| 698 | } |
| 699 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | /* Get pointer to next RX descriptor to be processed by SW */ |
| 704 | static struct mvneta_rx_desc * |
| 705 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) |
| 706 | { |
| 707 | int rx_desc = rxq->next_desc_to_proc; |
| 708 | |
| 709 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); |
willy tarreau | 34e4179 | 2014-01-16 08:20:15 +0100 | [diff] [blame] | 710 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 711 | return rxq->descs + rx_desc; |
| 712 | } |
| 713 | |
| 714 | /* Change maximum receive size of the port. */ |
| 715 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) |
| 716 | { |
| 717 | u32 val; |
| 718 | |
| 719 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
| 720 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; |
| 721 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << |
| 722 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; |
| 723 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); |
| 724 | } |
| 725 | |
| 726 | |
| 727 | /* Set rx queue offset */ |
| 728 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, |
| 729 | struct mvneta_rx_queue *rxq, |
| 730 | int offset) |
| 731 | { |
| 732 | u32 val; |
| 733 | |
| 734 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); |
| 735 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; |
| 736 | |
| 737 | /* Offset is in */ |
| 738 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); |
| 739 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); |
| 740 | } |
| 741 | |
| 742 | |
| 743 | /* Tx descriptors helper methods */ |
| 744 | |
| 745 | /* Update HW with number of TX descriptors to be sent */ |
| 746 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, |
| 747 | struct mvneta_tx_queue *txq, |
| 748 | int pend_desc) |
| 749 | { |
| 750 | u32 val; |
| 751 | |
| 752 | /* Only 255 descriptors can be added at once ; Assume caller |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 753 | * process TX desriptors in quanta less than 256 |
| 754 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 755 | val = pend_desc; |
| 756 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
| 757 | } |
| 758 | |
| 759 | /* Get pointer to next TX descriptor to be processed (send) by HW */ |
| 760 | static struct mvneta_tx_desc * |
| 761 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) |
| 762 | { |
| 763 | int tx_desc = txq->next_desc_to_proc; |
| 764 | |
| 765 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); |
| 766 | return txq->descs + tx_desc; |
| 767 | } |
| 768 | |
| 769 | /* Release the last allocated TX descriptor. Useful to handle DMA |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 770 | * mapping failures in the TX path. |
| 771 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 772 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
| 773 | { |
| 774 | if (txq->next_desc_to_proc == 0) |
| 775 | txq->next_desc_to_proc = txq->last_desc - 1; |
| 776 | else |
| 777 | txq->next_desc_to_proc--; |
| 778 | } |
| 779 | |
| 780 | /* Set rxq buf size */ |
| 781 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, |
| 782 | struct mvneta_rx_queue *rxq, |
| 783 | int buf_size) |
| 784 | { |
| 785 | u32 val; |
| 786 | |
| 787 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); |
| 788 | |
| 789 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; |
| 790 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); |
| 791 | |
| 792 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); |
| 793 | } |
| 794 | |
| 795 | /* Disable buffer management (BM) */ |
| 796 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, |
| 797 | struct mvneta_rx_queue *rxq) |
| 798 | { |
| 799 | u32 val; |
| 800 | |
| 801 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); |
| 802 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; |
| 803 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); |
| 804 | } |
| 805 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 806 | /* Start the Ethernet port RX and TX activity */ |
| 807 | static void mvneta_port_up(struct mvneta_port *pp) |
| 808 | { |
| 809 | int queue; |
| 810 | u32 q_map; |
| 811 | |
| 812 | /* Enable all initialized TXs. */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 813 | q_map = 0; |
| 814 | for (queue = 0; queue < txq_number; queue++) { |
| 815 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; |
| 816 | if (txq->descs != NULL) |
| 817 | q_map |= (1 << queue); |
| 818 | } |
| 819 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); |
| 820 | |
| 821 | /* Enable all initialized RXQs. */ |
Maxime Ripard | d893665 | 2015-09-25 18:09:37 +0200 | [diff] [blame] | 822 | mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 823 | } |
| 824 | |
| 825 | /* Stop the Ethernet port activity */ |
| 826 | static void mvneta_port_down(struct mvneta_port *pp) |
| 827 | { |
| 828 | u32 val; |
| 829 | int count; |
| 830 | |
| 831 | /* Stop Rx port activity. Check port Rx activity. */ |
| 832 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; |
| 833 | |
| 834 | /* Issue stop command for active channels only */ |
| 835 | if (val != 0) |
| 836 | mvreg_write(pp, MVNETA_RXQ_CMD, |
| 837 | val << MVNETA_RXQ_DISABLE_SHIFT); |
| 838 | |
| 839 | /* Wait for all Rx activity to terminate. */ |
| 840 | count = 0; |
| 841 | do { |
| 842 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { |
| 843 | netdev_warn(pp->dev, |
| 844 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", |
| 845 | val); |
| 846 | break; |
| 847 | } |
| 848 | mdelay(1); |
| 849 | |
| 850 | val = mvreg_read(pp, MVNETA_RXQ_CMD); |
| 851 | } while (val & 0xff); |
| 852 | |
| 853 | /* Stop Tx port activity. Check port Tx activity. Issue stop |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 854 | * command for active channels only |
| 855 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 856 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
| 857 | |
| 858 | if (val != 0) |
| 859 | mvreg_write(pp, MVNETA_TXQ_CMD, |
| 860 | (val << MVNETA_TXQ_DISABLE_SHIFT)); |
| 861 | |
| 862 | /* Wait for all Tx activity to terminate. */ |
| 863 | count = 0; |
| 864 | do { |
| 865 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { |
| 866 | netdev_warn(pp->dev, |
| 867 | "TIMEOUT for TX stopped status=0x%08x\n", |
| 868 | val); |
| 869 | break; |
| 870 | } |
| 871 | mdelay(1); |
| 872 | |
| 873 | /* Check TX Command reg that all Txqs are stopped */ |
| 874 | val = mvreg_read(pp, MVNETA_TXQ_CMD); |
| 875 | |
| 876 | } while (val & 0xff); |
| 877 | |
| 878 | /* Double check to verify that TX FIFO is empty */ |
| 879 | count = 0; |
| 880 | do { |
| 881 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { |
| 882 | netdev_warn(pp->dev, |
| 883 | "TX FIFO empty timeout status=0x08%x\n", |
| 884 | val); |
| 885 | break; |
| 886 | } |
| 887 | mdelay(1); |
| 888 | |
| 889 | val = mvreg_read(pp, MVNETA_PORT_STATUS); |
| 890 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && |
| 891 | (val & MVNETA_TX_IN_PRGRS)); |
| 892 | |
| 893 | udelay(200); |
| 894 | } |
| 895 | |
| 896 | /* Enable the port by setting the port enable bit of the MAC control register */ |
| 897 | static void mvneta_port_enable(struct mvneta_port *pp) |
| 898 | { |
| 899 | u32 val; |
| 900 | |
| 901 | /* Enable port */ |
| 902 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
| 903 | val |= MVNETA_GMAC0_PORT_ENABLE; |
| 904 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); |
| 905 | } |
| 906 | |
| 907 | /* Disable the port and wait for about 200 usec before retuning */ |
| 908 | static void mvneta_port_disable(struct mvneta_port *pp) |
| 909 | { |
| 910 | u32 val; |
| 911 | |
| 912 | /* Reset the Enable bit in the Serial Control Register */ |
| 913 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); |
| 914 | val &= ~MVNETA_GMAC0_PORT_ENABLE; |
| 915 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); |
| 916 | |
| 917 | udelay(200); |
| 918 | } |
| 919 | |
| 920 | /* Multicast tables methods */ |
| 921 | |
| 922 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ |
| 923 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) |
| 924 | { |
| 925 | int offset; |
| 926 | u32 val; |
| 927 | |
| 928 | if (queue == -1) { |
| 929 | val = 0; |
| 930 | } else { |
| 931 | val = 0x1 | (queue << 1); |
| 932 | val |= (val << 24) | (val << 16) | (val << 8); |
| 933 | } |
| 934 | |
| 935 | for (offset = 0; offset <= 0xc; offset += 4) |
| 936 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); |
| 937 | } |
| 938 | |
| 939 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ |
| 940 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) |
| 941 | { |
| 942 | int offset; |
| 943 | u32 val; |
| 944 | |
| 945 | if (queue == -1) { |
| 946 | val = 0; |
| 947 | } else { |
| 948 | val = 0x1 | (queue << 1); |
| 949 | val |= (val << 24) | (val << 16) | (val << 8); |
| 950 | } |
| 951 | |
| 952 | for (offset = 0; offset <= 0xfc; offset += 4) |
| 953 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); |
| 954 | |
| 955 | } |
| 956 | |
| 957 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ |
| 958 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) |
| 959 | { |
| 960 | int offset; |
| 961 | u32 val; |
| 962 | |
| 963 | if (queue == -1) { |
| 964 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); |
| 965 | val = 0; |
| 966 | } else { |
| 967 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); |
| 968 | val = 0x1 | (queue << 1); |
| 969 | val |= (val << 24) | (val << 16) | (val << 8); |
| 970 | } |
| 971 | |
| 972 | for (offset = 0; offset <= 0xfc; offset += 4) |
| 973 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); |
| 974 | } |
| 975 | |
| 976 | /* This method sets defaults to the NETA port: |
| 977 | * Clears interrupt Cause and Mask registers. |
| 978 | * Clears all MAC tables. |
| 979 | * Sets defaults to all registers. |
| 980 | * Resets RX and TX descriptor rings. |
| 981 | * Resets PHY. |
| 982 | * This method can be called after mvneta_port_down() to return the port |
| 983 | * settings to defaults. |
| 984 | */ |
| 985 | static void mvneta_defaults_set(struct mvneta_port *pp) |
| 986 | { |
| 987 | int cpu; |
| 988 | int queue; |
| 989 | u32 val; |
| 990 | |
| 991 | /* Clear all Cause registers */ |
| 992 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); |
| 993 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); |
| 994 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); |
| 995 | |
| 996 | /* Mask all interrupts */ |
| 997 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 998 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); |
| 999 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); |
| 1000 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
| 1001 | |
| 1002 | /* Enable MBUS Retry bit16 */ |
| 1003 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); |
| 1004 | |
| 1005 | /* Set CPU queue access map - all CPUs have access to all RX |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1006 | * queues and to all TX queues |
| 1007 | */ |
Maxime Ripard | 2502d0e | 2015-09-25 18:09:35 +0200 | [diff] [blame] | 1008 | for_each_present_cpu(cpu) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1009 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), |
| 1010 | (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | |
| 1011 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); |
| 1012 | |
| 1013 | /* Reset RX and TX DMAs */ |
| 1014 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); |
| 1015 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); |
| 1016 | |
| 1017 | /* Disable Legacy WRR, Disable EJP, Release from reset */ |
| 1018 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); |
| 1019 | for (queue = 0; queue < txq_number; queue++) { |
| 1020 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); |
| 1021 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); |
| 1022 | } |
| 1023 | |
| 1024 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); |
| 1025 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); |
| 1026 | |
| 1027 | /* Set Port Acceleration Mode */ |
| 1028 | val = MVNETA_ACC_MODE_EXT; |
| 1029 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
| 1030 | |
| 1031 | /* Update val of portCfg register accordingly with all RxQueue types */ |
| 1032 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); |
| 1033 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
| 1034 | |
| 1035 | val = 0; |
| 1036 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); |
| 1037 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); |
| 1038 | |
| 1039 | /* Build PORT_SDMA_CONFIG_REG */ |
| 1040 | val = 0; |
| 1041 | |
| 1042 | /* Default burst size */ |
| 1043 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); |
| 1044 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); |
Thomas Petazzoni | 9ad8fef | 2013-07-29 15:21:28 +0200 | [diff] [blame] | 1045 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1046 | |
Thomas Petazzoni | 9ad8fef | 2013-07-29 15:21:28 +0200 | [diff] [blame] | 1047 | #if defined(__BIG_ENDIAN) |
| 1048 | val |= MVNETA_DESC_SWAP; |
| 1049 | #endif |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1050 | |
| 1051 | /* Assign port SDMA configuration */ |
| 1052 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); |
| 1053 | |
Thomas Petazzoni | 7140860 | 2013-09-04 16:21:18 +0200 | [diff] [blame] | 1054 | /* Disable PHY polling in hardware, since we're using the |
| 1055 | * kernel phylib to do this. |
| 1056 | */ |
| 1057 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); |
| 1058 | val &= ~MVNETA_PHY_POLLING_ENABLE; |
| 1059 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); |
| 1060 | |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 1061 | if (pp->use_inband_status) { |
| 1062 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
| 1063 | val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | |
| 1064 | MVNETA_GMAC_FORCE_LINK_DOWN | |
| 1065 | MVNETA_GMAC_AN_FLOW_CTRL_EN); |
| 1066 | val |= MVNETA_GMAC_INBAND_AN_ENABLE | |
| 1067 | MVNETA_GMAC_AN_SPEED_EN | |
| 1068 | MVNETA_GMAC_AN_DUPLEX_EN; |
| 1069 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); |
| 1070 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); |
| 1071 | val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; |
| 1072 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); |
Stas Sergeev | 538761b | 2015-06-18 18:36:03 +0300 | [diff] [blame] | 1073 | } else { |
| 1074 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
| 1075 | val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | |
| 1076 | MVNETA_GMAC_AN_SPEED_EN | |
| 1077 | MVNETA_GMAC_AN_DUPLEX_EN); |
| 1078 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 1079 | } |
| 1080 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1081 | mvneta_set_ucast_table(pp, -1); |
| 1082 | mvneta_set_special_mcast_table(pp, -1); |
| 1083 | mvneta_set_other_mcast_table(pp, -1); |
| 1084 | |
| 1085 | /* Set port interrupt enable register - default enable all */ |
| 1086 | mvreg_write(pp, MVNETA_INTR_ENABLE, |
| 1087 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK |
| 1088 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); |
Andrew Lunn | e483911 | 2015-10-22 18:37:36 +0100 | [diff] [blame] | 1089 | |
| 1090 | mvneta_mib_counters_clear(pp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1091 | } |
| 1092 | |
| 1093 | /* Set max sizes for tx queues */ |
| 1094 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) |
| 1095 | |
| 1096 | { |
| 1097 | u32 val, size, mtu; |
| 1098 | int queue; |
| 1099 | |
| 1100 | mtu = max_tx_size * 8; |
| 1101 | if (mtu > MVNETA_TX_MTU_MAX) |
| 1102 | mtu = MVNETA_TX_MTU_MAX; |
| 1103 | |
| 1104 | /* Set MTU */ |
| 1105 | val = mvreg_read(pp, MVNETA_TX_MTU); |
| 1106 | val &= ~MVNETA_TX_MTU_MAX; |
| 1107 | val |= mtu; |
| 1108 | mvreg_write(pp, MVNETA_TX_MTU, val); |
| 1109 | |
| 1110 | /* TX token size and all TXQs token size must be larger that MTU */ |
| 1111 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); |
| 1112 | |
| 1113 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; |
| 1114 | if (size < mtu) { |
| 1115 | size = mtu; |
| 1116 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; |
| 1117 | val |= size; |
| 1118 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); |
| 1119 | } |
| 1120 | for (queue = 0; queue < txq_number; queue++) { |
| 1121 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); |
| 1122 | |
| 1123 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; |
| 1124 | if (size < mtu) { |
| 1125 | size = mtu; |
| 1126 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; |
| 1127 | val |= size; |
| 1128 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); |
| 1129 | } |
| 1130 | } |
| 1131 | } |
| 1132 | |
| 1133 | /* Set unicast address */ |
| 1134 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, |
| 1135 | int queue) |
| 1136 | { |
| 1137 | unsigned int unicast_reg; |
| 1138 | unsigned int tbl_offset; |
| 1139 | unsigned int reg_offset; |
| 1140 | |
| 1141 | /* Locate the Unicast table entry */ |
| 1142 | last_nibble = (0xf & last_nibble); |
| 1143 | |
| 1144 | /* offset from unicast tbl base */ |
| 1145 | tbl_offset = (last_nibble / 4) * 4; |
| 1146 | |
| 1147 | /* offset within the above reg */ |
| 1148 | reg_offset = last_nibble % 4; |
| 1149 | |
| 1150 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); |
| 1151 | |
| 1152 | if (queue == -1) { |
| 1153 | /* Clear accepts frame bit at specified unicast DA tbl entry */ |
| 1154 | unicast_reg &= ~(0xff << (8 * reg_offset)); |
| 1155 | } else { |
| 1156 | unicast_reg &= ~(0xff << (8 * reg_offset)); |
| 1157 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); |
| 1158 | } |
| 1159 | |
| 1160 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); |
| 1161 | } |
| 1162 | |
| 1163 | /* Set mac address */ |
| 1164 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, |
| 1165 | int queue) |
| 1166 | { |
| 1167 | unsigned int mac_h; |
| 1168 | unsigned int mac_l; |
| 1169 | |
| 1170 | if (queue != -1) { |
| 1171 | mac_l = (addr[4] << 8) | (addr[5]); |
| 1172 | mac_h = (addr[0] << 24) | (addr[1] << 16) | |
| 1173 | (addr[2] << 8) | (addr[3] << 0); |
| 1174 | |
| 1175 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); |
| 1176 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); |
| 1177 | } |
| 1178 | |
| 1179 | /* Accept frames of this address */ |
| 1180 | mvneta_set_ucast_addr(pp, addr[5], queue); |
| 1181 | } |
| 1182 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1183 | /* Set the number of packets that will be received before RX interrupt |
| 1184 | * will be generated by HW. |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1185 | */ |
| 1186 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, |
| 1187 | struct mvneta_rx_queue *rxq, u32 value) |
| 1188 | { |
| 1189 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), |
| 1190 | value | MVNETA_RXQ_NON_OCCUPIED(0)); |
| 1191 | rxq->pkts_coal = value; |
| 1192 | } |
| 1193 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1194 | /* Set the time delay in usec before RX interrupt will be generated by |
| 1195 | * HW. |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1196 | */ |
| 1197 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, |
| 1198 | struct mvneta_rx_queue *rxq, u32 value) |
| 1199 | { |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 1200 | u32 val; |
| 1201 | unsigned long clk_rate; |
| 1202 | |
| 1203 | clk_rate = clk_get_rate(pp->clk); |
| 1204 | val = (clk_rate / 1000000) * value; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1205 | |
| 1206 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); |
| 1207 | rxq->time_coal = value; |
| 1208 | } |
| 1209 | |
| 1210 | /* Set threshold for TX_DONE pkts coalescing */ |
| 1211 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, |
| 1212 | struct mvneta_tx_queue *txq, u32 value) |
| 1213 | { |
| 1214 | u32 val; |
| 1215 | |
| 1216 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); |
| 1217 | |
| 1218 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; |
| 1219 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); |
| 1220 | |
| 1221 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); |
| 1222 | |
| 1223 | txq->done_pkts_coal = value; |
| 1224 | } |
| 1225 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1226 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
| 1227 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, |
| 1228 | u32 phys_addr, u32 cookie) |
| 1229 | { |
| 1230 | rx_desc->buf_cookie = cookie; |
| 1231 | rx_desc->buf_phys_addr = phys_addr; |
| 1232 | } |
| 1233 | |
| 1234 | /* Decrement sent descriptors counter */ |
| 1235 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, |
| 1236 | struct mvneta_tx_queue *txq, |
| 1237 | int sent_desc) |
| 1238 | { |
| 1239 | u32 val; |
| 1240 | |
| 1241 | /* Only 255 TX descriptors can be updated at once */ |
| 1242 | while (sent_desc > 0xff) { |
| 1243 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; |
| 1244 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
| 1245 | sent_desc = sent_desc - 0xff; |
| 1246 | } |
| 1247 | |
| 1248 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; |
| 1249 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); |
| 1250 | } |
| 1251 | |
| 1252 | /* Get number of TX descriptors already sent by HW */ |
| 1253 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, |
| 1254 | struct mvneta_tx_queue *txq) |
| 1255 | { |
| 1256 | u32 val; |
| 1257 | int sent_desc; |
| 1258 | |
| 1259 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); |
| 1260 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> |
| 1261 | MVNETA_TXQ_SENT_DESC_SHIFT; |
| 1262 | |
| 1263 | return sent_desc; |
| 1264 | } |
| 1265 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1266 | /* Get number of sent descriptors and decrement counter. |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1267 | * The number of sent descriptors is returned. |
| 1268 | */ |
| 1269 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, |
| 1270 | struct mvneta_tx_queue *txq) |
| 1271 | { |
| 1272 | int sent_desc; |
| 1273 | |
| 1274 | /* Get number of sent descriptors */ |
| 1275 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); |
| 1276 | |
| 1277 | /* Decrement sent descriptors counter */ |
| 1278 | if (sent_desc) |
| 1279 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); |
| 1280 | |
| 1281 | return sent_desc; |
| 1282 | } |
| 1283 | |
| 1284 | /* Set TXQ descriptors fields relevant for CSUM calculation */ |
| 1285 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, |
| 1286 | int ip_hdr_len, int l4_proto) |
| 1287 | { |
| 1288 | u32 command; |
| 1289 | |
| 1290 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1291 | * G_L4_chk, L4_type; required only for checksum |
| 1292 | * calculation |
| 1293 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1294 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
| 1295 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; |
| 1296 | |
Thomas Fitzsimmons | 0a19858 | 2014-07-08 19:44:07 -0400 | [diff] [blame] | 1297 | if (l3_proto == htons(ETH_P_IP)) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1298 | command |= MVNETA_TXD_IP_CSUM; |
| 1299 | else |
| 1300 | command |= MVNETA_TX_L3_IP6; |
| 1301 | |
| 1302 | if (l4_proto == IPPROTO_TCP) |
| 1303 | command |= MVNETA_TX_L4_CSUM_FULL; |
| 1304 | else if (l4_proto == IPPROTO_UDP) |
| 1305 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; |
| 1306 | else |
| 1307 | command |= MVNETA_TX_L4_CSUM_NOT; |
| 1308 | |
| 1309 | return command; |
| 1310 | } |
| 1311 | |
| 1312 | |
| 1313 | /* Display more error info */ |
| 1314 | static void mvneta_rx_error(struct mvneta_port *pp, |
| 1315 | struct mvneta_rx_desc *rx_desc) |
| 1316 | { |
| 1317 | u32 status = rx_desc->status; |
| 1318 | |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 1319 | if (!mvneta_rxq_desc_is_first_last(status)) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1320 | netdev_err(pp->dev, |
| 1321 | "bad rx status %08x (buffer oversize), size=%d\n", |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 1322 | status, rx_desc->data_size); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1323 | return; |
| 1324 | } |
| 1325 | |
| 1326 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { |
| 1327 | case MVNETA_RXD_ERR_CRC: |
| 1328 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", |
| 1329 | status, rx_desc->data_size); |
| 1330 | break; |
| 1331 | case MVNETA_RXD_ERR_OVERRUN: |
| 1332 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", |
| 1333 | status, rx_desc->data_size); |
| 1334 | break; |
| 1335 | case MVNETA_RXD_ERR_LEN: |
| 1336 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", |
| 1337 | status, rx_desc->data_size); |
| 1338 | break; |
| 1339 | case MVNETA_RXD_ERR_RESOURCE: |
| 1340 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", |
| 1341 | status, rx_desc->data_size); |
| 1342 | break; |
| 1343 | } |
| 1344 | } |
| 1345 | |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 1346 | /* Handle RX checksum offload based on the descriptor's status */ |
| 1347 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1348 | struct sk_buff *skb) |
| 1349 | { |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 1350 | if ((status & MVNETA_RXD_L3_IP4) && |
| 1351 | (status & MVNETA_RXD_L4_CSUM_OK)) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1352 | skb->csum = 0; |
| 1353 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1354 | return; |
| 1355 | } |
| 1356 | |
| 1357 | skb->ip_summed = CHECKSUM_NONE; |
| 1358 | } |
| 1359 | |
willy tarreau | 6c49897 | 2014-01-16 08:20:12 +0100 | [diff] [blame] | 1360 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
| 1361 | * form tx_done reg. <cause> must not be null. The return value is always a |
| 1362 | * valid queue for matching the first one found in <cause>. |
| 1363 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1364 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
| 1365 | u32 cause) |
| 1366 | { |
| 1367 | int queue = fls(cause) - 1; |
| 1368 | |
willy tarreau | 6c49897 | 2014-01-16 08:20:12 +0100 | [diff] [blame] | 1369 | return &pp->txqs[queue]; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1370 | } |
| 1371 | |
| 1372 | /* Free tx queue skbuffs */ |
| 1373 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, |
| 1374 | struct mvneta_tx_queue *txq, int num) |
| 1375 | { |
| 1376 | int i; |
| 1377 | |
| 1378 | for (i = 0; i < num; i++) { |
| 1379 | struct mvneta_tx_desc *tx_desc = txq->descs + |
| 1380 | txq->txq_get_index; |
| 1381 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; |
| 1382 | |
| 1383 | mvneta_txq_inc_get(txq); |
| 1384 | |
Ezequiel Garcia | 2e3173a | 2014-05-30 13:40:07 -0300 | [diff] [blame] | 1385 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
| 1386 | dma_unmap_single(pp->dev->dev.parent, |
| 1387 | tx_desc->buf_phys_addr, |
| 1388 | tx_desc->data_size, DMA_TO_DEVICE); |
Ezequiel Garcia | ba7e46e | 2014-05-30 13:40:06 -0300 | [diff] [blame] | 1389 | if (!skb) |
| 1390 | continue; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1391 | dev_kfree_skb_any(skb); |
| 1392 | } |
| 1393 | } |
| 1394 | |
| 1395 | /* Handle end of transmission */ |
Arnaud Ebalard | cd71319 | 2014-01-16 08:20:19 +0100 | [diff] [blame] | 1396 | static void mvneta_txq_done(struct mvneta_port *pp, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1397 | struct mvneta_tx_queue *txq) |
| 1398 | { |
| 1399 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
| 1400 | int tx_done; |
| 1401 | |
| 1402 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); |
Arnaud Ebalard | cd71319 | 2014-01-16 08:20:19 +0100 | [diff] [blame] | 1403 | if (!tx_done) |
| 1404 | return; |
| 1405 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1406 | mvneta_txq_bufs_free(pp, txq, tx_done); |
| 1407 | |
| 1408 | txq->count -= tx_done; |
| 1409 | |
| 1410 | if (netif_tx_queue_stopped(nq)) { |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 1411 | if (txq->count <= txq->tx_wake_threshold) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1412 | netif_tx_wake_queue(nq); |
| 1413 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1414 | } |
| 1415 | |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1416 | static void *mvneta_frag_alloc(const struct mvneta_port *pp) |
| 1417 | { |
| 1418 | if (likely(pp->frag_size <= PAGE_SIZE)) |
| 1419 | return netdev_alloc_frag(pp->frag_size); |
| 1420 | else |
| 1421 | return kmalloc(pp->frag_size, GFP_ATOMIC); |
| 1422 | } |
| 1423 | |
| 1424 | static void mvneta_frag_free(const struct mvneta_port *pp, void *data) |
| 1425 | { |
| 1426 | if (likely(pp->frag_size <= PAGE_SIZE)) |
Alexander Duyck | 13dc0d2 | 2015-05-06 21:12:14 -0700 | [diff] [blame] | 1427 | skb_free_frag(data); |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1428 | else |
| 1429 | kfree(data); |
| 1430 | } |
| 1431 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1432 | /* Refill processing */ |
| 1433 | static int mvneta_rx_refill(struct mvneta_port *pp, |
| 1434 | struct mvneta_rx_desc *rx_desc) |
| 1435 | |
| 1436 | { |
| 1437 | dma_addr_t phys_addr; |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1438 | void *data; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1439 | |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1440 | data = mvneta_frag_alloc(pp); |
| 1441 | if (!data) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1442 | return -ENOMEM; |
| 1443 | |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1444 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1445 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
| 1446 | DMA_FROM_DEVICE); |
| 1447 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1448 | mvneta_frag_free(pp, data); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1449 | return -ENOMEM; |
| 1450 | } |
| 1451 | |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1452 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1453 | return 0; |
| 1454 | } |
| 1455 | |
| 1456 | /* Handle tx checksum */ |
| 1457 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) |
| 1458 | { |
| 1459 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 1460 | int ip_hdr_len = 0; |
Vlad Yasevich | 817dbfa | 2014-08-25 10:34:54 -0400 | [diff] [blame] | 1461 | __be16 l3_proto = vlan_get_protocol(skb); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1462 | u8 l4_proto; |
| 1463 | |
Vlad Yasevich | 817dbfa | 2014-08-25 10:34:54 -0400 | [diff] [blame] | 1464 | if (l3_proto == htons(ETH_P_IP)) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1465 | struct iphdr *ip4h = ip_hdr(skb); |
| 1466 | |
| 1467 | /* Calculate IPv4 checksum and L4 checksum */ |
| 1468 | ip_hdr_len = ip4h->ihl; |
| 1469 | l4_proto = ip4h->protocol; |
Vlad Yasevich | 817dbfa | 2014-08-25 10:34:54 -0400 | [diff] [blame] | 1470 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1471 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
| 1472 | |
| 1473 | /* Read l4_protocol from one of IPv6 extra headers */ |
| 1474 | if (skb_network_header_len(skb) > 0) |
| 1475 | ip_hdr_len = (skb_network_header_len(skb) >> 2); |
| 1476 | l4_proto = ip6h->nexthdr; |
| 1477 | } else |
| 1478 | return MVNETA_TX_L4_CSUM_NOT; |
| 1479 | |
| 1480 | return mvneta_txq_desc_csum(skb_network_offset(skb), |
Vlad Yasevich | 817dbfa | 2014-08-25 10:34:54 -0400 | [diff] [blame] | 1481 | l3_proto, ip_hdr_len, l4_proto); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | return MVNETA_TX_L4_CSUM_NOT; |
| 1485 | } |
| 1486 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1487 | /* Drop packets received by the RXQ and free buffers */ |
| 1488 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, |
| 1489 | struct mvneta_rx_queue *rxq) |
| 1490 | { |
| 1491 | int rx_done, i; |
| 1492 | |
| 1493 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); |
| 1494 | for (i = 0; i < rxq->size; i++) { |
| 1495 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1496 | void *data = (void *)rx_desc->buf_cookie; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1497 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1498 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
Ezequiel Garcia | a328f3a | 2013-12-05 13:35:37 -0300 | [diff] [blame] | 1499 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
Justin Maggard | 8c94ddb | 2015-11-09 17:21:05 -0800 | [diff] [blame] | 1500 | mvneta_frag_free(pp, data); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1501 | } |
| 1502 | |
| 1503 | if (rx_done) |
| 1504 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
| 1505 | } |
| 1506 | |
| 1507 | /* Main rx processing */ |
| 1508 | static int mvneta_rx(struct mvneta_port *pp, int rx_todo, |
| 1509 | struct mvneta_rx_queue *rxq) |
| 1510 | { |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 1511 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1512 | struct net_device *dev = pp->dev; |
Simon Guinot | a84e328 | 2015-07-19 13:00:53 +0200 | [diff] [blame] | 1513 | int rx_done; |
willy tarreau | dc4277d | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1514 | u32 rcvd_pkts = 0; |
| 1515 | u32 rcvd_bytes = 0; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1516 | |
| 1517 | /* Get number of received packets */ |
| 1518 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); |
| 1519 | |
| 1520 | if (rx_todo > rx_done) |
| 1521 | rx_todo = rx_done; |
| 1522 | |
| 1523 | rx_done = 0; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1524 | |
| 1525 | /* Fairness NAPI loop */ |
| 1526 | while (rx_done < rx_todo) { |
| 1527 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); |
| 1528 | struct sk_buff *skb; |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1529 | unsigned char *data; |
Simon Guinot | daf158d | 2015-09-15 22:41:21 +0200 | [diff] [blame] | 1530 | dma_addr_t phys_addr; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1531 | u32 rx_status; |
| 1532 | int rx_bytes, err; |
| 1533 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1534 | rx_done++; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1535 | rx_status = rx_desc->status; |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 1536 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1537 | data = (unsigned char *)rx_desc->buf_cookie; |
Simon Guinot | daf158d | 2015-09-15 22:41:21 +0200 | [diff] [blame] | 1538 | phys_addr = rx_desc->buf_phys_addr; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1539 | |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 1540 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 1541 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
| 1542 | err_drop_frame: |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1543 | dev->stats.rx_errors++; |
| 1544 | mvneta_rx_error(pp, rx_desc); |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1545 | /* leave the descriptor untouched */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1546 | continue; |
| 1547 | } |
| 1548 | |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 1549 | if (rx_bytes <= rx_copybreak) { |
| 1550 | /* better copy a small frame and not unmap the DMA region */ |
| 1551 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); |
| 1552 | if (unlikely(!skb)) |
| 1553 | goto err_drop_frame; |
| 1554 | |
| 1555 | dma_sync_single_range_for_cpu(dev->dev.parent, |
| 1556 | rx_desc->buf_phys_addr, |
| 1557 | MVNETA_MH_SIZE + NET_SKB_PAD, |
| 1558 | rx_bytes, |
| 1559 | DMA_FROM_DEVICE); |
| 1560 | memcpy(skb_put(skb, rx_bytes), |
| 1561 | data + MVNETA_MH_SIZE + NET_SKB_PAD, |
| 1562 | rx_bytes); |
| 1563 | |
| 1564 | skb->protocol = eth_type_trans(skb, dev); |
| 1565 | mvneta_rx_csum(pp, rx_status, skb); |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 1566 | napi_gro_receive(&port->napi, skb); |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 1567 | |
| 1568 | rcvd_pkts++; |
| 1569 | rcvd_bytes += rx_bytes; |
| 1570 | |
| 1571 | /* leave the descriptor and buffer untouched */ |
| 1572 | continue; |
| 1573 | } |
| 1574 | |
Simon Guinot | a84e328 | 2015-07-19 13:00:53 +0200 | [diff] [blame] | 1575 | /* Refill processing */ |
| 1576 | err = mvneta_rx_refill(pp, rx_desc); |
| 1577 | if (err) { |
| 1578 | netdev_err(dev, "Linux processing - Can't refill\n"); |
| 1579 | rxq->missed++; |
| 1580 | goto err_drop_frame; |
| 1581 | } |
| 1582 | |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 1583 | skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 1584 | |
Marcin Wojtas | 26c17a17 | 2015-11-30 13:27:44 +0100 | [diff] [blame] | 1585 | /* After refill old buffer has to be unmapped regardless |
| 1586 | * the skb is successfully built or not. |
| 1587 | */ |
Simon Guinot | daf158d | 2015-09-15 22:41:21 +0200 | [diff] [blame] | 1588 | dma_unmap_single(dev->dev.parent, phys_addr, |
Ezequiel Garcia | a328f3a | 2013-12-05 13:35:37 -0300 | [diff] [blame] | 1589 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1590 | |
Marcin Wojtas | 26c17a17 | 2015-11-30 13:27:44 +0100 | [diff] [blame] | 1591 | if (!skb) |
| 1592 | goto err_drop_frame; |
| 1593 | |
willy tarreau | dc4277d | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1594 | rcvd_pkts++; |
| 1595 | rcvd_bytes += rx_bytes; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1596 | |
| 1597 | /* Linux processing */ |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 1598 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1599 | skb_put(skb, rx_bytes); |
| 1600 | |
| 1601 | skb->protocol = eth_type_trans(skb, dev); |
| 1602 | |
willy tarreau | 5428213 | 2014-01-16 08:20:14 +0100 | [diff] [blame] | 1603 | mvneta_rx_csum(pp, rx_status, skb); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1604 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 1605 | napi_gro_receive(&port->napi, skb); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1606 | } |
| 1607 | |
willy tarreau | dc4277d | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1608 | if (rcvd_pkts) { |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1609 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
| 1610 | |
| 1611 | u64_stats_update_begin(&stats->syncp); |
| 1612 | stats->rx_packets += rcvd_pkts; |
| 1613 | stats->rx_bytes += rcvd_bytes; |
| 1614 | u64_stats_update_end(&stats->syncp); |
willy tarreau | dc4277d | 2014-01-16 08:20:07 +0100 | [diff] [blame] | 1615 | } |
| 1616 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1617 | /* Update rxq management counters */ |
Simon Guinot | a84e328 | 2015-07-19 13:00:53 +0200 | [diff] [blame] | 1618 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1619 | |
| 1620 | return rx_done; |
| 1621 | } |
| 1622 | |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 1623 | static inline void |
| 1624 | mvneta_tso_put_hdr(struct sk_buff *skb, |
| 1625 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) |
| 1626 | { |
| 1627 | struct mvneta_tx_desc *tx_desc; |
| 1628 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
| 1629 | |
| 1630 | txq->tx_skb[txq->txq_put_index] = NULL; |
| 1631 | tx_desc = mvneta_txq_next_desc_get(txq); |
| 1632 | tx_desc->data_size = hdr_len; |
| 1633 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); |
| 1634 | tx_desc->command |= MVNETA_TXD_F_DESC; |
| 1635 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + |
| 1636 | txq->txq_put_index * TSO_HEADER_SIZE; |
| 1637 | mvneta_txq_inc_put(txq); |
| 1638 | } |
| 1639 | |
| 1640 | static inline int |
| 1641 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, |
| 1642 | struct sk_buff *skb, char *data, int size, |
| 1643 | bool last_tcp, bool is_last) |
| 1644 | { |
| 1645 | struct mvneta_tx_desc *tx_desc; |
| 1646 | |
| 1647 | tx_desc = mvneta_txq_next_desc_get(txq); |
| 1648 | tx_desc->data_size = size; |
| 1649 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, |
| 1650 | size, DMA_TO_DEVICE); |
| 1651 | if (unlikely(dma_mapping_error(dev->dev.parent, |
| 1652 | tx_desc->buf_phys_addr))) { |
| 1653 | mvneta_txq_desc_put(txq); |
| 1654 | return -ENOMEM; |
| 1655 | } |
| 1656 | |
| 1657 | tx_desc->command = 0; |
| 1658 | txq->tx_skb[txq->txq_put_index] = NULL; |
| 1659 | |
| 1660 | if (last_tcp) { |
| 1661 | /* last descriptor in the TCP packet */ |
| 1662 | tx_desc->command = MVNETA_TXD_L_DESC; |
| 1663 | |
| 1664 | /* last descriptor in SKB */ |
| 1665 | if (is_last) |
| 1666 | txq->tx_skb[txq->txq_put_index] = skb; |
| 1667 | } |
| 1668 | mvneta_txq_inc_put(txq); |
| 1669 | return 0; |
| 1670 | } |
| 1671 | |
| 1672 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, |
| 1673 | struct mvneta_tx_queue *txq) |
| 1674 | { |
| 1675 | int total_len, data_left; |
| 1676 | int desc_count = 0; |
| 1677 | struct mvneta_port *pp = netdev_priv(dev); |
| 1678 | struct tso_t tso; |
| 1679 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
| 1680 | int i; |
| 1681 | |
| 1682 | /* Count needed descriptors */ |
| 1683 | if ((txq->count + tso_count_descs(skb)) >= txq->size) |
| 1684 | return 0; |
| 1685 | |
| 1686 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { |
| 1687 | pr_info("*** Is this even possible???!?!?\n"); |
| 1688 | return 0; |
| 1689 | } |
| 1690 | |
| 1691 | /* Initialize the TSO handler, and prepare the first payload */ |
| 1692 | tso_start(skb, &tso); |
| 1693 | |
| 1694 | total_len = skb->len - hdr_len; |
| 1695 | while (total_len > 0) { |
| 1696 | char *hdr; |
| 1697 | |
| 1698 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); |
| 1699 | total_len -= data_left; |
| 1700 | desc_count++; |
| 1701 | |
| 1702 | /* prepare packet headers: MAC + IP + TCP */ |
| 1703 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; |
| 1704 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); |
| 1705 | |
| 1706 | mvneta_tso_put_hdr(skb, pp, txq); |
| 1707 | |
| 1708 | while (data_left > 0) { |
| 1709 | int size; |
| 1710 | desc_count++; |
| 1711 | |
| 1712 | size = min_t(int, tso.size, data_left); |
| 1713 | |
| 1714 | if (mvneta_tso_put_data(dev, txq, skb, |
| 1715 | tso.data, size, |
| 1716 | size == data_left, |
| 1717 | total_len == 0)) |
| 1718 | goto err_release; |
| 1719 | data_left -= size; |
| 1720 | |
| 1721 | tso_build_data(skb, &tso, size); |
| 1722 | } |
| 1723 | } |
| 1724 | |
| 1725 | return desc_count; |
| 1726 | |
| 1727 | err_release: |
| 1728 | /* Release all used data descriptors; header descriptors must not |
| 1729 | * be DMA-unmapped. |
| 1730 | */ |
| 1731 | for (i = desc_count - 1; i >= 0; i--) { |
| 1732 | struct mvneta_tx_desc *tx_desc = txq->descs + i; |
Ezequiel Garcia | 2e3173a | 2014-05-30 13:40:07 -0300 | [diff] [blame] | 1733 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 1734 | dma_unmap_single(pp->dev->dev.parent, |
| 1735 | tx_desc->buf_phys_addr, |
| 1736 | tx_desc->data_size, |
| 1737 | DMA_TO_DEVICE); |
| 1738 | mvneta_txq_desc_put(txq); |
| 1739 | } |
| 1740 | return 0; |
| 1741 | } |
| 1742 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1743 | /* Handle tx fragmentation processing */ |
| 1744 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, |
| 1745 | struct mvneta_tx_queue *txq) |
| 1746 | { |
| 1747 | struct mvneta_tx_desc *tx_desc; |
Ezequiel Garcia | 3d4ea02 | 2014-05-22 20:06:57 -0300 | [diff] [blame] | 1748 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1749 | |
Ezequiel Garcia | 3d4ea02 | 2014-05-22 20:06:57 -0300 | [diff] [blame] | 1750 | for (i = 0; i < nr_frags; i++) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1751 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 1752 | void *addr = page_address(frag->page.p) + frag->page_offset; |
| 1753 | |
| 1754 | tx_desc = mvneta_txq_next_desc_get(txq); |
| 1755 | tx_desc->data_size = frag->size; |
| 1756 | |
| 1757 | tx_desc->buf_phys_addr = |
| 1758 | dma_map_single(pp->dev->dev.parent, addr, |
| 1759 | tx_desc->data_size, DMA_TO_DEVICE); |
| 1760 | |
| 1761 | if (dma_mapping_error(pp->dev->dev.parent, |
| 1762 | tx_desc->buf_phys_addr)) { |
| 1763 | mvneta_txq_desc_put(txq); |
| 1764 | goto error; |
| 1765 | } |
| 1766 | |
Ezequiel Garcia | 3d4ea02 | 2014-05-22 20:06:57 -0300 | [diff] [blame] | 1767 | if (i == nr_frags - 1) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1768 | /* Last descriptor */ |
| 1769 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1770 | txq->tx_skb[txq->txq_put_index] = skb; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1771 | } else { |
| 1772 | /* Descriptor in the middle: Not First, Not Last */ |
| 1773 | tx_desc->command = 0; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1774 | txq->tx_skb[txq->txq_put_index] = NULL; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1775 | } |
Ezequiel Garcia | 3d4ea02 | 2014-05-22 20:06:57 -0300 | [diff] [blame] | 1776 | mvneta_txq_inc_put(txq); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1777 | } |
| 1778 | |
| 1779 | return 0; |
| 1780 | |
| 1781 | error: |
| 1782 | /* Release all descriptors that were used to map fragments of |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1783 | * this packet, as well as the corresponding DMA mappings |
| 1784 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1785 | for (i = i - 1; i >= 0; i--) { |
| 1786 | tx_desc = txq->descs + i; |
| 1787 | dma_unmap_single(pp->dev->dev.parent, |
| 1788 | tx_desc->buf_phys_addr, |
| 1789 | tx_desc->data_size, |
| 1790 | DMA_TO_DEVICE); |
| 1791 | mvneta_txq_desc_put(txq); |
| 1792 | } |
| 1793 | |
| 1794 | return -ENOMEM; |
| 1795 | } |
| 1796 | |
| 1797 | /* Main tx processing */ |
| 1798 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) |
| 1799 | { |
| 1800 | struct mvneta_port *pp = netdev_priv(dev); |
Willy Tarreau | ee40a11 | 2013-04-11 23:00:37 +0200 | [diff] [blame] | 1801 | u16 txq_id = skb_get_queue_mapping(skb); |
| 1802 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1803 | struct mvneta_tx_desc *tx_desc; |
Eric Dumazet | 5f478b4 | 2014-12-02 04:30:59 -0800 | [diff] [blame] | 1804 | int len = skb->len; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1805 | int frags = 0; |
| 1806 | u32 tx_cmd; |
| 1807 | |
| 1808 | if (!netif_running(dev)) |
| 1809 | goto out; |
| 1810 | |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 1811 | if (skb_is_gso(skb)) { |
| 1812 | frags = mvneta_tx_tso(skb, dev, txq); |
| 1813 | goto out; |
| 1814 | } |
| 1815 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1816 | frags = skb_shinfo(skb)->nr_frags + 1; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1817 | |
| 1818 | /* Get a descriptor for the first part of the packet */ |
| 1819 | tx_desc = mvneta_txq_next_desc_get(txq); |
| 1820 | |
| 1821 | tx_cmd = mvneta_skb_tx_csum(pp, skb); |
| 1822 | |
| 1823 | tx_desc->data_size = skb_headlen(skb); |
| 1824 | |
| 1825 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, |
| 1826 | tx_desc->data_size, |
| 1827 | DMA_TO_DEVICE); |
| 1828 | if (unlikely(dma_mapping_error(dev->dev.parent, |
| 1829 | tx_desc->buf_phys_addr))) { |
| 1830 | mvneta_txq_desc_put(txq); |
| 1831 | frags = 0; |
| 1832 | goto out; |
| 1833 | } |
| 1834 | |
| 1835 | if (frags == 1) { |
| 1836 | /* First and Last descriptor */ |
| 1837 | tx_cmd |= MVNETA_TXD_FLZ_DESC; |
| 1838 | tx_desc->command = tx_cmd; |
| 1839 | txq->tx_skb[txq->txq_put_index] = skb; |
| 1840 | mvneta_txq_inc_put(txq); |
| 1841 | } else { |
| 1842 | /* First but not Last */ |
| 1843 | tx_cmd |= MVNETA_TXD_F_DESC; |
| 1844 | txq->tx_skb[txq->txq_put_index] = NULL; |
| 1845 | mvneta_txq_inc_put(txq); |
| 1846 | tx_desc->command = tx_cmd; |
| 1847 | /* Continue with other skb fragments */ |
| 1848 | if (mvneta_tx_frag_process(pp, skb, txq)) { |
| 1849 | dma_unmap_single(dev->dev.parent, |
| 1850 | tx_desc->buf_phys_addr, |
| 1851 | tx_desc->data_size, |
| 1852 | DMA_TO_DEVICE); |
| 1853 | mvneta_txq_desc_put(txq); |
| 1854 | frags = 0; |
| 1855 | goto out; |
| 1856 | } |
| 1857 | } |
| 1858 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1859 | out: |
| 1860 | if (frags > 0) { |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1861 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
Ezequiel Garcia | e19d2dd | 2014-05-19 13:59:54 -0300 | [diff] [blame] | 1862 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
| 1863 | |
| 1864 | txq->count += frags; |
| 1865 | mvneta_txq_pend_desc_add(pp, txq, frags); |
| 1866 | |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 1867 | if (txq->count >= txq->tx_stop_threshold) |
Ezequiel Garcia | e19d2dd | 2014-05-19 13:59:54 -0300 | [diff] [blame] | 1868 | netif_tx_stop_queue(nq); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1869 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1870 | u64_stats_update_begin(&stats->syncp); |
| 1871 | stats->tx_packets++; |
Eric Dumazet | 5f478b4 | 2014-12-02 04:30:59 -0800 | [diff] [blame] | 1872 | stats->tx_bytes += len; |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 1873 | u64_stats_update_end(&stats->syncp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1874 | } else { |
| 1875 | dev->stats.tx_dropped++; |
| 1876 | dev_kfree_skb_any(skb); |
| 1877 | } |
| 1878 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1879 | return NETDEV_TX_OK; |
| 1880 | } |
| 1881 | |
| 1882 | |
| 1883 | /* Free tx resources, when resetting a port */ |
| 1884 | static void mvneta_txq_done_force(struct mvneta_port *pp, |
| 1885 | struct mvneta_tx_queue *txq) |
| 1886 | |
| 1887 | { |
| 1888 | int tx_done = txq->count; |
| 1889 | |
| 1890 | mvneta_txq_bufs_free(pp, txq, tx_done); |
| 1891 | |
| 1892 | /* reset txq */ |
| 1893 | txq->count = 0; |
| 1894 | txq->txq_put_index = 0; |
| 1895 | txq->txq_get_index = 0; |
| 1896 | } |
| 1897 | |
willy tarreau | 6c49897 | 2014-01-16 08:20:12 +0100 | [diff] [blame] | 1898 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
| 1899 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. |
| 1900 | */ |
Arnaud Ebalard | 0713a86 | 2014-01-16 08:20:18 +0100 | [diff] [blame] | 1901 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1902 | { |
| 1903 | struct mvneta_tx_queue *txq; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1904 | struct netdev_queue *nq; |
| 1905 | |
willy tarreau | 6c49897 | 2014-01-16 08:20:12 +0100 | [diff] [blame] | 1906 | while (cause_tx_done) { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1907 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1908 | |
| 1909 | nq = netdev_get_tx_queue(pp->dev, txq->id); |
| 1910 | __netif_tx_lock(nq, smp_processor_id()); |
| 1911 | |
Arnaud Ebalard | 0713a86 | 2014-01-16 08:20:18 +0100 | [diff] [blame] | 1912 | if (txq->count) |
| 1913 | mvneta_txq_done(pp, txq); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1914 | |
| 1915 | __netif_tx_unlock(nq); |
| 1916 | cause_tx_done &= ~((1 << txq->id)); |
| 1917 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1918 | } |
| 1919 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 1920 | /* Compute crc8 of the specified address, using a unique algorithm , |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 1921 | * according to hw spec, different than generic crc8 algorithm |
| 1922 | */ |
| 1923 | static int mvneta_addr_crc(unsigned char *addr) |
| 1924 | { |
| 1925 | int crc = 0; |
| 1926 | int i; |
| 1927 | |
| 1928 | for (i = 0; i < ETH_ALEN; i++) { |
| 1929 | int j; |
| 1930 | |
| 1931 | crc = (crc ^ addr[i]) << 8; |
| 1932 | for (j = 7; j >= 0; j--) { |
| 1933 | if (crc & (0x100 << j)) |
| 1934 | crc ^= 0x107 << j; |
| 1935 | } |
| 1936 | } |
| 1937 | |
| 1938 | return crc; |
| 1939 | } |
| 1940 | |
| 1941 | /* This method controls the net device special MAC multicast support. |
| 1942 | * The Special Multicast Table for MAC addresses supports MAC of the form |
| 1943 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). |
| 1944 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast |
| 1945 | * Table entries in the DA-Filter table. This method set the Special |
| 1946 | * Multicast Table appropriate entry. |
| 1947 | */ |
| 1948 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, |
| 1949 | unsigned char last_byte, |
| 1950 | int queue) |
| 1951 | { |
| 1952 | unsigned int smc_table_reg; |
| 1953 | unsigned int tbl_offset; |
| 1954 | unsigned int reg_offset; |
| 1955 | |
| 1956 | /* Register offset from SMC table base */ |
| 1957 | tbl_offset = (last_byte / 4); |
| 1958 | /* Entry offset within the above reg */ |
| 1959 | reg_offset = last_byte % 4; |
| 1960 | |
| 1961 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST |
| 1962 | + tbl_offset * 4)); |
| 1963 | |
| 1964 | if (queue == -1) |
| 1965 | smc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1966 | else { |
| 1967 | smc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1968 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); |
| 1969 | } |
| 1970 | |
| 1971 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, |
| 1972 | smc_table_reg); |
| 1973 | } |
| 1974 | |
| 1975 | /* This method controls the network device Other MAC multicast support. |
| 1976 | * The Other Multicast Table is used for multicast of another type. |
| 1977 | * A CRC-8 is used as an index to the Other Multicast Table entries |
| 1978 | * in the DA-Filter table. |
| 1979 | * The method gets the CRC-8 value from the calling routine and |
| 1980 | * sets the Other Multicast Table appropriate entry according to the |
| 1981 | * specified CRC-8 . |
| 1982 | */ |
| 1983 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, |
| 1984 | unsigned char crc8, |
| 1985 | int queue) |
| 1986 | { |
| 1987 | unsigned int omc_table_reg; |
| 1988 | unsigned int tbl_offset; |
| 1989 | unsigned int reg_offset; |
| 1990 | |
| 1991 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ |
| 1992 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ |
| 1993 | |
| 1994 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); |
| 1995 | |
| 1996 | if (queue == -1) { |
| 1997 | /* Clear accepts frame bit at specified Other DA table entry */ |
| 1998 | omc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 1999 | } else { |
| 2000 | omc_table_reg &= ~(0xff << (8 * reg_offset)); |
| 2001 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); |
| 2002 | } |
| 2003 | |
| 2004 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); |
| 2005 | } |
| 2006 | |
| 2007 | /* The network device supports multicast using two tables: |
| 2008 | * 1) Special Multicast Table for MAC addresses of the form |
| 2009 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). |
| 2010 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast |
| 2011 | * Table entries in the DA-Filter table. |
| 2012 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value |
| 2013 | * is used as an index to the Other Multicast Table entries in the |
| 2014 | * DA-Filter table. |
| 2015 | */ |
| 2016 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, |
| 2017 | int queue) |
| 2018 | { |
| 2019 | unsigned char crc_result = 0; |
| 2020 | |
| 2021 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { |
| 2022 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); |
| 2023 | return 0; |
| 2024 | } |
| 2025 | |
| 2026 | crc_result = mvneta_addr_crc(p_addr); |
| 2027 | if (queue == -1) { |
| 2028 | if (pp->mcast_count[crc_result] == 0) { |
| 2029 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", |
| 2030 | crc_result); |
| 2031 | return -EINVAL; |
| 2032 | } |
| 2033 | |
| 2034 | pp->mcast_count[crc_result]--; |
| 2035 | if (pp->mcast_count[crc_result] != 0) { |
| 2036 | netdev_info(pp->dev, |
| 2037 | "After delete there are %d valid Mcast for crc8=0x%02x\n", |
| 2038 | pp->mcast_count[crc_result], crc_result); |
| 2039 | return -EINVAL; |
| 2040 | } |
| 2041 | } else |
| 2042 | pp->mcast_count[crc_result]++; |
| 2043 | |
| 2044 | mvneta_set_other_mcast_addr(pp, crc_result, queue); |
| 2045 | |
| 2046 | return 0; |
| 2047 | } |
| 2048 | |
| 2049 | /* Configure Fitering mode of Ethernet port */ |
| 2050 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, |
| 2051 | int is_promisc) |
| 2052 | { |
| 2053 | u32 port_cfg_reg, val; |
| 2054 | |
| 2055 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); |
| 2056 | |
| 2057 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); |
| 2058 | |
| 2059 | /* Set / Clear UPM bit in port configuration register */ |
| 2060 | if (is_promisc) { |
| 2061 | /* Accept all Unicast addresses */ |
| 2062 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; |
| 2063 | val |= MVNETA_FORCE_UNI; |
| 2064 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); |
| 2065 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); |
| 2066 | } else { |
| 2067 | /* Reject all Unicast addresses */ |
| 2068 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; |
| 2069 | val &= ~MVNETA_FORCE_UNI; |
| 2070 | } |
| 2071 | |
| 2072 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); |
| 2073 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); |
| 2074 | } |
| 2075 | |
| 2076 | /* register unicast and multicast addresses */ |
| 2077 | static void mvneta_set_rx_mode(struct net_device *dev) |
| 2078 | { |
| 2079 | struct mvneta_port *pp = netdev_priv(dev); |
| 2080 | struct netdev_hw_addr *ha; |
| 2081 | |
| 2082 | if (dev->flags & IFF_PROMISC) { |
| 2083 | /* Accept all: Multicast + Unicast */ |
| 2084 | mvneta_rx_unicast_promisc_set(pp, 1); |
| 2085 | mvneta_set_ucast_table(pp, rxq_def); |
| 2086 | mvneta_set_special_mcast_table(pp, rxq_def); |
| 2087 | mvneta_set_other_mcast_table(pp, rxq_def); |
| 2088 | } else { |
| 2089 | /* Accept single Unicast */ |
| 2090 | mvneta_rx_unicast_promisc_set(pp, 0); |
| 2091 | mvneta_set_ucast_table(pp, -1); |
| 2092 | mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); |
| 2093 | |
| 2094 | if (dev->flags & IFF_ALLMULTI) { |
| 2095 | /* Accept all multicast */ |
| 2096 | mvneta_set_special_mcast_table(pp, rxq_def); |
| 2097 | mvneta_set_other_mcast_table(pp, rxq_def); |
| 2098 | } else { |
| 2099 | /* Accept only initialized multicast */ |
| 2100 | mvneta_set_special_mcast_table(pp, -1); |
| 2101 | mvneta_set_other_mcast_table(pp, -1); |
| 2102 | |
| 2103 | if (!netdev_mc_empty(dev)) { |
| 2104 | netdev_for_each_mc_addr(ha, dev) { |
| 2105 | mvneta_mcast_addr_set(pp, ha->addr, |
| 2106 | rxq_def); |
| 2107 | } |
| 2108 | } |
| 2109 | } |
| 2110 | } |
| 2111 | } |
| 2112 | |
| 2113 | /* Interrupt handling - the callback for request_irq() */ |
| 2114 | static irqreturn_t mvneta_isr(int irq, void *dev_id) |
| 2115 | { |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2116 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2117 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2118 | disable_percpu_irq(port->pp->dev->irq); |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2119 | napi_schedule(&port->napi); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2120 | |
| 2121 | return IRQ_HANDLED; |
| 2122 | } |
| 2123 | |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 2124 | static int mvneta_fixed_link_update(struct mvneta_port *pp, |
| 2125 | struct phy_device *phy) |
| 2126 | { |
| 2127 | struct fixed_phy_status status; |
| 2128 | struct fixed_phy_status changed = {}; |
| 2129 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); |
| 2130 | |
| 2131 | status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); |
| 2132 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) |
| 2133 | status.speed = SPEED_1000; |
| 2134 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) |
| 2135 | status.speed = SPEED_100; |
| 2136 | else |
| 2137 | status.speed = SPEED_10; |
| 2138 | status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); |
| 2139 | changed.link = 1; |
| 2140 | changed.speed = 1; |
| 2141 | changed.duplex = 1; |
| 2142 | fixed_phy_update_state(phy, &status, &changed); |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2146 | /* NAPI handler |
| 2147 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted |
| 2148 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). |
| 2149 | * Bits 8 -15 of the cause Rx Tx register indicate that are received |
| 2150 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). |
| 2151 | * Each CPU has its own causeRxTx register |
| 2152 | */ |
| 2153 | static int mvneta_poll(struct napi_struct *napi, int budget) |
| 2154 | { |
| 2155 | int rx_done = 0; |
| 2156 | u32 cause_rx_tx; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2157 | struct mvneta_port *pp = netdev_priv(napi->dev); |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2158 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2159 | |
| 2160 | if (!netif_running(pp->dev)) { |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2161 | napi_complete(&port->napi); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2162 | return rx_done; |
| 2163 | } |
| 2164 | |
| 2165 | /* Read cause register */ |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 2166 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
| 2167 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { |
| 2168 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); |
| 2169 | |
| 2170 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); |
| 2171 | if (pp->use_inband_status && (cause_misc & |
| 2172 | (MVNETA_CAUSE_PHY_STATUS_CHANGE | |
| 2173 | MVNETA_CAUSE_LINK_CHANGE | |
| 2174 | MVNETA_CAUSE_PSC_SYNC_CHANGE))) { |
| 2175 | mvneta_fixed_link_update(pp, pp->phy_dev); |
| 2176 | } |
| 2177 | } |
willy tarreau | 71f6d1b | 2014-01-16 08:20:11 +0100 | [diff] [blame] | 2178 | |
| 2179 | /* Release Tx descriptors */ |
| 2180 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { |
Arnaud Ebalard | 0713a86 | 2014-01-16 08:20:18 +0100 | [diff] [blame] | 2181 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
willy tarreau | 71f6d1b | 2014-01-16 08:20:11 +0100 | [diff] [blame] | 2182 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
| 2183 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2184 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2185 | /* For the case where the last mvneta_poll did not process all |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2186 | * RX packets |
| 2187 | */ |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2188 | cause_rx_tx |= port->cause_rx_tx; |
Maxime Ripard | d893665 | 2015-09-25 18:09:37 +0200 | [diff] [blame] | 2189 | rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); |
| 2190 | budget -= rx_done; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2191 | |
| 2192 | if (budget > 0) { |
| 2193 | cause_rx_tx = 0; |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2194 | napi_complete(&port->napi); |
| 2195 | enable_percpu_irq(pp->dev->irq, 0); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2196 | } |
| 2197 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2198 | port->cause_rx_tx = cause_rx_tx; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2199 | return rx_done; |
| 2200 | } |
| 2201 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2202 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
| 2203 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, |
| 2204 | int num) |
| 2205 | { |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2206 | int i; |
| 2207 | |
| 2208 | for (i = 0; i < num; i++) { |
willy tarreau | a1a65ab | 2014-01-16 08:20:13 +0100 | [diff] [blame] | 2209 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
| 2210 | if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { |
| 2211 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2212 | __func__, rxq->id, i, num); |
| 2213 | break; |
| 2214 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2215 | } |
| 2216 | |
| 2217 | /* Add this number of RX descriptors as non occupied (ready to |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2218 | * get packets) |
| 2219 | */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2220 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
| 2221 | |
| 2222 | return i; |
| 2223 | } |
| 2224 | |
| 2225 | /* Free all packets pending transmit from all TXQs and reset TX port */ |
| 2226 | static void mvneta_tx_reset(struct mvneta_port *pp) |
| 2227 | { |
| 2228 | int queue; |
| 2229 | |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 2230 | /* free the skb's in the tx ring */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2231 | for (queue = 0; queue < txq_number; queue++) |
| 2232 | mvneta_txq_done_force(pp, &pp->txqs[queue]); |
| 2233 | |
| 2234 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); |
| 2235 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); |
| 2236 | } |
| 2237 | |
| 2238 | static void mvneta_rx_reset(struct mvneta_port *pp) |
| 2239 | { |
| 2240 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); |
| 2241 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); |
| 2242 | } |
| 2243 | |
| 2244 | /* Rx/Tx queue initialization/cleanup methods */ |
| 2245 | |
| 2246 | /* Create a specified RX queue */ |
| 2247 | static int mvneta_rxq_init(struct mvneta_port *pp, |
| 2248 | struct mvneta_rx_queue *rxq) |
| 2249 | |
| 2250 | { |
| 2251 | rxq->size = pp->rx_ring_size; |
| 2252 | |
| 2253 | /* Allocate memory for RX descriptors */ |
| 2254 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, |
| 2255 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2256 | &rxq->descs_phys, GFP_KERNEL); |
Joe Perches | d0320f7 | 2013-03-14 13:07:21 +0000 | [diff] [blame] | 2257 | if (rxq->descs == NULL) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2258 | return -ENOMEM; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2259 | |
| 2260 | BUG_ON(rxq->descs != |
| 2261 | PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); |
| 2262 | |
| 2263 | rxq->last_desc = rxq->size - 1; |
| 2264 | |
| 2265 | /* Set Rx descriptors queue starting address */ |
| 2266 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); |
| 2267 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); |
| 2268 | |
| 2269 | /* Set Offset */ |
| 2270 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); |
| 2271 | |
| 2272 | /* Set coalescing pkts and time */ |
| 2273 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); |
| 2274 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); |
| 2275 | |
| 2276 | /* Fill RXQ with buffers from RX pool */ |
| 2277 | mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); |
| 2278 | mvneta_rxq_bm_disable(pp, rxq); |
| 2279 | mvneta_rxq_fill(pp, rxq, rxq->size); |
| 2280 | |
| 2281 | return 0; |
| 2282 | } |
| 2283 | |
| 2284 | /* Cleanup Rx queue */ |
| 2285 | static void mvneta_rxq_deinit(struct mvneta_port *pp, |
| 2286 | struct mvneta_rx_queue *rxq) |
| 2287 | { |
| 2288 | mvneta_rxq_drop_pkts(pp, rxq); |
| 2289 | |
| 2290 | if (rxq->descs) |
| 2291 | dma_free_coherent(pp->dev->dev.parent, |
| 2292 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2293 | rxq->descs, |
| 2294 | rxq->descs_phys); |
| 2295 | |
| 2296 | rxq->descs = NULL; |
| 2297 | rxq->last_desc = 0; |
| 2298 | rxq->next_desc_to_proc = 0; |
| 2299 | rxq->descs_phys = 0; |
| 2300 | } |
| 2301 | |
| 2302 | /* Create and initialize a tx queue */ |
| 2303 | static int mvneta_txq_init(struct mvneta_port *pp, |
| 2304 | struct mvneta_tx_queue *txq) |
| 2305 | { |
| 2306 | txq->size = pp->tx_ring_size; |
| 2307 | |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 2308 | /* A queue must always have room for at least one skb. |
| 2309 | * Therefore, stop the queue when the free entries reaches |
| 2310 | * the maximum number of descriptors per skb. |
| 2311 | */ |
| 2312 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; |
| 2313 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; |
| 2314 | |
| 2315 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2316 | /* Allocate memory for TX descriptors */ |
| 2317 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, |
| 2318 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2319 | &txq->descs_phys, GFP_KERNEL); |
Joe Perches | d0320f7 | 2013-03-14 13:07:21 +0000 | [diff] [blame] | 2320 | if (txq->descs == NULL) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2321 | return -ENOMEM; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2322 | |
| 2323 | /* Make sure descriptor address is cache line size aligned */ |
| 2324 | BUG_ON(txq->descs != |
| 2325 | PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); |
| 2326 | |
| 2327 | txq->last_desc = txq->size - 1; |
| 2328 | |
| 2329 | /* Set maximum bandwidth for enabled TXQs */ |
| 2330 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); |
| 2331 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); |
| 2332 | |
| 2333 | /* Set Tx descriptors queue starting address */ |
| 2334 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); |
| 2335 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); |
| 2336 | |
| 2337 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); |
| 2338 | if (txq->tx_skb == NULL) { |
| 2339 | dma_free_coherent(pp->dev->dev.parent, |
| 2340 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2341 | txq->descs, txq->descs_phys); |
| 2342 | return -ENOMEM; |
| 2343 | } |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 2344 | |
| 2345 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ |
| 2346 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, |
| 2347 | txq->size * TSO_HEADER_SIZE, |
| 2348 | &txq->tso_hdrs_phys, GFP_KERNEL); |
| 2349 | if (txq->tso_hdrs == NULL) { |
| 2350 | kfree(txq->tx_skb); |
| 2351 | dma_free_coherent(pp->dev->dev.parent, |
| 2352 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2353 | txq->descs, txq->descs_phys); |
| 2354 | return -ENOMEM; |
| 2355 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2356 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
| 2357 | |
| 2358 | return 0; |
| 2359 | } |
| 2360 | |
| 2361 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ |
| 2362 | static void mvneta_txq_deinit(struct mvneta_port *pp, |
| 2363 | struct mvneta_tx_queue *txq) |
| 2364 | { |
| 2365 | kfree(txq->tx_skb); |
| 2366 | |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 2367 | if (txq->tso_hdrs) |
| 2368 | dma_free_coherent(pp->dev->dev.parent, |
| 2369 | txq->size * TSO_HEADER_SIZE, |
| 2370 | txq->tso_hdrs, txq->tso_hdrs_phys); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2371 | if (txq->descs) |
| 2372 | dma_free_coherent(pp->dev->dev.parent, |
| 2373 | txq->size * MVNETA_DESC_ALIGNED_SIZE, |
| 2374 | txq->descs, txq->descs_phys); |
| 2375 | |
| 2376 | txq->descs = NULL; |
| 2377 | txq->last_desc = 0; |
| 2378 | txq->next_desc_to_proc = 0; |
| 2379 | txq->descs_phys = 0; |
| 2380 | |
| 2381 | /* Set minimum bandwidth for disabled TXQs */ |
| 2382 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); |
| 2383 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); |
| 2384 | |
| 2385 | /* Set Tx descriptors queue starting address and size */ |
| 2386 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); |
| 2387 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); |
| 2388 | } |
| 2389 | |
| 2390 | /* Cleanup all Tx queues */ |
| 2391 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) |
| 2392 | { |
| 2393 | int queue; |
| 2394 | |
| 2395 | for (queue = 0; queue < txq_number; queue++) |
| 2396 | mvneta_txq_deinit(pp, &pp->txqs[queue]); |
| 2397 | } |
| 2398 | |
| 2399 | /* Cleanup all Rx queues */ |
| 2400 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) |
| 2401 | { |
Maxime Ripard | d893665 | 2015-09-25 18:09:37 +0200 | [diff] [blame] | 2402 | mvneta_rxq_deinit(pp, &pp->rxqs[rxq_def]); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2403 | } |
| 2404 | |
| 2405 | |
| 2406 | /* Init all Rx queues */ |
| 2407 | static int mvneta_setup_rxqs(struct mvneta_port *pp) |
| 2408 | { |
Maxime Ripard | d893665 | 2015-09-25 18:09:37 +0200 | [diff] [blame] | 2409 | int err = mvneta_rxq_init(pp, &pp->rxqs[rxq_def]); |
| 2410 | if (err) { |
| 2411 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", |
| 2412 | __func__, rxq_def); |
| 2413 | mvneta_cleanup_rxqs(pp); |
| 2414 | return err; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2415 | } |
| 2416 | |
| 2417 | return 0; |
| 2418 | } |
| 2419 | |
| 2420 | /* Init all tx queues */ |
| 2421 | static int mvneta_setup_txqs(struct mvneta_port *pp) |
| 2422 | { |
| 2423 | int queue; |
| 2424 | |
| 2425 | for (queue = 0; queue < txq_number; queue++) { |
| 2426 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); |
| 2427 | if (err) { |
| 2428 | netdev_err(pp->dev, "%s: can't create txq=%d\n", |
| 2429 | __func__, queue); |
| 2430 | mvneta_cleanup_txqs(pp); |
| 2431 | return err; |
| 2432 | } |
| 2433 | } |
| 2434 | |
| 2435 | return 0; |
| 2436 | } |
| 2437 | |
| 2438 | static void mvneta_start_dev(struct mvneta_port *pp) |
| 2439 | { |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2440 | unsigned int cpu; |
| 2441 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2442 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
| 2443 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); |
| 2444 | |
| 2445 | /* start the Rx/Tx activity */ |
| 2446 | mvneta_port_enable(pp); |
| 2447 | |
| 2448 | /* Enable polling on the port */ |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2449 | for_each_present_cpu(cpu) { |
| 2450 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
| 2451 | |
| 2452 | napi_enable(&port->napi); |
| 2453 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2454 | |
| 2455 | /* Unmask interrupts */ |
| 2456 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 2457 | MVNETA_RX_INTR_MASK(rxq_number) | |
| 2458 | MVNETA_TX_INTR_MASK(txq_number) | |
| 2459 | MVNETA_MISCINTR_INTR_MASK); |
| 2460 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
| 2461 | MVNETA_CAUSE_PHY_STATUS_CHANGE | |
| 2462 | MVNETA_CAUSE_LINK_CHANGE | |
| 2463 | MVNETA_CAUSE_PSC_SYNC_CHANGE); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2464 | |
| 2465 | phy_start(pp->phy_dev); |
| 2466 | netif_tx_start_all_queues(pp->dev); |
| 2467 | } |
| 2468 | |
| 2469 | static void mvneta_stop_dev(struct mvneta_port *pp) |
| 2470 | { |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2471 | unsigned int cpu; |
| 2472 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2473 | phy_stop(pp->phy_dev); |
| 2474 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2475 | for_each_present_cpu(cpu) { |
| 2476 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
| 2477 | |
| 2478 | napi_disable(&port->napi); |
| 2479 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2480 | |
| 2481 | netif_carrier_off(pp->dev); |
| 2482 | |
| 2483 | mvneta_port_down(pp); |
| 2484 | netif_tx_stop_all_queues(pp->dev); |
| 2485 | |
| 2486 | /* Stop the port activity */ |
| 2487 | mvneta_port_disable(pp); |
| 2488 | |
| 2489 | /* Clear all ethernet port interrupts */ |
| 2490 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); |
| 2491 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); |
| 2492 | |
| 2493 | /* Mask all ethernet port interrupts */ |
| 2494 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 2495 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); |
| 2496 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); |
| 2497 | |
| 2498 | mvneta_tx_reset(pp); |
| 2499 | mvneta_rx_reset(pp); |
| 2500 | } |
| 2501 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2502 | /* Return positive if MTU is valid */ |
| 2503 | static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) |
| 2504 | { |
| 2505 | if (mtu < 68) { |
| 2506 | netdev_err(dev, "cannot change mtu to less than 68\n"); |
| 2507 | return -EINVAL; |
| 2508 | } |
| 2509 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2510 | /* 9676 == 9700 - 20 and rounding to 8 */ |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2511 | if (mtu > 9676) { |
| 2512 | netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); |
| 2513 | mtu = 9676; |
| 2514 | } |
| 2515 | |
| 2516 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
| 2517 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", |
| 2518 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); |
| 2519 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); |
| 2520 | } |
| 2521 | |
| 2522 | return mtu; |
| 2523 | } |
| 2524 | |
| 2525 | /* Change the device mtu */ |
| 2526 | static int mvneta_change_mtu(struct net_device *dev, int mtu) |
| 2527 | { |
| 2528 | struct mvneta_port *pp = netdev_priv(dev); |
| 2529 | int ret; |
| 2530 | |
| 2531 | mtu = mvneta_check_mtu_valid(dev, mtu); |
| 2532 | if (mtu < 0) |
| 2533 | return -EINVAL; |
| 2534 | |
| 2535 | dev->mtu = mtu; |
| 2536 | |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 2537 | if (!netif_running(dev)) { |
| 2538 | netdev_update_features(dev); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2539 | return 0; |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 2540 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2541 | |
Thomas Petazzoni | 6a20c17 | 2012-11-19 11:41:25 +0100 | [diff] [blame] | 2542 | /* The interface is running, so we have to force a |
Ezequiel Garcia | a92dbd9 | 2014-05-22 20:06:58 -0300 | [diff] [blame] | 2543 | * reallocation of the queues |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2544 | */ |
| 2545 | mvneta_stop_dev(pp); |
| 2546 | |
| 2547 | mvneta_cleanup_txqs(pp); |
| 2548 | mvneta_cleanup_rxqs(pp); |
| 2549 | |
Ezequiel Garcia | a92dbd9 | 2014-05-22 20:06:58 -0300 | [diff] [blame] | 2550 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 2551 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
| 2552 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2553 | |
| 2554 | ret = mvneta_setup_rxqs(pp); |
| 2555 | if (ret) { |
Ezequiel Garcia | a92dbd9 | 2014-05-22 20:06:58 -0300 | [diff] [blame] | 2556 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2557 | return ret; |
| 2558 | } |
| 2559 | |
Ezequiel Garcia | a92dbd9 | 2014-05-22 20:06:58 -0300 | [diff] [blame] | 2560 | ret = mvneta_setup_txqs(pp); |
| 2561 | if (ret) { |
| 2562 | netdev_err(dev, "unable to setup txqs after MTU change\n"); |
| 2563 | return ret; |
| 2564 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2565 | |
| 2566 | mvneta_start_dev(pp); |
| 2567 | mvneta_port_up(pp); |
| 2568 | |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 2569 | netdev_update_features(dev); |
| 2570 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2571 | return 0; |
| 2572 | } |
| 2573 | |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 2574 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
| 2575 | netdev_features_t features) |
| 2576 | { |
| 2577 | struct mvneta_port *pp = netdev_priv(dev); |
| 2578 | |
| 2579 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { |
| 2580 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); |
| 2581 | netdev_info(dev, |
| 2582 | "Disable IP checksum for MTU greater than %dB\n", |
| 2583 | pp->tx_csum_limit); |
| 2584 | } |
| 2585 | |
| 2586 | return features; |
| 2587 | } |
| 2588 | |
Thomas Petazzoni | 8cc3e43 | 2013-06-04 04:52:23 +0000 | [diff] [blame] | 2589 | /* Get mac address */ |
| 2590 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) |
| 2591 | { |
| 2592 | u32 mac_addr_l, mac_addr_h; |
| 2593 | |
| 2594 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); |
| 2595 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); |
| 2596 | addr[0] = (mac_addr_h >> 24) & 0xFF; |
| 2597 | addr[1] = (mac_addr_h >> 16) & 0xFF; |
| 2598 | addr[2] = (mac_addr_h >> 8) & 0xFF; |
| 2599 | addr[3] = mac_addr_h & 0xFF; |
| 2600 | addr[4] = (mac_addr_l >> 8) & 0xFF; |
| 2601 | addr[5] = mac_addr_l & 0xFF; |
| 2602 | } |
| 2603 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2604 | /* Handle setting mac address */ |
| 2605 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) |
| 2606 | { |
| 2607 | struct mvneta_port *pp = netdev_priv(dev); |
Ezequiel Garcia | e68de36 | 2014-05-22 20:07:00 -0300 | [diff] [blame] | 2608 | struct sockaddr *sockaddr = addr; |
| 2609 | int ret; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2610 | |
Ezequiel Garcia | e68de36 | 2014-05-22 20:07:00 -0300 | [diff] [blame] | 2611 | ret = eth_prepare_mac_addr_change(dev, addr); |
| 2612 | if (ret < 0) |
| 2613 | return ret; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2614 | /* Remove previous address table entry */ |
| 2615 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); |
| 2616 | |
| 2617 | /* Set new addr in hw */ |
Ezequiel Garcia | e68de36 | 2014-05-22 20:07:00 -0300 | [diff] [blame] | 2618 | mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2619 | |
Ezequiel Garcia | e68de36 | 2014-05-22 20:07:00 -0300 | [diff] [blame] | 2620 | eth_commit_mac_addr_change(dev, addr); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2621 | return 0; |
| 2622 | } |
| 2623 | |
| 2624 | static void mvneta_adjust_link(struct net_device *ndev) |
| 2625 | { |
| 2626 | struct mvneta_port *pp = netdev_priv(ndev); |
| 2627 | struct phy_device *phydev = pp->phy_dev; |
| 2628 | int status_change = 0; |
| 2629 | |
| 2630 | if (phydev->link) { |
| 2631 | if ((pp->speed != phydev->speed) || |
| 2632 | (pp->duplex != phydev->duplex)) { |
| 2633 | u32 val; |
| 2634 | |
| 2635 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
| 2636 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | |
| 2637 | MVNETA_GMAC_CONFIG_GMII_SPEED | |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 2638 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2639 | |
| 2640 | if (phydev->duplex) |
| 2641 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; |
| 2642 | |
| 2643 | if (phydev->speed == SPEED_1000) |
| 2644 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; |
Thomas Petazzoni | 4d12bc6 | 2014-07-08 10:49:43 +0200 | [diff] [blame] | 2645 | else if (phydev->speed == SPEED_100) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2646 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
| 2647 | |
| 2648 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); |
| 2649 | |
| 2650 | pp->duplex = phydev->duplex; |
| 2651 | pp->speed = phydev->speed; |
| 2652 | } |
| 2653 | } |
| 2654 | |
| 2655 | if (phydev->link != pp->link) { |
| 2656 | if (!phydev->link) { |
| 2657 | pp->duplex = -1; |
| 2658 | pp->speed = 0; |
| 2659 | } |
| 2660 | |
| 2661 | pp->link = phydev->link; |
| 2662 | status_change = 1; |
| 2663 | } |
| 2664 | |
| 2665 | if (status_change) { |
| 2666 | if (phydev->link) { |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 2667 | if (!pp->use_inband_status) { |
| 2668 | u32 val = mvreg_read(pp, |
| 2669 | MVNETA_GMAC_AUTONEG_CONFIG); |
| 2670 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; |
| 2671 | val |= MVNETA_GMAC_FORCE_LINK_PASS; |
| 2672 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, |
| 2673 | val); |
| 2674 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2675 | mvneta_port_up(pp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2676 | } else { |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 2677 | if (!pp->use_inband_status) { |
| 2678 | u32 val = mvreg_read(pp, |
| 2679 | MVNETA_GMAC_AUTONEG_CONFIG); |
| 2680 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; |
| 2681 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; |
| 2682 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, |
| 2683 | val); |
| 2684 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2685 | mvneta_port_down(pp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2686 | } |
Ezequiel Garcia | 0089b74 | 2014-10-31 12:57:20 -0300 | [diff] [blame] | 2687 | phy_print_status(phydev); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2688 | } |
| 2689 | } |
| 2690 | |
| 2691 | static int mvneta_mdio_probe(struct mvneta_port *pp) |
| 2692 | { |
| 2693 | struct phy_device *phy_dev; |
| 2694 | |
| 2695 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, |
| 2696 | pp->phy_interface); |
| 2697 | if (!phy_dev) { |
| 2698 | netdev_err(pp->dev, "could not find the PHY\n"); |
| 2699 | return -ENODEV; |
| 2700 | } |
| 2701 | |
| 2702 | phy_dev->supported &= PHY_GBIT_FEATURES; |
| 2703 | phy_dev->advertising = phy_dev->supported; |
| 2704 | |
| 2705 | pp->phy_dev = phy_dev; |
| 2706 | pp->link = 0; |
| 2707 | pp->duplex = 0; |
| 2708 | pp->speed = 0; |
| 2709 | |
| 2710 | return 0; |
| 2711 | } |
| 2712 | |
| 2713 | static void mvneta_mdio_remove(struct mvneta_port *pp) |
| 2714 | { |
| 2715 | phy_disconnect(pp->phy_dev); |
| 2716 | pp->phy_dev = NULL; |
| 2717 | } |
| 2718 | |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 2719 | static void mvneta_percpu_enable(void *arg) |
| 2720 | { |
| 2721 | struct mvneta_port *pp = arg; |
| 2722 | |
| 2723 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); |
| 2724 | } |
| 2725 | |
| 2726 | static void mvneta_percpu_disable(void *arg) |
| 2727 | { |
| 2728 | struct mvneta_port *pp = arg; |
| 2729 | |
| 2730 | disable_percpu_irq(pp->dev->irq); |
| 2731 | } |
| 2732 | |
| 2733 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
| 2734 | { |
| 2735 | int online_cpu_idx, cpu, i = 0; |
| 2736 | |
| 2737 | online_cpu_idx = rxq_def % num_online_cpus(); |
| 2738 | |
| 2739 | for_each_online_cpu(cpu) { |
| 2740 | if (i == online_cpu_idx) |
| 2741 | /* Enable per-CPU interrupt on the one CPU we |
| 2742 | * just elected |
| 2743 | */ |
| 2744 | smp_call_function_single(cpu, mvneta_percpu_enable, |
| 2745 | pp, true); |
| 2746 | else |
| 2747 | /* Disable per-CPU interrupt on all the other CPU */ |
| 2748 | smp_call_function_single(cpu, mvneta_percpu_disable, |
| 2749 | pp, true); |
| 2750 | i++; |
| 2751 | } |
| 2752 | }; |
| 2753 | |
| 2754 | static int mvneta_percpu_notifier(struct notifier_block *nfb, |
| 2755 | unsigned long action, void *hcpu) |
| 2756 | { |
| 2757 | struct mvneta_port *pp = container_of(nfb, struct mvneta_port, |
| 2758 | cpu_notifier); |
| 2759 | int cpu = (unsigned long)hcpu, other_cpu; |
| 2760 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
| 2761 | |
| 2762 | switch (action) { |
| 2763 | case CPU_ONLINE: |
| 2764 | case CPU_ONLINE_FROZEN: |
| 2765 | netif_tx_stop_all_queues(pp->dev); |
| 2766 | |
| 2767 | /* We have to synchronise on tha napi of each CPU |
| 2768 | * except the one just being waked up |
| 2769 | */ |
| 2770 | for_each_online_cpu(other_cpu) { |
| 2771 | if (other_cpu != cpu) { |
| 2772 | struct mvneta_pcpu_port *other_port = |
| 2773 | per_cpu_ptr(pp->ports, other_cpu); |
| 2774 | |
| 2775 | napi_synchronize(&other_port->napi); |
| 2776 | } |
| 2777 | } |
| 2778 | |
| 2779 | /* Mask all ethernet port interrupts */ |
| 2780 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 2781 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); |
| 2782 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); |
| 2783 | napi_enable(&port->napi); |
| 2784 | |
| 2785 | /* Enable per-CPU interrupt on the one CPU we care |
| 2786 | * about. |
| 2787 | */ |
| 2788 | mvneta_percpu_elect(pp); |
| 2789 | |
| 2790 | /* Unmask all ethernet port interrupts */ |
| 2791 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, |
| 2792 | MVNETA_RX_INTR_MASK(rxq_number) | |
| 2793 | MVNETA_TX_INTR_MASK(txq_number) | |
| 2794 | MVNETA_MISCINTR_INTR_MASK); |
| 2795 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
| 2796 | MVNETA_CAUSE_PHY_STATUS_CHANGE | |
| 2797 | MVNETA_CAUSE_LINK_CHANGE | |
| 2798 | MVNETA_CAUSE_PSC_SYNC_CHANGE); |
| 2799 | netif_tx_start_all_queues(pp->dev); |
| 2800 | break; |
| 2801 | case CPU_DOWN_PREPARE: |
| 2802 | case CPU_DOWN_PREPARE_FROZEN: |
| 2803 | netif_tx_stop_all_queues(pp->dev); |
| 2804 | /* Mask all ethernet port interrupts */ |
| 2805 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); |
| 2806 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); |
| 2807 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); |
| 2808 | |
| 2809 | napi_synchronize(&port->napi); |
| 2810 | napi_disable(&port->napi); |
| 2811 | /* Disable per-CPU interrupts on the CPU that is |
| 2812 | * brought down. |
| 2813 | */ |
| 2814 | smp_call_function_single(cpu, mvneta_percpu_disable, |
| 2815 | pp, true); |
| 2816 | |
| 2817 | break; |
| 2818 | case CPU_DEAD: |
| 2819 | case CPU_DEAD_FROZEN: |
| 2820 | /* Check if a new CPU must be elected now this on is down */ |
| 2821 | mvneta_percpu_elect(pp); |
| 2822 | /* Unmask all ethernet port interrupts */ |
| 2823 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, |
| 2824 | MVNETA_RX_INTR_MASK(rxq_number) | |
| 2825 | MVNETA_TX_INTR_MASK(txq_number) | |
| 2826 | MVNETA_MISCINTR_INTR_MASK); |
| 2827 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
| 2828 | MVNETA_CAUSE_PHY_STATUS_CHANGE | |
| 2829 | MVNETA_CAUSE_LINK_CHANGE | |
| 2830 | MVNETA_CAUSE_PSC_SYNC_CHANGE); |
| 2831 | netif_tx_start_all_queues(pp->dev); |
| 2832 | break; |
| 2833 | } |
| 2834 | |
| 2835 | return NOTIFY_OK; |
| 2836 | } |
| 2837 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2838 | static int mvneta_open(struct net_device *dev) |
| 2839 | { |
| 2840 | struct mvneta_port *pp = netdev_priv(dev); |
| 2841 | int ret; |
| 2842 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2843 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
willy tarreau | 8ec2cd4 | 2014-01-16 08:20:16 +0100 | [diff] [blame] | 2844 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
| 2845 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2846 | |
| 2847 | ret = mvneta_setup_rxqs(pp); |
| 2848 | if (ret) |
| 2849 | return ret; |
| 2850 | |
| 2851 | ret = mvneta_setup_txqs(pp); |
| 2852 | if (ret) |
| 2853 | goto err_cleanup_rxqs; |
| 2854 | |
| 2855 | /* Connect to port interrupt line */ |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2856 | ret = request_percpu_irq(pp->dev->irq, mvneta_isr, |
| 2857 | MVNETA_DRIVER_NAME, pp->ports); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2858 | if (ret) { |
| 2859 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); |
| 2860 | goto err_cleanup_txqs; |
| 2861 | } |
| 2862 | |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 2863 | /* Even though the documentation says that request_percpu_irq |
| 2864 | * doesn't enable the interrupts automatically, it actually |
| 2865 | * does so on the local CPU. |
| 2866 | * |
| 2867 | * Make sure it's disabled. |
| 2868 | */ |
| 2869 | mvneta_percpu_disable(pp); |
| 2870 | |
| 2871 | /* Elect a CPU to handle our RX queue interrupt */ |
| 2872 | mvneta_percpu_elect(pp); |
| 2873 | |
| 2874 | /* Register a CPU notifier to handle the case where our CPU |
| 2875 | * might be taken offline. |
| 2876 | */ |
| 2877 | register_cpu_notifier(&pp->cpu_notifier); |
| 2878 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2879 | /* In default link is down */ |
| 2880 | netif_carrier_off(pp->dev); |
| 2881 | |
| 2882 | ret = mvneta_mdio_probe(pp); |
| 2883 | if (ret < 0) { |
| 2884 | netdev_err(dev, "cannot probe MDIO bus\n"); |
| 2885 | goto err_free_irq; |
| 2886 | } |
| 2887 | |
| 2888 | mvneta_start_dev(pp); |
| 2889 | |
| 2890 | return 0; |
| 2891 | |
| 2892 | err_free_irq: |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2893 | free_percpu_irq(pp->dev->irq, pp->ports); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2894 | err_cleanup_txqs: |
| 2895 | mvneta_cleanup_txqs(pp); |
| 2896 | err_cleanup_rxqs: |
| 2897 | mvneta_cleanup_rxqs(pp); |
| 2898 | return ret; |
| 2899 | } |
| 2900 | |
| 2901 | /* Stop the port, free port interrupt line */ |
| 2902 | static int mvneta_stop(struct net_device *dev) |
| 2903 | { |
| 2904 | struct mvneta_port *pp = netdev_priv(dev); |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 2905 | int cpu; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2906 | |
| 2907 | mvneta_stop_dev(pp); |
| 2908 | mvneta_mdio_remove(pp); |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 2909 | unregister_cpu_notifier(&pp->cpu_notifier); |
| 2910 | for_each_present_cpu(cpu) |
| 2911 | smp_call_function_single(cpu, mvneta_percpu_disable, pp, true); |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 2912 | free_percpu_irq(dev->irq, pp->ports); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2913 | mvneta_cleanup_rxqs(pp); |
| 2914 | mvneta_cleanup_txqs(pp); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2915 | |
| 2916 | return 0; |
| 2917 | } |
| 2918 | |
Thomas Petazzoni | 15f5945 | 2013-09-04 16:26:52 +0200 | [diff] [blame] | 2919 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 2920 | { |
| 2921 | struct mvneta_port *pp = netdev_priv(dev); |
Thomas Petazzoni | 15f5945 | 2013-09-04 16:26:52 +0200 | [diff] [blame] | 2922 | |
| 2923 | if (!pp->phy_dev) |
| 2924 | return -ENOTSUPP; |
| 2925 | |
Stas Sergeev | ecf7b36 | 2015-04-01 19:23:29 +0300 | [diff] [blame] | 2926 | return phy_mii_ioctl(pp->phy_dev, ifr, cmd); |
Thomas Petazzoni | 15f5945 | 2013-09-04 16:26:52 +0200 | [diff] [blame] | 2927 | } |
| 2928 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 2929 | /* Ethtool methods */ |
| 2930 | |
| 2931 | /* Get settings (phy address, speed) for ethtools */ |
| 2932 | int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 2933 | { |
| 2934 | struct mvneta_port *pp = netdev_priv(dev); |
| 2935 | |
| 2936 | if (!pp->phy_dev) |
| 2937 | return -ENODEV; |
| 2938 | |
| 2939 | return phy_ethtool_gset(pp->phy_dev, cmd); |
| 2940 | } |
| 2941 | |
| 2942 | /* Set settings (phy address, speed) for ethtools */ |
| 2943 | int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 2944 | { |
| 2945 | struct mvneta_port *pp = netdev_priv(dev); |
| 2946 | |
| 2947 | if (!pp->phy_dev) |
| 2948 | return -ENODEV; |
| 2949 | |
| 2950 | return phy_ethtool_sset(pp->phy_dev, cmd); |
| 2951 | } |
| 2952 | |
| 2953 | /* Set interrupt coalescing for ethtools */ |
| 2954 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, |
| 2955 | struct ethtool_coalesce *c) |
| 2956 | { |
| 2957 | struct mvneta_port *pp = netdev_priv(dev); |
| 2958 | int queue; |
| 2959 | |
| 2960 | for (queue = 0; queue < rxq_number; queue++) { |
| 2961 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; |
| 2962 | rxq->time_coal = c->rx_coalesce_usecs; |
| 2963 | rxq->pkts_coal = c->rx_max_coalesced_frames; |
| 2964 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); |
| 2965 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); |
| 2966 | } |
| 2967 | |
| 2968 | for (queue = 0; queue < txq_number; queue++) { |
| 2969 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; |
| 2970 | txq->done_pkts_coal = c->tx_max_coalesced_frames; |
| 2971 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
| 2972 | } |
| 2973 | |
| 2974 | return 0; |
| 2975 | } |
| 2976 | |
| 2977 | /* get coalescing for ethtools */ |
| 2978 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, |
| 2979 | struct ethtool_coalesce *c) |
| 2980 | { |
| 2981 | struct mvneta_port *pp = netdev_priv(dev); |
| 2982 | |
| 2983 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; |
| 2984 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; |
| 2985 | |
| 2986 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; |
| 2987 | return 0; |
| 2988 | } |
| 2989 | |
| 2990 | |
| 2991 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, |
| 2992 | struct ethtool_drvinfo *drvinfo) |
| 2993 | { |
| 2994 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, |
| 2995 | sizeof(drvinfo->driver)); |
| 2996 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, |
| 2997 | sizeof(drvinfo->version)); |
| 2998 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), |
| 2999 | sizeof(drvinfo->bus_info)); |
| 3000 | } |
| 3001 | |
| 3002 | |
| 3003 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, |
| 3004 | struct ethtool_ringparam *ring) |
| 3005 | { |
| 3006 | struct mvneta_port *pp = netdev_priv(netdev); |
| 3007 | |
| 3008 | ring->rx_max_pending = MVNETA_MAX_RXD; |
| 3009 | ring->tx_max_pending = MVNETA_MAX_TXD; |
| 3010 | ring->rx_pending = pp->rx_ring_size; |
| 3011 | ring->tx_pending = pp->tx_ring_size; |
| 3012 | } |
| 3013 | |
| 3014 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, |
| 3015 | struct ethtool_ringparam *ring) |
| 3016 | { |
| 3017 | struct mvneta_port *pp = netdev_priv(dev); |
| 3018 | |
| 3019 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) |
| 3020 | return -EINVAL; |
| 3021 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? |
| 3022 | ring->rx_pending : MVNETA_MAX_RXD; |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 3023 | |
| 3024 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, |
| 3025 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); |
| 3026 | if (pp->tx_ring_size != ring->tx_pending) |
| 3027 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", |
| 3028 | pp->tx_ring_size, ring->tx_pending); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3029 | |
| 3030 | if (netif_running(dev)) { |
| 3031 | mvneta_stop(dev); |
| 3032 | if (mvneta_open(dev)) { |
| 3033 | netdev_err(dev, |
| 3034 | "error on opening device after ring param change\n"); |
| 3035 | return -ENOMEM; |
| 3036 | } |
| 3037 | } |
| 3038 | |
| 3039 | return 0; |
| 3040 | } |
| 3041 | |
Russell King | 9b0cdef | 2015-10-22 18:37:30 +0100 | [diff] [blame] | 3042 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
| 3043 | u8 *data) |
| 3044 | { |
| 3045 | if (sset == ETH_SS_STATS) { |
| 3046 | int i; |
| 3047 | |
| 3048 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) |
| 3049 | memcpy(data + i * ETH_GSTRING_LEN, |
| 3050 | mvneta_statistics[i].name, ETH_GSTRING_LEN); |
| 3051 | } |
| 3052 | } |
| 3053 | |
| 3054 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) |
| 3055 | { |
| 3056 | const struct mvneta_statistic *s; |
| 3057 | void __iomem *base = pp->base; |
| 3058 | u32 high, low, val; |
| 3059 | int i; |
| 3060 | |
| 3061 | for (i = 0, s = mvneta_statistics; |
| 3062 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); |
| 3063 | s++, i++) { |
| 3064 | val = 0; |
| 3065 | |
| 3066 | switch (s->type) { |
| 3067 | case T_REG_32: |
| 3068 | val = readl_relaxed(base + s->offset); |
| 3069 | break; |
| 3070 | case T_REG_64: |
| 3071 | /* Docs say to read low 32-bit then high */ |
| 3072 | low = readl_relaxed(base + s->offset); |
| 3073 | high = readl_relaxed(base + s->offset + 4); |
| 3074 | val = (u64)high << 32 | low; |
| 3075 | break; |
| 3076 | } |
| 3077 | |
| 3078 | pp->ethtool_stats[i] += val; |
| 3079 | } |
| 3080 | } |
| 3081 | |
| 3082 | static void mvneta_ethtool_get_stats(struct net_device *dev, |
| 3083 | struct ethtool_stats *stats, u64 *data) |
| 3084 | { |
| 3085 | struct mvneta_port *pp = netdev_priv(dev); |
| 3086 | int i; |
| 3087 | |
| 3088 | mvneta_ethtool_update_stats(pp); |
| 3089 | |
| 3090 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) |
| 3091 | *data++ = pp->ethtool_stats[i]; |
| 3092 | } |
| 3093 | |
| 3094 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) |
| 3095 | { |
| 3096 | if (sset == ETH_SS_STATS) |
| 3097 | return ARRAY_SIZE(mvneta_statistics); |
| 3098 | return -EOPNOTSUPP; |
| 3099 | } |
| 3100 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3101 | static const struct net_device_ops mvneta_netdev_ops = { |
| 3102 | .ndo_open = mvneta_open, |
| 3103 | .ndo_stop = mvneta_stop, |
| 3104 | .ndo_start_xmit = mvneta_tx, |
| 3105 | .ndo_set_rx_mode = mvneta_set_rx_mode, |
| 3106 | .ndo_set_mac_address = mvneta_set_mac_addr, |
| 3107 | .ndo_change_mtu = mvneta_change_mtu, |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 3108 | .ndo_fix_features = mvneta_fix_features, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3109 | .ndo_get_stats64 = mvneta_get_stats64, |
Thomas Petazzoni | 15f5945 | 2013-09-04 16:26:52 +0200 | [diff] [blame] | 3110 | .ndo_do_ioctl = mvneta_ioctl, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3111 | }; |
| 3112 | |
| 3113 | const struct ethtool_ops mvneta_eth_tool_ops = { |
| 3114 | .get_link = ethtool_op_get_link, |
| 3115 | .get_settings = mvneta_ethtool_get_settings, |
| 3116 | .set_settings = mvneta_ethtool_set_settings, |
| 3117 | .set_coalesce = mvneta_ethtool_set_coalesce, |
| 3118 | .get_coalesce = mvneta_ethtool_get_coalesce, |
| 3119 | .get_drvinfo = mvneta_ethtool_get_drvinfo, |
| 3120 | .get_ringparam = mvneta_ethtool_get_ringparam, |
| 3121 | .set_ringparam = mvneta_ethtool_set_ringparam, |
Russell King | 9b0cdef | 2015-10-22 18:37:30 +0100 | [diff] [blame] | 3122 | .get_strings = mvneta_ethtool_get_strings, |
| 3123 | .get_ethtool_stats = mvneta_ethtool_get_stats, |
| 3124 | .get_sset_count = mvneta_ethtool_get_sset_count, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3125 | }; |
| 3126 | |
| 3127 | /* Initialize hw */ |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 3128 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3129 | { |
| 3130 | int queue; |
| 3131 | |
| 3132 | /* Disable port */ |
| 3133 | mvneta_port_disable(pp); |
| 3134 | |
| 3135 | /* Set port default values */ |
| 3136 | mvneta_defaults_set(pp); |
| 3137 | |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 3138 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), |
| 3139 | GFP_KERNEL); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3140 | if (!pp->txqs) |
| 3141 | return -ENOMEM; |
| 3142 | |
| 3143 | /* Initialize TX descriptor rings */ |
| 3144 | for (queue = 0; queue < txq_number; queue++) { |
| 3145 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; |
| 3146 | txq->id = queue; |
| 3147 | txq->size = pp->tx_ring_size; |
| 3148 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; |
| 3149 | } |
| 3150 | |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 3151 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), |
| 3152 | GFP_KERNEL); |
| 3153 | if (!pp->rxqs) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3154 | return -ENOMEM; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3155 | |
| 3156 | /* Create Rx descriptor rings */ |
| 3157 | for (queue = 0; queue < rxq_number; queue++) { |
| 3158 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; |
| 3159 | rxq->id = queue; |
| 3160 | rxq->size = pp->rx_ring_size; |
| 3161 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; |
| 3162 | rxq->time_coal = MVNETA_RX_COAL_USEC; |
| 3163 | } |
| 3164 | |
| 3165 | return 0; |
| 3166 | } |
| 3167 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3168 | /* platform glue : initialize decoding windows */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 3169 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
| 3170 | const struct mbus_dram_target_info *dram) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3171 | { |
| 3172 | u32 win_enable; |
| 3173 | u32 win_protect; |
| 3174 | int i; |
| 3175 | |
| 3176 | for (i = 0; i < 6; i++) { |
| 3177 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); |
| 3178 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); |
| 3179 | |
| 3180 | if (i < 4) |
| 3181 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); |
| 3182 | } |
| 3183 | |
| 3184 | win_enable = 0x3f; |
| 3185 | win_protect = 0; |
| 3186 | |
| 3187 | for (i = 0; i < dram->num_cs; i++) { |
| 3188 | const struct mbus_dram_window *cs = dram->cs + i; |
| 3189 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | |
| 3190 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); |
| 3191 | |
| 3192 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
| 3193 | (cs->size - 1) & 0xffff0000); |
| 3194 | |
| 3195 | win_enable &= ~(1 << i); |
| 3196 | win_protect |= 3 << (2 * i); |
| 3197 | } |
| 3198 | |
| 3199 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); |
Marcin Wojtas | db6ba9a | 2015-11-30 13:27:41 +0100 | [diff] [blame] | 3200 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3201 | } |
| 3202 | |
| 3203 | /* Power up the port */ |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3204 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3205 | { |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3206 | u32 ctrl; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3207 | |
| 3208 | /* MAC Cause register should be cleared */ |
| 3209 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); |
| 3210 | |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3211 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3212 | |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3213 | /* Even though it might look weird, when we're configured in |
| 3214 | * SGMII or QSGMII mode, the RGMII bit needs to be set. |
| 3215 | */ |
| 3216 | switch(phy_mode) { |
| 3217 | case PHY_INTERFACE_MODE_QSGMII: |
| 3218 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); |
| 3219 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; |
| 3220 | break; |
| 3221 | case PHY_INTERFACE_MODE_SGMII: |
| 3222 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); |
| 3223 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; |
| 3224 | break; |
| 3225 | case PHY_INTERFACE_MODE_RGMII: |
| 3226 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 3227 | ctrl |= MVNETA_GMAC2_PORT_RGMII; |
| 3228 | break; |
| 3229 | default: |
| 3230 | return -EINVAL; |
| 3231 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3232 | |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 3233 | if (pp->use_inband_status) |
| 3234 | ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE; |
| 3235 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3236 | /* Cancel Port Reset */ |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3237 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; |
| 3238 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3239 | |
| 3240 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & |
| 3241 | MVNETA_GMAC2_PORT_RESET) != 0) |
| 3242 | continue; |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3243 | |
| 3244 | return 0; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3245 | } |
| 3246 | |
| 3247 | /* Device initialization routine */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 3248 | static int mvneta_probe(struct platform_device *pdev) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3249 | { |
| 3250 | const struct mbus_dram_target_info *dram_target_info; |
Thomas Petazzoni | c3f0dd3 | 2014-03-27 11:39:29 +0100 | [diff] [blame] | 3251 | struct resource *res; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3252 | struct device_node *dn = pdev->dev.of_node; |
| 3253 | struct device_node *phy_node; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3254 | struct mvneta_port *pp; |
| 3255 | struct net_device *dev; |
Thomas Petazzoni | 8cc3e43 | 2013-06-04 04:52:23 +0000 | [diff] [blame] | 3256 | const char *dt_mac_addr; |
| 3257 | char hw_mac_addr[ETH_ALEN]; |
| 3258 | const char *mac_from; |
Stas Sergeev | f8af8e6 | 2015-07-20 17:49:58 -0700 | [diff] [blame] | 3259 | const char *managed; |
Marcin Wojtas | 9110ee0 | 2015-11-30 13:27:45 +0100 | [diff] [blame] | 3260 | int tx_csum_limit; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3261 | int phy_mode; |
| 3262 | int err; |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 3263 | int cpu; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3264 | |
Willy Tarreau | ee40a11 | 2013-04-11 23:00:37 +0200 | [diff] [blame] | 3265 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3266 | if (!dev) |
| 3267 | return -ENOMEM; |
| 3268 | |
| 3269 | dev->irq = irq_of_parse_and_map(dn, 0); |
| 3270 | if (dev->irq == 0) { |
| 3271 | err = -EINVAL; |
| 3272 | goto err_free_netdev; |
| 3273 | } |
| 3274 | |
| 3275 | phy_node = of_parse_phandle(dn, "phy", 0); |
| 3276 | if (!phy_node) { |
Thomas Petazzoni | 83895be | 2014-05-16 16:14:06 +0200 | [diff] [blame] | 3277 | if (!of_phy_is_fixed_link(dn)) { |
| 3278 | dev_err(&pdev->dev, "no PHY specified\n"); |
| 3279 | err = -ENODEV; |
| 3280 | goto err_free_irq; |
| 3281 | } |
| 3282 | |
| 3283 | err = of_phy_register_fixed_link(dn); |
| 3284 | if (err < 0) { |
| 3285 | dev_err(&pdev->dev, "cannot register fixed PHY\n"); |
| 3286 | goto err_free_irq; |
| 3287 | } |
| 3288 | |
| 3289 | /* In the case of a fixed PHY, the DT node associated |
| 3290 | * to the PHY is the Ethernet MAC DT node. |
| 3291 | */ |
Uwe Kleine-König | c891c24 | 2014-08-07 21:58:46 +0200 | [diff] [blame] | 3292 | phy_node = of_node_get(dn); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3293 | } |
| 3294 | |
| 3295 | phy_mode = of_get_phy_mode(dn); |
| 3296 | if (phy_mode < 0) { |
| 3297 | dev_err(&pdev->dev, "incorrect phy-mode\n"); |
| 3298 | err = -EINVAL; |
Uwe Kleine-König | c891c24 | 2014-08-07 21:58:46 +0200 | [diff] [blame] | 3299 | goto err_put_phy_node; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3300 | } |
| 3301 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3302 | dev->tx_queue_len = MVNETA_MAX_TXD; |
| 3303 | dev->watchdog_timeo = 5 * HZ; |
| 3304 | dev->netdev_ops = &mvneta_netdev_ops; |
| 3305 | |
Wilfried Klaebe | 7ad24ea | 2014-05-11 00:12:32 +0000 | [diff] [blame] | 3306 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3307 | |
| 3308 | pp = netdev_priv(dev); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3309 | pp->phy_node = phy_node; |
| 3310 | pp->phy_interface = phy_mode; |
Stas Sergeev | f8af8e6 | 2015-07-20 17:49:58 -0700 | [diff] [blame] | 3311 | |
| 3312 | err = of_property_read_string(dn, "managed", &managed); |
| 3313 | pp->use_inband_status = (err == 0 && |
| 3314 | strcmp(managed, "in-band-status") == 0); |
Maxime Ripard | f864288 | 2015-09-25 18:09:38 +0200 | [diff] [blame] | 3315 | pp->cpu_notifier.notifier_call = mvneta_percpu_notifier; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3316 | |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 3317 | pp->clk = devm_clk_get(&pdev->dev, NULL); |
| 3318 | if (IS_ERR(pp->clk)) { |
| 3319 | err = PTR_ERR(pp->clk); |
Uwe Kleine-König | c891c24 | 2014-08-07 21:58:46 +0200 | [diff] [blame] | 3320 | goto err_put_phy_node; |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 3321 | } |
| 3322 | |
| 3323 | clk_prepare_enable(pp->clk); |
| 3324 | |
Thomas Petazzoni | c3f0dd3 | 2014-03-27 11:39:29 +0100 | [diff] [blame] | 3325 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 3326 | pp->base = devm_ioremap_resource(&pdev->dev, res); |
| 3327 | if (IS_ERR(pp->base)) { |
| 3328 | err = PTR_ERR(pp->base); |
Arnaud Patard \(Rtp\) | 5445eaf | 2013-07-29 21:56:48 +0200 | [diff] [blame] | 3329 | goto err_clk; |
| 3330 | } |
| 3331 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 3332 | /* Alloc per-cpu port structure */ |
| 3333 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); |
| 3334 | if (!pp->ports) { |
| 3335 | err = -ENOMEM; |
| 3336 | goto err_clk; |
| 3337 | } |
| 3338 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 3339 | /* Alloc per-cpu stats */ |
WANG Cong | 1c213bd | 2014-02-13 11:46:28 -0800 | [diff] [blame] | 3340 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 3341 | if (!pp->stats) { |
| 3342 | err = -ENOMEM; |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 3343 | goto err_free_ports; |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 3344 | } |
| 3345 | |
Thomas Petazzoni | 8cc3e43 | 2013-06-04 04:52:23 +0000 | [diff] [blame] | 3346 | dt_mac_addr = of_get_mac_address(dn); |
Luka Perkov | 6c7a9a3 | 2013-10-30 00:10:01 +0100 | [diff] [blame] | 3347 | if (dt_mac_addr) { |
Thomas Petazzoni | 8cc3e43 | 2013-06-04 04:52:23 +0000 | [diff] [blame] | 3348 | mac_from = "device tree"; |
| 3349 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); |
| 3350 | } else { |
| 3351 | mvneta_get_mac_addr(pp, hw_mac_addr); |
| 3352 | if (is_valid_ether_addr(hw_mac_addr)) { |
| 3353 | mac_from = "hardware"; |
| 3354 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); |
| 3355 | } else { |
| 3356 | mac_from = "random"; |
| 3357 | eth_hw_addr_random(dev); |
| 3358 | } |
| 3359 | } |
| 3360 | |
Marcin Wojtas | 9110ee0 | 2015-11-30 13:27:45 +0100 | [diff] [blame] | 3361 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
| 3362 | if (tx_csum_limit < 0 || |
| 3363 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { |
| 3364 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; |
| 3365 | dev_info(&pdev->dev, |
| 3366 | "Wrong TX csum limit in DT, set to %dB\n", |
| 3367 | MVNETA_TX_CSUM_DEF_SIZE); |
| 3368 | } |
| 3369 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { |
| 3370 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; |
| 3371 | } else { |
| 3372 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; |
| 3373 | } |
| 3374 | |
| 3375 | pp->tx_csum_limit = tx_csum_limit; |
Simon Guinot | b65657f | 2015-06-30 16:20:22 +0200 | [diff] [blame] | 3376 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3377 | pp->tx_ring_size = MVNETA_MAX_TXD; |
| 3378 | pp->rx_ring_size = MVNETA_MAX_RXD; |
| 3379 | |
| 3380 | pp->dev = dev; |
| 3381 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 3382 | |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 3383 | err = mvneta_init(&pdev->dev, pp); |
| 3384 | if (err < 0) |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 3385 | goto err_free_stats; |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3386 | |
| 3387 | err = mvneta_port_power_up(pp, phy_mode); |
| 3388 | if (err < 0) { |
| 3389 | dev_err(&pdev->dev, "can't power up port\n"); |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 3390 | goto err_free_stats; |
Thomas Petazzoni | 3f1dd4b | 2014-04-15 15:50:20 +0200 | [diff] [blame] | 3391 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3392 | |
| 3393 | dram_target_info = mv_mbus_dram_info(); |
| 3394 | if (dram_target_info) |
| 3395 | mvneta_conf_mbus_windows(pp, dram_target_info); |
| 3396 | |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 3397 | for_each_present_cpu(cpu) { |
| 3398 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
| 3399 | |
| 3400 | netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT); |
| 3401 | port->pp = pp; |
| 3402 | } |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3403 | |
Ezequiel Garcia | 2adb719 | 2014-05-19 13:59:55 -0300 | [diff] [blame] | 3404 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
Ezequiel Garcia | 01ef26c | 2014-05-19 13:59:53 -0300 | [diff] [blame] | 3405 | dev->hw_features |= dev->features; |
| 3406 | dev->vlan_features |= dev->features; |
willy tarreau | b50b72d | 2013-04-06 08:47:01 +0000 | [diff] [blame] | 3407 | dev->priv_flags |= IFF_UNICAST_FLT; |
Ezequiel Garcia | 8eef5f9 | 2014-05-30 13:40:05 -0300 | [diff] [blame] | 3408 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
willy tarreau | b50b72d | 2013-04-06 08:47:01 +0000 | [diff] [blame] | 3409 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3410 | err = register_netdev(dev); |
| 3411 | if (err < 0) { |
| 3412 | dev_err(&pdev->dev, "failed to register\n"); |
Ezequiel Garcia | 9672850 | 2014-05-22 20:06:59 -0300 | [diff] [blame] | 3413 | goto err_free_stats; |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3414 | } |
| 3415 | |
Thomas Petazzoni | 8cc3e43 | 2013-06-04 04:52:23 +0000 | [diff] [blame] | 3416 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
| 3417 | dev->dev_addr); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3418 | |
| 3419 | platform_set_drvdata(pdev, pp->dev); |
| 3420 | |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 3421 | if (pp->use_inband_status) { |
| 3422 | struct phy_device *phy = of_phy_find_device(dn); |
| 3423 | |
| 3424 | mvneta_fixed_link_update(pp, phy); |
Russell King | 04d53b2 | 2015-09-24 20:36:18 +0100 | [diff] [blame] | 3425 | |
| 3426 | put_device(&phy->dev); |
Stas Sergeev | 898b297 | 2015-04-01 20:32:49 +0300 | [diff] [blame] | 3427 | } |
| 3428 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3429 | return 0; |
| 3430 | |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 3431 | err_free_stats: |
| 3432 | free_percpu(pp->stats); |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 3433 | err_free_ports: |
| 3434 | free_percpu(pp->ports); |
Arnaud Patard \(Rtp\) | 5445eaf | 2013-07-29 21:56:48 +0200 | [diff] [blame] | 3435 | err_clk: |
| 3436 | clk_disable_unprepare(pp->clk); |
Uwe Kleine-König | c891c24 | 2014-08-07 21:58:46 +0200 | [diff] [blame] | 3437 | err_put_phy_node: |
| 3438 | of_node_put(phy_node); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3439 | err_free_irq: |
| 3440 | irq_dispose_mapping(dev->irq); |
| 3441 | err_free_netdev: |
| 3442 | free_netdev(dev); |
| 3443 | return err; |
| 3444 | } |
| 3445 | |
| 3446 | /* Device removal routine */ |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 3447 | static int mvneta_remove(struct platform_device *pdev) |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3448 | { |
| 3449 | struct net_device *dev = platform_get_drvdata(pdev); |
| 3450 | struct mvneta_port *pp = netdev_priv(dev); |
| 3451 | |
| 3452 | unregister_netdev(dev); |
Thomas Petazzoni | 189dd62 | 2012-11-19 14:15:25 +0100 | [diff] [blame] | 3453 | clk_disable_unprepare(pp->clk); |
Maxime Ripard | 12bb03b | 2015-09-25 18:09:36 +0200 | [diff] [blame] | 3454 | free_percpu(pp->ports); |
willy tarreau | 74c41b0 | 2014-01-16 08:20:08 +0100 | [diff] [blame] | 3455 | free_percpu(pp->stats); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3456 | irq_dispose_mapping(dev->irq); |
Uwe Kleine-König | c891c24 | 2014-08-07 21:58:46 +0200 | [diff] [blame] | 3457 | of_node_put(pp->phy_node); |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3458 | free_netdev(dev); |
| 3459 | |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3460 | return 0; |
| 3461 | } |
| 3462 | |
| 3463 | static const struct of_device_id mvneta_match[] = { |
| 3464 | { .compatible = "marvell,armada-370-neta" }, |
Simon Guinot | f522a97 | 2015-06-30 16:20:20 +0200 | [diff] [blame] | 3465 | { .compatible = "marvell,armada-xp-neta" }, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3466 | { } |
| 3467 | }; |
| 3468 | MODULE_DEVICE_TABLE(of, mvneta_match); |
| 3469 | |
| 3470 | static struct platform_driver mvneta_driver = { |
| 3471 | .probe = mvneta_probe, |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 3472 | .remove = mvneta_remove, |
Thomas Petazzoni | c5aff18 | 2012-08-17 14:04:28 +0300 | [diff] [blame] | 3473 | .driver = { |
| 3474 | .name = MVNETA_DRIVER_NAME, |
| 3475 | .of_match_table = mvneta_match, |
| 3476 | }, |
| 3477 | }; |
| 3478 | |
| 3479 | module_platform_driver(mvneta_driver); |
| 3480 | |
| 3481 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); |
| 3482 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); |
| 3483 | MODULE_LICENSE("GPL"); |
| 3484 | |
| 3485 | module_param(rxq_number, int, S_IRUGO); |
| 3486 | module_param(txq_number, int, S_IRUGO); |
| 3487 | |
| 3488 | module_param(rxq_def, int, S_IRUGO); |
willy tarreau | f19fadf | 2014-01-16 08:20:17 +0100 | [diff] [blame] | 3489 | module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); |