Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 533743dccb517b0331eccc111e3c2b8f021559b5 / . / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
blob: 214ac6ce3104173bd93d05d03b9e04dedf6230fb [file] [log] [blame]
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]21#include <linux/io.h>
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]22#include <linux/kernel.h>
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]23#include <linux/pinctrl/pinconf-generic.h>
24
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]25#include <mach/r8a7740.h>
26#include <mach/irqs.h>
27
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]28#include "core.h"
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]29#include "sh_pfc.h"
30
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]31#define CPU_ALL_PORT(fn, pfx, sfx) \
32 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
33 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
34 PORT_10(fn, pfx##20, sfx), \
35 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
36
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]37#define IRQC_PIN_MUX(irq, pin) \
38static const unsigned int intc_irq##irq##_pins[] = { \
39 pin, \
40}; \
41static const unsigned int intc_irq##irq##_mux[] = { \
42 IRQ##irq##_MARK, \
43}
44
45#define IRQC_PINS_MUX(irq, idx, pin) \
46static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
47 pin, \
48}; \
49static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
50 IRQ##irq##_PORT##pin##_MARK, \
51}
52
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]53enum {
54 PINMUX_RESERVED = 0,
55
56 /* PORT0_DATA -> PORT211_DATA */
57 PINMUX_DATA_BEGIN,
58 PORT_ALL(DATA),
59 PINMUX_DATA_END,
60
61 /* PORT0_IN -> PORT211_IN */
62 PINMUX_INPUT_BEGIN,
63 PORT_ALL(IN),
64 PINMUX_INPUT_END,
65
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]66 /* PORT0_OUT -> PORT211_OUT */
67 PINMUX_OUTPUT_BEGIN,
68 PORT_ALL(OUT),
69 PINMUX_OUTPUT_END,
70
71 PINMUX_FUNCTION_BEGIN,
72 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
73 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
74 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
75 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
76 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
77 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
78 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
79 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
80 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
81 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
82
83 MSEL1CR_31_0, MSEL1CR_31_1,
84 MSEL1CR_30_0, MSEL1CR_30_1,
85 MSEL1CR_29_0, MSEL1CR_29_1,
86 MSEL1CR_28_0, MSEL1CR_28_1,
87 MSEL1CR_27_0, MSEL1CR_27_1,
88 MSEL1CR_26_0, MSEL1CR_26_1,
89 MSEL1CR_16_0, MSEL1CR_16_1,
90 MSEL1CR_15_0, MSEL1CR_15_1,
91 MSEL1CR_14_0, MSEL1CR_14_1,
92 MSEL1CR_13_0, MSEL1CR_13_1,
93 MSEL1CR_12_0, MSEL1CR_12_1,
94 MSEL1CR_9_0, MSEL1CR_9_1,
95 MSEL1CR_7_0, MSEL1CR_7_1,
96 MSEL1CR_6_0, MSEL1CR_6_1,
97 MSEL1CR_5_0, MSEL1CR_5_1,
98 MSEL1CR_4_0, MSEL1CR_4_1,
99 MSEL1CR_3_0, MSEL1CR_3_1,
100 MSEL1CR_2_0, MSEL1CR_2_1,
101 MSEL1CR_0_0, MSEL1CR_0_1,
102
103 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
104 MSEL3CR_6_0, MSEL3CR_6_1,
105
106 MSEL4CR_19_0, MSEL4CR_19_1,
107 MSEL4CR_18_0, MSEL4CR_18_1,
108 MSEL4CR_15_0, MSEL4CR_15_1,
109 MSEL4CR_10_0, MSEL4CR_10_1,
110 MSEL4CR_6_0, MSEL4CR_6_1,
111 MSEL4CR_4_0, MSEL4CR_4_1,
112 MSEL4CR_1_0, MSEL4CR_1_1,
113
114 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
115 MSEL5CR_30_0, MSEL5CR_30_1,
116 MSEL5CR_29_0, MSEL5CR_29_1,
117 MSEL5CR_27_0, MSEL5CR_27_1,
118 MSEL5CR_25_0, MSEL5CR_25_1,
119 MSEL5CR_23_0, MSEL5CR_23_1,
120 MSEL5CR_21_0, MSEL5CR_21_1,
121 MSEL5CR_19_0, MSEL5CR_19_1,
122 MSEL5CR_17_0, MSEL5CR_17_1,
123 MSEL5CR_15_0, MSEL5CR_15_1,
124 MSEL5CR_14_0, MSEL5CR_14_1,
125 MSEL5CR_13_0, MSEL5CR_13_1,
126 MSEL5CR_12_0, MSEL5CR_12_1,
127 MSEL5CR_11_0, MSEL5CR_11_1,
128 MSEL5CR_10_0, MSEL5CR_10_1,
129 MSEL5CR_8_0, MSEL5CR_8_1,
130 MSEL5CR_7_0, MSEL5CR_7_1,
131 MSEL5CR_6_0, MSEL5CR_6_1,
132 MSEL5CR_5_0, MSEL5CR_5_1,
133 MSEL5CR_4_0, MSEL5CR_4_1,
134 MSEL5CR_3_0, MSEL5CR_3_1,
135 MSEL5CR_2_0, MSEL5CR_2_1,
136 MSEL5CR_0_0, MSEL5CR_0_1,
137 PINMUX_FUNCTION_END,
138
139 PINMUX_MARK_BEGIN,
140
141 /* IRQ */
142 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
143 IRQ1_MARK,
144 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
145 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
146 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
147 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
148 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
149 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
150 IRQ8_MARK,
151 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
152 IRQ10_MARK,
153 IRQ11_MARK,
154 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
155 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
156 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
157 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
158 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
159 IRQ17_MARK,
160 IRQ18_MARK,
161 IRQ19_MARK,
162 IRQ20_MARK,
163 IRQ21_MARK,
164 IRQ22_MARK,
165 IRQ23_MARK,
166 IRQ24_MARK,
167 IRQ25_MARK,
168 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
169 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
170 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
171 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
172 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
173 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
174
175 /* Function */
176
177 /* DBGT */
178 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
179 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
180 DBGMD21_MARK,
181
182 /* FSI-A */
183 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
184 FSIAISLD_PORT5_MARK,
185 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
186 FSIASPDIF_PORT18_MARK,
187 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
188 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
189 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
190
191 /* FSI-B */
192 FSIBCK_MARK,
193
194 /* FMSI */
195 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
196 FMSISLD_PORT6_MARK,
197 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
198 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
199 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
200
201 /* SCIFA0 */
202 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
203 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
204
205 /* SCIFA1 */
206 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
207 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
208
209 /* SCIFA2 */
210 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
211 SCIFA2_SCK_PORT199_MARK,
212 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
213 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
214
215 /* SCIFA3 */
216 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
217 SCIFA3_SCK_PORT116_MARK,
218 SCIFA3_CTS_PORT117_MARK,
219 SCIFA3_RXD_PORT174_MARK,
220 SCIFA3_TXD_PORT175_MARK,
221
222 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
223 SCIFA3_SCK_PORT158_MARK,
224 SCIFA3_CTS_PORT162_MARK,
225 SCIFA3_RXD_PORT159_MARK,
226 SCIFA3_TXD_PORT160_MARK,
227
228 /* SCIFA4 */
229 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
230 SCIFA4_TXD_PORT13_MARK,
231
232 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
233 SCIFA4_TXD_PORT203_MARK,
234
235 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
236 SCIFA4_TXD_PORT93_MARK,
237
238 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
239 SCIFA4_SCK_PORT205_MARK,
240
241 /* SCIFA5 */
242 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
243 SCIFA5_RXD_PORT10_MARK,
244
245 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
246 SCIFA5_TXD_PORT208_MARK,
247
248 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
249 SCIFA5_RXD_PORT92_MARK,
250
251 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
252 SCIFA5_SCK_PORT206_MARK,
253
254 /* SCIFA6 */
255 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
256
257 /* SCIFA7 */
258 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
259
260 /* SCIFAB */
261 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
262 SCIFB_RXD_PORT191_MARK,
263 SCIFB_TXD_PORT192_MARK,
264 SCIFB_RTS_PORT186_MARK,
265 SCIFB_CTS_PORT187_MARK,
266
267 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
268 SCIFB_RXD_PORT3_MARK,
269 SCIFB_TXD_PORT4_MARK,
270 SCIFB_RTS_PORT172_MARK,
271 SCIFB_CTS_PORT173_MARK,
272
273 /* LCD0 */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]274 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
275 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
276 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
277 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
278 LCD0_D16_MARK, LCD0_D17_MARK,
279 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
280 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
281 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
282 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
283 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
284
285 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
286 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
287 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
288 LCD0_LCLK_PORT165_MARK,
289
290 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
291 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
292 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
293 LCD0_LCLK_PORT102_MARK,
294
295 /* LCD1 */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]296 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
297 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
298 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
299 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
300 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
301 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
302 LCD1_DON_MARK, LCD1_VCPWC_MARK,
303 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
304
305 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
306 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
307 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
308 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
309
310 /* RSPI */
311 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
312 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
313 RSPI_MISO_A_MARK,
314
315 /* VIO CKO */
316 VIO_CKO1_MARK, /* needs fixup */
317 VIO_CKO2_MARK,
318 VIO_CKO_1_MARK,
319 VIO_CKO_MARK,
320
321 /* VIO0 */
322 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
323 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
324 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
325 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
326 VIO0_FIELD_MARK,
327
328 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
329 VIO0_D14_PORT25_MARK,
330 VIO0_D15_PORT24_MARK,
331
332 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
333 VIO0_D14_PORT95_MARK,
334 VIO0_D15_PORT96_MARK,
335
336 /* VIO1 */
337 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
338 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
339 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
340
341 /* TPU0 */
342 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
343 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
344 TPU0TO2_PORT202_MARK,
345
346 /* SSP1 0 */
347 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
348 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
349 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
350
351 /* SSP1 1 */
352 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
353 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
354 STP1_IPSYNC_MARK,
355
356 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
357 STP1_IPEN_PORT187_MARK,
358
359 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
360 STP1_IPEN_PORT193_MARK,
361
362 /* SIM */
363 SIM_RST_MARK, SIM_CLK_MARK,
364 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
365 SIM_D_PORT199_MARK,
366
367 /* SDHI0 */
368 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
369 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
370
371 /* SDHI1 */
372 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
373 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
374
375 /* SDHI2 */
376 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
377 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
378
379 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
380 SDHI2_WP_PORT25_MARK,
381
382 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
383 SDHI2_CD_PORT202_MARK,
384
385 /* MSIOF2 */
386 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
387 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
388 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
389 MSIOF2_RSCK_MARK,
390
391 /* KEYSC */
392 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
393 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
394 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
395
396 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
397 KEYIN1_PORT44_MARK,
398 KEYIN2_PORT45_MARK,
399 KEYIN3_PORT46_MARK,
400
401 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
402 KEYIN1_PORT57_MARK,
403 KEYIN2_PORT56_MARK,
404 KEYIN3_PORT55_MARK,
405
406 /* VOU */
407 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
408 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
409 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
410 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
411 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
412
413 /* MEMC */
414 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
415 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
416 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
417 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
418 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
419
420 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
421 MEMC_ADV_MARK,
422 MEMC_WAIT_MARK,
423 MEMC_BUSCLK_MARK,
424
425 MEMC_A1_MARK, /* MSEL4CR_6_1 */
426 MEMC_DREQ0_MARK,
427 MEMC_DREQ1_MARK,
428 MEMC_A0_MARK,
429
430 /* MMC */
431 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
432 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
433 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
434 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
435
436 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
437 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
438 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
439 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
440
441 /* MSIOF0 */
442 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
443 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
444 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
445 MSIOF0_TSYNC_MARK,
446
447 /* MSIOF1 */
448 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
449 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
450
451 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
452 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
453 MSIOF1_TSYNC_PORT120_MARK,
454 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
455
456 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
457 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
458 MSIOF1_RXD_PORT75_MARK,
459 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
460
461 /* GPIO */
462 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
463
464 /* USB0 */
465 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
466
467 /* USB1 */
468 USB1_OCI_MARK, USB1_PPON_MARK,
469
470 /* BBIF1 */
471 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
472 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
473 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
474
475 /* BBIF2 */
476 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
477 BBIF2_RXD2_PORT60_MARK,
478 BBIF2_TSYNC2_PORT6_MARK,
479 BBIF2_TSCK2_PORT59_MARK,
480
481 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
482 BBIF2_TXD2_PORT183_MARK,
483 BBIF2_TSCK2_PORT89_MARK,
484 BBIF2_TSYNC2_PORT184_MARK,
485
486 /* BSC / FLCTL / PCMCIA */
487 CS0_MARK, CS2_MARK, CS4_MARK,
488 CS5B_MARK, CS6A_MARK,
489 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
490 CS5A_PORT19_MARK,
491 IOIS16_MARK, /* ? */
492
493 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
494 A4_FOE_MARK, /* share with FLCTL */
495 A5_FCDE_MARK, /* share with FLCTL */
496 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
497 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
498 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
499 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
500 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
501 A26_MARK,
502
503 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
504 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
505 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
506 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
507 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
508 D15_NAF15_MARK, /* share with FLCTL */
509 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
510 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
511 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
512 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
513
514 WE0_FWE_MARK, /* share with FLCTL */
515 WE1_MARK,
516 WE2_ICIORD_MARK, /* share with PCMCIA */
517 WE3_ICIOWR_MARK, /* share with PCMCIA */
518 CKO_MARK, BS_MARK, RDWR_MARK,
519 RD_FSC_MARK, /* share with FLCTL */
520 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
521 WAIT_PORT90_MARK,
522
523 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
524
525 /* IRDA */
526 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
527
528 /* ATAPI */
529 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
530 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
531 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
532 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
533 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
534 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
535 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
536 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
537
538 /* RMII */
539 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
540 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
541 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
542 RMII_REF50CK_MARK, /* for RMII */
543 RMII_REF125CK_MARK, /* for GMII */
544
545 /* GEther */
546 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
547 ET_ETXD2_MARK, ET_ETXD3_MARK,
548 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
549 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
550 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
551 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
552 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
553 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
554 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
555 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
556
557 /* DMA0 */
558 DREQ0_MARK, DACK0_MARK,
559
560 /* DMA1 */
561 DREQ1_MARK, DACK1_MARK,
562
563 /* SYSC */
564 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
565
566 /* IRREM */
567 IROUT_MARK,
568
569 /* SDENC */
570 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
571
572 /* HDMI */
573 HDMI_HPD_MARK, HDMI_CEC_MARK,
574
575 /* DEBUG */
576 EDEBGREQ_PULLUP_MARK, /* for JTAG */
577 EDEBGREQ_PULLDOWN_MARK,
578
579 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
580 TRACEAUD_FROM_LCDC0_MARK,
581 TRACEAUD_FROM_MEMC_MARK,
582
583 PINMUX_MARK_END,
584};
585
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]586#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
587#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
588
Laurent Pinchart533743d2013-07-15 13:03:20 +0200[diff] [blame^]589static const u16 pinmux_data[] = {
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]590 PINMUX_DATA_GP_ALL(),
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]591
592 /* Port0 */
593 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
594 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
595 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
596 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
597 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
598 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
599 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
600
601 /* Port1 */
602 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
603 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
604 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
605 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
606 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
607 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
608 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
609
610 /* Port2 */
611 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
612 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
613 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
614 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
615 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
616
617 /* Port3 */
618 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
619 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
620 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
621 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
622
623 /* Port4 */
624 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
625 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
626 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
627 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
628
629 /* Port5 */
630 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
631 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
632 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
633 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
634 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
635
636 /* Port6 */
637 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
638 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
639 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
640 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
641 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
642
643 /* Port7 */
644 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
645
646 /* Port8 */
647 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
648
649 /* Port9 */
650 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
651 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
652
653 /* Port10 */
654 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
655 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
656 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
657
658 /* Port11 */
659 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
660 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
661 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
662
663 /* Port12 */
664 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
665 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
666 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
667 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
668 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
669
670 /* Port13 */
671 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
672 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
673 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
674 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
675
676 /* Port14 */
677 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
678 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
679 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
680 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
681 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
682
683 /* Port15 */
684 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
685 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
686 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
687 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
688 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
689
690 /* Port16 */
691 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
692 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
693
694 /* Port17 */
695 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
696 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
697
698 /* Port18 */
699 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
700 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
701
702 /* Port19 */
703 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
704 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
705 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
706
707 /* Port20 */
708 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
709 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
710 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
711
712 /* Port21 */
713 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
714 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
715 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
716 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
717 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
718 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
719
720 /* Port22 */
721 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
722 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
723 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
724
725 /* Port23 */
726 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
727 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
728 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
729 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
730 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
731 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
732
733 /* Port24 */
734 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
735 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
736 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
737 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
738
739 /* Port25 */
740 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
741 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
742 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
743 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
744
745 /* Port26 */
746 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
747 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
748 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
749
750 /* Port27 - Port39 Function */
751 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
752 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
753 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
754 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
755 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
756 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
757 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
758 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
759 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
760 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
761 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
762 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
763 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
764
765 /* Port38 IRQ */
766 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
767
768 /* Port40 */
769 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
770 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
771 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
772
773 /* Port41 */
774 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
775 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
776 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
777
778 /* Port42 */
779 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
780 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
781 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
782
783 /* Port43 */
784 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
785 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
786 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
787 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
788
789 /* Port44 */
790 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
791 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
792 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
793 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
794
795 /* Port45 */
796 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
797 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
798 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
799 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
800
801 /* Port46 */
802 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
803 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
804 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
805
806 /* Port47 */
807 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
808 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
809 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
810
811 /* Port48 */
812 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
813 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
814 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
815
816 /* Port49 */
817 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
818 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
819 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
820 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
821
822 /* Port50 */
823 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
824 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
825 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
826 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
827
828 /* Port51 */
829 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
830 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
831 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
832
833 /* Port52 */
834 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
835 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
836 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
837
838 /* Port53 */
839 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
840 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
841 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
842
843 /* Port54 */
844 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
845 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
846 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
847
848 /* Port55 */
849 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
850 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
851 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
852 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
853
854 /* Port56 */
855 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
856 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
857 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
858 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
859 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
860
861 /* Port57 */
862 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
863 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
864 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
865 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
866 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
867
868 /* Port58 */
Laurent Pinchartb7983902013-04-19 11:52:59 +0200[diff] [blame]869 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]870 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
871 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
872 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
873 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
874
875 /* Port59 */
876 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
877 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
878 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
879
880 /* Port60 */
881 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
882 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
883 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
884
885 /* Port61 */
886 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
887 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
888
889 /* Port62 */
890 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
891 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
892 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
893 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
894
895 /* Port63 */
896 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
897 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
898 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
899
900 /* Port64 */
901 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
902 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
903 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
904 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
905
906 /* Port65 */
907 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
908 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
909 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
910
911 /* Port66 */
912 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
913 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
914 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
915 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
916
917 /* Port67 - Port73 Function1 */
918 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
919 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
920 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
921 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
922 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
923 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
924 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
925
926 /* Port67 - Port73 Function2 */
927 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
928 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
929 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
930 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
931 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
932 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
933 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
934
935 /* Port67 - Port73 Function4 */
936 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
937 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
938 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
939 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
940 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
941 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
942 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
943
944 /* Port67 - Port73 Function6 */
945 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
946 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
947 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
948 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
949 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
950 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
951 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
952
953 /* Port67 - Port71 IRQ */
954 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
955 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
956 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
957 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
958 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
959
960 /* Port74 */
961 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
962 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
963 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
964 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
965 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
966
967 /* Port75 */
968 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
969 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
970 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
971 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
972 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
973
974 /* Port76 - Port80 Function */
975 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
976 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
977 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
978 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
979 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
980
981 /* Port81 */
982 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
983 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
984
985 /* Port82 - Port88 Function */
986 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
987 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
988 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
989 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
990 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
991 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
992 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
993
994 /* Port89 */
995 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
996 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
997 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
998
999 /* Port90 */
1000 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1001 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1002 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1003 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1004
1005 /* Port91 */
1006 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1007 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1008 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1009 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1010
1011 /* Port92 */
1012 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1013 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1014 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1015 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1016 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1017
1018 /* Port93 */
1019 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1020 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1021 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1022 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1023 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1024
1025 /* Port94 */
1026 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1027 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1028 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1029 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1030 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1031
1032 /* Port95 */
1033 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1034 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1035
1036 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1037 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1038 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1039 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1040
1041 /* Port96 */
1042 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1043 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1044
1045 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1046 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1047 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1048 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1049
1050 /* Port97 */
1051 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1052 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1053 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1054 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1055 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1056
1057 /* Port98 */
1058 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1059 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1060 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1061 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1062
1063 /* Port99 */
1064 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1065 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1066 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1067 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1068 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1069
1070 /* Port100 */
1071 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1072 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1073 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1074 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1075
1076 /* Port101 */
1077 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1078
1079 /* Port102 */
1080 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1081 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1082
1083 /* Port103 */
1084 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1085 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1086 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1087
1088 /* Port104 */
1089 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1090 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1091 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1092
1093 /* Port105 */
1094 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1095 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1096
1097 /* Port106 */
1098 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1099 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1100
1101 /* Port107 - Port115 Function */
1102 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1103 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1104 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1105 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1106 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1107 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1108 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1109 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1110 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1111
1112 /* Port116 */
1113 PINMUX_DATA(A25_MARK, PORT116_FN1),
1114 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1115 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1116 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1117 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1118
1119 /* Port117 */
1120 PINMUX_DATA(A24_MARK, PORT117_FN1),
1121 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1122 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1123 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1124 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1125
1126 /* Port118 */
1127 PINMUX_DATA(A23_MARK, PORT118_FN1),
1128 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1129 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1130 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1131 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1132
1133 /* Port119 */
1134 PINMUX_DATA(A22_MARK, PORT119_FN1),
1135 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1136 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1137 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1138 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1139
1140 /* Port120 */
1141 PINMUX_DATA(A21_MARK, PORT120_FN1),
1142 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1143 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1144 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1145
1146 /* Port121 */
1147 PINMUX_DATA(A20_MARK, PORT121_FN1),
1148 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1149 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1150 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1151
1152 /* Port122 */
1153 PINMUX_DATA(A19_MARK, PORT122_FN1),
1154 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1155
1156 /* Port123 */
1157 PINMUX_DATA(A18_MARK, PORT123_FN1),
1158 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1159
1160 /* Port124 */
1161 PINMUX_DATA(A17_MARK, PORT124_FN1),
1162 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1163
1164 /* Port125 - Port141 Function */
1165 PINMUX_DATA(A16_MARK, PORT125_FN1),
1166 PINMUX_DATA(A15_MARK, PORT126_FN1),
1167 PINMUX_DATA(A14_MARK, PORT127_FN1),
1168 PINMUX_DATA(A13_MARK, PORT128_FN1),
1169 PINMUX_DATA(A12_MARK, PORT129_FN1),
1170 PINMUX_DATA(A11_MARK, PORT130_FN1),
1171 PINMUX_DATA(A10_MARK, PORT131_FN1),
1172 PINMUX_DATA(A9_MARK, PORT132_FN1),
1173 PINMUX_DATA(A8_MARK, PORT133_FN1),
1174 PINMUX_DATA(A7_MARK, PORT134_FN1),
1175 PINMUX_DATA(A6_MARK, PORT135_FN1),
1176 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1177 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1178 PINMUX_DATA(A3_MARK, PORT138_FN1),
1179 PINMUX_DATA(A2_MARK, PORT139_FN1),
1180 PINMUX_DATA(A1_MARK, PORT140_FN1),
1181 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1182
1183 /* Port142 - Port157 Function1 */
1184 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1185 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1186 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1187 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1188 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1189 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1190 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1191 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1192 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1193 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1194 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1195 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1196 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1197 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1198 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1199 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1200
1201 /* Port142 - Port149 Function3 */
1202 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1204 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1205 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1206 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1207 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1208 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1209 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1210
1211 /* Port158 */
1212 PINMUX_DATA(D31_MARK, PORT158_FN1),
1213 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1214 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1215 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1216 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1217 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1218
1219 /* Port159 */
1220 PINMUX_DATA(D30_MARK, PORT159_FN1),
1221 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1222 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1223 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1224 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1225
1226 /* Port160 */
1227 PINMUX_DATA(D29_MARK, PORT160_FN1),
1228 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1229 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1230 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1231 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1232
1233 /* Port161 */
1234 PINMUX_DATA(D28_MARK, PORT161_FN1),
1235 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1236 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1237 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1238 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1239 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1240
1241 /* Port162 */
1242 PINMUX_DATA(D27_MARK, PORT162_FN1),
1243 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1244 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1245 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1246 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1247
1248 /* Port163 */
1249 PINMUX_DATA(D26_MARK, PORT163_FN1),
1250 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1251 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1252 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1253 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1254 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1255
1256 /* Port164 */
1257 PINMUX_DATA(D25_MARK, PORT164_FN1),
1258 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1259 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1260 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1261 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1262
1263 /* Port165 */
1264 PINMUX_DATA(D24_MARK, PORT165_FN1),
1265 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1266 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1267 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1268
1269 /* Port166 - Port171 Function1 */
1270 PINMUX_DATA(D21_MARK, PORT166_FN1),
1271 PINMUX_DATA(D20_MARK, PORT167_FN1),
1272 PINMUX_DATA(D19_MARK, PORT168_FN1),
1273 PINMUX_DATA(D18_MARK, PORT169_FN1),
1274 PINMUX_DATA(D17_MARK, PORT170_FN1),
1275 PINMUX_DATA(D16_MARK, PORT171_FN1),
1276
1277 /* Port166 - Port171 Function3 */
1278 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1279 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1280 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1281 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1282 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1283 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1284
1285 /* Port166 - Port171 Function6 */
1286 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1287 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1288 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1289 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1290 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1291 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1292
1293 /* Port167 - Port171 IRQ */
1294 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1295 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1296 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1297 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1298 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1299
1300 /* Port172 */
1301 PINMUX_DATA(D23_MARK, PORT172_FN1),
1302 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1303 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1304 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1305 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1306
1307 /* Port173 */
1308 PINMUX_DATA(D22_MARK, PORT173_FN1),
1309 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1310 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1311 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1312 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1313
1314 /* Port174 */
1315 PINMUX_DATA(A26_MARK, PORT174_FN1),
1316 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1317 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1318 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1319
1320 /* Port175 */
1321 PINMUX_DATA(A0_MARK, PORT175_FN1),
1322 PINMUX_DATA(BS_MARK, PORT175_FN2),
1323 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1324 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1325
1326 /* Port176 */
1327 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1328
1329 /* Port177 */
1330 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1331 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1332 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1333 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1334
1335 /* Port178 */
1336 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1337 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1338 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1339
1340 /* Port179 */
1341 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1342 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1343 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1344
1345 /* Port180 */
1346 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1347 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1348 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1349 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1350 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1351
1352 /* Port181 */
1353 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1354 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1355 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1356
1357 /* Port182 */
1358 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1359 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1360 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1361
1362 /* Port183 */
1363 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1364 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1365 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1366
1367 /* Port184 */
1368 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1369 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1370 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1371
1372 /* Port185 - Port192 Function1 */
1373 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1374 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1375 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1376 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1377 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1378 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1379 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1380
1381 /* Port185 - Port192 Function3 */
1382 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1383 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1384 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1385 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1386 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1387 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1388 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1389 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1390
1391 /* Port185 - Port192 Function6 */
1392 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1393 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1394 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1395 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1396 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1397 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1398 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1399 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1400
1401 /* Port193 */
1402 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1403 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1404 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1405 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1406
1407 /* Port194 */
1408 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1409 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1410 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1411 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1412
1413 /* Port195 */
1414 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1415 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1416 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1417 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1418
1419 /* Port196 */
1420 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1421 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1422 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1423 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1424
1425 /* Port197 */
1426 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1427 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1428 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1429 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1430
1431 /* Port198 */
1432 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1433 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1434 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1435 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1436
1437 /* Port199 */
1438 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1439 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1440 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1441 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1442 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1443 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1444
1445 /* Port200 */
1446 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1447 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1448 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1449 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1450 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1451
1452 /* Port201 */
1453 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1454 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1455
1456 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1457 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1458 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1459 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1460
1461 /* Port202 */
1462 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1463 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1464
1465 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1466 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1467 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1468 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1469 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1470 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1471
1472 /* Port203 - Port208 Function1 */
1473 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1474 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1475 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1476 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1477 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1478 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1479
1480 /* Port203 - Port208 Function3 */
1481 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1482 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1483 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1484 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1485 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1486 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1487
1488 /* Port203 - Port208 Function6 */
1489 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1490 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1491 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1492 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1493 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1494 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1495
1496 /* Port203 - Port208 Function7 */
1497 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1498 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1499 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1500 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1501 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1502 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1503
1504 /* Port209 */
1505 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1506 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1507
1508 /* Port210 */
1509 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1510 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1511
1512 /* Port211 */
1513 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1514 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1515
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1516 /* SDENC */
1517 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1518 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1519
1520 /* SYSC */
1521 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1522 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1523
1524 /* DEBUG */
1525 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1526 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1527
1528 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1529 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1530 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1531};
1532
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]1533#define R8A7740_PIN(pin, cfgs) \
1534 { \
1535 .name = __stringify(PORT##pin), \
1536 .enum_id = PORT##pin##_DATA, \
1537 .configs = cfgs, \
1538 }
1539
1540#define __I (SH_PFC_PIN_CFG_INPUT)
1541#define __O (SH_PFC_PIN_CFG_OUTPUT)
1542#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1543#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1544#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1545#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1546
1547#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD)
1548#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU)
1549#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD)
1550#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO)
1551#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD)
1552#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU)
1553#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD)
1554#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O)
1555#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD)
1556
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1557static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]1558 /* Table 56-1 (I/O and Pull U/D) */
1559 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1560 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1561 R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1562 R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1563 R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1564 R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1565 R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1566 R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1567 R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1568 R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1569 R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1570 R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1571 R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1572 R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1573 R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1574 R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1575 R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1576 R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1577 R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1578 R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1579 R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1580 R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1581 R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1582 R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1583 R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1584 R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1585 R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1586 R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1587 R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1588 R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1589 R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1590 R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1591 R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1592 R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1593 R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1594 R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1595 R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1596 R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1597 R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1598 R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1599 R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1600 R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1601 R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1602 R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1603 R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1604 R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1605 R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1606 R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1607 R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1608 R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1609 R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1610 R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1611 R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1612 R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1613 R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1614 R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1615 R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1616 R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1617 R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1618 R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1619 R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1620 R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1621 R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1622 R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1623 R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1624 R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1625 R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1626 R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1627 R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1628 R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1629 R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1630 R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1631 R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1632 R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1633 R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1634 R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1635 R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1636 R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1637 R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1638 R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1639 R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1640 R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1641 R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1642 R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1643 R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1644 R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1645 R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1646 R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1647 R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1648 R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1649 R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1650 R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1651 R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1652 R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1653 R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1654 R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1655 R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1656 R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1657 R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1658 R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1659 R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1660 R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1661 R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1662 R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1663 R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1664 R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1665};
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1666
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]1667/* - BSC -------------------------------------------------------------------- */
1668static const unsigned int bsc_data8_pins[] = {
1669 /* D[0:7] */
1670 157, 156, 155, 154, 153, 152, 151, 150,
1671};
1672static const unsigned int bsc_data8_mux[] = {
1673 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1674 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1675};
1676static const unsigned int bsc_data16_pins[] = {
1677 /* D[0:15] */
1678 157, 156, 155, 154, 153, 152, 151, 150,
1679 149, 148, 147, 146, 145, 144, 143, 142,
1680};
1681static const unsigned int bsc_data16_mux[] = {
1682 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1683 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1684 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1685 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1686};
1687static const unsigned int bsc_data32_pins[] = {
1688 /* D[0:31] */
1689 157, 156, 155, 154, 153, 152, 151, 150,
1690 149, 148, 147, 146, 145, 144, 143, 142,
1691 171, 170, 169, 168, 167, 166, 173, 172,
1692 165, 164, 163, 162, 161, 160, 159, 158,
1693};
1694static const unsigned int bsc_data32_mux[] = {
1695 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1696 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1697 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1698 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1699 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1700 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1701 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1702 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1703};
1704static const unsigned int bsc_cs0_pins[] = {
1705 /* CS */
1706 109,
1707};
1708static const unsigned int bsc_cs0_mux[] = {
1709 CS0_MARK,
1710};
1711static const unsigned int bsc_cs2_pins[] = {
1712 /* CS */
1713 110,
1714};
1715static const unsigned int bsc_cs2_mux[] = {
1716 CS2_MARK,
1717};
1718static const unsigned int bsc_cs4_pins[] = {
1719 /* CS */
1720 111,
1721};
1722static const unsigned int bsc_cs4_mux[] = {
1723 CS4_MARK,
1724};
1725static const unsigned int bsc_cs5a_0_pins[] = {
1726 /* CS */
1727 105,
1728};
1729static const unsigned int bsc_cs5a_0_mux[] = {
1730 CS5A_PORT105_MARK,
1731};
1732static const unsigned int bsc_cs5a_1_pins[] = {
1733 /* CS */
1734 19,
1735};
1736static const unsigned int bsc_cs5a_1_mux[] = {
1737 CS5A_PORT19_MARK,
1738};
1739static const unsigned int bsc_cs5b_pins[] = {
1740 /* CS */
1741 103,
1742};
1743static const unsigned int bsc_cs5b_mux[] = {
1744 CS5B_MARK,
1745};
1746static const unsigned int bsc_cs6a_pins[] = {
1747 /* CS */
1748 104,
1749};
1750static const unsigned int bsc_cs6a_mux[] = {
1751 CS6A_MARK,
1752};
1753static const unsigned int bsc_rd_we8_pins[] = {
1754 /* RD, WE[0] */
1755 115, 113,
1756};
1757static const unsigned int bsc_rd_we8_mux[] = {
1758 RD_FSC_MARK, WE0_FWE_MARK,
1759};
1760static const unsigned int bsc_rd_we16_pins[] = {
1761 /* RD, WE[0:1] */
1762 115, 113, 112,
1763};
1764static const unsigned int bsc_rd_we16_mux[] = {
1765 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1766};
1767static const unsigned int bsc_rd_we32_pins[] = {
1768 /* RD, WE[0:3] */
1769 115, 113, 112, 108, 107,
1770};
1771static const unsigned int bsc_rd_we32_mux[] = {
1772 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1773};
1774static const unsigned int bsc_bs_pins[] = {
1775 /* BS */
1776 175,
1777};
1778static const unsigned int bsc_bs_mux[] = {
1779 BS_MARK,
1780};
1781static const unsigned int bsc_rdwr_pins[] = {
1782 /* RDWR */
1783 114,
1784};
1785static const unsigned int bsc_rdwr_mux[] = {
1786 RDWR_MARK,
1787};
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]1788/* - CEU0 ------------------------------------------------------------------- */
1789static const unsigned int ceu0_data_0_7_pins[] = {
1790 /* D[0:7] */
1791 34, 33, 32, 31, 30, 29, 28, 27,
1792};
1793static const unsigned int ceu0_data_0_7_mux[] = {
1794 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1795 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1796};
1797static const unsigned int ceu0_data_8_15_0_pins[] = {
1798 /* D[8:15] */
1799 182, 181, 180, 179, 178, 26, 25, 24,
1800};
1801static const unsigned int ceu0_data_8_15_0_mux[] = {
1802 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1803 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1804 VIO0_D15_PORT24_MARK,
1805};
1806static const unsigned int ceu0_data_8_15_1_pins[] = {
1807 /* D[8:15] */
1808 182, 181, 180, 179, 178, 22, 95, 96,
1809};
1810static const unsigned int ceu0_data_8_15_1_mux[] = {
1811 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1812 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1813 VIO0_D15_PORT96_MARK,
1814};
1815static const unsigned int ceu0_clk_0_pins[] = {
1816 /* CKO */
1817 36,
1818};
1819static const unsigned int ceu0_clk_0_mux[] = {
1820 VIO_CKO_MARK,
1821};
1822static const unsigned int ceu0_clk_1_pins[] = {
1823 /* CKO */
1824 14,
1825};
1826static const unsigned int ceu0_clk_1_mux[] = {
1827 VIO_CKO1_MARK,
1828};
1829static const unsigned int ceu0_clk_2_pins[] = {
1830 /* CKO */
1831 15,
1832};
1833static const unsigned int ceu0_clk_2_mux[] = {
1834 VIO_CKO2_MARK,
1835};
1836static const unsigned int ceu0_sync_pins[] = {
1837 /* CLK, VD, HD */
1838 35, 39, 37,
1839};
1840static const unsigned int ceu0_sync_mux[] = {
1841 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1842};
1843static const unsigned int ceu0_field_pins[] = {
1844 /* FIELD */
1845 38,
1846};
1847static const unsigned int ceu0_field_mux[] = {
1848 VIO0_FIELD_MARK,
1849};
1850/* - CEU1 ------------------------------------------------------------------- */
1851static const unsigned int ceu1_data_pins[] = {
1852 /* D[0:7] */
1853 182, 181, 180, 179, 178, 26, 25, 24,
1854};
1855static const unsigned int ceu1_data_mux[] = {
1856 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1857 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1858};
1859static const unsigned int ceu1_clk_pins[] = {
1860 /* CKO */
1861 23,
1862};
1863static const unsigned int ceu1_clk_mux[] = {
1864 VIO_CKO_1_MARK,
1865};
1866static const unsigned int ceu1_sync_pins[] = {
1867 /* CLK, VD, HD */
1868 197, 198, 160,
1869};
1870static const unsigned int ceu1_sync_mux[] = {
1871 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1872};
1873static const unsigned int ceu1_field_pins[] = {
1874 /* FIELD */
1875 21,
1876};
1877static const unsigned int ceu1_field_mux[] = {
1878 VIO1_FIELD_MARK,
1879};
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]1880/* - FSIA ------------------------------------------------------------------- */
1881static const unsigned int fsia_mclk_in_pins[] = {
1882 /* CK */
1883 11,
1884};
1885static const unsigned int fsia_mclk_in_mux[] = {
1886 FSIACK_MARK,
1887};
1888static const unsigned int fsia_mclk_out_pins[] = {
1889 /* OMC */
1890 10,
1891};
1892static const unsigned int fsia_mclk_out_mux[] = {
1893 FSIAOMC_MARK,
1894};
1895static const unsigned int fsia_sclk_in_pins[] = {
1896 /* ILR, IBT */
1897 12, 13,
1898};
1899static const unsigned int fsia_sclk_in_mux[] = {
1900 FSIAILR_MARK, FSIAIBT_MARK,
1901};
1902static const unsigned int fsia_sclk_out_pins[] = {
1903 /* OLR, OBT */
1904 7, 8,
1905};
1906static const unsigned int fsia_sclk_out_mux[] = {
1907 FSIAOLR_MARK, FSIAOBT_MARK,
1908};
1909static const unsigned int fsia_data_in_0_pins[] = {
1910 /* ISLD */
1911 0,
1912};
1913static const unsigned int fsia_data_in_0_mux[] = {
1914 FSIAISLD_PORT0_MARK,
1915};
1916static const unsigned int fsia_data_in_1_pins[] = {
1917 /* ISLD */
1918 5,
1919};
1920static const unsigned int fsia_data_in_1_mux[] = {
1921 FSIAISLD_PORT5_MARK,
1922};
1923static const unsigned int fsia_data_out_0_pins[] = {
1924 /* OSLD */
1925 9,
1926};
1927static const unsigned int fsia_data_out_0_mux[] = {
1928 FSIAOSLD_MARK,
1929};
1930static const unsigned int fsia_data_out_1_pins[] = {
1931 /* OSLD */
1932 0,
1933};
1934static const unsigned int fsia_data_out_1_mux[] = {
1935 FSIAOSLD1_MARK,
1936};
1937static const unsigned int fsia_data_out_2_pins[] = {
1938 /* OSLD */
1939 1,
1940};
1941static const unsigned int fsia_data_out_2_mux[] = {
1942 FSIAOSLD2_MARK,
1943};
1944static const unsigned int fsia_spdif_0_pins[] = {
1945 /* SPDIF */
1946 9,
1947};
1948static const unsigned int fsia_spdif_0_mux[] = {
1949 FSIASPDIF_PORT9_MARK,
1950};
1951static const unsigned int fsia_spdif_1_pins[] = {
1952 /* SPDIF */
1953 18,
1954};
1955static const unsigned int fsia_spdif_1_mux[] = {
1956 FSIASPDIF_PORT18_MARK,
1957};
1958/* - FSIB ------------------------------------------------------------------- */
1959static const unsigned int fsib_mclk_in_pins[] = {
1960 /* CK */
1961 11,
1962};
1963static const unsigned int fsib_mclk_in_mux[] = {
1964 FSIBCK_MARK,
1965};
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]1966/* - GETHER ----------------------------------------------------------------- */
1967static const unsigned int gether_rmii_pins[] = {
1968 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1969 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1970};
1971static const unsigned int gether_rmii_mux[] = {
1972 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1973 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1974 RMII_MDC_MARK, RMII_MDIO_MARK,
1975};
1976static const unsigned int gether_mii_pins[] = {
1977 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1978 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1979 * CRS, COL, MDC, MDIO,
1980 */
1981 185, 186, 187, 188, 174, 161, 204,
1982 171, 170, 169, 168, 184, 183, 203,
1983 205, 163, 206, 207,
1984};
1985static const unsigned int gether_mii_mux[] = {
1986 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1987 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1988 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1989 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1990 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1991};
1992static const unsigned int gether_gmii_pins[] = {
1993 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
1994 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1995 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1996 */
1997 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1998 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1999 205, 163, 206, 207,
2000};
2001static const unsigned int gether_gmii_mux[] = {
2002 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
2003 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
2004 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
2005 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
2006 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
2007 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
2008 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2009 RMII_REF125CK_MARK,
2010};
2011static const unsigned int gether_int_pins[] = {
2012 /* PHY_INT */
2013 164,
2014};
2015static const unsigned int gether_int_mux[] = {
2016 ET_PHY_INT_MARK,
2017};
2018static const unsigned int gether_link_pins[] = {
2019 /* LINK */
2020 177,
2021};
2022static const unsigned int gether_link_mux[] = {
2023 ET_LINK_MARK,
2024};
2025static const unsigned int gether_wol_pins[] = {
2026 /* WOL */
2027 175,
2028};
2029static const unsigned int gether_wol_mux[] = {
2030 ET_WOL_MARK,
2031};
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2032/* - HDMI ------------------------------------------------------------------- */
2033static const unsigned int hdmi_pins[] = {
2034 /* HPD, CEC */
2035 210, 211,
2036};
2037static const unsigned int hdmi_mux[] = {
2038 HDMI_HPD_MARK, HDMI_CEC_MARK,
2039};
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2040/* - INTC ------------------------------------------------------------------- */
2041IRQC_PINS_MUX(0, 0, 2);
2042IRQC_PINS_MUX(0, 1, 13);
2043IRQC_PIN_MUX(1, 20);
2044IRQC_PINS_MUX(2, 0, 11);
2045IRQC_PINS_MUX(2, 1, 12);
2046IRQC_PINS_MUX(3, 0, 10);
2047IRQC_PINS_MUX(3, 1, 14);
2048IRQC_PINS_MUX(4, 0, 15);
2049IRQC_PINS_MUX(4, 1, 172);
2050IRQC_PINS_MUX(5, 0, 0);
2051IRQC_PINS_MUX(5, 1, 1);
2052IRQC_PINS_MUX(6, 0, 121);
2053IRQC_PINS_MUX(6, 1, 173);
2054IRQC_PINS_MUX(7, 0, 120);
2055IRQC_PINS_MUX(7, 1, 209);
2056IRQC_PIN_MUX(8, 119);
2057IRQC_PINS_MUX(9, 0, 118);
2058IRQC_PINS_MUX(9, 1, 210);
2059IRQC_PIN_MUX(10, 19);
2060IRQC_PIN_MUX(11, 104);
2061IRQC_PINS_MUX(12, 0, 42);
2062IRQC_PINS_MUX(12, 1, 97);
2063IRQC_PINS_MUX(13, 0, 64);
2064IRQC_PINS_MUX(13, 1, 98);
2065IRQC_PINS_MUX(14, 0, 63);
2066IRQC_PINS_MUX(14, 1, 99);
2067IRQC_PINS_MUX(15, 0, 62);
2068IRQC_PINS_MUX(15, 1, 100);
2069IRQC_PINS_MUX(16, 0, 68);
2070IRQC_PINS_MUX(16, 1, 211);
2071IRQC_PIN_MUX(17, 69);
2072IRQC_PIN_MUX(18, 70);
2073IRQC_PIN_MUX(19, 71);
2074IRQC_PIN_MUX(20, 67);
2075IRQC_PIN_MUX(21, 202);
2076IRQC_PIN_MUX(22, 95);
2077IRQC_PIN_MUX(23, 96);
2078IRQC_PIN_MUX(24, 180);
2079IRQC_PIN_MUX(25, 38);
2080IRQC_PINS_MUX(26, 0, 58);
2081IRQC_PINS_MUX(26, 1, 81);
2082IRQC_PINS_MUX(27, 0, 57);
2083IRQC_PINS_MUX(27, 1, 168);
2084IRQC_PINS_MUX(28, 0, 56);
2085IRQC_PINS_MUX(28, 1, 169);
2086IRQC_PINS_MUX(29, 0, 50);
2087IRQC_PINS_MUX(29, 1, 170);
2088IRQC_PINS_MUX(30, 0, 49);
2089IRQC_PINS_MUX(30, 1, 171);
2090IRQC_PINS_MUX(31, 0, 41);
2091IRQC_PINS_MUX(31, 1, 167);
2092
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2093/* - LCD0 ------------------------------------------------------------------- */
2094static const unsigned int lcd0_data8_pins[] = {
2095 /* D[0:7] */
2096 58, 57, 56, 55, 54, 53, 52, 51,
2097};
2098static const unsigned int lcd0_data8_mux[] = {
2099 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2100 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2101};
2102static const unsigned int lcd0_data9_pins[] = {
2103 /* D[0:8] */
2104 58, 57, 56, 55, 54, 53, 52, 51,
2105 50,
2106};
2107static const unsigned int lcd0_data9_mux[] = {
2108 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2109 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2110 LCD0_D8_MARK,
2111};
2112static const unsigned int lcd0_data12_pins[] = {
2113 /* D[0:11] */
2114 58, 57, 56, 55, 54, 53, 52, 51,
2115 50, 49, 48, 47,
2116};
2117static const unsigned int lcd0_data12_mux[] = {
2118 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2119 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2120 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2121};
2122static const unsigned int lcd0_data16_pins[] = {
2123 /* D[0:15] */
2124 58, 57, 56, 55, 54, 53, 52, 51,
2125 50, 49, 48, 47, 46, 45, 44, 43,
2126};
2127static const unsigned int lcd0_data16_mux[] = {
2128 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2129 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2130 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2131 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2132};
2133static const unsigned int lcd0_data18_pins[] = {
2134 /* D[0:17] */
2135 58, 57, 56, 55, 54, 53, 52, 51,
2136 50, 49, 48, 47, 46, 45, 44, 43,
2137 42, 41,
2138};
2139static const unsigned int lcd0_data18_mux[] = {
2140 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2141 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2142 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2143 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2144 LCD0_D16_MARK, LCD0_D17_MARK,
2145};
2146static const unsigned int lcd0_data24_0_pins[] = {
2147 /* D[0:23] */
2148 58, 57, 56, 55, 54, 53, 52, 51,
2149 50, 49, 48, 47, 46, 45, 44, 43,
2150 42, 41, 40, 4, 3, 2, 0, 1,
2151};
2152static const unsigned int lcd0_data24_0_mux[] = {
2153 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2154 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2155 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2156 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2157 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2158 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2159 LCD0_D23_PORT1_MARK,
2160};
2161static const unsigned int lcd0_data24_1_pins[] = {
2162 /* D[0:23] */
2163 58, 57, 56, 55, 54, 53, 52, 51,
2164 50, 49, 48, 47, 46, 45, 44, 43,
2165 42, 41, 163, 162, 161, 158, 160, 159,
2166};
2167static const unsigned int lcd0_data24_1_mux[] = {
2168 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2169 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2170 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2171 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2172 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2173 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2174};
2175static const unsigned int lcd0_display_pins[] = {
2176 /* DON, VCPWC, VEPWC */
2177 61, 59, 60,
2178};
2179static const unsigned int lcd0_display_mux[] = {
2180 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2181};
2182static const unsigned int lcd0_lclk_0_pins[] = {
2183 /* LCLK */
2184 102,
2185};
2186static const unsigned int lcd0_lclk_0_mux[] = {
2187 LCD0_LCLK_PORT102_MARK,
2188};
2189static const unsigned int lcd0_lclk_1_pins[] = {
2190 /* LCLK */
2191 165,
2192};
2193static const unsigned int lcd0_lclk_1_mux[] = {
2194 LCD0_LCLK_PORT165_MARK,
2195};
2196static const unsigned int lcd0_sync_pins[] = {
2197 /* VSYN, HSYN, DCK, DISP */
2198 63, 64, 62, 65,
2199};
2200static const unsigned int lcd0_sync_mux[] = {
2201 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2202};
2203static const unsigned int lcd0_sys_pins[] = {
2204 /* CS, WR, RD, RS */
2205 64, 62, 164, 65,
2206};
2207static const unsigned int lcd0_sys_mux[] = {
2208 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2209};
2210/* - LCD1 ------------------------------------------------------------------- */
2211static const unsigned int lcd1_data8_pins[] = {
2212 /* D[0:7] */
2213 4, 3, 2, 1, 0, 91, 92, 23,
2214};
2215static const unsigned int lcd1_data8_mux[] = {
2216 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2217 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2218};
2219static const unsigned int lcd1_data9_pins[] = {
2220 /* D[0:8] */
2221 4, 3, 2, 1, 0, 91, 92, 23,
2222 93,
2223};
2224static const unsigned int lcd1_data9_mux[] = {
2225 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2226 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2227 LCD1_D8_MARK,
2228};
2229static const unsigned int lcd1_data12_pins[] = {
2230 /* D[0:12] */
2231 4, 3, 2, 1, 0, 91, 92, 23,
2232 93, 94, 21, 201,
2233};
2234static const unsigned int lcd1_data12_mux[] = {
2235 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2236 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2237 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2238};
2239static const unsigned int lcd1_data16_pins[] = {
2240 /* D[0:15] */
2241 4, 3, 2, 1, 0, 91, 92, 23,
2242 93, 94, 21, 201, 200, 199, 196, 195,
2243};
2244static const unsigned int lcd1_data16_mux[] = {
2245 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2246 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2247 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2248 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2249};
2250static const unsigned int lcd1_data18_pins[] = {
2251 /* D[0:17] */
2252 4, 3, 2, 1, 0, 91, 92, 23,
2253 93, 94, 21, 201, 200, 199, 196, 195,
2254 194, 193,
2255};
2256static const unsigned int lcd1_data18_mux[] = {
2257 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2258 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2259 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2260 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2261 LCD1_D16_MARK, LCD1_D17_MARK,
2262};
2263static const unsigned int lcd1_data24_pins[] = {
2264 /* D[0:23] */
2265 4, 3, 2, 1, 0, 91, 92, 23,
2266 93, 94, 21, 201, 200, 199, 196, 195,
2267 194, 193, 198, 197, 75, 74, 15, 14,
2268};
2269static const unsigned int lcd1_data24_mux[] = {
2270 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2271 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2272 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2273 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2274 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2275 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2276};
2277static const unsigned int lcd1_display_pins[] = {
2278 /* DON, VCPWC, VEPWC */
2279 100, 5, 6,
2280};
2281static const unsigned int lcd1_display_mux[] = {
2282 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2283};
2284static const unsigned int lcd1_lclk_pins[] = {
2285 /* LCLK */
2286 40,
2287};
2288static const unsigned int lcd1_lclk_mux[] = {
2289 LCD1_LCLK_MARK,
2290};
2291static const unsigned int lcd1_sync_pins[] = {
2292 /* VSYN, HSYN, DCK, DISP */
2293 98, 97, 99, 12,
2294};
2295static const unsigned int lcd1_sync_mux[] = {
2296 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2297};
2298static const unsigned int lcd1_sys_pins[] = {
2299 /* CS, WR, RD, RS */
2300 97, 99, 13, 12,
2301};
2302static const unsigned int lcd1_sys_mux[] = {
2303 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2304};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2305/* - MMCIF ------------------------------------------------------------------ */
2306static const unsigned int mmc0_data1_0_pins[] = {
2307 /* D[0] */
2308 68,
2309};
2310static const unsigned int mmc0_data1_0_mux[] = {
2311 MMC0_D0_PORT68_MARK,
2312};
2313static const unsigned int mmc0_data4_0_pins[] = {
2314 /* D[0:3] */
2315 68, 69, 70, 71,
2316};
2317static const unsigned int mmc0_data4_0_mux[] = {
2318 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2319};
2320static const unsigned int mmc0_data8_0_pins[] = {
2321 /* D[0:7] */
2322 68, 69, 70, 71, 72, 73, 74, 75,
2323};
2324static const unsigned int mmc0_data8_0_mux[] = {
2325 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2326 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2327};
2328static const unsigned int mmc0_ctrl_0_pins[] = {
2329 /* CMD, CLK */
2330 67, 66,
2331};
2332static const unsigned int mmc0_ctrl_0_mux[] = {
2333 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2334};
2335
2336static const unsigned int mmc0_data1_1_pins[] = {
2337 /* D[0] */
2338 149,
2339};
2340static const unsigned int mmc0_data1_1_mux[] = {
2341 MMC1_D0_PORT149_MARK,
2342};
2343static const unsigned int mmc0_data4_1_pins[] = {
2344 /* D[0:3] */
2345 149, 148, 147, 146,
2346};
2347static const unsigned int mmc0_data4_1_mux[] = {
2348 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2349};
2350static const unsigned int mmc0_data8_1_pins[] = {
2351 /* D[0:7] */
2352 149, 148, 147, 146, 145, 144, 143, 142,
2353};
2354static const unsigned int mmc0_data8_1_mux[] = {
2355 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2356 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2357};
2358static const unsigned int mmc0_ctrl_1_pins[] = {
2359 /* CMD, CLK */
2360 104, 103,
2361};
2362static const unsigned int mmc0_ctrl_1_mux[] = {
2363 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2364};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2365/* - SCIFA0 ----------------------------------------------------------------- */
2366static const unsigned int scifa0_data_pins[] = {
2367 /* RXD, TXD */
2368 197, 198,
2369};
2370static const unsigned int scifa0_data_mux[] = {
2371 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2372};
2373static const unsigned int scifa0_clk_pins[] = {
2374 /* SCK */
2375 188,
2376};
2377static const unsigned int scifa0_clk_mux[] = {
2378 SCIFA0_SCK_MARK,
2379};
2380static const unsigned int scifa0_ctrl_pins[] = {
2381 /* RTS, CTS */
2382 194, 193,
2383};
2384static const unsigned int scifa0_ctrl_mux[] = {
2385 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2386};
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2387/* - SCIFA1 ----------------------------------------------------------------- */
2388static const unsigned int scifa1_data_pins[] = {
2389 /* RXD, TXD */
2390 195, 196,
2391};
2392static const unsigned int scifa1_data_mux[] = {
2393 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2394};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2395static const unsigned int scifa1_clk_pins[] = {
2396 /* SCK */
2397 185,
2398};
2399static const unsigned int scifa1_clk_mux[] = {
2400 SCIFA1_SCK_MARK,
2401};
2402static const unsigned int scifa1_ctrl_pins[] = {
2403 /* RTS, CTS */
2404 23, 21,
2405};
2406static const unsigned int scifa1_ctrl_mux[] = {
2407 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2408};
2409/* - SCIFA2 ----------------------------------------------------------------- */
2410static const unsigned int scifa2_data_pins[] = {
2411 /* RXD, TXD */
2412 200, 201,
2413};
2414static const unsigned int scifa2_data_mux[] = {
2415 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2416};
2417static const unsigned int scifa2_clk_0_pins[] = {
2418 /* SCK */
2419 22,
2420};
2421static const unsigned int scifa2_clk_0_mux[] = {
2422 SCIFA2_SCK_PORT22_MARK,
2423};
2424static const unsigned int scifa2_clk_1_pins[] = {
2425 /* SCK */
2426 199,
2427};
2428static const unsigned int scifa2_clk_1_mux[] = {
2429 SCIFA2_SCK_PORT199_MARK,
2430};
2431static const unsigned int scifa2_ctrl_pins[] = {
2432 /* RTS, CTS */
2433 96, 95,
2434};
2435static const unsigned int scifa2_ctrl_mux[] = {
2436 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2437};
2438/* - SCIFA3 ----------------------------------------------------------------- */
2439static const unsigned int scifa3_data_0_pins[] = {
2440 /* RXD, TXD */
2441 174, 175,
2442};
2443static const unsigned int scifa3_data_0_mux[] = {
2444 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2445};
2446static const unsigned int scifa3_clk_0_pins[] = {
2447 /* SCK */
2448 116,
2449};
2450static const unsigned int scifa3_clk_0_mux[] = {
2451 SCIFA3_SCK_PORT116_MARK,
2452};
2453static const unsigned int scifa3_ctrl_0_pins[] = {
2454 /* RTS, CTS */
2455 105, 117,
2456};
2457static const unsigned int scifa3_ctrl_0_mux[] = {
2458 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2459};
2460static const unsigned int scifa3_data_1_pins[] = {
2461 /* RXD, TXD */
2462 159, 160,
2463};
2464static const unsigned int scifa3_data_1_mux[] = {
2465 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2466};
2467static const unsigned int scifa3_clk_1_pins[] = {
2468 /* SCK */
2469 158,
2470};
2471static const unsigned int scifa3_clk_1_mux[] = {
2472 SCIFA3_SCK_PORT158_MARK,
2473};
2474static const unsigned int scifa3_ctrl_1_pins[] = {
2475 /* RTS, CTS */
2476 161, 162,
2477};
2478static const unsigned int scifa3_ctrl_1_mux[] = {
2479 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2480};
2481/* - SCIFA4 ----------------------------------------------------------------- */
2482static const unsigned int scifa4_data_0_pins[] = {
2483 /* RXD, TXD */
2484 12, 13,
2485};
2486static const unsigned int scifa4_data_0_mux[] = {
2487 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2488};
2489static const unsigned int scifa4_data_1_pins[] = {
2490 /* RXD, TXD */
2491 204, 203,
2492};
2493static const unsigned int scifa4_data_1_mux[] = {
2494 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2495};
2496static const unsigned int scifa4_data_2_pins[] = {
2497 /* RXD, TXD */
2498 94, 93,
2499};
2500static const unsigned int scifa4_data_2_mux[] = {
2501 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2502};
2503static const unsigned int scifa4_clk_0_pins[] = {
2504 /* SCK */
2505 21,
2506};
2507static const unsigned int scifa4_clk_0_mux[] = {
2508 SCIFA4_SCK_PORT21_MARK,
2509};
2510static const unsigned int scifa4_clk_1_pins[] = {
2511 /* SCK */
2512 205,
2513};
2514static const unsigned int scifa4_clk_1_mux[] = {
2515 SCIFA4_SCK_PORT205_MARK,
2516};
2517/* - SCIFA5 ----------------------------------------------------------------- */
2518static const unsigned int scifa5_data_0_pins[] = {
2519 /* RXD, TXD */
2520 10, 20,
2521};
2522static const unsigned int scifa5_data_0_mux[] = {
2523 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2524};
2525static const unsigned int scifa5_data_1_pins[] = {
2526 /* RXD, TXD */
2527 207, 208,
2528};
2529static const unsigned int scifa5_data_1_mux[] = {
2530 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2531};
2532static const unsigned int scifa5_data_2_pins[] = {
2533 /* RXD, TXD */
2534 92, 91,
2535};
2536static const unsigned int scifa5_data_2_mux[] = {
2537 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2538};
2539static const unsigned int scifa5_clk_0_pins[] = {
2540 /* SCK */
2541 23,
2542};
2543static const unsigned int scifa5_clk_0_mux[] = {
2544 SCIFA5_SCK_PORT23_MARK,
2545};
2546static const unsigned int scifa5_clk_1_pins[] = {
2547 /* SCK */
2548 206,
2549};
2550static const unsigned int scifa5_clk_1_mux[] = {
2551 SCIFA5_SCK_PORT206_MARK,
2552};
2553/* - SCIFA6 ----------------------------------------------------------------- */
2554static const unsigned int scifa6_data_pins[] = {
2555 /* RXD, TXD */
2556 25, 26,
2557};
2558static const unsigned int scifa6_data_mux[] = {
2559 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2560};
2561static const unsigned int scifa6_clk_pins[] = {
2562 /* SCK */
2563 24,
2564};
2565static const unsigned int scifa6_clk_mux[] = {
2566 SCIFA6_SCK_MARK,
2567};
2568/* - SCIFA7 ----------------------------------------------------------------- */
2569static const unsigned int scifa7_data_pins[] = {
2570 /* RXD, TXD */
2571 0, 1,
2572};
2573static const unsigned int scifa7_data_mux[] = {
2574 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2575};
2576/* - SCIFB ------------------------------------------------------------------ */
2577static const unsigned int scifb_data_0_pins[] = {
2578 /* RXD, TXD */
2579 191, 192,
2580};
2581static const unsigned int scifb_data_0_mux[] = {
2582 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2583};
2584static const unsigned int scifb_clk_0_pins[] = {
2585 /* SCK */
2586 190,
2587};
2588static const unsigned int scifb_clk_0_mux[] = {
2589 SCIFB_SCK_PORT190_MARK,
2590};
2591static const unsigned int scifb_ctrl_0_pins[] = {
2592 /* RTS, CTS */
2593 186, 187,
2594};
2595static const unsigned int scifb_ctrl_0_mux[] = {
2596 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2597};
2598static const unsigned int scifb_data_1_pins[] = {
2599 /* RXD, TXD */
2600 3, 4,
2601};
2602static const unsigned int scifb_data_1_mux[] = {
2603 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2604};
2605static const unsigned int scifb_clk_1_pins[] = {
2606 /* SCK */
2607 2,
2608};
2609static const unsigned int scifb_clk_1_mux[] = {
2610 SCIFB_SCK_PORT2_MARK,
2611};
2612static const unsigned int scifb_ctrl_1_pins[] = {
2613 /* RTS, CTS */
2614 172, 173,
2615};
2616static const unsigned int scifb_ctrl_1_mux[] = {
2617 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2618};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2619/* - SDHI0 ------------------------------------------------------------------ */
2620static const unsigned int sdhi0_data1_pins[] = {
2621 /* D0 */
2622 77,
2623};
2624static const unsigned int sdhi0_data1_mux[] = {
2625 SDHI0_D0_MARK,
2626};
2627static const unsigned int sdhi0_data4_pins[] = {
2628 /* D[0:3] */
2629 77, 78, 79, 80,
2630};
2631static const unsigned int sdhi0_data4_mux[] = {
2632 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2633};
2634static const unsigned int sdhi0_ctrl_pins[] = {
2635 /* CMD, CLK */
2636 76, 82,
2637};
2638static const unsigned int sdhi0_ctrl_mux[] = {
2639 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2640};
2641static const unsigned int sdhi0_cd_pins[] = {
2642 /* CD */
2643 81,
2644};
2645static const unsigned int sdhi0_cd_mux[] = {
2646 SDHI0_CD_MARK,
2647};
2648static const unsigned int sdhi0_wp_pins[] = {
2649 /* WP */
2650 83,
2651};
2652static const unsigned int sdhi0_wp_mux[] = {
2653 SDHI0_WP_MARK,
2654};
2655/* - SDHI1 ------------------------------------------------------------------ */
2656static const unsigned int sdhi1_data1_pins[] = {
2657 /* D0 */
2658 68,
2659};
2660static const unsigned int sdhi1_data1_mux[] = {
2661 SDHI1_D0_MARK,
2662};
2663static const unsigned int sdhi1_data4_pins[] = {
2664 /* D[0:3] */
2665 68, 69, 70, 71,
2666};
2667static const unsigned int sdhi1_data4_mux[] = {
2668 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2669};
2670static const unsigned int sdhi1_ctrl_pins[] = {
2671 /* CMD, CLK */
2672 67, 66,
2673};
2674static const unsigned int sdhi1_ctrl_mux[] = {
2675 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2676};
2677static const unsigned int sdhi1_cd_pins[] = {
2678 /* CD */
2679 72,
2680};
2681static const unsigned int sdhi1_cd_mux[] = {
2682 SDHI1_CD_MARK,
2683};
2684static const unsigned int sdhi1_wp_pins[] = {
2685 /* WP */
2686 73,
2687};
2688static const unsigned int sdhi1_wp_mux[] = {
2689 SDHI1_WP_MARK,
2690};
2691/* - SDHI2 ------------------------------------------------------------------ */
2692static const unsigned int sdhi2_data1_pins[] = {
2693 /* D0 */
2694 205,
2695};
2696static const unsigned int sdhi2_data1_mux[] = {
2697 SDHI2_D0_MARK,
2698};
2699static const unsigned int sdhi2_data4_pins[] = {
2700 /* D[0:3] */
2701 205, 206, 207, 208,
2702};
2703static const unsigned int sdhi2_data4_mux[] = {
2704 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2705};
2706static const unsigned int sdhi2_ctrl_pins[] = {
2707 /* CMD, CLK */
2708 204, 203,
2709};
2710static const unsigned int sdhi2_ctrl_mux[] = {
2711 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2712};
2713static const unsigned int sdhi2_cd_0_pins[] = {
2714 /* CD */
2715 202,
2716};
2717static const unsigned int sdhi2_cd_0_mux[] = {
2718 SDHI2_CD_PORT202_MARK,
2719};
2720static const unsigned int sdhi2_wp_0_pins[] = {
2721 /* WP */
2722 177,
2723};
2724static const unsigned int sdhi2_wp_0_mux[] = {
2725 SDHI2_WP_PORT177_MARK,
2726};
2727static const unsigned int sdhi2_cd_1_pins[] = {
2728 /* CD */
2729 24,
2730};
2731static const unsigned int sdhi2_cd_1_mux[] = {
2732 SDHI2_CD_PORT24_MARK,
2733};
2734static const unsigned int sdhi2_wp_1_pins[] = {
2735 /* WP */
2736 25,
2737};
2738static const unsigned int sdhi2_wp_1_mux[] = {
2739 SDHI2_WP_PORT25_MARK,
2740};
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]2741/* - TPU0 ------------------------------------------------------------------- */
2742static const unsigned int tpu0_to0_pins[] = {
2743 /* TO */
2744 23,
2745};
2746static const unsigned int tpu0_to0_mux[] = {
2747 TPU0TO0_MARK,
2748};
2749static const unsigned int tpu0_to1_pins[] = {
2750 /* TO */
2751 21,
2752};
2753static const unsigned int tpu0_to1_mux[] = {
2754 TPU0TO1_MARK,
2755};
2756static const unsigned int tpu0_to2_0_pins[] = {
2757 /* TO */
2758 66,
2759};
2760static const unsigned int tpu0_to2_0_mux[] = {
2761 TPU0TO2_PORT66_MARK,
2762};
2763static const unsigned int tpu0_to2_1_pins[] = {
2764 /* TO */
2765 202,
2766};
2767static const unsigned int tpu0_to2_1_mux[] = {
2768 TPU0TO2_PORT202_MARK,
2769};
2770static const unsigned int tpu0_to3_pins[] = {
2771 /* TO */
2772 180,
2773};
2774static const unsigned int tpu0_to3_mux[] = {
2775 TPU0TO3_MARK,
2776};
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2777
2778static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]2779 SH_PFC_PIN_GROUP(bsc_data8),
2780 SH_PFC_PIN_GROUP(bsc_data16),
2781 SH_PFC_PIN_GROUP(bsc_data32),
2782 SH_PFC_PIN_GROUP(bsc_cs0),
2783 SH_PFC_PIN_GROUP(bsc_cs2),
2784 SH_PFC_PIN_GROUP(bsc_cs4),
2785 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2786 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2787 SH_PFC_PIN_GROUP(bsc_cs5b),
2788 SH_PFC_PIN_GROUP(bsc_cs6a),
2789 SH_PFC_PIN_GROUP(bsc_rd_we8),
2790 SH_PFC_PIN_GROUP(bsc_rd_we16),
2791 SH_PFC_PIN_GROUP(bsc_rd_we32),
2792 SH_PFC_PIN_GROUP(bsc_bs),
2793 SH_PFC_PIN_GROUP(bsc_rdwr),
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]2794 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2795 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2796 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2797 SH_PFC_PIN_GROUP(ceu0_clk_0),
2798 SH_PFC_PIN_GROUP(ceu0_clk_1),
2799 SH_PFC_PIN_GROUP(ceu0_clk_2),
2800 SH_PFC_PIN_GROUP(ceu0_sync),
2801 SH_PFC_PIN_GROUP(ceu0_field),
2802 SH_PFC_PIN_GROUP(ceu1_data),
2803 SH_PFC_PIN_GROUP(ceu1_clk),
2804 SH_PFC_PIN_GROUP(ceu1_sync),
2805 SH_PFC_PIN_GROUP(ceu1_field),
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]2806 SH_PFC_PIN_GROUP(fsia_mclk_in),
2807 SH_PFC_PIN_GROUP(fsia_mclk_out),
2808 SH_PFC_PIN_GROUP(fsia_sclk_in),
2809 SH_PFC_PIN_GROUP(fsia_sclk_out),
2810 SH_PFC_PIN_GROUP(fsia_data_in_0),
2811 SH_PFC_PIN_GROUP(fsia_data_in_1),
2812 SH_PFC_PIN_GROUP(fsia_data_out_0),
2813 SH_PFC_PIN_GROUP(fsia_data_out_1),
2814 SH_PFC_PIN_GROUP(fsia_data_out_2),
2815 SH_PFC_PIN_GROUP(fsia_spdif_0),
2816 SH_PFC_PIN_GROUP(fsia_spdif_1),
2817 SH_PFC_PIN_GROUP(fsib_mclk_in),
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]2818 SH_PFC_PIN_GROUP(gether_rmii),
2819 SH_PFC_PIN_GROUP(gether_mii),
2820 SH_PFC_PIN_GROUP(gether_gmii),
2821 SH_PFC_PIN_GROUP(gether_int),
2822 SH_PFC_PIN_GROUP(gether_link),
2823 SH_PFC_PIN_GROUP(gether_wol),
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2824 SH_PFC_PIN_GROUP(hdmi),
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2825 SH_PFC_PIN_GROUP(intc_irq0_0),
2826 SH_PFC_PIN_GROUP(intc_irq0_1),
2827 SH_PFC_PIN_GROUP(intc_irq1),
2828 SH_PFC_PIN_GROUP(intc_irq2_0),
2829 SH_PFC_PIN_GROUP(intc_irq2_1),
2830 SH_PFC_PIN_GROUP(intc_irq3_0),
2831 SH_PFC_PIN_GROUP(intc_irq3_1),
2832 SH_PFC_PIN_GROUP(intc_irq4_0),
2833 SH_PFC_PIN_GROUP(intc_irq4_1),
2834 SH_PFC_PIN_GROUP(intc_irq5_0),
2835 SH_PFC_PIN_GROUP(intc_irq5_1),
2836 SH_PFC_PIN_GROUP(intc_irq6_0),
2837 SH_PFC_PIN_GROUP(intc_irq6_1),
2838 SH_PFC_PIN_GROUP(intc_irq7_0),
2839 SH_PFC_PIN_GROUP(intc_irq7_1),
2840 SH_PFC_PIN_GROUP(intc_irq8),
2841 SH_PFC_PIN_GROUP(intc_irq9_0),
2842 SH_PFC_PIN_GROUP(intc_irq9_1),
2843 SH_PFC_PIN_GROUP(intc_irq10),
2844 SH_PFC_PIN_GROUP(intc_irq11),
2845 SH_PFC_PIN_GROUP(intc_irq12_0),
2846 SH_PFC_PIN_GROUP(intc_irq12_1),
2847 SH_PFC_PIN_GROUP(intc_irq13_0),
2848 SH_PFC_PIN_GROUP(intc_irq13_1),
2849 SH_PFC_PIN_GROUP(intc_irq14_0),
2850 SH_PFC_PIN_GROUP(intc_irq14_1),
2851 SH_PFC_PIN_GROUP(intc_irq15_0),
2852 SH_PFC_PIN_GROUP(intc_irq15_1),
2853 SH_PFC_PIN_GROUP(intc_irq16_0),
2854 SH_PFC_PIN_GROUP(intc_irq16_1),
2855 SH_PFC_PIN_GROUP(intc_irq17),
2856 SH_PFC_PIN_GROUP(intc_irq18),
2857 SH_PFC_PIN_GROUP(intc_irq19),
2858 SH_PFC_PIN_GROUP(intc_irq20),
2859 SH_PFC_PIN_GROUP(intc_irq21),
2860 SH_PFC_PIN_GROUP(intc_irq22),
2861 SH_PFC_PIN_GROUP(intc_irq23),
2862 SH_PFC_PIN_GROUP(intc_irq24),
2863 SH_PFC_PIN_GROUP(intc_irq25),
2864 SH_PFC_PIN_GROUP(intc_irq26_0),
2865 SH_PFC_PIN_GROUP(intc_irq26_1),
2866 SH_PFC_PIN_GROUP(intc_irq27_0),
2867 SH_PFC_PIN_GROUP(intc_irq27_1),
2868 SH_PFC_PIN_GROUP(intc_irq28_0),
2869 SH_PFC_PIN_GROUP(intc_irq28_1),
2870 SH_PFC_PIN_GROUP(intc_irq29_0),
2871 SH_PFC_PIN_GROUP(intc_irq29_1),
2872 SH_PFC_PIN_GROUP(intc_irq30_0),
2873 SH_PFC_PIN_GROUP(intc_irq30_1),
2874 SH_PFC_PIN_GROUP(intc_irq31_0),
2875 SH_PFC_PIN_GROUP(intc_irq31_1),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2876 SH_PFC_PIN_GROUP(lcd0_data8),
2877 SH_PFC_PIN_GROUP(lcd0_data9),
2878 SH_PFC_PIN_GROUP(lcd0_data12),
2879 SH_PFC_PIN_GROUP(lcd0_data16),
2880 SH_PFC_PIN_GROUP(lcd0_data18),
2881 SH_PFC_PIN_GROUP(lcd0_data24_0),
2882 SH_PFC_PIN_GROUP(lcd0_data24_1),
2883 SH_PFC_PIN_GROUP(lcd0_display),
2884 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2885 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2886 SH_PFC_PIN_GROUP(lcd0_sync),
2887 SH_PFC_PIN_GROUP(lcd0_sys),
2888 SH_PFC_PIN_GROUP(lcd1_data8),
2889 SH_PFC_PIN_GROUP(lcd1_data9),
2890 SH_PFC_PIN_GROUP(lcd1_data12),
2891 SH_PFC_PIN_GROUP(lcd1_data16),
2892 SH_PFC_PIN_GROUP(lcd1_data18),
2893 SH_PFC_PIN_GROUP(lcd1_data24),
2894 SH_PFC_PIN_GROUP(lcd1_display),
2895 SH_PFC_PIN_GROUP(lcd1_lclk),
2896 SH_PFC_PIN_GROUP(lcd1_sync),
2897 SH_PFC_PIN_GROUP(lcd1_sys),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2898 SH_PFC_PIN_GROUP(mmc0_data1_0),
2899 SH_PFC_PIN_GROUP(mmc0_data4_0),
2900 SH_PFC_PIN_GROUP(mmc0_data8_0),
2901 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2902 SH_PFC_PIN_GROUP(mmc0_data1_1),
2903 SH_PFC_PIN_GROUP(mmc0_data4_1),
2904 SH_PFC_PIN_GROUP(mmc0_data8_1),
2905 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2906 SH_PFC_PIN_GROUP(scifa0_data),
2907 SH_PFC_PIN_GROUP(scifa0_clk),
2908 SH_PFC_PIN_GROUP(scifa0_ctrl),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2909 SH_PFC_PIN_GROUP(scifa1_data),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2910 SH_PFC_PIN_GROUP(scifa1_clk),
2911 SH_PFC_PIN_GROUP(scifa1_ctrl),
2912 SH_PFC_PIN_GROUP(scifa2_data),
2913 SH_PFC_PIN_GROUP(scifa2_clk_0),
2914 SH_PFC_PIN_GROUP(scifa2_clk_1),
2915 SH_PFC_PIN_GROUP(scifa2_ctrl),
2916 SH_PFC_PIN_GROUP(scifa3_data_0),
2917 SH_PFC_PIN_GROUP(scifa3_clk_0),
2918 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2919 SH_PFC_PIN_GROUP(scifa3_data_1),
2920 SH_PFC_PIN_GROUP(scifa3_clk_1),
2921 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2922 SH_PFC_PIN_GROUP(scifa4_data_0),
2923 SH_PFC_PIN_GROUP(scifa4_data_1),
2924 SH_PFC_PIN_GROUP(scifa4_data_2),
2925 SH_PFC_PIN_GROUP(scifa4_clk_0),
2926 SH_PFC_PIN_GROUP(scifa4_clk_1),
2927 SH_PFC_PIN_GROUP(scifa5_data_0),
2928 SH_PFC_PIN_GROUP(scifa5_data_1),
2929 SH_PFC_PIN_GROUP(scifa5_data_2),
2930 SH_PFC_PIN_GROUP(scifa5_clk_0),
2931 SH_PFC_PIN_GROUP(scifa5_clk_1),
2932 SH_PFC_PIN_GROUP(scifa6_data),
2933 SH_PFC_PIN_GROUP(scifa6_clk),
2934 SH_PFC_PIN_GROUP(scifa7_data),
2935 SH_PFC_PIN_GROUP(scifb_data_0),
2936 SH_PFC_PIN_GROUP(scifb_clk_0),
2937 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2938 SH_PFC_PIN_GROUP(scifb_data_1),
2939 SH_PFC_PIN_GROUP(scifb_clk_1),
2940 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2941 SH_PFC_PIN_GROUP(sdhi0_data1),
2942 SH_PFC_PIN_GROUP(sdhi0_data4),
2943 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2944 SH_PFC_PIN_GROUP(sdhi0_cd),
2945 SH_PFC_PIN_GROUP(sdhi0_wp),
2946 SH_PFC_PIN_GROUP(sdhi1_data1),
2947 SH_PFC_PIN_GROUP(sdhi1_data4),
2948 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2949 SH_PFC_PIN_GROUP(sdhi1_cd),
2950 SH_PFC_PIN_GROUP(sdhi1_wp),
2951 SH_PFC_PIN_GROUP(sdhi2_data1),
2952 SH_PFC_PIN_GROUP(sdhi2_data4),
2953 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2954 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2955 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2956 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2957 SH_PFC_PIN_GROUP(sdhi2_wp_1),
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]2958 SH_PFC_PIN_GROUP(tpu0_to0),
2959 SH_PFC_PIN_GROUP(tpu0_to1),
2960 SH_PFC_PIN_GROUP(tpu0_to2_0),
2961 SH_PFC_PIN_GROUP(tpu0_to2_1),
2962 SH_PFC_PIN_GROUP(tpu0_to3),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2963};
2964
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]2965static const char * const bsc_groups[] = {
2966 "bsc_data8",
2967 "bsc_data16",
2968 "bsc_data32",
2969 "bsc_cs0",
2970 "bsc_cs2",
2971 "bsc_cs4",
2972 "bsc_cs5a_0",
2973 "bsc_cs5a_1",
2974 "bsc_cs5b",
2975 "bsc_cs6a",
2976 "bsc_rd_we8",
2977 "bsc_rd_we16",
2978 "bsc_rd_we32",
2979 "bsc_bs",
2980 "bsc_rdwr",
2981};
2982
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]2983static const char * const ceu0_groups[] = {
2984 "ceu0_data_0_7",
2985 "ceu0_data_8_15_0",
2986 "ceu0_data_8_15_1",
2987 "ceu0_clk_0",
2988 "ceu0_clk_1",
2989 "ceu0_clk_2",
2990 "ceu0_sync",
2991 "ceu0_field",
2992};
2993
2994static const char * const ceu1_groups[] = {
2995 "ceu1_data",
2996 "ceu1_clk",
2997 "ceu1_sync",
2998 "ceu1_field",
2999};
3000
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]3001static const char * const fsia_groups[] = {
3002 "fsia_mclk_in",
3003 "fsia_mclk_out",
3004 "fsia_sclk_in",
3005 "fsia_sclk_out",
3006 "fsia_data_in_0",
3007 "fsia_data_in_1",
3008 "fsia_data_out_0",
3009 "fsia_data_out_1",
3010 "fsia_data_out_2",
3011 "fsia_spdif_0",
3012 "fsia_spdif_1",
3013};
3014
3015static const char * const fsib_groups[] = {
3016 "fsib_mclk_in",
3017};
3018
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]3019static const char * const gether_groups[] = {
3020 "gether_rmii",
3021 "gether_mii",
3022 "gether_gmii",
3023 "gether_int",
3024 "gether_link",
3025 "gether_wol",
3026};
3027
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]3028static const char * const hdmi_groups[] = {
3029 "hdmi",
3030};
3031
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]3032static const char * const intc_groups[] = {
3033 "intc_irq0_0",
3034 "intc_irq0_1",
3035 "intc_irq1",
3036 "intc_irq2_0",
3037 "intc_irq2_1",
3038 "intc_irq3_0",
3039 "intc_irq3_1",
3040 "intc_irq4_0",
3041 "intc_irq4_1",
3042 "intc_irq5_0",
3043 "intc_irq5_1",
3044 "intc_irq6_0",
3045 "intc_irq6_1",
3046 "intc_irq7_0",
3047 "intc_irq7_1",
3048 "intc_irq8",
3049 "intc_irq9_0",
3050 "intc_irq9_1",
3051 "intc_irq10",
3052 "intc_irq11",
3053 "intc_irq12_0",
3054 "intc_irq12_1",
3055 "intc_irq13_0",
3056 "intc_irq13_1",
3057 "intc_irq14_0",
3058 "intc_irq14_1",
3059 "intc_irq15_0",
3060 "intc_irq15_1",
3061 "intc_irq16_0",
3062 "intc_irq16_1",
3063 "intc_irq17",
3064 "intc_irq18",
3065 "intc_irq19",
3066 "intc_irq20",
3067 "intc_irq21",
3068 "intc_irq22",
3069 "intc_irq23",
3070 "intc_irq24",
3071 "intc_irq25",
3072 "intc_irq26_0",
3073 "intc_irq26_1",
3074 "intc_irq27_0",
3075 "intc_irq27_1",
3076 "intc_irq28_0",
3077 "intc_irq28_1",
3078 "intc_irq29_0",
3079 "intc_irq29_1",
3080 "intc_irq30_0",
3081 "intc_irq30_1",
3082 "intc_irq31_0",
3083 "intc_irq31_1",
3084};
3085
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3086static const char * const lcd0_groups[] = {
3087 "lcd0_data8",
3088 "lcd0_data9",
3089 "lcd0_data12",
3090 "lcd0_data16",
3091 "lcd0_data18",
3092 "lcd0_data24_0",
3093 "lcd0_data24_1",
3094 "lcd0_display",
3095 "lcd0_lclk_0",
3096 "lcd0_lclk_1",
3097 "lcd0_sync",
3098 "lcd0_sys",
3099};
3100
3101static const char * const lcd1_groups[] = {
3102 "lcd1_data8",
3103 "lcd1_data9",
3104 "lcd1_data12",
3105 "lcd1_data16",
3106 "lcd1_data18",
3107 "lcd1_data24",
3108 "lcd1_display",
3109 "lcd1_lclk",
3110 "lcd1_sync",
3111 "lcd1_sys",
3112};
3113
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3114static const char * const mmc0_groups[] = {
3115 "mmc0_data1_0",
3116 "mmc0_data4_0",
3117 "mmc0_data8_0",
3118 "mmc0_ctrl_0",
3119 "mmc0_data1_1",
3120 "mmc0_data4_1",
3121 "mmc0_data8_1",
3122 "mmc0_ctrl_1",
3123};
3124
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3125static const char * const scifa0_groups[] = {
3126 "scifa0_data",
3127 "scifa0_clk",
3128 "scifa0_ctrl",
3129};
3130
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3131static const char * const scifa1_groups[] = {
3132 "scifa1_data",
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3133 "scifa1_clk",
3134 "scifa1_ctrl",
3135};
3136
3137static const char * const scifa2_groups[] = {
3138 "scifa2_data",
3139 "scifa2_clk_0",
3140 "scifa2_clk_1",
3141 "scifa2_ctrl",
3142};
3143
3144static const char * const scifa3_groups[] = {
3145 "scifa3_data_0",
3146 "scifa3_clk_0",
3147 "scifa3_ctrl_0",
3148 "scifa3_data_1",
3149 "scifa3_clk_1",
3150 "scifa3_ctrl_1",
3151};
3152
3153static const char * const scifa4_groups[] = {
3154 "scifa4_data_0",
3155 "scifa4_data_1",
3156 "scifa4_data_2",
3157 "scifa4_clk_0",
3158 "scifa4_clk_1",
3159};
3160
3161static const char * const scifa5_groups[] = {
3162 "scifa5_data_0",
3163 "scifa5_data_1",
3164 "scifa5_data_2",
3165 "scifa5_clk_0",
3166 "scifa5_clk_1",
3167};
3168
3169static const char * const scifa6_groups[] = {
3170 "scifa6_data",
3171 "scifa6_clk",
3172};
3173
3174static const char * const scifa7_groups[] = {
3175 "scifa7_data",
3176};
3177
3178static const char * const scifb_groups[] = {
3179 "scifb_data_0",
3180 "scifb_clk_0",
3181 "scifb_ctrl_0",
3182 "scifb_data_1",
3183 "scifb_clk_1",
3184 "scifb_ctrl_1",
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3185};
3186
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3187static const char * const sdhi0_groups[] = {
3188 "sdhi0_data1",
3189 "sdhi0_data4",
3190 "sdhi0_ctrl",
3191 "sdhi0_cd",
3192 "sdhi0_wp",
3193};
3194
3195static const char * const sdhi1_groups[] = {
3196 "sdhi1_data1",
3197 "sdhi1_data4",
3198 "sdhi1_ctrl",
3199 "sdhi1_cd",
3200 "sdhi1_wp",
3201};
3202
3203static const char * const sdhi2_groups[] = {
3204 "sdhi2_data1",
3205 "sdhi2_data4",
3206 "sdhi2_ctrl",
3207 "sdhi2_cd_0",
3208 "sdhi2_wp_0",
3209 "sdhi2_cd_1",
3210 "sdhi2_wp_1",
3211};
3212
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]3213static const char * const tpu0_groups[] = {
3214 "tpu0_to0",
3215 "tpu0_to1",
3216 "tpu0_to2_0",
3217 "tpu0_to2_1",
3218 "tpu0_to3",
3219};
3220
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3221static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]3222 SH_PFC_FUNCTION(bsc),
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]3223 SH_PFC_FUNCTION(ceu0),
3224 SH_PFC_FUNCTION(ceu1),
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]3225 SH_PFC_FUNCTION(fsia),
3226 SH_PFC_FUNCTION(fsib),
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]3227 SH_PFC_FUNCTION(gether),
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]3228 SH_PFC_FUNCTION(hdmi),
Laurent Pinchartd0316962013-04-18 10:54:18 +0200[diff] [blame]3229 SH_PFC_FUNCTION(intc),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3230 SH_PFC_FUNCTION(lcd0),
3231 SH_PFC_FUNCTION(lcd1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3232 SH_PFC_FUNCTION(mmc0),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3233 SH_PFC_FUNCTION(scifa0),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3234 SH_PFC_FUNCTION(scifa1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3235 SH_PFC_FUNCTION(scifa2),
3236 SH_PFC_FUNCTION(scifa3),
3237 SH_PFC_FUNCTION(scifa4),
3238 SH_PFC_FUNCTION(scifa5),
3239 SH_PFC_FUNCTION(scifa6),
3240 SH_PFC_FUNCTION(scifa7),
3241 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3242 SH_PFC_FUNCTION(sdhi0),
3243 SH_PFC_FUNCTION(sdhi1),
3244 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchartc2ad27e2013-04-23 16:04:07 +0200[diff] [blame]3245 SH_PFC_FUNCTION(tpu0),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3246};
3247
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]3248#undef PORTCR
3249#define PORTCR(nr, reg) \
3250 { \
3251 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3252 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3253 PORT##nr##_FN0, PORT##nr##_FN1, \
3254 PORT##nr##_FN2, PORT##nr##_FN3, \
3255 PORT##nr##_FN4, PORT##nr##_FN5, \
3256 PORT##nr##_FN6, PORT##nr##_FN7 } \
3257 }
3258
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3259static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3260 PORTCR(0, 0xe6050000), /* PORT0CR */
3261 PORTCR(1, 0xe6050001), /* PORT1CR */
3262 PORTCR(2, 0xe6050002), /* PORT2CR */
3263 PORTCR(3, 0xe6050003), /* PORT3CR */
3264 PORTCR(4, 0xe6050004), /* PORT4CR */
3265 PORTCR(5, 0xe6050005), /* PORT5CR */
3266 PORTCR(6, 0xe6050006), /* PORT6CR */
3267 PORTCR(7, 0xe6050007), /* PORT7CR */
3268 PORTCR(8, 0xe6050008), /* PORT8CR */
3269 PORTCR(9, 0xe6050009), /* PORT9CR */
3270 PORTCR(10, 0xe605000a), /* PORT10CR */
3271 PORTCR(11, 0xe605000b), /* PORT11CR */
3272 PORTCR(12, 0xe605000c), /* PORT12CR */
3273 PORTCR(13, 0xe605000d), /* PORT13CR */
3274 PORTCR(14, 0xe605000e), /* PORT14CR */
3275 PORTCR(15, 0xe605000f), /* PORT15CR */
3276 PORTCR(16, 0xe6050010), /* PORT16CR */
3277 PORTCR(17, 0xe6050011), /* PORT17CR */
3278 PORTCR(18, 0xe6050012), /* PORT18CR */
3279 PORTCR(19, 0xe6050013), /* PORT19CR */
3280 PORTCR(20, 0xe6050014), /* PORT20CR */
3281 PORTCR(21, 0xe6050015), /* PORT21CR */
3282 PORTCR(22, 0xe6050016), /* PORT22CR */
3283 PORTCR(23, 0xe6050017), /* PORT23CR */
3284 PORTCR(24, 0xe6050018), /* PORT24CR */
3285 PORTCR(25, 0xe6050019), /* PORT25CR */
3286 PORTCR(26, 0xe605001a), /* PORT26CR */
3287 PORTCR(27, 0xe605001b), /* PORT27CR */
3288 PORTCR(28, 0xe605001c), /* PORT28CR */
3289 PORTCR(29, 0xe605001d), /* PORT29CR */
3290 PORTCR(30, 0xe605001e), /* PORT30CR */
3291 PORTCR(31, 0xe605001f), /* PORT31CR */
3292 PORTCR(32, 0xe6050020), /* PORT32CR */
3293 PORTCR(33, 0xe6050021), /* PORT33CR */
3294 PORTCR(34, 0xe6050022), /* PORT34CR */
3295 PORTCR(35, 0xe6050023), /* PORT35CR */
3296 PORTCR(36, 0xe6050024), /* PORT36CR */
3297 PORTCR(37, 0xe6050025), /* PORT37CR */
3298 PORTCR(38, 0xe6050026), /* PORT38CR */
3299 PORTCR(39, 0xe6050027), /* PORT39CR */
3300 PORTCR(40, 0xe6050028), /* PORT40CR */
3301 PORTCR(41, 0xe6050029), /* PORT41CR */
3302 PORTCR(42, 0xe605002a), /* PORT42CR */
3303 PORTCR(43, 0xe605002b), /* PORT43CR */
3304 PORTCR(44, 0xe605002c), /* PORT44CR */
3305 PORTCR(45, 0xe605002d), /* PORT45CR */
3306 PORTCR(46, 0xe605002e), /* PORT46CR */
3307 PORTCR(47, 0xe605002f), /* PORT47CR */
3308 PORTCR(48, 0xe6050030), /* PORT48CR */
3309 PORTCR(49, 0xe6050031), /* PORT49CR */
3310 PORTCR(50, 0xe6050032), /* PORT50CR */
3311 PORTCR(51, 0xe6050033), /* PORT51CR */
3312 PORTCR(52, 0xe6050034), /* PORT52CR */
3313 PORTCR(53, 0xe6050035), /* PORT53CR */
3314 PORTCR(54, 0xe6050036), /* PORT54CR */
3315 PORTCR(55, 0xe6050037), /* PORT55CR */
3316 PORTCR(56, 0xe6050038), /* PORT56CR */
3317 PORTCR(57, 0xe6050039), /* PORT57CR */
3318 PORTCR(58, 0xe605003a), /* PORT58CR */
3319 PORTCR(59, 0xe605003b), /* PORT59CR */
3320 PORTCR(60, 0xe605003c), /* PORT60CR */
3321 PORTCR(61, 0xe605003d), /* PORT61CR */
3322 PORTCR(62, 0xe605003e), /* PORT62CR */
3323 PORTCR(63, 0xe605003f), /* PORT63CR */
3324 PORTCR(64, 0xe6050040), /* PORT64CR */
3325 PORTCR(65, 0xe6050041), /* PORT65CR */
3326 PORTCR(66, 0xe6050042), /* PORT66CR */
3327 PORTCR(67, 0xe6050043), /* PORT67CR */
3328 PORTCR(68, 0xe6050044), /* PORT68CR */
3329 PORTCR(69, 0xe6050045), /* PORT69CR */
3330 PORTCR(70, 0xe6050046), /* PORT70CR */
3331 PORTCR(71, 0xe6050047), /* PORT71CR */
3332 PORTCR(72, 0xe6050048), /* PORT72CR */
3333 PORTCR(73, 0xe6050049), /* PORT73CR */
3334 PORTCR(74, 0xe605004a), /* PORT74CR */
3335 PORTCR(75, 0xe605004b), /* PORT75CR */
3336 PORTCR(76, 0xe605004c), /* PORT76CR */
3337 PORTCR(77, 0xe605004d), /* PORT77CR */
3338 PORTCR(78, 0xe605004e), /* PORT78CR */
3339 PORTCR(79, 0xe605004f), /* PORT79CR */
3340 PORTCR(80, 0xe6050050), /* PORT80CR */
3341 PORTCR(81, 0xe6050051), /* PORT81CR */
3342 PORTCR(82, 0xe6050052), /* PORT82CR */
3343 PORTCR(83, 0xe6050053), /* PORT83CR */
3344
3345 PORTCR(84, 0xe6051054), /* PORT84CR */
3346 PORTCR(85, 0xe6051055), /* PORT85CR */
3347 PORTCR(86, 0xe6051056), /* PORT86CR */
3348 PORTCR(87, 0xe6051057), /* PORT87CR */
3349 PORTCR(88, 0xe6051058), /* PORT88CR */
3350 PORTCR(89, 0xe6051059), /* PORT89CR */
3351 PORTCR(90, 0xe605105a), /* PORT90CR */
3352 PORTCR(91, 0xe605105b), /* PORT91CR */
3353 PORTCR(92, 0xe605105c), /* PORT92CR */
3354 PORTCR(93, 0xe605105d), /* PORT93CR */
3355 PORTCR(94, 0xe605105e), /* PORT94CR */
3356 PORTCR(95, 0xe605105f), /* PORT95CR */
3357 PORTCR(96, 0xe6051060), /* PORT96CR */
3358 PORTCR(97, 0xe6051061), /* PORT97CR */
3359 PORTCR(98, 0xe6051062), /* PORT98CR */
3360 PORTCR(99, 0xe6051063), /* PORT99CR */
3361 PORTCR(100, 0xe6051064), /* PORT100CR */
3362 PORTCR(101, 0xe6051065), /* PORT101CR */
3363 PORTCR(102, 0xe6051066), /* PORT102CR */
3364 PORTCR(103, 0xe6051067), /* PORT103CR */
3365 PORTCR(104, 0xe6051068), /* PORT104CR */
3366 PORTCR(105, 0xe6051069), /* PORT105CR */
3367 PORTCR(106, 0xe605106a), /* PORT106CR */
3368 PORTCR(107, 0xe605106b), /* PORT107CR */
3369 PORTCR(108, 0xe605106c), /* PORT108CR */
3370 PORTCR(109, 0xe605106d), /* PORT109CR */
3371 PORTCR(110, 0xe605106e), /* PORT110CR */
3372 PORTCR(111, 0xe605106f), /* PORT111CR */
3373 PORTCR(112, 0xe6051070), /* PORT112CR */
3374 PORTCR(113, 0xe6051071), /* PORT113CR */
3375 PORTCR(114, 0xe6051072), /* PORT114CR */
3376
3377 PORTCR(115, 0xe6052073), /* PORT115CR */
3378 PORTCR(116, 0xe6052074), /* PORT116CR */
3379 PORTCR(117, 0xe6052075), /* PORT117CR */
3380 PORTCR(118, 0xe6052076), /* PORT118CR */
3381 PORTCR(119, 0xe6052077), /* PORT119CR */
3382 PORTCR(120, 0xe6052078), /* PORT120CR */
3383 PORTCR(121, 0xe6052079), /* PORT121CR */
3384 PORTCR(122, 0xe605207a), /* PORT122CR */
3385 PORTCR(123, 0xe605207b), /* PORT123CR */
3386 PORTCR(124, 0xe605207c), /* PORT124CR */
3387 PORTCR(125, 0xe605207d), /* PORT125CR */
3388 PORTCR(126, 0xe605207e), /* PORT126CR */
3389 PORTCR(127, 0xe605207f), /* PORT127CR */
3390 PORTCR(128, 0xe6052080), /* PORT128CR */
3391 PORTCR(129, 0xe6052081), /* PORT129CR */
3392 PORTCR(130, 0xe6052082), /* PORT130CR */
3393 PORTCR(131, 0xe6052083), /* PORT131CR */
3394 PORTCR(132, 0xe6052084), /* PORT132CR */
3395 PORTCR(133, 0xe6052085), /* PORT133CR */
3396 PORTCR(134, 0xe6052086), /* PORT134CR */
3397 PORTCR(135, 0xe6052087), /* PORT135CR */
3398 PORTCR(136, 0xe6052088), /* PORT136CR */
3399 PORTCR(137, 0xe6052089), /* PORT137CR */
3400 PORTCR(138, 0xe605208a), /* PORT138CR */
3401 PORTCR(139, 0xe605208b), /* PORT139CR */
3402 PORTCR(140, 0xe605208c), /* PORT140CR */
3403 PORTCR(141, 0xe605208d), /* PORT141CR */
3404 PORTCR(142, 0xe605208e), /* PORT142CR */
3405 PORTCR(143, 0xe605208f), /* PORT143CR */
3406 PORTCR(144, 0xe6052090), /* PORT144CR */
3407 PORTCR(145, 0xe6052091), /* PORT145CR */
3408 PORTCR(146, 0xe6052092), /* PORT146CR */
3409 PORTCR(147, 0xe6052093), /* PORT147CR */
3410 PORTCR(148, 0xe6052094), /* PORT148CR */
3411 PORTCR(149, 0xe6052095), /* PORT149CR */
3412 PORTCR(150, 0xe6052096), /* PORT150CR */
3413 PORTCR(151, 0xe6052097), /* PORT151CR */
3414 PORTCR(152, 0xe6052098), /* PORT152CR */
3415 PORTCR(153, 0xe6052099), /* PORT153CR */
3416 PORTCR(154, 0xe605209a), /* PORT154CR */
3417 PORTCR(155, 0xe605209b), /* PORT155CR */
3418 PORTCR(156, 0xe605209c), /* PORT156CR */
3419 PORTCR(157, 0xe605209d), /* PORT157CR */
3420 PORTCR(158, 0xe605209e), /* PORT158CR */
3421 PORTCR(159, 0xe605209f), /* PORT159CR */
3422 PORTCR(160, 0xe60520a0), /* PORT160CR */
3423 PORTCR(161, 0xe60520a1), /* PORT161CR */
3424 PORTCR(162, 0xe60520a2), /* PORT162CR */
3425 PORTCR(163, 0xe60520a3), /* PORT163CR */
3426 PORTCR(164, 0xe60520a4), /* PORT164CR */
3427 PORTCR(165, 0xe60520a5), /* PORT165CR */
3428 PORTCR(166, 0xe60520a6), /* PORT166CR */
3429 PORTCR(167, 0xe60520a7), /* PORT167CR */
3430 PORTCR(168, 0xe60520a8), /* PORT168CR */
3431 PORTCR(169, 0xe60520a9), /* PORT169CR */
3432 PORTCR(170, 0xe60520aa), /* PORT170CR */
3433 PORTCR(171, 0xe60520ab), /* PORT171CR */
3434 PORTCR(172, 0xe60520ac), /* PORT172CR */
3435 PORTCR(173, 0xe60520ad), /* PORT173CR */
3436 PORTCR(174, 0xe60520ae), /* PORT174CR */
3437 PORTCR(175, 0xe60520af), /* PORT175CR */
3438 PORTCR(176, 0xe60520b0), /* PORT176CR */
3439 PORTCR(177, 0xe60520b1), /* PORT177CR */
3440 PORTCR(178, 0xe60520b2), /* PORT178CR */
3441 PORTCR(179, 0xe60520b3), /* PORT179CR */
3442 PORTCR(180, 0xe60520b4), /* PORT180CR */
3443 PORTCR(181, 0xe60520b5), /* PORT181CR */
3444 PORTCR(182, 0xe60520b6), /* PORT182CR */
3445 PORTCR(183, 0xe60520b7), /* PORT183CR */
3446 PORTCR(184, 0xe60520b8), /* PORT184CR */
3447 PORTCR(185, 0xe60520b9), /* PORT185CR */
3448 PORTCR(186, 0xe60520ba), /* PORT186CR */
3449 PORTCR(187, 0xe60520bb), /* PORT187CR */
3450 PORTCR(188, 0xe60520bc), /* PORT188CR */
3451 PORTCR(189, 0xe60520bd), /* PORT189CR */
3452 PORTCR(190, 0xe60520be), /* PORT190CR */
3453 PORTCR(191, 0xe60520bf), /* PORT191CR */
3454 PORTCR(192, 0xe60520c0), /* PORT192CR */
3455 PORTCR(193, 0xe60520c1), /* PORT193CR */
3456 PORTCR(194, 0xe60520c2), /* PORT194CR */
3457 PORTCR(195, 0xe60520c3), /* PORT195CR */
3458 PORTCR(196, 0xe60520c4), /* PORT196CR */
3459 PORTCR(197, 0xe60520c5), /* PORT197CR */
3460 PORTCR(198, 0xe60520c6), /* PORT198CR */
3461 PORTCR(199, 0xe60520c7), /* PORT199CR */
3462 PORTCR(200, 0xe60520c8), /* PORT200CR */
3463 PORTCR(201, 0xe60520c9), /* PORT201CR */
3464 PORTCR(202, 0xe60520ca), /* PORT202CR */
3465 PORTCR(203, 0xe60520cb), /* PORT203CR */
3466 PORTCR(204, 0xe60520cc), /* PORT204CR */
3467 PORTCR(205, 0xe60520cd), /* PORT205CR */
3468 PORTCR(206, 0xe60520ce), /* PORT206CR */
3469 PORTCR(207, 0xe60520cf), /* PORT207CR */
3470 PORTCR(208, 0xe60520d0), /* PORT208CR */
3471 PORTCR(209, 0xe60520d1), /* PORT209CR */
3472
3473 PORTCR(210, 0xe60530d2), /* PORT210CR */
3474 PORTCR(211, 0xe60530d3), /* PORT211CR */
3475
3476 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3477 MSEL1CR_31_0, MSEL1CR_31_1,
3478 MSEL1CR_30_0, MSEL1CR_30_1,
3479 MSEL1CR_29_0, MSEL1CR_29_1,
3480 MSEL1CR_28_0, MSEL1CR_28_1,
3481 MSEL1CR_27_0, MSEL1CR_27_1,
3482 MSEL1CR_26_0, MSEL1CR_26_1,
3483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3484 0, 0, 0, 0, 0, 0, 0, 0,
3485 MSEL1CR_16_0, MSEL1CR_16_1,
3486 MSEL1CR_15_0, MSEL1CR_15_1,
3487 MSEL1CR_14_0, MSEL1CR_14_1,
3488 MSEL1CR_13_0, MSEL1CR_13_1,
3489 MSEL1CR_12_0, MSEL1CR_12_1,
3490 0, 0, 0, 0,
3491 MSEL1CR_9_0, MSEL1CR_9_1,
3492 0, 0,
3493 MSEL1CR_7_0, MSEL1CR_7_1,
3494 MSEL1CR_6_0, MSEL1CR_6_1,
3495 MSEL1CR_5_0, MSEL1CR_5_1,
3496 MSEL1CR_4_0, MSEL1CR_4_1,
3497 MSEL1CR_3_0, MSEL1CR_3_1,
3498 MSEL1CR_2_0, MSEL1CR_2_1,
3499 0, 0,
3500 MSEL1CR_0_0, MSEL1CR_0_1,
3501 }
3502 },
3503 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3504 0, 0, 0, 0, 0, 0, 0, 0,
3505 0, 0, 0, 0, 0, 0, 0, 0,
3506 0, 0, 0, 0, 0, 0, 0, 0,
3507 0, 0, 0, 0, 0, 0, 0, 0,
3508 MSEL3CR_15_0, MSEL3CR_15_1,
3509 0, 0, 0, 0, 0, 0, 0, 0,
3510 0, 0, 0, 0, 0, 0, 0, 0,
3511 MSEL3CR_6_0, MSEL3CR_6_1,
3512 0, 0, 0, 0, 0, 0, 0, 0,
3513 0, 0, 0, 0,
3514 }
3515 },
3516 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3517 0, 0, 0, 0, 0, 0, 0, 0,
3518 0, 0, 0, 0, 0, 0, 0, 0,
3519 0, 0, 0, 0, 0, 0, 0, 0,
3520 MSEL4CR_19_0, MSEL4CR_19_1,
3521 MSEL4CR_18_0, MSEL4CR_18_1,
3522 0, 0, 0, 0,
3523 MSEL4CR_15_0, MSEL4CR_15_1,
3524 0, 0, 0, 0, 0, 0, 0, 0,
3525 MSEL4CR_10_0, MSEL4CR_10_1,
3526 0, 0, 0, 0, 0, 0,
3527 MSEL4CR_6_0, MSEL4CR_6_1,
3528 0, 0,
3529 MSEL4CR_4_0, MSEL4CR_4_1,
3530 0, 0, 0, 0,
3531 MSEL4CR_1_0, MSEL4CR_1_1,
3532 0, 0,
3533 }
3534 },
3535 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3536 MSEL5CR_31_0, MSEL5CR_31_1,
3537 MSEL5CR_30_0, MSEL5CR_30_1,
3538 MSEL5CR_29_0, MSEL5CR_29_1,
3539 0, 0,
3540 MSEL5CR_27_0, MSEL5CR_27_1,
3541 0, 0,
3542 MSEL5CR_25_0, MSEL5CR_25_1,
3543 0, 0,
3544 MSEL5CR_23_0, MSEL5CR_23_1,
3545 0, 0,
3546 MSEL5CR_21_0, MSEL5CR_21_1,
3547 0, 0,
3548 MSEL5CR_19_0, MSEL5CR_19_1,
3549 0, 0,
3550 MSEL5CR_17_0, MSEL5CR_17_1,
3551 0, 0,
3552 MSEL5CR_15_0, MSEL5CR_15_1,
3553 MSEL5CR_14_0, MSEL5CR_14_1,
3554 MSEL5CR_13_0, MSEL5CR_13_1,
3555 MSEL5CR_12_0, MSEL5CR_12_1,
3556 MSEL5CR_11_0, MSEL5CR_11_1,
3557 MSEL5CR_10_0, MSEL5CR_10_1,
3558 0, 0,
3559 MSEL5CR_8_0, MSEL5CR_8_1,
3560 MSEL5CR_7_0, MSEL5CR_7_1,
3561 MSEL5CR_6_0, MSEL5CR_6_1,
3562 MSEL5CR_5_0, MSEL5CR_5_1,
3563 MSEL5CR_4_0, MSEL5CR_4_1,
3564 MSEL5CR_3_0, MSEL5CR_3_1,
3565 MSEL5CR_2_0, MSEL5CR_2_1,
3566 0, 0,
3567 MSEL5CR_0_0, MSEL5CR_0_1,
3568 }
3569 },
3570 { },
3571};
3572
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3573static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3574 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3575 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3576 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3577 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3578 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3579 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3580 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3581 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3582 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3583 },
3584 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3585 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3586 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3587 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3588 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3589 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3590 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3591 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3592 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3593 },
3594 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3595 0, 0, 0, 0,
3596 0, 0, 0, 0,
3597 0, 0, 0, 0,
3598 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3599 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3600 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3601 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3602 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3603 },
3604 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3605 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3606 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3607 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3608 0, 0, 0, 0,
3609 0, 0, 0, 0,
3610 0, 0, 0, 0,
3611 0, 0, 0, 0,
3612 0, 0, 0, 0 }
3613 },
3614 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3615 0, 0, 0, 0,
3616 0, 0, 0, 0,
3617 0, 0, 0, 0,
3618 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3619 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3620 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3621 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3622 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3623 },
3624 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3625 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3626 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3627 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3628 PORT115_DATA, 0, 0, 0,
3629 0, 0, 0, 0,
3630 0, 0, 0, 0,
3631 0, 0, 0, 0,
3632 0, 0, 0, 0 }
3633 },
3634 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3635 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3636 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3637 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3638 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3639 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3640 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3641 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3642 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3643 },
3644 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3645 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3646 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3647 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3648 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3649 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3650 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3651 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3652 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3653 },
3654 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3655 0, 0, 0, 0,
3656 0, 0, 0, 0,
3657 0, 0, 0, 0,
3658 0, 0, PORT209_DATA, PORT208_DATA,
3659 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3660 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3661 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3662 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3663 },
3664 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3665 0, 0, 0, 0,
3666 0, 0, 0, 0,
3667 0, 0, 0, 0,
3668 PORT211_DATA, PORT210_DATA, 0, 0,
3669 0, 0, 0, 0,
3670 0, 0, 0, 0,
3671 0, 0, 0, 0,
3672 0, 0, 0, 0 }
3673 },
3674 { },
3675};
3676
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3677static const struct pinmux_irq pinmux_irqs[] = {
Laurent Pinchart7d568452013-04-23 00:36:40 +0200[diff] [blame]3678 PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */
3679 PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */
3680 PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */
3681 PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */
3682 PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */
3683 PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */
3684 PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */
3685 PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */
3686 PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */
3687 PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */
3688 PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */
3689 PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */
3690 PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */
3691 PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */
3692 PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */
3693 PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */
3694 PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */
3695 PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */
3696 PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */
3697 PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */
3698 PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */
3699 PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */
3700 PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */
3701 PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */
3702 PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */
3703 PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */
3704 PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */
3705 PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */
3706 PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */
3707 PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */
3708 PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */
3709 PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3710};
3711
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]3712#define PORTnCR_PULMD_OFF (0 << 6)
3713#define PORTnCR_PULMD_DOWN (2 << 6)
3714#define PORTnCR_PULMD_UP (3 << 6)
3715#define PORTnCR_PULMD_MASK (3 << 6)
3716
3717struct r8a7740_portcr_group {
3718 unsigned int end_pin;
3719 unsigned int offset;
3720};
3721
3722static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3723 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3724};
3725
3726static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3727{
3728 unsigned int i;
3729
3730 for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3731 const struct r8a7740_portcr_group *group =
3732 &r8a7740_portcr_offsets[i];
3733
3734 if (i <= group->end_pin)
3735 return pfc->window->virt + group->offset + pin;
3736 }
3737
3738 return NULL;
3739}
3740
3741static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3742{
3743 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3744 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3745
3746 switch (value) {
3747 case PORTnCR_PULMD_UP:
3748 return PIN_CONFIG_BIAS_PULL_UP;
3749 case PORTnCR_PULMD_DOWN:
3750 return PIN_CONFIG_BIAS_PULL_DOWN;
3751 case PORTnCR_PULMD_OFF:
3752 default:
3753 return PIN_CONFIG_BIAS_DISABLE;
3754 }
3755}
3756
3757static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3758 unsigned int bias)
3759{
3760 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3761 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3762
3763 switch (bias) {
3764 case PIN_CONFIG_BIAS_PULL_UP:
3765 value |= PORTnCR_PULMD_UP;
3766 break;
3767 case PIN_CONFIG_BIAS_PULL_DOWN:
3768 value |= PORTnCR_PULMD_DOWN;
3769 break;
3770 }
3771
3772 iowrite8(value, addr);
3773}
3774
3775static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
3776 .get_bias = r8a7740_pinmux_get_bias,
3777 .set_bias = r8a7740_pinmux_set_bias,
3778};
3779
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3780const struct sh_pfc_soc_info r8a7740_pinmux_info = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3781 .name = "r8a7740_pfc",
Laurent Pinchart80da8e02013-04-23 14:24:19 +0200[diff] [blame]3782 .ops = &r8a7740_pinmux_ops,
3783
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3784 .input = { PINMUX_INPUT_BEGIN,
3785 PINMUX_INPUT_END },
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3786 .output = { PINMUX_OUTPUT_BEGIN,
3787 PINMUX_OUTPUT_END },
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3788 .function = { PINMUX_FUNCTION_BEGIN,
3789 PINMUX_FUNCTION_END },
3790
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3791 .pins = pinmux_pins,
3792 .nr_pins = ARRAY_SIZE(pinmux_pins),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3793 .groups = pinmux_groups,
3794 .nr_groups = ARRAY_SIZE(pinmux_groups),
3795 .functions = pinmux_functions,
3796 .nr_functions = ARRAY_SIZE(pinmux_functions),
3797
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3798 .cfg_regs = pinmux_config_regs,
3799 .data_regs = pinmux_data_regs,
3800
3801 .gpio_data = pinmux_data,
3802 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3803
3804 .gpio_irq = pinmux_irqs,
3805 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3806};