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gerrit-public.fairphone.software / kernel / msm-4.9 / 533743dccb517b0331eccc111e3c2b8f021559b5 / . / drivers / pinctrl / sh-pfc / pfc-sh73a0.c
blob: 985acd023dd2a3350c198fe3b40021d22a8903f4 [file] [log] [blame]
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1/*
2 * sh73a0 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Copyright (C) 2010 NISHIMOTO Hiroki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]21#include <linux/io.h>
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]22#include <linux/kernel.h>
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]23#include <linux/module.h>
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]24#include <linux/pinctrl/pinconf-generic.h>
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]25#include <linux/regulator/driver.h>
26#include <linux/regulator/machine.h>
27#include <linux/slab.h>
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]28
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]29#include <mach/irqs.h>
30
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]31#include "core.h"
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]32#include "sh_pfc.h"
33
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]34#define CPU_ALL_PORT(fn, pfx, sfx) \
Guennadi Liakhovetski942785d2013-02-12 16:34:31 +0100[diff] [blame]35 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]36 PORT_10(fn, pfx##10, sfx), \
37 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
38 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
39 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
40 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
41 PORT_1(fn, pfx##118, sfx), \
42 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
43 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
44 PORT_10(fn, pfx##15, sfx), \
45 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
46 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
47 PORT_1(fn, pfx##164, sfx), \
48 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
49 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
50 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
51 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
52 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
53 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
54 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
55 PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
56 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
57 PORT_1(fn, pfx##282, sfx), \
58 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
59 PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
60
61enum {
62 PINMUX_RESERVED = 0,
63
64 PINMUX_DATA_BEGIN,
65 PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
66 PINMUX_DATA_END,
67
68 PINMUX_INPUT_BEGIN,
69 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
70 PINMUX_INPUT_END,
71
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]72 PINMUX_OUTPUT_BEGIN,
73 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
74 PINMUX_OUTPUT_END,
75
76 PINMUX_FUNCTION_BEGIN,
77 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
78 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
79 PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
80 PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
81 PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
82 PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
83 PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
84 PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
85 PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
86 PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
87
88 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
89 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
90 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
91 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
92 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
93 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
94 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
95 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
96 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
97 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
98 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
99 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
100 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
101 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
102 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
103 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
104 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
105 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
106 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
107 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
108 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
109 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
110 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
111 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
112 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
113 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
114 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
115 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
116 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
117 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
118 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
119 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
120 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
121 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
122 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
123 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
124 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
125 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
126 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
127 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
128 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
129 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
130 PINMUX_FUNCTION_END,
131
132 PINMUX_MARK_BEGIN,
133 /* Hardware manual Table 25-1 (Function 0-7) */
134 VBUS_0_MARK,
135 GPI0_MARK,
136 GPI1_MARK,
137 GPI2_MARK,
138 GPI3_MARK,
139 GPI4_MARK,
140 GPI5_MARK,
141 GPI6_MARK,
142 GPI7_MARK,
143 SCIFA7_RXD_MARK,
144 SCIFA7_CTS__MARK,
145 GPO7_MARK, MFG0_OUT2_MARK,
146 GPO6_MARK, MFG1_OUT2_MARK,
147 GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
148 SCIFA0_TXD_MARK,
149 SCIFA7_TXD_MARK,
150 SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
151 GPO0_MARK,
152 GPO1_MARK,
153 GPO2_MARK, STATUS0_MARK,
154 GPO3_MARK, STATUS1_MARK,
155 GPO4_MARK, STATUS2_MARK,
156 VINT_MARK,
157 TCKON_MARK,
158 XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
159 MFG0_OUT1_MARK, PORT27_IROUT_MARK,
160 XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
161 PORT28_TPU1TO1_MARK,
162 SIM_RST_MARK, PORT29_TPU1TO1_MARK,
163 SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
164 SIM_D_MARK, PORT31_IROUT_MARK,
165 SCIFA4_TXD_MARK,
166 SCIFA4_RXD_MARK, XWUP_MARK,
167 SCIFA4_RTS__MARK,
168 SCIFA4_CTS__MARK,
169 FSIBOBT_MARK, FSIBIBT_MARK,
170 FSIBOLR_MARK, FSIBILR_MARK,
171 FSIBOSLD_MARK,
172 FSIBISLD_MARK,
173 VACK_MARK,
174 XTAL1L_MARK,
175 SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
176 SCIFA0_RXD_MARK,
177 SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
178 FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
179 FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
180 FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
181 FSICISLD_MARK, FSIDISLD_MARK,
182 FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
183 FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
184
185 FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
186 FSIAOSLD_MARK, BBIF2_TXD2_MARK,
187 FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
188 PORT53_FSICSPDIF_MARK,
189 FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
190 FSICCK_MARK, FSICOMC_MARK,
191 FSIAISLD_MARK, TPU0TO0_MARK,
192 A0_MARK, BS__MARK,
193 A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
194 A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
195 A14_MARK, KEYOUT5_MARK,
196 A15_MARK, KEYOUT4_MARK,
197 A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
198 A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
199 A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
200 A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
201 A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
202 A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
203 A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
204 A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
205 A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
206 A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
207 A26_MARK, KEYIN6_MARK,
208 KEYIN7_MARK,
209 D0_NAF0_MARK,
210 D1_NAF1_MARK,
211 D2_NAF2_MARK,
212 D3_NAF3_MARK,
213 D4_NAF4_MARK,
214 D5_NAF5_MARK,
215 D6_NAF6_MARK,
216 D7_NAF7_MARK,
217 D8_NAF8_MARK,
218 D9_NAF9_MARK,
219 D10_NAF10_MARK,
220 D11_NAF11_MARK,
221 D12_NAF12_MARK,
222 D13_NAF13_MARK,
223 D14_NAF14_MARK,
224 D15_NAF15_MARK,
225 CS4__MARK,
226 CS5A__MARK, PORT91_RDWR_MARK,
227 CS5B__MARK, FCE1__MARK,
228 CS6B__MARK, DACK0_MARK,
229 FCE0__MARK, CS6A__MARK,
230 WAIT__MARK, DREQ0_MARK,
231 RD__FSC_MARK,
232 WE0__FWE_MARK, RDWR_FWE_MARK,
233 WE1__MARK,
234 FRB_MARK,
235 CKO_MARK,
236 NBRSTOUT__MARK,
237 NBRST__MARK,
238 BBIF2_TXD_MARK,
239 BBIF2_RXD_MARK,
240 BBIF2_SYNC_MARK,
241 BBIF2_SCK_MARK,
242 SCIFA3_CTS__MARK, MFG3_IN2_MARK,
243 SCIFA3_RXD_MARK, MFG3_IN1_MARK,
244 BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
245 SCIFA3_TXD_MARK,
246 HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
247 HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
248 HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
249 HSI_TX_READY_MARK, BBIF1_TXD_MARK,
250 HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
251 PORT115_I2C_SCL3_MARK,
252 HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
253 PORT116_I2C_SDA3_MARK,
254 HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
255 HSI_TX_FLAG_MARK,
256 VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
257
258 VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
259 VIO2_HD_MARK, LCD2D1_MARK,
260 VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
261 VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
262 PORT131_KEYOUT11_MARK, LCD2D11_MARK,
263 VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
264 PORT132_KEYOUT10_MARK, LCD2D12_MARK,
265 VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
266 VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
267 VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
268 VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
269 VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
270 VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
271 VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
272 VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
273 VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
274 VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
275 VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
276 VIO2_D5_MARK, LCD2D3_MARK,
277 VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
278 VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
279 PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
280 VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
281 LCD2D18_MARK,
282 VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
283 VIO_CKO_MARK,
284 A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
285 MFG0_IN2_MARK,
286 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
287 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
288 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
289 SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
290 SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
291 SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
292 SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
293 DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
294 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
295 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
296 PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
297 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
298 PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
299 LCDD0_MARK,
300 LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
301 LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
302 LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
303 LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
304 LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
305 LCDD6_MARK,
306 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
307 LCDD8_MARK, D16_MARK,
308 LCDD9_MARK, D17_MARK,
309 LCDD10_MARK, D18_MARK,
310 LCDD11_MARK, D19_MARK,
311 LCDD12_MARK, D20_MARK,
312 LCDD13_MARK, D21_MARK,
313 LCDD14_MARK, D22_MARK,
314 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
315 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
316 LCDD17_MARK, D25_MARK,
317 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
318 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
319 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
320 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
321 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
322 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
323 LCDDCK_MARK, LCDWR__MARK,
324 LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
325 VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
326 LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
327 PORT218_VIO_CKOR_MARK,
328 LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
329 MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
330 LCDVSYN_MARK, LCDVSYN2_MARK,
331 LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
332 MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
333 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
334 VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
335
336 SCIFA1_TXD_MARK, OVCN2_MARK,
337 EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
338 SCIFA1_RTS__MARK, IDIN_MARK,
339 SCIFA1_RXD_MARK,
340 SCIFA1_CTS__MARK, MFG1_IN1_MARK,
341 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
342 MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
343 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
344 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
345 MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
346 MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
347 MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
348 MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
349 MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
350 MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
351 SCIFA6_TXD_MARK,
352 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
353 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
354 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
355 PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
356 MSIOF2R_RXD_MARK,
357 PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
358 MSIOF2R_TXD_MARK,
359 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
360 TPU1TO0_MARK,
361 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
362 TPU3TO1_MARK,
363 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
364 TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
365 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
366 MSIOF2R_TSYNC_MARK,
367 SDHICLK0_MARK,
368 SDHICD0_MARK,
369 SDHID0_0_MARK,
370 SDHID0_1_MARK,
371 SDHID0_2_MARK,
372 SDHID0_3_MARK,
373 SDHICMD0_MARK,
374 SDHIWP0_MARK,
375 SDHICLK1_MARK,
376 SDHID1_0_MARK, TS_SPSYNC2_MARK,
377 SDHID1_1_MARK, TS_SDAT2_MARK,
378 SDHID1_2_MARK, TS_SDEN2_MARK,
379 SDHID1_3_MARK, TS_SCK2_MARK,
380 SDHICMD1_MARK,
381 SDHICLK2_MARK,
382 SDHID2_0_MARK, TS_SPSYNC4_MARK,
383 SDHID2_1_MARK, TS_SDAT4_MARK,
384 SDHID2_2_MARK, TS_SDEN4_MARK,
385 SDHID2_3_MARK, TS_SCK4_MARK,
386 SDHICMD2_MARK,
387 MMCCLK0_MARK,
388 MMCD0_0_MARK,
389 MMCD0_1_MARK,
390 MMCD0_2_MARK,
391 MMCD0_3_MARK,
392 MMCD0_4_MARK, TS_SPSYNC5_MARK,
393 MMCD0_5_MARK, TS_SDAT5_MARK,
394 MMCD0_6_MARK, TS_SDEN5_MARK,
395 MMCD0_7_MARK, TS_SCK5_MARK,
396 MMCCMD0_MARK,
397 RESETOUTS__MARK, EXTAL2OUT_MARK,
398 MCP_WAIT__MCP_FRB_MARK,
399 MCP_CKO_MARK, MMCCLK1_MARK,
400 MCP_D15_MCP_NAF15_MARK,
401 MCP_D14_MCP_NAF14_MARK,
402 MCP_D13_MCP_NAF13_MARK,
403 MCP_D12_MCP_NAF12_MARK,
404 MCP_D11_MCP_NAF11_MARK,
405 MCP_D10_MCP_NAF10_MARK,
406 MCP_D9_MCP_NAF9_MARK,
407 MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
408 MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
409
410 MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
411 MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
412 MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
413 MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
414 MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
415 MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
416 MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
417 MCP_NBRSTOUT__MARK,
418 MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
419
420 /* MSEL2 special cases */
421 TSIF2_TS_XX1_MARK,
422 TSIF2_TS_XX2_MARK,
423 TSIF2_TS_XX3_MARK,
424 TSIF2_TS_XX4_MARK,
425 TSIF2_TS_XX5_MARK,
426 TSIF1_TS_XX1_MARK,
427 TSIF1_TS_XX2_MARK,
428 TSIF1_TS_XX3_MARK,
429 TSIF1_TS_XX4_MARK,
430 TSIF1_TS_XX5_MARK,
431 TSIF0_TS_XX1_MARK,
432 TSIF0_TS_XX2_MARK,
433 TSIF0_TS_XX3_MARK,
434 TSIF0_TS_XX4_MARK,
435 TSIF0_TS_XX5_MARK,
436 MST1_TS_XX1_MARK,
437 MST1_TS_XX2_MARK,
438 MST1_TS_XX3_MARK,
439 MST1_TS_XX4_MARK,
440 MST1_TS_XX5_MARK,
441 MST0_TS_XX1_MARK,
442 MST0_TS_XX2_MARK,
443 MST0_TS_XX3_MARK,
444 MST0_TS_XX4_MARK,
445 MST0_TS_XX5_MARK,
446
447 /* MSEL3 special cases */
448 SDHI0_VCCQ_MC0_ON_MARK,
449 SDHI0_VCCQ_MC0_OFF_MARK,
450 DEBUG_MON_VIO_MARK,
451 DEBUG_MON_LCDD_MARK,
452 LCDC_LCDC0_MARK,
453 LCDC_LCDC1_MARK,
454
455 /* MSEL4 special cases */
456 IRQ9_MEM_INT_MARK,
457 IRQ9_MCP_INT_MARK,
458 A11_MARK,
459 KEYOUT8_MARK,
460 TPU4TO3_MARK,
461 RESETA_N_PU_ON_MARK,
462 RESETA_N_PU_OFF_MARK,
463 EDBGREQ_PD_MARK,
464 EDBGREQ_PU_MARK,
465
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]466 PINMUX_MARK_END,
467};
468
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]469#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
470#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
471
Laurent Pinchart533743d2013-07-15 13:03:20 +0200[diff] [blame^]472static const u16 pinmux_data[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]473 /* specify valid pin states for each pin in GPIO mode */
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]474 PINMUX_DATA_GP_ALL(),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]475
476 /* Table 25-1 (Function 0-7) */
477 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
478 PINMUX_DATA(GPI0_MARK, PORT1_FN1),
479 PINMUX_DATA(GPI1_MARK, PORT2_FN1),
480 PINMUX_DATA(GPI2_MARK, PORT3_FN1),
481 PINMUX_DATA(GPI3_MARK, PORT4_FN1),
482 PINMUX_DATA(GPI4_MARK, PORT5_FN1),
483 PINMUX_DATA(GPI5_MARK, PORT6_FN1),
484 PINMUX_DATA(GPI6_MARK, PORT7_FN1),
485 PINMUX_DATA(GPI7_MARK, PORT8_FN1),
486 PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
487 PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
488 PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
489 PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
490 PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
491 PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
492 PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
493 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
494 PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
495 PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
496 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
497 PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
498 PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
499 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
500 PINMUX_DATA(GPO0_MARK, PORT20_FN1),
501 PINMUX_DATA(GPO1_MARK, PORT21_FN1),
502 PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
503 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
504 PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
505 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
506 PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
507 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
508 PINMUX_DATA(VINT_MARK, PORT25_FN1),
509 PINMUX_DATA(TCKON_MARK, PORT26_FN1),
510 PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
511 PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
512 MSEL2CR_MSEL16_1), \
513 PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
514 MSEL2CR_MSEL18_1), \
515 PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
516 PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
517 PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
518 PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
519 MSEL2CR_MSEL16_1), \
520 PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
521 MSEL2CR_MSEL18_1), \
522 PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
523 PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
524 PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
525 PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
526 PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
527 PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
528 PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
529 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
530 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
531 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
532 PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
533 PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
534 PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
535 PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
536 PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
537 PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
538 PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
539 PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
540 PINMUX_DATA(VACK_MARK, PORT40_FN1),
541 PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
542 PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
543 PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
544 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
545 PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
546 PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
547 PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
548 PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
549 PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
550 PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
551 PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
552 PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
553 PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
554 PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
555 PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
556 PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
557 PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
558 PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
559 PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
560 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
561 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
562 PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
563 PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
564 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
565 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
566 PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
567
568 PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
569 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
570 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
571 PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
572 PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
573 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
574 PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
575 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
576 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
577 PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
578 PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
579 PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
580 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
581 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
582 PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
583 PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
584 PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
585 PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
586 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
587 PINMUX_DATA(A0_MARK, PORT57_FN1), \
588 PINMUX_DATA(BS__MARK, PORT57_FN2),
589 PINMUX_DATA(A12_MARK, PORT58_FN1), \
590 PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
591 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
592 PINMUX_DATA(A13_MARK, PORT59_FN1), \
593 PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
594 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
595 PINMUX_DATA(A14_MARK, PORT60_FN1), \
596 PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
597 PINMUX_DATA(A15_MARK, PORT61_FN1), \
598 PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
599 PINMUX_DATA(A16_MARK, PORT62_FN1), \
600 PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
601 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
602 PINMUX_DATA(A17_MARK, PORT63_FN1), \
603 PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
604 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
605 PINMUX_DATA(A18_MARK, PORT64_FN1), \
606 PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
607 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
608 PINMUX_DATA(A19_MARK, PORT65_FN1), \
609 PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
610 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
611 PINMUX_DATA(A20_MARK, PORT66_FN1), \
612 PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
613 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
614 PINMUX_DATA(A21_MARK, PORT67_FN1), \
615 PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
616 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
617 PINMUX_DATA(A22_MARK, PORT68_FN1), \
618 PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
619 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
620 PINMUX_DATA(A23_MARK, PORT69_FN1), \
621 PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
622 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
623 PINMUX_DATA(A24_MARK, PORT70_FN1), \
624 PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
625 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
626 PINMUX_DATA(A25_MARK, PORT71_FN1), \
627 PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
628 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
629 PINMUX_DATA(A26_MARK, PORT72_FN1), \
630 PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
631 PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
632 PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
633 PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
634 PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
635 PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
636 PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
637 PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
638 PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
639 PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
640 PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
641 PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
642 PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
643 PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
644 PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
645 PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
646 PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
647 PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
648 PINMUX_DATA(CS4__MARK, PORT90_FN1),
649 PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
650 PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
651 PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
652 PINMUX_DATA(FCE1__MARK, PORT92_FN2),
653 PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
654 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
655 PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
656 PINMUX_DATA(CS6A__MARK, PORT94_FN2),
657 PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
658 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
659 PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
660 PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
661 PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
662 PINMUX_DATA(WE1__MARK, PORT98_FN1),
663 PINMUX_DATA(FRB_MARK, PORT99_FN1),
664 PINMUX_DATA(CKO_MARK, PORT100_FN1),
665 PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
666 PINMUX_DATA(NBRST__MARK, PORT102_FN1),
667 PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
668 PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
669 PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
670 PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
671 PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
672 PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
673 PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
674 PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
675 PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
676 PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
677 PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
678 PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
679 PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
680 PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
681 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
682 PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
683 PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
684 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
685 PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
686 PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
687 PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
688 PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
689 PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
690 PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
691 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
692 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
693 PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
694 PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
695 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
696 PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
697 PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
698 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
699 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
700 PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
701 PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
702 PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
703
704 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
705 PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
706 PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
707 PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
708 PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
709 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
710 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
711 MSEL4CR_MSEL10_1), \
712 PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
713 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
714 PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
715 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
716 PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
717 PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
718 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
719 PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
720 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
721 PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
722 PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
723 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
724 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
725 PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
726 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
727 PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
728 PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
729 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
730 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
731 PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
732 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
733 PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
734 PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
735 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
736 PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
737 PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
738 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
739 PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
740 PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
741 PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
742 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
743 PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
744 PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
745 PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
746 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
747 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
748 PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
749 PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
750 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
751 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
752 PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
753 PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
754 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
755 PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
756 PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
757 PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
758 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
759 PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
760 PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
761 PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
762 PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
763 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
764 PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
765 PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
766 PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
767 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
768 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
769 PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
770 PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
771 PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
772 PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
773 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
774 PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
775 PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
776 PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
777 PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
778 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
779 PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
780 PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
781 PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
782 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
783 PINMUX_DATA(A27_MARK, PORT149_FN1), \
784 PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
785 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
786 PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
787 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
788 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
789 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
790 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
791 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
792 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
793 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
794 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
795 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
796 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
797 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
798 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
799 PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
800 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
801 PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
802 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
803 MSEL4CR_MSEL10_0),
804 PINMUX_DATA(DINT__MARK, PORT158_FN1), \
805 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
806 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
807 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
808 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
809 PINMUX_DATA(NMI_MARK, PORT159_FN3),
810 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
811 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
812 PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
813 PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
814 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
815 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
816 PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
817 PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
818 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
819 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
820 PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
821 PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
822 MSEL4CR_MSEL20_1), \
823 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
824 PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
825 PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
826 MSEL4CR_MSEL20_1), \
827 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
828 PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
829 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
830 MSEL4CR_MSEL20_1), \
831 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
832 PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
833 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
834 MSEL4CR_MSEL20_1),
835 PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
836 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
837 MSEL4CR_MSEL20_1), \
838 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
839 PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
840 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
841 PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
842 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
843 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
844 PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
845 PINMUX_DATA(D16_MARK, PORT200_FN6),
846 PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
847 PINMUX_DATA(D17_MARK, PORT201_FN6),
848 PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
849 PINMUX_DATA(D18_MARK, PORT202_FN6),
850 PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
851 PINMUX_DATA(D19_MARK, PORT203_FN6),
852 PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
853 PINMUX_DATA(D20_MARK, PORT204_FN6),
854 PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
855 PINMUX_DATA(D21_MARK, PORT205_FN6),
856 PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
857 PINMUX_DATA(D22_MARK, PORT206_FN6),
858 PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
859 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
860 PINMUX_DATA(D23_MARK, PORT207_FN6),
861 PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
862 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
863 PINMUX_DATA(D24_MARK, PORT208_FN6),
864 PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
865 PINMUX_DATA(D25_MARK, PORT209_FN6),
866 PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
867 PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
868 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
869 PINMUX_DATA(D26_MARK, PORT210_FN6),
870 PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
871 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
872 PINMUX_DATA(D27_MARK, PORT211_FN6),
873 PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
874 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
875 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
876 PINMUX_DATA(D28_MARK, PORT212_FN6),
877 PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
878 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
879 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
880 PINMUX_DATA(D29_MARK, PORT213_FN6),
881 PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
882 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
883 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
884 PINMUX_DATA(D30_MARK, PORT214_FN6),
885 PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
886 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
887 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
888 PINMUX_DATA(D31_MARK, PORT215_FN6),
889 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
890 PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
891 PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
892 PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
893 PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
894 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
895 PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
896 MSEL4CR_MSEL26_1), \
897 PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
898 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
899 PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
900 PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
901 PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
902 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
903 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
904 PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
905 PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
906 PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
907 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
908 PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
909 MSEL4CR_MSEL26_1), \
910 PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
911 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
912 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
913 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
914 PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
915 PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
916 PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
917 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
918 PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
919 MSEL4CR_MSEL26_1), \
920 PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
921 PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
922 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
923 PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
924 PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
925 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
926 PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
927 MSEL4CR_MSEL26_1), \
928 PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
929
930 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
931 PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
932 PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
933 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
934 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
935 PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
936 PINMUX_DATA(IDIN_MARK, PORT227_FN4),
937 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
938 PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
939 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
940 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
941 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
942 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
943 PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
944 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
945 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
946 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
947 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
948 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
949 PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
950 PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
951 MSEL4CR_MSEL26_0), \
952 PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
953 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
954 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
955 PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
956 MSEL4CR_MSEL26_0), \
957 PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
958 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
959 PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
960 MSEL2CR_MSEL16_0),
961 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
962 PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
963 MSEL2CR_MSEL16_0),
964 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
965 PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
966 MSEL4CR_MSEL26_0), \
967 PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
968 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
969 PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
970 MSEL4CR_MSEL26_0), \
971 PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
972 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
973 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
974 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
975 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
976 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
977 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
978 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
979 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
980 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
981 PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
982 MSEL4CR_MSEL20_0), \
983 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
984 PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
985 PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
986 PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
987 MSEL4CR_MSEL20_0), \
988 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
989 PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
990 PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
991 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
992 MSEL4CR_MSEL20_0), \
993 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
994 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
995 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
996 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
997 MSEL4CR_MSEL20_0), \
998 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
999 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
1000 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
1001 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
1002 MSEL4CR_MSEL20_0), \
1003 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1004 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1005 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1006 PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1007 MSEL2CR_MSEL18_0), \
1008 PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1009 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1010 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1011 PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1012 MSEL2CR_MSEL18_0), \
1013 PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1014 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1015 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1016 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1017 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1018 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1019 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1020 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1021 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1022 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1023 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1024 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1025 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1026 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1027 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1028 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1029 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1030 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1031 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1032 PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1033 PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1034 PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1035 PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1036 PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1037 PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1038 PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1039 PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1040 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1041 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1042 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1043 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1044 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1045 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1046 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1047 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1048 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1049 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1050 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1051 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1052 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1053 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1054 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1055 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1056 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1057 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1058 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1059 PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1060 PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1061 PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1062 PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1063 PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1064 PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1065 PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1066 PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1067 PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1068 PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1069 PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1070 PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1071 PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1072
1073 PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1074 PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1075 PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1076 PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1077 PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1078 PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1079 PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1080 PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1081 PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1082 PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1083 PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1084 PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1085 PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1086 PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1087 PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1088 PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1089 PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1090
1091 /* MSEL2 special cases */
1092 PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1093 MSEL2CR_MSEL12_0),
1094 PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1095 MSEL2CR_MSEL12_1),
1096 PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1097 MSEL2CR_MSEL12_0),
1098 PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1099 MSEL2CR_MSEL12_1),
1100 PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1101 MSEL2CR_MSEL12_0),
1102 PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1103 MSEL2CR_MSEL9_0),
1104 PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1105 MSEL2CR_MSEL9_1),
1106 PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1107 MSEL2CR_MSEL9_0),
1108 PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1109 MSEL2CR_MSEL9_1),
1110 PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1111 MSEL2CR_MSEL9_0),
1112 PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1113 MSEL2CR_MSEL6_0),
1114 PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1115 MSEL2CR_MSEL6_1),
1116 PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1117 MSEL2CR_MSEL6_0),
1118 PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1119 MSEL2CR_MSEL6_1),
1120 PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1121 MSEL2CR_MSEL6_0),
1122 PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1123 MSEL2CR_MSEL3_0),
1124 PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1125 MSEL2CR_MSEL3_1),
1126 PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1127 MSEL2CR_MSEL3_0),
1128 PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1129 MSEL2CR_MSEL3_1),
1130 PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1131 MSEL2CR_MSEL3_0),
1132 PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1133 MSEL2CR_MSEL0_0),
1134 PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1135 MSEL2CR_MSEL0_1),
1136 PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1137 MSEL2CR_MSEL0_0),
1138 PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1139 MSEL2CR_MSEL0_1),
1140 PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1141 MSEL2CR_MSEL0_0),
1142
1143 /* MSEL3 special cases */
1144 PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1145 PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1146 PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1147 PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1148 PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1149 PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1150
1151 /* MSEL4 special cases */
1152 PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1153 PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1154 PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1155 PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1156 PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1157 PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1158 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1159 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1160 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1161};
1162
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1163#define SH73A0_PIN(pin, cfgs) \
1164 { \
1165 .name = __stringify(PORT##pin), \
1166 .enum_id = PORT##pin##_DATA, \
1167 .configs = cfgs, \
1168 }
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1169
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1170#define __I (SH_PFC_PIN_CFG_INPUT)
1171#define __O (SH_PFC_PIN_CFG_OUTPUT)
1172#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1173#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1174#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1175#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1176
1177#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
1178#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
1179#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
1180#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
1181#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
1182#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
1183#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
1184#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
1185
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1186static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1187 /* Table 25-1 (I/O and Pull U/D) */
1188 SH73A0_PIN_I_PD(0),
1189 SH73A0_PIN_I_PU(1),
1190 SH73A0_PIN_I_PU(2),
1191 SH73A0_PIN_I_PU(3),
1192 SH73A0_PIN_I_PU(4),
1193 SH73A0_PIN_I_PU(5),
1194 SH73A0_PIN_I_PU(6),
1195 SH73A0_PIN_I_PU(7),
1196 SH73A0_PIN_I_PU(8),
1197 SH73A0_PIN_I_PD(9),
1198 SH73A0_PIN_I_PD(10),
1199 SH73A0_PIN_I_PU_PD(11),
1200 SH73A0_PIN_IO_PU_PD(12),
1201 SH73A0_PIN_IO_PU_PD(13),
1202 SH73A0_PIN_IO_PU_PD(14),
1203 SH73A0_PIN_IO_PU_PD(15),
1204 SH73A0_PIN_IO_PD(16),
1205 SH73A0_PIN_IO_PD(17),
1206 SH73A0_PIN_IO_PU(18),
1207 SH73A0_PIN_IO_PU(19),
1208 SH73A0_PIN_O(20),
1209 SH73A0_PIN_O(21),
1210 SH73A0_PIN_O(22),
1211 SH73A0_PIN_O(23),
1212 SH73A0_PIN_O(24),
1213 SH73A0_PIN_I_PD(25),
1214 SH73A0_PIN_I_PD(26),
1215 SH73A0_PIN_IO_PU(27),
1216 SH73A0_PIN_IO_PU(28),
1217 SH73A0_PIN_IO_PD(29),
1218 SH73A0_PIN_IO_PD(30),
1219 SH73A0_PIN_IO_PU(31),
1220 SH73A0_PIN_IO_PD(32),
1221 SH73A0_PIN_I_PU_PD(33),
1222 SH73A0_PIN_IO_PD(34),
1223 SH73A0_PIN_I_PU_PD(35),
1224 SH73A0_PIN_IO_PD(36),
1225 SH73A0_PIN_IO(37),
1226 SH73A0_PIN_O(38),
1227 SH73A0_PIN_I_PU(39),
1228 SH73A0_PIN_I_PU_PD(40),
1229 SH73A0_PIN_O(41),
1230 SH73A0_PIN_IO_PD(42),
1231 SH73A0_PIN_IO_PU_PD(43),
1232 SH73A0_PIN_IO_PU_PD(44),
1233 SH73A0_PIN_IO_PD(45),
1234 SH73A0_PIN_IO_PD(46),
1235 SH73A0_PIN_IO_PD(47),
1236 SH73A0_PIN_I_PD(48),
1237 SH73A0_PIN_IO_PU_PD(49),
1238 SH73A0_PIN_IO_PD(50),
1239 SH73A0_PIN_IO_PD(51),
1240 SH73A0_PIN_O(52),
1241 SH73A0_PIN_IO_PU_PD(53),
1242 SH73A0_PIN_IO_PU_PD(54),
1243 SH73A0_PIN_IO_PD(55),
1244 SH73A0_PIN_I_PU_PD(56),
1245 SH73A0_PIN_IO(57),
1246 SH73A0_PIN_IO(58),
1247 SH73A0_PIN_IO(59),
1248 SH73A0_PIN_IO(60),
1249 SH73A0_PIN_IO(61),
1250 SH73A0_PIN_IO_PD(62),
1251 SH73A0_PIN_IO_PD(63),
1252 SH73A0_PIN_IO_PU_PD(64),
1253 SH73A0_PIN_IO_PD(65),
1254 SH73A0_PIN_IO_PU_PD(66),
1255 SH73A0_PIN_IO_PU_PD(67),
1256 SH73A0_PIN_IO_PU_PD(68),
1257 SH73A0_PIN_IO_PU_PD(69),
1258 SH73A0_PIN_IO_PU_PD(70),
1259 SH73A0_PIN_IO_PU_PD(71),
1260 SH73A0_PIN_IO_PU_PD(72),
1261 SH73A0_PIN_I_PU_PD(73),
1262 SH73A0_PIN_IO_PU(74),
1263 SH73A0_PIN_IO_PU(75),
1264 SH73A0_PIN_IO_PU(76),
1265 SH73A0_PIN_IO_PU(77),
1266 SH73A0_PIN_IO_PU(78),
1267 SH73A0_PIN_IO_PU(79),
1268 SH73A0_PIN_IO_PU(80),
1269 SH73A0_PIN_IO_PU(81),
1270 SH73A0_PIN_IO_PU(82),
1271 SH73A0_PIN_IO_PU(83),
1272 SH73A0_PIN_IO_PU(84),
1273 SH73A0_PIN_IO_PU(85),
1274 SH73A0_PIN_IO_PU(86),
1275 SH73A0_PIN_IO_PU(87),
1276 SH73A0_PIN_IO_PU(88),
1277 SH73A0_PIN_IO_PU(89),
1278 SH73A0_PIN_O(90),
1279 SH73A0_PIN_IO_PU(91),
1280 SH73A0_PIN_O(92),
1281 SH73A0_PIN_IO_PU(93),
1282 SH73A0_PIN_O(94),
1283 SH73A0_PIN_I_PU_PD(95),
1284 SH73A0_PIN_IO(96),
1285 SH73A0_PIN_IO(97),
1286 SH73A0_PIN_IO(98),
1287 SH73A0_PIN_I_PU(99),
1288 SH73A0_PIN_O(100),
1289 SH73A0_PIN_O(101),
1290 SH73A0_PIN_I_PU(102),
1291 SH73A0_PIN_IO_PD(103),
1292 SH73A0_PIN_I_PU_PD(104),
1293 SH73A0_PIN_I_PD(105),
1294 SH73A0_PIN_I_PD(106),
1295 SH73A0_PIN_I_PU_PD(107),
1296 SH73A0_PIN_I_PU_PD(108),
1297 SH73A0_PIN_IO_PD(109),
1298 SH73A0_PIN_IO_PD(110),
1299 SH73A0_PIN_IO_PU_PD(111),
1300 SH73A0_PIN_IO_PU_PD(112),
1301 SH73A0_PIN_IO_PU_PD(113),
1302 SH73A0_PIN_IO_PD(114),
1303 SH73A0_PIN_IO_PU(115),
1304 SH73A0_PIN_IO_PU(116),
1305 SH73A0_PIN_IO_PU_PD(117),
1306 SH73A0_PIN_IO_PU_PD(118),
1307 SH73A0_PIN_IO_PD(128),
1308 SH73A0_PIN_IO_PD(129),
1309 SH73A0_PIN_IO_PU_PD(130),
1310 SH73A0_PIN_IO_PD(131),
1311 SH73A0_PIN_IO_PD(132),
1312 SH73A0_PIN_IO_PD(133),
1313 SH73A0_PIN_IO_PU_PD(134),
1314 SH73A0_PIN_IO_PU_PD(135),
1315 SH73A0_PIN_IO_PU_PD(136),
1316 SH73A0_PIN_IO_PU_PD(137),
1317 SH73A0_PIN_IO_PD(138),
1318 SH73A0_PIN_IO_PD(139),
1319 SH73A0_PIN_IO_PD(140),
1320 SH73A0_PIN_IO_PD(141),
1321 SH73A0_PIN_IO_PD(142),
1322 SH73A0_PIN_IO_PD(143),
1323 SH73A0_PIN_IO_PU_PD(144),
1324 SH73A0_PIN_IO_PD(145),
1325 SH73A0_PIN_IO_PU_PD(146),
1326 SH73A0_PIN_IO_PU_PD(147),
1327 SH73A0_PIN_IO_PU_PD(148),
1328 SH73A0_PIN_IO_PU_PD(149),
1329 SH73A0_PIN_I_PU_PD(150),
1330 SH73A0_PIN_IO_PU_PD(151),
1331 SH73A0_PIN_IO_PU_PD(152),
1332 SH73A0_PIN_IO_PD(153),
1333 SH73A0_PIN_IO_PD(154),
1334 SH73A0_PIN_I_PU_PD(155),
1335 SH73A0_PIN_IO_PU_PD(156),
1336 SH73A0_PIN_I_PD(157),
1337 SH73A0_PIN_IO_PD(158),
1338 SH73A0_PIN_IO_PU_PD(159),
1339 SH73A0_PIN_IO_PU_PD(160),
1340 SH73A0_PIN_I_PU_PD(161),
1341 SH73A0_PIN_I_PU_PD(162),
1342 SH73A0_PIN_IO_PU_PD(163),
1343 SH73A0_PIN_I_PU_PD(164),
1344 SH73A0_PIN_IO_PD(192),
1345 SH73A0_PIN_IO_PU_PD(193),
1346 SH73A0_PIN_IO_PD(194),
1347 SH73A0_PIN_IO_PU_PD(195),
1348 SH73A0_PIN_IO_PD(196),
1349 SH73A0_PIN_IO_PD(197),
1350 SH73A0_PIN_IO_PD(198),
1351 SH73A0_PIN_IO_PD(199),
1352 SH73A0_PIN_IO_PU_PD(200),
1353 SH73A0_PIN_IO_PU_PD(201),
1354 SH73A0_PIN_IO_PU_PD(202),
1355 SH73A0_PIN_IO_PU_PD(203),
1356 SH73A0_PIN_IO_PU_PD(204),
1357 SH73A0_PIN_IO_PU_PD(205),
1358 SH73A0_PIN_IO_PU_PD(206),
1359 SH73A0_PIN_IO_PD(207),
1360 SH73A0_PIN_IO_PD(208),
1361 SH73A0_PIN_IO_PD(209),
1362 SH73A0_PIN_IO_PD(210),
1363 SH73A0_PIN_IO_PD(211),
1364 SH73A0_PIN_IO_PD(212),
1365 SH73A0_PIN_IO_PD(213),
1366 SH73A0_PIN_IO_PU_PD(214),
1367 SH73A0_PIN_IO_PU_PD(215),
1368 SH73A0_PIN_IO_PD(216),
1369 SH73A0_PIN_IO_PD(217),
1370 SH73A0_PIN_O(218),
1371 SH73A0_PIN_IO_PD(219),
1372 SH73A0_PIN_IO_PD(220),
1373 SH73A0_PIN_IO_PU_PD(221),
1374 SH73A0_PIN_IO_PU_PD(222),
1375 SH73A0_PIN_I_PU_PD(223),
1376 SH73A0_PIN_I_PU_PD(224),
1377 SH73A0_PIN_IO_PU_PD(225),
1378 SH73A0_PIN_O(226),
1379 SH73A0_PIN_IO_PU_PD(227),
1380 SH73A0_PIN_I_PU_PD(228),
1381 SH73A0_PIN_I_PD(229),
1382 SH73A0_PIN_IO(230),
1383 SH73A0_PIN_IO_PU_PD(231),
1384 SH73A0_PIN_IO_PU_PD(232),
1385 SH73A0_PIN_I_PU_PD(233),
1386 SH73A0_PIN_IO_PU_PD(234),
1387 SH73A0_PIN_IO_PU_PD(235),
1388 SH73A0_PIN_IO_PU_PD(236),
1389 SH73A0_PIN_IO_PD(237),
1390 SH73A0_PIN_IO_PU_PD(238),
1391 SH73A0_PIN_IO_PU_PD(239),
1392 SH73A0_PIN_IO_PU_PD(240),
1393 SH73A0_PIN_O(241),
1394 SH73A0_PIN_I_PD(242),
1395 SH73A0_PIN_IO_PU_PD(243),
1396 SH73A0_PIN_IO_PU_PD(244),
1397 SH73A0_PIN_IO_PU_PD(245),
1398 SH73A0_PIN_IO_PU_PD(246),
1399 SH73A0_PIN_IO_PU_PD(247),
1400 SH73A0_PIN_IO_PU_PD(248),
1401 SH73A0_PIN_IO_PU_PD(249),
1402 SH73A0_PIN_IO_PU_PD(250),
1403 SH73A0_PIN_IO_PU_PD(251),
1404 SH73A0_PIN_IO_PU_PD(252),
1405 SH73A0_PIN_IO_PU_PD(253),
1406 SH73A0_PIN_IO_PU_PD(254),
1407 SH73A0_PIN_IO_PU_PD(255),
1408 SH73A0_PIN_IO_PU_PD(256),
1409 SH73A0_PIN_IO_PU_PD(257),
1410 SH73A0_PIN_IO_PU_PD(258),
1411 SH73A0_PIN_IO_PU_PD(259),
1412 SH73A0_PIN_IO_PU_PD(260),
1413 SH73A0_PIN_IO_PU_PD(261),
1414 SH73A0_PIN_IO_PU_PD(262),
1415 SH73A0_PIN_IO_PU_PD(263),
1416 SH73A0_PIN_IO_PU_PD(264),
1417 SH73A0_PIN_IO_PU_PD(265),
1418 SH73A0_PIN_IO_PU_PD(266),
1419 SH73A0_PIN_IO_PU_PD(267),
1420 SH73A0_PIN_IO_PU_PD(268),
1421 SH73A0_PIN_IO_PU_PD(269),
1422 SH73A0_PIN_IO_PU_PD(270),
1423 SH73A0_PIN_IO_PU_PD(271),
1424 SH73A0_PIN_IO_PU_PD(272),
1425 SH73A0_PIN_IO_PU_PD(273),
1426 SH73A0_PIN_IO_PU_PD(274),
1427 SH73A0_PIN_IO_PU_PD(275),
1428 SH73A0_PIN_IO_PU_PD(276),
1429 SH73A0_PIN_IO_PU_PD(277),
1430 SH73A0_PIN_IO_PU_PD(278),
1431 SH73A0_PIN_IO_PU_PD(279),
1432 SH73A0_PIN_IO_PU_PD(280),
1433 SH73A0_PIN_O(281),
1434 SH73A0_PIN_O(282),
1435 SH73A0_PIN_I_PU(288),
1436 SH73A0_PIN_IO_PU_PD(289),
1437 SH73A0_PIN_IO_PU_PD(290),
1438 SH73A0_PIN_IO_PU_PD(291),
1439 SH73A0_PIN_IO_PU_PD(292),
1440 SH73A0_PIN_IO_PU_PD(293),
1441 SH73A0_PIN_IO_PU_PD(294),
1442 SH73A0_PIN_IO_PU_PD(295),
1443 SH73A0_PIN_IO_PU_PD(296),
1444 SH73A0_PIN_IO_PU_PD(297),
1445 SH73A0_PIN_IO_PU_PD(298),
1446 SH73A0_PIN_IO_PU_PD(299),
1447 SH73A0_PIN_IO_PU_PD(300),
1448 SH73A0_PIN_IO_PU_PD(301),
1449 SH73A0_PIN_IO_PU_PD(302),
1450 SH73A0_PIN_IO_PU_PD(303),
1451 SH73A0_PIN_IO_PU_PD(304),
1452 SH73A0_PIN_IO_PU_PD(305),
1453 SH73A0_PIN_O(306),
1454 SH73A0_PIN_O(307),
1455 SH73A0_PIN_I_PU(308),
1456 SH73A0_PIN_O(309),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1457};
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1458
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]1459static const struct pinmux_range pinmux_ranges[] = {
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]1460 {.begin = 0, .end = 118,},
1461 {.begin = 128, .end = 164,},
1462 {.begin = 192, .end = 282,},
1463 {.begin = 288, .end = 309,},
1464};
1465
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]1466/* Pin numbers for pins without a corresponding GPIO port number are computed
1467 * from the row and column numbers with a 1000 offset to avoid collisions with
1468 * GPIO port numbers.
1469 */
1470#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1471
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]1472/* - BSC -------------------------------------------------------------------- */
1473static const unsigned int bsc_data_0_7_pins[] = {
1474 /* D[0:7] */
1475 74, 75, 76, 77, 78, 79, 80, 81,
1476};
1477static const unsigned int bsc_data_0_7_mux[] = {
1478 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1479 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1480};
1481static const unsigned int bsc_data_8_15_pins[] = {
1482 /* D[8:15] */
1483 82, 83, 84, 85, 86, 87, 88, 89,
1484};
1485static const unsigned int bsc_data_8_15_mux[] = {
1486 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1487 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1488};
1489static const unsigned int bsc_cs4_pins[] = {
1490 /* CS */
1491 90,
1492};
1493static const unsigned int bsc_cs4_mux[] = {
1494 CS4__MARK,
1495};
1496static const unsigned int bsc_cs5_a_pins[] = {
1497 /* CS */
1498 91,
1499};
1500static const unsigned int bsc_cs5_a_mux[] = {
1501 CS5A__MARK,
1502};
1503static const unsigned int bsc_cs5_b_pins[] = {
1504 /* CS */
1505 92,
1506};
1507static const unsigned int bsc_cs5_b_mux[] = {
1508 CS5B__MARK,
1509};
1510static const unsigned int bsc_cs6_a_pins[] = {
1511 /* CS */
1512 94,
1513};
1514static const unsigned int bsc_cs6_a_mux[] = {
1515 CS6A__MARK,
1516};
1517static const unsigned int bsc_cs6_b_pins[] = {
1518 /* CS */
1519 93,
1520};
1521static const unsigned int bsc_cs6_b_mux[] = {
1522 CS6B__MARK,
1523};
1524static const unsigned int bsc_rd_pins[] = {
1525 /* RD */
1526 96,
1527};
1528static const unsigned int bsc_rd_mux[] = {
1529 RD__FSC_MARK,
1530};
1531static const unsigned int bsc_rdwr_0_pins[] = {
1532 /* RDWR */
1533 91,
1534};
1535static const unsigned int bsc_rdwr_0_mux[] = {
1536 PORT91_RDWR_MARK,
1537};
1538static const unsigned int bsc_rdwr_1_pins[] = {
1539 /* RDWR */
1540 97,
1541};
1542static const unsigned int bsc_rdwr_1_mux[] = {
1543 RDWR_FWE_MARK,
1544};
1545static const unsigned int bsc_rdwr_2_pins[] = {
1546 /* RDWR */
1547 149,
1548};
1549static const unsigned int bsc_rdwr_2_mux[] = {
1550 PORT149_RDWR_MARK,
1551};
1552static const unsigned int bsc_we0_pins[] = {
1553 /* WE0 */
1554 97,
1555};
1556static const unsigned int bsc_we0_mux[] = {
1557 WE0__FWE_MARK,
1558};
1559static const unsigned int bsc_we1_pins[] = {
1560 /* WE1 */
1561 98,
1562};
1563static const unsigned int bsc_we1_mux[] = {
1564 WE1__MARK,
1565};
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]1566/* - FSIA ------------------------------------------------------------------- */
1567static const unsigned int fsia_mclk_in_pins[] = {
1568 /* CK */
1569 49,
1570};
1571static const unsigned int fsia_mclk_in_mux[] = {
1572 FSIACK_MARK,
1573};
1574static const unsigned int fsia_mclk_out_pins[] = {
1575 /* OMC */
1576 49,
1577};
1578static const unsigned int fsia_mclk_out_mux[] = {
1579 FSIAOMC_MARK,
1580};
1581static const unsigned int fsia_sclk_in_pins[] = {
1582 /* ILR, IBT */
1583 50, 51,
1584};
1585static const unsigned int fsia_sclk_in_mux[] = {
1586 FSIAILR_MARK, FSIAIBT_MARK,
1587};
1588static const unsigned int fsia_sclk_out_pins[] = {
1589 /* OLR, OBT */
1590 50, 51,
1591};
1592static const unsigned int fsia_sclk_out_mux[] = {
1593 FSIAOLR_MARK, FSIAOBT_MARK,
1594};
1595static const unsigned int fsia_data_in_pins[] = {
1596 /* ISLD */
1597 55,
1598};
1599static const unsigned int fsia_data_in_mux[] = {
1600 FSIAISLD_MARK,
1601};
1602static const unsigned int fsia_data_out_pins[] = {
1603 /* OSLD */
1604 52,
1605};
1606static const unsigned int fsia_data_out_mux[] = {
1607 FSIAOSLD_MARK,
1608};
1609static const unsigned int fsia_spdif_pins[] = {
1610 /* SPDIF */
1611 53,
1612};
1613static const unsigned int fsia_spdif_mux[] = {
1614 FSIASPDIF_MARK,
1615};
1616/* - FSIB ------------------------------------------------------------------- */
1617static const unsigned int fsib_mclk_in_pins[] = {
1618 /* CK */
1619 54,
1620};
1621static const unsigned int fsib_mclk_in_mux[] = {
1622 FSIBCK_MARK,
1623};
1624static const unsigned int fsib_mclk_out_pins[] = {
1625 /* OMC */
1626 54,
1627};
1628static const unsigned int fsib_mclk_out_mux[] = {
1629 FSIBOMC_MARK,
1630};
1631static const unsigned int fsib_sclk_in_pins[] = {
1632 /* ILR, IBT */
1633 37, 36,
1634};
1635static const unsigned int fsib_sclk_in_mux[] = {
1636 FSIBILR_MARK, FSIBIBT_MARK,
1637};
1638static const unsigned int fsib_sclk_out_pins[] = {
1639 /* OLR, OBT */
1640 37, 36,
1641};
1642static const unsigned int fsib_sclk_out_mux[] = {
1643 FSIBOLR_MARK, FSIBOBT_MARK,
1644};
1645static const unsigned int fsib_data_in_pins[] = {
1646 /* ISLD */
1647 39,
1648};
1649static const unsigned int fsib_data_in_mux[] = {
1650 FSIBISLD_MARK,
1651};
1652static const unsigned int fsib_data_out_pins[] = {
1653 /* OSLD */
1654 38,
1655};
1656static const unsigned int fsib_data_out_mux[] = {
1657 FSIBOSLD_MARK,
1658};
1659static const unsigned int fsib_spdif_pins[] = {
1660 /* SPDIF */
1661 53,
1662};
1663static const unsigned int fsib_spdif_mux[] = {
1664 FSIBSPDIF_MARK,
1665};
1666/* - FSIC ------------------------------------------------------------------- */
1667static const unsigned int fsic_mclk_in_pins[] = {
1668 /* CK */
1669 54,
1670};
1671static const unsigned int fsic_mclk_in_mux[] = {
1672 FSICCK_MARK,
1673};
1674static const unsigned int fsic_mclk_out_pins[] = {
1675 /* OMC */
1676 54,
1677};
1678static const unsigned int fsic_mclk_out_mux[] = {
1679 FSICOMC_MARK,
1680};
1681static const unsigned int fsic_sclk_in_pins[] = {
1682 /* ILR, IBT */
1683 46, 45,
1684};
1685static const unsigned int fsic_sclk_in_mux[] = {
1686 FSICILR_MARK, FSICIBT_MARK,
1687};
1688static const unsigned int fsic_sclk_out_pins[] = {
1689 /* OLR, OBT */
1690 46, 45,
1691};
1692static const unsigned int fsic_sclk_out_mux[] = {
1693 FSICOLR_MARK, FSICOBT_MARK,
1694};
1695static const unsigned int fsic_data_in_pins[] = {
1696 /* ISLD */
1697 48,
1698};
1699static const unsigned int fsic_data_in_mux[] = {
1700 FSICISLD_MARK,
1701};
1702static const unsigned int fsic_data_out_pins[] = {
1703 /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1704 47, 44, 42, 16,
1705};
1706static const unsigned int fsic_data_out_mux[] = {
1707 FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1708};
1709static const unsigned int fsic_spdif_0_pins[] = {
1710 /* SPDIF */
1711 53,
1712};
1713static const unsigned int fsic_spdif_0_mux[] = {
1714 PORT53_FSICSPDIF_MARK,
1715};
1716static const unsigned int fsic_spdif_1_pins[] = {
1717 /* SPDIF */
1718 47,
1719};
1720static const unsigned int fsic_spdif_1_mux[] = {
1721 PORT47_FSICSPDIF_MARK,
1722};
1723/* - FSID ------------------------------------------------------------------- */
1724static const unsigned int fsid_sclk_in_pins[] = {
1725 /* ILR, IBT */
1726 46, 45,
1727};
1728static const unsigned int fsid_sclk_in_mux[] = {
1729 FSIDILR_MARK, FSIDIBT_MARK,
1730};
1731static const unsigned int fsid_sclk_out_pins[] = {
1732 /* OLR, OBT */
1733 46, 45,
1734};
1735static const unsigned int fsid_sclk_out_mux[] = {
1736 FSIDOLR_MARK, FSIDOBT_MARK,
1737};
1738static const unsigned int fsid_data_in_pins[] = {
1739 /* ISLD */
1740 48,
1741};
1742static const unsigned int fsid_data_in_mux[] = {
1743 FSIDISLD_MARK,
1744};
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]1745/* - I2C2 ------------------------------------------------------------------- */
1746static const unsigned int i2c2_0_pins[] = {
1747 /* SCL, SDA */
1748 237, 236,
1749};
1750static const unsigned int i2c2_0_mux[] = {
1751 PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1752};
1753static const unsigned int i2c2_1_pins[] = {
1754 /* SCL, SDA */
1755 27, 28,
1756};
1757static const unsigned int i2c2_1_mux[] = {
1758 PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1759};
1760static const unsigned int i2c2_2_pins[] = {
1761 /* SCL, SDA */
1762 115, 116,
1763};
1764static const unsigned int i2c2_2_mux[] = {
1765 PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1766};
1767/* - I2C3 ------------------------------------------------------------------- */
1768static const unsigned int i2c3_0_pins[] = {
1769 /* SCL, SDA */
1770 248, 249,
1771};
1772static const unsigned int i2c3_0_mux[] = {
1773 PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1774};
1775static const unsigned int i2c3_1_pins[] = {
1776 /* SCL, SDA */
1777 27, 28,
1778};
1779static const unsigned int i2c3_1_mux[] = {
1780 PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1781};
1782static const unsigned int i2c3_2_pins[] = {
1783 /* SCL, SDA */
1784 115, 116,
1785};
1786static const unsigned int i2c3_2_mux[] = {
1787 PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1788};
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]1789/* - IrDA ------------------------------------------------------------------- */
1790static const unsigned int irda_0_pins[] = {
1791 /* OUT, IN, FIRSEL */
1792 241, 242, 243,
1793};
1794static const unsigned int irda_0_mux[] = {
1795 PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1796};
1797static const unsigned int irda_1_pins[] = {
1798 /* OUT, IN, FIRSEL */
1799 49, 53, 54,
1800};
1801static const unsigned int irda_1_mux[] = {
1802 PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1803};
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]1804/* - KEYSC ------------------------------------------------------------------ */
1805static const unsigned int keysc_in5_pins[] = {
1806 /* KEYIN[0:4] */
1807 66, 67, 68, 69, 70,
1808};
1809static const unsigned int keysc_in5_mux[] = {
1810 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1811 KEYIN4_MARK,
1812};
1813static const unsigned int keysc_in6_pins[] = {
1814 /* KEYIN[0:5] */
1815 66, 67, 68, 69, 70, 71,
1816};
1817static const unsigned int keysc_in6_mux[] = {
1818 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1819 KEYIN4_MARK, KEYIN5_MARK,
1820};
1821static const unsigned int keysc_in7_pins[] = {
1822 /* KEYIN[0:6] */
1823 66, 67, 68, 69, 70, 71, 72,
1824};
1825static const unsigned int keysc_in7_mux[] = {
1826 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1827 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1828};
1829static const unsigned int keysc_in8_pins[] = {
1830 /* KEYIN[0:7] */
1831 66, 67, 68, 69, 70, 71, 72, 73,
1832};
1833static const unsigned int keysc_in8_mux[] = {
1834 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1835 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1836};
1837static const unsigned int keysc_out04_pins[] = {
1838 /* KEYOUT[0:4] */
1839 65, 64, 63, 62, 61,
1840};
1841static const unsigned int keysc_out04_mux[] = {
1842 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1843};
1844static const unsigned int keysc_out5_pins[] = {
1845 /* KEYOUT5 */
1846 60,
1847};
1848static const unsigned int keysc_out5_mux[] = {
1849 KEYOUT5_MARK,
1850};
1851static const unsigned int keysc_out6_0_pins[] = {
1852 /* KEYOUT6 */
1853 59,
1854};
1855static const unsigned int keysc_out6_0_mux[] = {
1856 PORT59_KEYOUT6_MARK,
1857};
1858static const unsigned int keysc_out6_1_pins[] = {
1859 /* KEYOUT6 */
1860 131,
1861};
1862static const unsigned int keysc_out6_1_mux[] = {
1863 PORT131_KEYOUT6_MARK,
1864};
1865static const unsigned int keysc_out6_2_pins[] = {
1866 /* KEYOUT6 */
1867 143,
1868};
1869static const unsigned int keysc_out6_2_mux[] = {
1870 PORT143_KEYOUT6_MARK,
1871};
1872static const unsigned int keysc_out7_0_pins[] = {
1873 /* KEYOUT7 */
1874 58,
1875};
1876static const unsigned int keysc_out7_0_mux[] = {
1877 PORT58_KEYOUT7_MARK,
1878};
1879static const unsigned int keysc_out7_1_pins[] = {
1880 /* KEYOUT7 */
1881 132,
1882};
1883static const unsigned int keysc_out7_1_mux[] = {
1884 PORT132_KEYOUT7_MARK,
1885};
1886static const unsigned int keysc_out7_2_pins[] = {
1887 /* KEYOUT7 */
1888 144,
1889};
1890static const unsigned int keysc_out7_2_mux[] = {
1891 PORT144_KEYOUT7_MARK,
1892};
1893static const unsigned int keysc_out8_0_pins[] = {
1894 /* KEYOUT8 */
1895 PIN_NUMBER(6, 26),
1896};
1897static const unsigned int keysc_out8_0_mux[] = {
1898 KEYOUT8_MARK,
1899};
1900static const unsigned int keysc_out8_1_pins[] = {
1901 /* KEYOUT8 */
1902 136,
1903};
1904static const unsigned int keysc_out8_1_mux[] = {
1905 PORT136_KEYOUT8_MARK,
1906};
1907static const unsigned int keysc_out8_2_pins[] = {
1908 /* KEYOUT8 */
1909 138,
1910};
1911static const unsigned int keysc_out8_2_mux[] = {
1912 PORT138_KEYOUT8_MARK,
1913};
1914static const unsigned int keysc_out9_0_pins[] = {
1915 /* KEYOUT9 */
1916 137,
1917};
1918static const unsigned int keysc_out9_0_mux[] = {
1919 PORT137_KEYOUT9_MARK,
1920};
1921static const unsigned int keysc_out9_1_pins[] = {
1922 /* KEYOUT9 */
1923 139,
1924};
1925static const unsigned int keysc_out9_1_mux[] = {
1926 PORT139_KEYOUT9_MARK,
1927};
1928static const unsigned int keysc_out9_2_pins[] = {
1929 /* KEYOUT9 */
1930 149,
1931};
1932static const unsigned int keysc_out9_2_mux[] = {
1933 PORT149_KEYOUT9_MARK,
1934};
1935static const unsigned int keysc_out10_0_pins[] = {
1936 /* KEYOUT10 */
1937 132,
1938};
1939static const unsigned int keysc_out10_0_mux[] = {
1940 PORT132_KEYOUT10_MARK,
1941};
1942static const unsigned int keysc_out10_1_pins[] = {
1943 /* KEYOUT10 */
1944 142,
1945};
1946static const unsigned int keysc_out10_1_mux[] = {
1947 PORT142_KEYOUT10_MARK,
1948};
1949static const unsigned int keysc_out11_0_pins[] = {
1950 /* KEYOUT11 */
1951 131,
1952};
1953static const unsigned int keysc_out11_0_mux[] = {
1954 PORT131_KEYOUT11_MARK,
1955};
1956static const unsigned int keysc_out11_1_pins[] = {
1957 /* KEYOUT11 */
1958 143,
1959};
1960static const unsigned int keysc_out11_1_mux[] = {
1961 PORT143_KEYOUT11_MARK,
1962};
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]1963/* - LCD -------------------------------------------------------------------- */
1964static const unsigned int lcd_data8_pins[] = {
1965 /* D[0:7] */
1966 192, 193, 194, 195, 196, 197, 198, 199,
1967};
1968static const unsigned int lcd_data8_mux[] = {
1969 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1970 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1971};
1972static const unsigned int lcd_data9_pins[] = {
1973 /* D[0:8] */
1974 192, 193, 194, 195, 196, 197, 198, 199,
1975 200,
1976};
1977static const unsigned int lcd_data9_mux[] = {
1978 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1979 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1980 LCDD8_MARK,
1981};
1982static const unsigned int lcd_data12_pins[] = {
1983 /* D[0:11] */
1984 192, 193, 194, 195, 196, 197, 198, 199,
1985 200, 201, 202, 203,
1986};
1987static const unsigned int lcd_data12_mux[] = {
1988 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1989 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1990 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1991};
1992static const unsigned int lcd_data16_pins[] = {
1993 /* D[0:15] */
1994 192, 193, 194, 195, 196, 197, 198, 199,
1995 200, 201, 202, 203, 204, 205, 206, 207,
1996};
1997static const unsigned int lcd_data16_mux[] = {
1998 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1999 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2000 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2001 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2002};
2003static const unsigned int lcd_data18_pins[] = {
2004 /* D[0:17] */
2005 192, 193, 194, 195, 196, 197, 198, 199,
2006 200, 201, 202, 203, 204, 205, 206, 207,
2007 208, 209,
2008};
2009static const unsigned int lcd_data18_mux[] = {
2010 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2011 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2012 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2013 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2014 LCDD16_MARK, LCDD17_MARK,
2015};
2016static const unsigned int lcd_data24_pins[] = {
2017 /* D[0:23] */
2018 192, 193, 194, 195, 196, 197, 198, 199,
2019 200, 201, 202, 203, 204, 205, 206, 207,
2020 208, 209, 210, 211, 212, 213, 214, 215
2021};
2022static const unsigned int lcd_data24_mux[] = {
2023 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2024 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2025 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2026 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2027 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2028 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2029};
2030static const unsigned int lcd_display_pins[] = {
2031 /* DON */
2032 222,
2033};
2034static const unsigned int lcd_display_mux[] = {
2035 LCDDON_MARK,
2036};
2037static const unsigned int lcd_lclk_pins[] = {
2038 /* LCLK */
2039 221,
2040};
2041static const unsigned int lcd_lclk_mux[] = {
2042 LCDLCLK_MARK,
2043};
2044static const unsigned int lcd_sync_pins[] = {
2045 /* VSYN, HSYN, DCK, DISP */
2046 220, 218, 216, 219,
2047};
2048static const unsigned int lcd_sync_mux[] = {
2049 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2050};
2051static const unsigned int lcd_sys_pins[] = {
2052 /* CS, WR, RD, RS */
2053 218, 216, 217, 219,
2054};
2055static const unsigned int lcd_sys_mux[] = {
2056 LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2057};
2058/* - LCD2 ------------------------------------------------------------------- */
2059static const unsigned int lcd2_data8_pins[] = {
2060 /* D[0:7] */
2061 128, 129, 142, 143, 144, 145, 138, 139,
2062};
2063static const unsigned int lcd2_data8_mux[] = {
2064 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2065 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2066};
2067static const unsigned int lcd2_data9_pins[] = {
2068 /* D[0:8] */
2069 128, 129, 142, 143, 144, 145, 138, 139,
2070 140,
2071};
2072static const unsigned int lcd2_data9_mux[] = {
2073 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2074 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2075 LCD2D8_MARK,
2076};
2077static const unsigned int lcd2_data12_pins[] = {
2078 /* D[0:12] */
2079 128, 129, 142, 143, 144, 145, 138, 139,
2080 140, 141, 130, 131,
2081};
2082static const unsigned int lcd2_data12_mux[] = {
2083 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2084 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2085 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2086};
2087static const unsigned int lcd2_data16_pins[] = {
2088 /* D[0:15] */
2089 128, 129, 142, 143, 144, 145, 138, 139,
2090 140, 141, 130, 131, 132, 133, 134, 135,
2091};
2092static const unsigned int lcd2_data16_mux[] = {
2093 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2094 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2095 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2096 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2097};
2098static const unsigned int lcd2_data18_pins[] = {
2099 /* D[0:17] */
2100 128, 129, 142, 143, 144, 145, 138, 139,
2101 140, 141, 130, 131, 132, 133, 134, 135,
2102 136, 137,
2103};
2104static const unsigned int lcd2_data18_mux[] = {
2105 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2106 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2107 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2108 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2109 LCD2D16_MARK, LCD2D17_MARK,
2110};
2111static const unsigned int lcd2_data24_pins[] = {
2112 /* D[0:23] */
2113 128, 129, 142, 143, 144, 145, 138, 139,
2114 140, 141, 130, 131, 132, 133, 134, 135,
2115 136, 137, 146, 147, 234, 235, 238, 239
2116};
2117static const unsigned int lcd2_data24_mux[] = {
2118 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2119 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2120 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2121 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2122 LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2123 LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2124};
2125static const unsigned int lcd2_sync_0_pins[] = {
2126 /* VSYN, HSYN, DCK, DISP */
2127 128, 129, 146, 145,
2128};
2129static const unsigned int lcd2_sync_0_mux[] = {
2130 PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2131 LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2132};
2133static const unsigned int lcd2_sync_1_pins[] = {
2134 /* VSYN, HSYN, DCK, DISP */
2135 222, 221, 219, 217,
2136};
2137static const unsigned int lcd2_sync_1_mux[] = {
2138 PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2139 LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2140};
2141static const unsigned int lcd2_sys_0_pins[] = {
2142 /* CS, WR, RD, RS */
2143 129, 146, 147, 145,
2144};
2145static const unsigned int lcd2_sys_0_mux[] = {
2146 PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2147 LCD2RD__MARK, PORT145_LCD2RS_MARK,
2148};
2149static const unsigned int lcd2_sys_1_pins[] = {
2150 /* CS, WR, RD, RS */
2151 221, 219, 147, 217,
2152};
2153static const unsigned int lcd2_sys_1_mux[] = {
2154 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2155 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2156};
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2157/* - MMCIF ------------------------------------------------------------------ */
2158static const unsigned int mmc0_data1_0_pins[] = {
2159 /* D[0] */
2160 271,
2161};
2162static const unsigned int mmc0_data1_0_mux[] = {
2163 MMCD0_0_MARK,
2164};
2165static const unsigned int mmc0_data4_0_pins[] = {
2166 /* D[0:3] */
2167 271, 272, 273, 274,
2168};
2169static const unsigned int mmc0_data4_0_mux[] = {
2170 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2171};
2172static const unsigned int mmc0_data8_0_pins[] = {
2173 /* D[0:7] */
2174 271, 272, 273, 274, 275, 276, 277, 278,
2175};
2176static const unsigned int mmc0_data8_0_mux[] = {
2177 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2178 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2179};
2180static const unsigned int mmc0_ctrl_0_pins[] = {
2181 /* CMD, CLK */
2182 279, 270,
2183};
2184static const unsigned int mmc0_ctrl_0_mux[] = {
2185 MMCCMD0_MARK, MMCCLK0_MARK,
2186};
2187
2188static const unsigned int mmc0_data1_1_pins[] = {
2189 /* D[0] */
2190 305,
2191};
2192static const unsigned int mmc0_data1_1_mux[] = {
2193 MMCD1_0_MARK,
2194};
2195static const unsigned int mmc0_data4_1_pins[] = {
2196 /* D[0:3] */
2197 305, 304, 303, 302,
2198};
2199static const unsigned int mmc0_data4_1_mux[] = {
2200 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2201};
2202static const unsigned int mmc0_data8_1_pins[] = {
2203 /* D[0:7] */
2204 305, 304, 303, 302, 301, 300, 299, 298,
2205};
2206static const unsigned int mmc0_data8_1_mux[] = {
2207 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2208 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2209};
2210static const unsigned int mmc0_ctrl_1_pins[] = {
2211 /* CMD, CLK */
2212 297, 289,
2213};
2214static const unsigned int mmc0_ctrl_1_mux[] = {
2215 MMCCMD1_MARK, MMCCLK1_MARK,
2216};
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2217/* - SCIFA0 ----------------------------------------------------------------- */
2218static const unsigned int scifa0_data_pins[] = {
2219 /* RXD, TXD */
2220 43, 17,
2221};
2222static const unsigned int scifa0_data_mux[] = {
2223 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2224};
2225static const unsigned int scifa0_clk_pins[] = {
2226 /* SCK */
2227 16,
2228};
2229static const unsigned int scifa0_clk_mux[] = {
2230 SCIFA0_SCK_MARK,
2231};
2232static const unsigned int scifa0_ctrl_pins[] = {
2233 /* RTS, CTS */
2234 42, 44,
2235};
2236static const unsigned int scifa0_ctrl_mux[] = {
2237 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2238};
2239/* - SCIFA1 ----------------------------------------------------------------- */
2240static const unsigned int scifa1_data_pins[] = {
2241 /* RXD, TXD */
2242 228, 225,
2243};
2244static const unsigned int scifa1_data_mux[] = {
2245 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2246};
2247static const unsigned int scifa1_clk_pins[] = {
2248 /* SCK */
2249 226,
2250};
2251static const unsigned int scifa1_clk_mux[] = {
2252 SCIFA1_SCK_MARK,
2253};
2254static const unsigned int scifa1_ctrl_pins[] = {
2255 /* RTS, CTS */
2256 227, 229,
2257};
2258static const unsigned int scifa1_ctrl_mux[] = {
2259 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2260};
2261/* - SCIFA2 ----------------------------------------------------------------- */
2262static const unsigned int scifa2_data_0_pins[] = {
2263 /* RXD, TXD */
2264 155, 154,
2265};
2266static const unsigned int scifa2_data_0_mux[] = {
2267 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2268};
2269static const unsigned int scifa2_clk_0_pins[] = {
2270 /* SCK */
2271 158,
2272};
2273static const unsigned int scifa2_clk_0_mux[] = {
2274 SCIFA2_SCK1_MARK,
2275};
2276static const unsigned int scifa2_ctrl_0_pins[] = {
2277 /* RTS, CTS */
2278 156, 157,
2279};
2280static const unsigned int scifa2_ctrl_0_mux[] = {
2281 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2282};
2283static const unsigned int scifa2_data_1_pins[] = {
2284 /* RXD, TXD */
2285 233, 230,
2286};
2287static const unsigned int scifa2_data_1_mux[] = {
2288 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2289};
2290static const unsigned int scifa2_clk_1_pins[] = {
2291 /* SCK */
2292 232,
2293};
2294static const unsigned int scifa2_clk_1_mux[] = {
2295 SCIFA2_SCK2_MARK,
2296};
2297static const unsigned int scifa2_ctrl_1_pins[] = {
2298 /* RTS, CTS */
2299 234, 231,
2300};
2301static const unsigned int scifa2_ctrl_1_mux[] = {
2302 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2303};
2304/* - SCIFA3 ----------------------------------------------------------------- */
2305static const unsigned int scifa3_data_pins[] = {
2306 /* RXD, TXD */
2307 108, 110,
2308};
2309static const unsigned int scifa3_data_mux[] = {
2310 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2311};
2312static const unsigned int scifa3_ctrl_pins[] = {
2313 /* RTS, CTS */
2314 109, 107,
2315};
2316static const unsigned int scifa3_ctrl_mux[] = {
2317 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2318};
2319/* - SCIFA4 ----------------------------------------------------------------- */
2320static const unsigned int scifa4_data_pins[] = {
2321 /* RXD, TXD */
2322 33, 32,
2323};
2324static const unsigned int scifa4_data_mux[] = {
2325 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2326};
2327static const unsigned int scifa4_ctrl_pins[] = {
2328 /* RTS, CTS */
2329 34, 35,
2330};
2331static const unsigned int scifa4_ctrl_mux[] = {
2332 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2333};
2334/* - SCIFA5 ----------------------------------------------------------------- */
2335static const unsigned int scifa5_data_0_pins[] = {
2336 /* RXD, TXD */
2337 246, 247,
2338};
2339static const unsigned int scifa5_data_0_mux[] = {
2340 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2341};
2342static const unsigned int scifa5_clk_0_pins[] = {
2343 /* SCK */
2344 248,
2345};
2346static const unsigned int scifa5_clk_0_mux[] = {
2347 PORT248_SCIFA5_SCK_MARK,
2348};
2349static const unsigned int scifa5_ctrl_0_pins[] = {
2350 /* RTS, CTS */
2351 245, 244,
2352};
2353static const unsigned int scifa5_ctrl_0_mux[] = {
2354 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2355};
2356static const unsigned int scifa5_data_1_pins[] = {
2357 /* RXD, TXD */
2358 195, 196,
2359};
2360static const unsigned int scifa5_data_1_mux[] = {
2361 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2362};
2363static const unsigned int scifa5_clk_1_pins[] = {
2364 /* SCK */
2365 197,
2366};
2367static const unsigned int scifa5_clk_1_mux[] = {
2368 PORT197_SCIFA5_SCK_MARK,
2369};
2370static const unsigned int scifa5_ctrl_1_pins[] = {
2371 /* RTS, CTS */
2372 194, 193,
2373};
2374static const unsigned int scifa5_ctrl_1_mux[] = {
2375 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2376};
2377static const unsigned int scifa5_data_2_pins[] = {
2378 /* RXD, TXD */
2379 162, 160,
2380};
2381static const unsigned int scifa5_data_2_mux[] = {
2382 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2383};
2384static const unsigned int scifa5_clk_2_pins[] = {
2385 /* SCK */
2386 159,
2387};
2388static const unsigned int scifa5_clk_2_mux[] = {
2389 PORT159_SCIFA5_SCK_MARK,
2390};
2391static const unsigned int scifa5_ctrl_2_pins[] = {
2392 /* RTS, CTS */
2393 163, 161,
2394};
2395static const unsigned int scifa5_ctrl_2_mux[] = {
2396 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2397};
2398/* - SCIFA6 ----------------------------------------------------------------- */
2399static const unsigned int scifa6_pins[] = {
2400 /* TXD */
2401 240,
2402};
2403static const unsigned int scifa6_mux[] = {
2404 SCIFA6_TXD_MARK,
2405};
2406/* - SCIFA7 ----------------------------------------------------------------- */
2407static const unsigned int scifa7_data_pins[] = {
2408 /* RXD, TXD */
2409 12, 18,
2410};
2411static const unsigned int scifa7_data_mux[] = {
2412 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2413};
2414static const unsigned int scifa7_ctrl_pins[] = {
2415 /* RTS, CTS */
2416 19, 13,
2417};
2418static const unsigned int scifa7_ctrl_mux[] = {
2419 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2420};
2421/* - SCIFB ------------------------------------------------------------------ */
2422static const unsigned int scifb_data_0_pins[] = {
2423 /* RXD, TXD */
2424 162, 160,
2425};
2426static const unsigned int scifb_data_0_mux[] = {
2427 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2428};
2429static const unsigned int scifb_clk_0_pins[] = {
2430 /* SCK */
2431 159,
2432};
2433static const unsigned int scifb_clk_0_mux[] = {
2434 PORT159_SCIFB_SCK_MARK,
2435};
2436static const unsigned int scifb_ctrl_0_pins[] = {
2437 /* RTS, CTS */
2438 163, 161,
2439};
2440static const unsigned int scifb_ctrl_0_mux[] = {
2441 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2442};
2443static const unsigned int scifb_data_1_pins[] = {
2444 /* RXD, TXD */
2445 246, 247,
2446};
2447static const unsigned int scifb_data_1_mux[] = {
2448 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2449};
2450static const unsigned int scifb_clk_1_pins[] = {
2451 /* SCK */
2452 248,
2453};
2454static const unsigned int scifb_clk_1_mux[] = {
2455 PORT248_SCIFB_SCK_MARK,
2456};
2457static const unsigned int scifb_ctrl_1_pins[] = {
2458 /* RTS, CTS */
2459 245, 244,
2460};
2461static const unsigned int scifb_ctrl_1_mux[] = {
2462 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2463};
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2464/* - SDHI0 ------------------------------------------------------------------ */
2465static const unsigned int sdhi0_data1_pins[] = {
2466 /* D0 */
2467 252,
2468};
2469static const unsigned int sdhi0_data1_mux[] = {
2470 SDHID0_0_MARK,
2471};
2472static const unsigned int sdhi0_data4_pins[] = {
2473 /* D[0:3] */
2474 252, 253, 254, 255,
2475};
2476static const unsigned int sdhi0_data4_mux[] = {
2477 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2478};
2479static const unsigned int sdhi0_ctrl_pins[] = {
2480 /* CMD, CLK */
2481 256, 250,
2482};
2483static const unsigned int sdhi0_ctrl_mux[] = {
2484 SDHICMD0_MARK, SDHICLK0_MARK,
2485};
2486static const unsigned int sdhi0_cd_pins[] = {
2487 /* CD */
2488 251,
2489};
2490static const unsigned int sdhi0_cd_mux[] = {
2491 SDHICD0_MARK,
2492};
2493static const unsigned int sdhi0_wp_pins[] = {
2494 /* WP */
2495 257,
2496};
2497static const unsigned int sdhi0_wp_mux[] = {
2498 SDHIWP0_MARK,
2499};
2500/* - SDHI1 ------------------------------------------------------------------ */
2501static const unsigned int sdhi1_data1_pins[] = {
2502 /* D0 */
2503 259,
2504};
2505static const unsigned int sdhi1_data1_mux[] = {
2506 SDHID1_0_MARK,
2507};
2508static const unsigned int sdhi1_data4_pins[] = {
2509 /* D[0:3] */
2510 259, 260, 261, 262,
2511};
2512static const unsigned int sdhi1_data4_mux[] = {
2513 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2514};
2515static const unsigned int sdhi1_ctrl_pins[] = {
2516 /* CMD, CLK */
2517 263, 258,
2518};
2519static const unsigned int sdhi1_ctrl_mux[] = {
2520 SDHICMD1_MARK, SDHICLK1_MARK,
2521};
2522/* - SDHI2 ------------------------------------------------------------------ */
2523static const unsigned int sdhi2_data1_pins[] = {
2524 /* D0 */
2525 265,
2526};
2527static const unsigned int sdhi2_data1_mux[] = {
2528 SDHID2_0_MARK,
2529};
2530static const unsigned int sdhi2_data4_pins[] = {
2531 /* D[0:3] */
2532 265, 266, 267, 268,
2533};
2534static const unsigned int sdhi2_data4_mux[] = {
2535 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2536};
2537static const unsigned int sdhi2_ctrl_pins[] = {
2538 /* CMD, CLK */
2539 269, 264,
2540};
2541static const unsigned int sdhi2_ctrl_mux[] = {
2542 SDHICMD2_MARK, SDHICLK2_MARK,
2543};
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame]2544/* - TPU0 ------------------------------------------------------------------- */
2545static const unsigned int tpu0_to0_pins[] = {
2546 /* TO */
2547 55,
2548};
2549static const unsigned int tpu0_to0_mux[] = {
2550 TPU0TO0_MARK,
2551};
2552static const unsigned int tpu0_to1_pins[] = {
2553 /* TO */
2554 59,
2555};
2556static const unsigned int tpu0_to1_mux[] = {
2557 TPU0TO1_MARK,
2558};
2559static const unsigned int tpu0_to2_pins[] = {
2560 /* TO */
2561 140,
2562};
2563static const unsigned int tpu0_to2_mux[] = {
2564 TPU0TO2_MARK,
2565};
2566static const unsigned int tpu0_to3_pins[] = {
2567 /* TO */
2568 141,
2569};
2570static const unsigned int tpu0_to3_mux[] = {
2571 TPU0TO3_MARK,
2572};
2573/* - TPU1 ------------------------------------------------------------------- */
2574static const unsigned int tpu1_to0_pins[] = {
2575 /* TO */
2576 246,
2577};
2578static const unsigned int tpu1_to0_mux[] = {
2579 TPU1TO0_MARK,
2580};
2581static const unsigned int tpu1_to1_0_pins[] = {
2582 /* TO */
2583 28,
2584};
2585static const unsigned int tpu1_to1_0_mux[] = {
2586 PORT28_TPU1TO1_MARK,
2587};
2588static const unsigned int tpu1_to1_1_pins[] = {
2589 /* TO */
2590 29,
2591};
2592static const unsigned int tpu1_to1_1_mux[] = {
2593 PORT29_TPU1TO1_MARK,
2594};
2595static const unsigned int tpu1_to2_pins[] = {
2596 /* TO */
2597 153,
2598};
2599static const unsigned int tpu1_to2_mux[] = {
2600 TPU1TO2_MARK,
2601};
2602static const unsigned int tpu1_to3_pins[] = {
2603 /* TO */
2604 145,
2605};
2606static const unsigned int tpu1_to3_mux[] = {
2607 TPU1TO3_MARK,
2608};
2609/* - TPU2 ------------------------------------------------------------------- */
2610static const unsigned int tpu2_to0_pins[] = {
2611 /* TO */
2612 248,
2613};
2614static const unsigned int tpu2_to0_mux[] = {
2615 TPU2TO0_MARK,
2616};
2617static const unsigned int tpu2_to1_pins[] = {
2618 /* TO */
2619 197,
2620};
2621static const unsigned int tpu2_to1_mux[] = {
2622 TPU2TO1_MARK,
2623};
2624static const unsigned int tpu2_to2_pins[] = {
2625 /* TO */
2626 50,
2627};
2628static const unsigned int tpu2_to2_mux[] = {
2629 TPU2TO2_MARK,
2630};
2631static const unsigned int tpu2_to3_pins[] = {
2632 /* TO */
2633 51,
2634};
2635static const unsigned int tpu2_to3_mux[] = {
2636 TPU2TO3_MARK,
2637};
2638/* - TPU3 ------------------------------------------------------------------- */
2639static const unsigned int tpu3_to0_pins[] = {
2640 /* TO */
2641 163,
2642};
2643static const unsigned int tpu3_to0_mux[] = {
2644 TPU3TO0_MARK,
2645};
2646static const unsigned int tpu3_to1_pins[] = {
2647 /* TO */
2648 247,
2649};
2650static const unsigned int tpu3_to1_mux[] = {
2651 TPU3TO1_MARK,
2652};
2653static const unsigned int tpu3_to2_pins[] = {
2654 /* TO */
2655 54,
2656};
2657static const unsigned int tpu3_to2_mux[] = {
2658 TPU3TO2_MARK,
2659};
2660static const unsigned int tpu3_to3_pins[] = {
2661 /* TO */
2662 53,
2663};
2664static const unsigned int tpu3_to3_mux[] = {
2665 TPU3TO3_MARK,
2666};
2667/* - TPU4 ------------------------------------------------------------------- */
2668static const unsigned int tpu4_to0_pins[] = {
2669 /* TO */
2670 241,
2671};
2672static const unsigned int tpu4_to0_mux[] = {
2673 TPU4TO0_MARK,
2674};
2675static const unsigned int tpu4_to1_pins[] = {
2676 /* TO */
2677 199,
2678};
2679static const unsigned int tpu4_to1_mux[] = {
2680 TPU4TO1_MARK,
2681};
2682static const unsigned int tpu4_to2_pins[] = {
2683 /* TO */
2684 58,
2685};
2686static const unsigned int tpu4_to2_mux[] = {
2687 TPU4TO2_MARK,
2688};
2689static const unsigned int tpu4_to3_pins[] = {
2690 /* TO */
2691};
2692static const unsigned int tpu4_to3_mux[] = {
2693 TPU4TO3_MARK,
2694};
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]2695/* - USB -------------------------------------------------------------------- */
2696static const unsigned int usb_vbus_pins[] = {
2697 /* VBUS */
2698 0,
2699};
2700static const unsigned int usb_vbus_mux[] = {
2701 VBUS_0_MARK,
2702};
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2703
2704static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]2705 SH_PFC_PIN_GROUP(bsc_data_0_7),
2706 SH_PFC_PIN_GROUP(bsc_data_8_15),
2707 SH_PFC_PIN_GROUP(bsc_cs4),
2708 SH_PFC_PIN_GROUP(bsc_cs5_a),
2709 SH_PFC_PIN_GROUP(bsc_cs5_b),
2710 SH_PFC_PIN_GROUP(bsc_cs6_a),
2711 SH_PFC_PIN_GROUP(bsc_cs6_b),
2712 SH_PFC_PIN_GROUP(bsc_rd),
2713 SH_PFC_PIN_GROUP(bsc_rdwr_0),
2714 SH_PFC_PIN_GROUP(bsc_rdwr_1),
2715 SH_PFC_PIN_GROUP(bsc_rdwr_2),
2716 SH_PFC_PIN_GROUP(bsc_we0),
2717 SH_PFC_PIN_GROUP(bsc_we1),
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2718 SH_PFC_PIN_GROUP(fsia_mclk_in),
2719 SH_PFC_PIN_GROUP(fsia_mclk_out),
2720 SH_PFC_PIN_GROUP(fsia_sclk_in),
2721 SH_PFC_PIN_GROUP(fsia_sclk_out),
2722 SH_PFC_PIN_GROUP(fsia_data_in),
2723 SH_PFC_PIN_GROUP(fsia_data_out),
2724 SH_PFC_PIN_GROUP(fsia_spdif),
2725 SH_PFC_PIN_GROUP(fsib_mclk_in),
2726 SH_PFC_PIN_GROUP(fsib_mclk_out),
2727 SH_PFC_PIN_GROUP(fsib_sclk_in),
2728 SH_PFC_PIN_GROUP(fsib_sclk_out),
2729 SH_PFC_PIN_GROUP(fsib_data_in),
2730 SH_PFC_PIN_GROUP(fsib_data_out),
2731 SH_PFC_PIN_GROUP(fsib_spdif),
2732 SH_PFC_PIN_GROUP(fsic_mclk_in),
2733 SH_PFC_PIN_GROUP(fsic_mclk_out),
2734 SH_PFC_PIN_GROUP(fsic_sclk_in),
2735 SH_PFC_PIN_GROUP(fsic_sclk_out),
2736 SH_PFC_PIN_GROUP(fsic_data_in),
2737 SH_PFC_PIN_GROUP(fsic_data_out),
2738 SH_PFC_PIN_GROUP(fsic_spdif_0),
2739 SH_PFC_PIN_GROUP(fsic_spdif_1),
2740 SH_PFC_PIN_GROUP(fsid_sclk_in),
2741 SH_PFC_PIN_GROUP(fsid_sclk_out),
2742 SH_PFC_PIN_GROUP(fsid_data_in),
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2743 SH_PFC_PIN_GROUP(i2c2_0),
2744 SH_PFC_PIN_GROUP(i2c2_1),
2745 SH_PFC_PIN_GROUP(i2c2_2),
2746 SH_PFC_PIN_GROUP(i2c3_0),
2747 SH_PFC_PIN_GROUP(i2c3_1),
2748 SH_PFC_PIN_GROUP(i2c3_2),
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]2749 SH_PFC_PIN_GROUP(irda_0),
2750 SH_PFC_PIN_GROUP(irda_1),
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]2751 SH_PFC_PIN_GROUP(keysc_in5),
2752 SH_PFC_PIN_GROUP(keysc_in6),
2753 SH_PFC_PIN_GROUP(keysc_in7),
2754 SH_PFC_PIN_GROUP(keysc_in8),
2755 SH_PFC_PIN_GROUP(keysc_out04),
2756 SH_PFC_PIN_GROUP(keysc_out5),
2757 SH_PFC_PIN_GROUP(keysc_out6_0),
2758 SH_PFC_PIN_GROUP(keysc_out6_1),
2759 SH_PFC_PIN_GROUP(keysc_out6_2),
2760 SH_PFC_PIN_GROUP(keysc_out7_0),
2761 SH_PFC_PIN_GROUP(keysc_out7_1),
2762 SH_PFC_PIN_GROUP(keysc_out7_2),
2763 SH_PFC_PIN_GROUP(keysc_out8_0),
2764 SH_PFC_PIN_GROUP(keysc_out8_1),
2765 SH_PFC_PIN_GROUP(keysc_out8_2),
2766 SH_PFC_PIN_GROUP(keysc_out9_0),
2767 SH_PFC_PIN_GROUP(keysc_out9_1),
2768 SH_PFC_PIN_GROUP(keysc_out9_2),
2769 SH_PFC_PIN_GROUP(keysc_out10_0),
2770 SH_PFC_PIN_GROUP(keysc_out10_1),
2771 SH_PFC_PIN_GROUP(keysc_out11_0),
2772 SH_PFC_PIN_GROUP(keysc_out11_1),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2773 SH_PFC_PIN_GROUP(lcd_data8),
2774 SH_PFC_PIN_GROUP(lcd_data9),
2775 SH_PFC_PIN_GROUP(lcd_data12),
2776 SH_PFC_PIN_GROUP(lcd_data16),
2777 SH_PFC_PIN_GROUP(lcd_data18),
2778 SH_PFC_PIN_GROUP(lcd_data24),
2779 SH_PFC_PIN_GROUP(lcd_display),
2780 SH_PFC_PIN_GROUP(lcd_lclk),
2781 SH_PFC_PIN_GROUP(lcd_sync),
2782 SH_PFC_PIN_GROUP(lcd_sys),
2783 SH_PFC_PIN_GROUP(lcd2_data8),
2784 SH_PFC_PIN_GROUP(lcd2_data9),
2785 SH_PFC_PIN_GROUP(lcd2_data12),
2786 SH_PFC_PIN_GROUP(lcd2_data16),
2787 SH_PFC_PIN_GROUP(lcd2_data18),
2788 SH_PFC_PIN_GROUP(lcd2_data24),
2789 SH_PFC_PIN_GROUP(lcd2_sync_0),
2790 SH_PFC_PIN_GROUP(lcd2_sync_1),
2791 SH_PFC_PIN_GROUP(lcd2_sys_0),
2792 SH_PFC_PIN_GROUP(lcd2_sys_1),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2793 SH_PFC_PIN_GROUP(mmc0_data1_0),
2794 SH_PFC_PIN_GROUP(mmc0_data4_0),
2795 SH_PFC_PIN_GROUP(mmc0_data8_0),
2796 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2797 SH_PFC_PIN_GROUP(mmc0_data1_1),
2798 SH_PFC_PIN_GROUP(mmc0_data4_1),
2799 SH_PFC_PIN_GROUP(mmc0_data8_1),
2800 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2801 SH_PFC_PIN_GROUP(scifa0_data),
2802 SH_PFC_PIN_GROUP(scifa0_clk),
2803 SH_PFC_PIN_GROUP(scifa0_ctrl),
2804 SH_PFC_PIN_GROUP(scifa1_data),
2805 SH_PFC_PIN_GROUP(scifa1_clk),
2806 SH_PFC_PIN_GROUP(scifa1_ctrl),
2807 SH_PFC_PIN_GROUP(scifa2_data_0),
2808 SH_PFC_PIN_GROUP(scifa2_clk_0),
2809 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2810 SH_PFC_PIN_GROUP(scifa2_data_1),
2811 SH_PFC_PIN_GROUP(scifa2_clk_1),
2812 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2813 SH_PFC_PIN_GROUP(scifa3_data),
2814 SH_PFC_PIN_GROUP(scifa3_ctrl),
2815 SH_PFC_PIN_GROUP(scifa4_data),
2816 SH_PFC_PIN_GROUP(scifa4_ctrl),
2817 SH_PFC_PIN_GROUP(scifa5_data_0),
2818 SH_PFC_PIN_GROUP(scifa5_clk_0),
2819 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2820 SH_PFC_PIN_GROUP(scifa5_data_1),
2821 SH_PFC_PIN_GROUP(scifa5_clk_1),
2822 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2823 SH_PFC_PIN_GROUP(scifa5_data_2),
2824 SH_PFC_PIN_GROUP(scifa5_clk_2),
2825 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2826 SH_PFC_PIN_GROUP(scifa6),
2827 SH_PFC_PIN_GROUP(scifa7_data),
2828 SH_PFC_PIN_GROUP(scifa7_ctrl),
2829 SH_PFC_PIN_GROUP(scifb_data_0),
2830 SH_PFC_PIN_GROUP(scifb_clk_0),
2831 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2832 SH_PFC_PIN_GROUP(scifb_data_1),
2833 SH_PFC_PIN_GROUP(scifb_clk_1),
2834 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2835 SH_PFC_PIN_GROUP(sdhi0_data1),
2836 SH_PFC_PIN_GROUP(sdhi0_data4),
2837 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2838 SH_PFC_PIN_GROUP(sdhi0_cd),
2839 SH_PFC_PIN_GROUP(sdhi0_wp),
2840 SH_PFC_PIN_GROUP(sdhi1_data1),
2841 SH_PFC_PIN_GROUP(sdhi1_data4),
2842 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2843 SH_PFC_PIN_GROUP(sdhi2_data1),
2844 SH_PFC_PIN_GROUP(sdhi2_data4),
2845 SH_PFC_PIN_GROUP(sdhi2_ctrl),
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame]2846 SH_PFC_PIN_GROUP(tpu0_to0),
2847 SH_PFC_PIN_GROUP(tpu0_to1),
2848 SH_PFC_PIN_GROUP(tpu0_to2),
2849 SH_PFC_PIN_GROUP(tpu0_to3),
2850 SH_PFC_PIN_GROUP(tpu1_to0),
2851 SH_PFC_PIN_GROUP(tpu1_to1_0),
2852 SH_PFC_PIN_GROUP(tpu1_to1_1),
2853 SH_PFC_PIN_GROUP(tpu1_to2),
2854 SH_PFC_PIN_GROUP(tpu1_to3),
2855 SH_PFC_PIN_GROUP(tpu2_to0),
2856 SH_PFC_PIN_GROUP(tpu2_to1),
2857 SH_PFC_PIN_GROUP(tpu2_to2),
2858 SH_PFC_PIN_GROUP(tpu2_to3),
2859 SH_PFC_PIN_GROUP(tpu3_to0),
2860 SH_PFC_PIN_GROUP(tpu3_to1),
2861 SH_PFC_PIN_GROUP(tpu3_to2),
2862 SH_PFC_PIN_GROUP(tpu3_to3),
2863 SH_PFC_PIN_GROUP(tpu4_to0),
2864 SH_PFC_PIN_GROUP(tpu4_to1),
2865 SH_PFC_PIN_GROUP(tpu4_to2),
2866 SH_PFC_PIN_GROUP(tpu4_to3),
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]2867 SH_PFC_PIN_GROUP(usb_vbus),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2868};
2869
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]2870static const char * const bsc_groups[] = {
2871 "bsc_data_0_7",
2872 "bsc_data_8_15",
2873 "bsc_cs4",
2874 "bsc_cs5_a",
2875 "bsc_cs5_b",
2876 "bsc_cs6_a",
2877 "bsc_cs6_b",
2878 "bsc_rd",
2879 "bsc_rdwr_0",
2880 "bsc_rdwr_1",
2881 "bsc_rdwr_2",
2882 "bsc_we0",
2883 "bsc_we1",
2884};
2885
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2886static const char * const fsia_groups[] = {
2887 "fsia_mclk_in",
2888 "fsia_mclk_out",
2889 "fsia_sclk_in",
2890 "fsia_sclk_out",
2891 "fsia_data_in",
2892 "fsia_data_out",
2893 "fsia_spdif",
2894};
2895
2896static const char * const fsib_groups[] = {
2897 "fsib_mclk_in",
2898 "fsib_mclk_out",
2899 "fsib_sclk_in",
2900 "fsib_sclk_out",
2901 "fsib_data_in",
2902 "fsib_data_out",
2903 "fsib_spdif",
2904};
2905
2906static const char * const fsic_groups[] = {
2907 "fsic_mclk_in",
2908 "fsic_mclk_out",
2909 "fsic_sclk_in",
2910 "fsic_sclk_out",
2911 "fsic_data_in",
2912 "fsic_data_out",
2913 "fsic_spdif",
2914};
2915
2916static const char * const fsid_groups[] = {
2917 "fsid_sclk_in",
2918 "fsid_sclk_out",
2919 "fsid_data_in",
2920};
2921
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2922static const char * const i2c2_groups[] = {
2923 "i2c2_0",
2924 "i2c2_1",
2925 "i2c2_2",
2926};
2927
2928static const char * const i2c3_groups[] = {
2929 "i2c3_0",
2930 "i2c3_1",
2931 "i2c3_2",
2932};
2933
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]2934static const char * const irda_groups[] = {
2935 "irda_0",
2936 "irda_1",
2937};
2938
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]2939static const char * const keysc_groups[] = {
2940 "keysc_in5",
2941 "keysc_in6",
2942 "keysc_in7",
2943 "keysc_in8",
2944 "keysc_out04",
2945 "keysc_out5",
2946 "keysc_out6_0",
2947 "keysc_out6_1",
2948 "keysc_out6_2",
2949 "keysc_out7_0",
2950 "keysc_out7_1",
2951 "keysc_out7_2",
2952 "keysc_out8_0",
2953 "keysc_out8_1",
2954 "keysc_out8_2",
2955 "keysc_out9_0",
2956 "keysc_out9_1",
2957 "keysc_out9_2",
2958 "keysc_out10_0",
2959 "keysc_out10_1",
2960 "keysc_out11_0",
2961 "keysc_out11_1",
2962};
2963
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2964static const char * const lcd_groups[] = {
2965 "lcd_data8",
2966 "lcd_data9",
2967 "lcd_data12",
2968 "lcd_data16",
2969 "lcd_data18",
2970 "lcd_data24",
2971 "lcd_display",
2972 "lcd_lclk",
2973 "lcd_sync",
2974 "lcd_sys",
2975};
2976
2977static const char * const lcd2_groups[] = {
2978 "lcd2_data8",
2979 "lcd2_data9",
2980 "lcd2_data12",
2981 "lcd2_data16",
2982 "lcd2_data18",
2983 "lcd2_data24",
2984 "lcd2_sync_0",
2985 "lcd2_sync_1",
2986 "lcd2_sys_0",
2987 "lcd2_sys_1",
2988};
2989
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2990static const char * const mmc0_groups[] = {
2991 "mmc0_data1_0",
2992 "mmc0_data4_0",
2993 "mmc0_data8_0",
2994 "mmc0_ctrl_0",
2995 "mmc0_data1_1",
2996 "mmc0_data4_1",
2997 "mmc0_data8_1",
2998 "mmc0_ctrl_1",
2999};
3000
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]3001static const char * const scifa0_groups[] = {
3002 "scifa0_data",
3003 "scifa0_clk",
3004 "scifa0_ctrl",
3005};
3006
3007static const char * const scifa1_groups[] = {
3008 "scifa1_data",
3009 "scifa1_clk",
3010 "scifa1_ctrl",
3011};
3012
3013static const char * const scifa2_groups[] = {
3014 "scifa2_data_0",
3015 "scifa2_clk_0",
3016 "scifa2_ctrl_0",
3017 "scifa2_data_1",
3018 "scifa2_clk_1",
3019 "scifa2_ctrl_1",
3020};
3021
3022static const char * const scifa3_groups[] = {
3023 "scifa3_data",
3024 "scifa3_ctrl",
3025};
3026
3027static const char * const scifa4_groups[] = {
3028 "scifa4_data",
3029 "scifa4_ctrl",
3030};
3031
3032static const char * const scifa5_groups[] = {
3033 "scifa5_data_0",
3034 "scifa5_clk_0",
3035 "scifa5_ctrl_0",
3036 "scifa5_data_1",
3037 "scifa5_clk_1",
3038 "scifa5_ctrl_1",
3039 "scifa5_data_2",
3040 "scifa5_clk_2",
3041 "scifa5_ctrl_2",
3042};
3043
3044static const char * const scifa6_groups[] = {
3045 "scifa6",
3046};
3047
3048static const char * const scifa7_groups[] = {
3049 "scifa7_data",
3050 "scifa7_ctrl",
3051};
3052
3053static const char * const scifb_groups[] = {
3054 "scifb_data_0",
3055 "scifb_clk_0",
3056 "scifb_ctrl_0",
3057 "scifb_data_1",
3058 "scifb_clk_1",
3059 "scifb_ctrl_1",
3060};
3061
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]3062static const char * const sdhi0_groups[] = {
3063 "sdhi0_data1",
3064 "sdhi0_data4",
3065 "sdhi0_ctrl",
3066 "sdhi0_cd",
3067 "sdhi0_wp",
3068};
3069
3070static const char * const sdhi1_groups[] = {
3071 "sdhi1_data1",
3072 "sdhi1_data4",
3073 "sdhi1_ctrl",
3074};
3075
3076static const char * const sdhi2_groups[] = {
3077 "sdhi2_data1",
3078 "sdhi2_data4",
3079 "sdhi2_ctrl",
3080};
3081
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]3082static const char * const usb_groups[] = {
3083 "usb_vbus",
3084};
3085
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame]3086static const char * const tpu0_groups[] = {
3087 "tpu0_to0",
3088 "tpu0_to1",
3089 "tpu0_to2",
3090 "tpu0_to3",
3091};
3092
3093static const char * const tpu1_groups[] = {
3094 "tpu1_to0",
3095 "tpu1_to1_0",
3096 "tpu1_to1_1",
3097 "tpu1_to2",
3098 "tpu1_to3",
3099};
3100
3101static const char * const tpu2_groups[] = {
3102 "tpu2_to0",
3103 "tpu2_to1",
3104 "tpu2_to2",
3105 "tpu2_to3",
3106};
3107
3108static const char * const tpu3_groups[] = {
3109 "tpu3_to0",
3110 "tpu3_to1",
3111 "tpu3_to2",
3112 "tpu3_to3",
3113};
3114
3115static const char * const tpu4_groups[] = {
3116 "tpu4_to0",
3117 "tpu4_to1",
3118 "tpu4_to2",
3119 "tpu4_to3",
3120};
3121
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3122static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]3123 SH_PFC_FUNCTION(bsc),
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]3124 SH_PFC_FUNCTION(fsia),
3125 SH_PFC_FUNCTION(fsib),
3126 SH_PFC_FUNCTION(fsic),
3127 SH_PFC_FUNCTION(fsid),
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]3128 SH_PFC_FUNCTION(i2c2),
3129 SH_PFC_FUNCTION(i2c3),
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]3130 SH_PFC_FUNCTION(irda),
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]3131 SH_PFC_FUNCTION(keysc),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3132 SH_PFC_FUNCTION(lcd),
3133 SH_PFC_FUNCTION(lcd2),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]3134 SH_PFC_FUNCTION(mmc0),
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]3135 SH_PFC_FUNCTION(scifa0),
3136 SH_PFC_FUNCTION(scifa1),
3137 SH_PFC_FUNCTION(scifa2),
3138 SH_PFC_FUNCTION(scifa3),
3139 SH_PFC_FUNCTION(scifa4),
3140 SH_PFC_FUNCTION(scifa5),
3141 SH_PFC_FUNCTION(scifa6),
3142 SH_PFC_FUNCTION(scifa7),
3143 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]3144 SH_PFC_FUNCTION(sdhi0),
3145 SH_PFC_FUNCTION(sdhi1),
3146 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame]3147 SH_PFC_FUNCTION(tpu0),
3148 SH_PFC_FUNCTION(tpu1),
3149 SH_PFC_FUNCTION(tpu2),
3150 SH_PFC_FUNCTION(tpu3),
3151 SH_PFC_FUNCTION(tpu4),
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]3152 SH_PFC_FUNCTION(usb),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3153};
3154
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]3155#undef PORTCR
3156#define PORTCR(nr, reg) \
3157 { \
3158 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3159 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3160 PORT##nr##_FN0, PORT##nr##_FN1, \
3161 PORT##nr##_FN2, PORT##nr##_FN3, \
3162 PORT##nr##_FN4, PORT##nr##_FN5, \
3163 PORT##nr##_FN6, PORT##nr##_FN7 } \
3164 }
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3165static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3166 PORTCR(0, 0xe6050000), /* PORT0CR */
3167 PORTCR(1, 0xe6050001), /* PORT1CR */
3168 PORTCR(2, 0xe6050002), /* PORT2CR */
3169 PORTCR(3, 0xe6050003), /* PORT3CR */
3170 PORTCR(4, 0xe6050004), /* PORT4CR */
3171 PORTCR(5, 0xe6050005), /* PORT5CR */
3172 PORTCR(6, 0xe6050006), /* PORT6CR */
3173 PORTCR(7, 0xe6050007), /* PORT7CR */
3174 PORTCR(8, 0xe6050008), /* PORT8CR */
3175 PORTCR(9, 0xe6050009), /* PORT9CR */
3176
3177 PORTCR(10, 0xe605000a), /* PORT10CR */
3178 PORTCR(11, 0xe605000b), /* PORT11CR */
3179 PORTCR(12, 0xe605000c), /* PORT12CR */
3180 PORTCR(13, 0xe605000d), /* PORT13CR */
3181 PORTCR(14, 0xe605000e), /* PORT14CR */
3182 PORTCR(15, 0xe605000f), /* PORT15CR */
3183 PORTCR(16, 0xe6050010), /* PORT16CR */
3184 PORTCR(17, 0xe6050011), /* PORT17CR */
3185 PORTCR(18, 0xe6050012), /* PORT18CR */
3186 PORTCR(19, 0xe6050013), /* PORT19CR */
3187
3188 PORTCR(20, 0xe6050014), /* PORT20CR */
3189 PORTCR(21, 0xe6050015), /* PORT21CR */
3190 PORTCR(22, 0xe6050016), /* PORT22CR */
3191 PORTCR(23, 0xe6050017), /* PORT23CR */
3192 PORTCR(24, 0xe6050018), /* PORT24CR */
3193 PORTCR(25, 0xe6050019), /* PORT25CR */
3194 PORTCR(26, 0xe605001a), /* PORT26CR */
3195 PORTCR(27, 0xe605001b), /* PORT27CR */
3196 PORTCR(28, 0xe605001c), /* PORT28CR */
3197 PORTCR(29, 0xe605001d), /* PORT29CR */
3198
3199 PORTCR(30, 0xe605001e), /* PORT30CR */
3200 PORTCR(31, 0xe605001f), /* PORT31CR */
3201 PORTCR(32, 0xe6051020), /* PORT32CR */
3202 PORTCR(33, 0xe6051021), /* PORT33CR */
3203 PORTCR(34, 0xe6051022), /* PORT34CR */
3204 PORTCR(35, 0xe6051023), /* PORT35CR */
3205 PORTCR(36, 0xe6051024), /* PORT36CR */
3206 PORTCR(37, 0xe6051025), /* PORT37CR */
3207 PORTCR(38, 0xe6051026), /* PORT38CR */
3208 PORTCR(39, 0xe6051027), /* PORT39CR */
3209
3210 PORTCR(40, 0xe6051028), /* PORT40CR */
3211 PORTCR(41, 0xe6051029), /* PORT41CR */
3212 PORTCR(42, 0xe605102a), /* PORT42CR */
3213 PORTCR(43, 0xe605102b), /* PORT43CR */
3214 PORTCR(44, 0xe605102c), /* PORT44CR */
3215 PORTCR(45, 0xe605102d), /* PORT45CR */
3216 PORTCR(46, 0xe605102e), /* PORT46CR */
3217 PORTCR(47, 0xe605102f), /* PORT47CR */
3218 PORTCR(48, 0xe6051030), /* PORT48CR */
3219 PORTCR(49, 0xe6051031), /* PORT49CR */
3220
3221 PORTCR(50, 0xe6051032), /* PORT50CR */
3222 PORTCR(51, 0xe6051033), /* PORT51CR */
3223 PORTCR(52, 0xe6051034), /* PORT52CR */
3224 PORTCR(53, 0xe6051035), /* PORT53CR */
3225 PORTCR(54, 0xe6051036), /* PORT54CR */
3226 PORTCR(55, 0xe6051037), /* PORT55CR */
3227 PORTCR(56, 0xe6051038), /* PORT56CR */
3228 PORTCR(57, 0xe6051039), /* PORT57CR */
3229 PORTCR(58, 0xe605103a), /* PORT58CR */
3230 PORTCR(59, 0xe605103b), /* PORT59CR */
3231
3232 PORTCR(60, 0xe605103c), /* PORT60CR */
3233 PORTCR(61, 0xe605103d), /* PORT61CR */
3234 PORTCR(62, 0xe605103e), /* PORT62CR */
3235 PORTCR(63, 0xe605103f), /* PORT63CR */
3236 PORTCR(64, 0xe6051040), /* PORT64CR */
3237 PORTCR(65, 0xe6051041), /* PORT65CR */
3238 PORTCR(66, 0xe6051042), /* PORT66CR */
3239 PORTCR(67, 0xe6051043), /* PORT67CR */
3240 PORTCR(68, 0xe6051044), /* PORT68CR */
3241 PORTCR(69, 0xe6051045), /* PORT69CR */
3242
3243 PORTCR(70, 0xe6051046), /* PORT70CR */
3244 PORTCR(71, 0xe6051047), /* PORT71CR */
3245 PORTCR(72, 0xe6051048), /* PORT72CR */
3246 PORTCR(73, 0xe6051049), /* PORT73CR */
3247 PORTCR(74, 0xe605104a), /* PORT74CR */
3248 PORTCR(75, 0xe605104b), /* PORT75CR */
3249 PORTCR(76, 0xe605104c), /* PORT76CR */
3250 PORTCR(77, 0xe605104d), /* PORT77CR */
3251 PORTCR(78, 0xe605104e), /* PORT78CR */
3252 PORTCR(79, 0xe605104f), /* PORT79CR */
3253
3254 PORTCR(80, 0xe6051050), /* PORT80CR */
3255 PORTCR(81, 0xe6051051), /* PORT81CR */
3256 PORTCR(82, 0xe6051052), /* PORT82CR */
3257 PORTCR(83, 0xe6051053), /* PORT83CR */
3258 PORTCR(84, 0xe6051054), /* PORT84CR */
3259 PORTCR(85, 0xe6051055), /* PORT85CR */
3260 PORTCR(86, 0xe6051056), /* PORT86CR */
3261 PORTCR(87, 0xe6051057), /* PORT87CR */
3262 PORTCR(88, 0xe6051058), /* PORT88CR */
3263 PORTCR(89, 0xe6051059), /* PORT89CR */
3264
3265 PORTCR(90, 0xe605105a), /* PORT90CR */
3266 PORTCR(91, 0xe605105b), /* PORT91CR */
3267 PORTCR(92, 0xe605105c), /* PORT92CR */
3268 PORTCR(93, 0xe605105d), /* PORT93CR */
3269 PORTCR(94, 0xe605105e), /* PORT94CR */
3270 PORTCR(95, 0xe605105f), /* PORT95CR */
3271 PORTCR(96, 0xe6052060), /* PORT96CR */
3272 PORTCR(97, 0xe6052061), /* PORT97CR */
3273 PORTCR(98, 0xe6052062), /* PORT98CR */
3274 PORTCR(99, 0xe6052063), /* PORT99CR */
3275
3276 PORTCR(100, 0xe6052064), /* PORT100CR */
3277 PORTCR(101, 0xe6052065), /* PORT101CR */
3278 PORTCR(102, 0xe6052066), /* PORT102CR */
3279 PORTCR(103, 0xe6052067), /* PORT103CR */
3280 PORTCR(104, 0xe6052068), /* PORT104CR */
3281 PORTCR(105, 0xe6052069), /* PORT105CR */
3282 PORTCR(106, 0xe605206a), /* PORT106CR */
3283 PORTCR(107, 0xe605206b), /* PORT107CR */
3284 PORTCR(108, 0xe605206c), /* PORT108CR */
3285 PORTCR(109, 0xe605206d), /* PORT109CR */
3286
3287 PORTCR(110, 0xe605206e), /* PORT110CR */
3288 PORTCR(111, 0xe605206f), /* PORT111CR */
3289 PORTCR(112, 0xe6052070), /* PORT112CR */
3290 PORTCR(113, 0xe6052071), /* PORT113CR */
3291 PORTCR(114, 0xe6052072), /* PORT114CR */
3292 PORTCR(115, 0xe6052073), /* PORT115CR */
3293 PORTCR(116, 0xe6052074), /* PORT116CR */
3294 PORTCR(117, 0xe6052075), /* PORT117CR */
3295 PORTCR(118, 0xe6052076), /* PORT118CR */
3296
3297 PORTCR(128, 0xe6052080), /* PORT128CR */
3298 PORTCR(129, 0xe6052081), /* PORT129CR */
3299
3300 PORTCR(130, 0xe6052082), /* PORT130CR */
3301 PORTCR(131, 0xe6052083), /* PORT131CR */
3302 PORTCR(132, 0xe6052084), /* PORT132CR */
3303 PORTCR(133, 0xe6052085), /* PORT133CR */
3304 PORTCR(134, 0xe6052086), /* PORT134CR */
3305 PORTCR(135, 0xe6052087), /* PORT135CR */
3306 PORTCR(136, 0xe6052088), /* PORT136CR */
3307 PORTCR(137, 0xe6052089), /* PORT137CR */
3308 PORTCR(138, 0xe605208a), /* PORT138CR */
3309 PORTCR(139, 0xe605208b), /* PORT139CR */
3310
3311 PORTCR(140, 0xe605208c), /* PORT140CR */
3312 PORTCR(141, 0xe605208d), /* PORT141CR */
3313 PORTCR(142, 0xe605208e), /* PORT142CR */
3314 PORTCR(143, 0xe605208f), /* PORT143CR */
3315 PORTCR(144, 0xe6052090), /* PORT144CR */
3316 PORTCR(145, 0xe6052091), /* PORT145CR */
3317 PORTCR(146, 0xe6052092), /* PORT146CR */
3318 PORTCR(147, 0xe6052093), /* PORT147CR */
3319 PORTCR(148, 0xe6052094), /* PORT148CR */
3320 PORTCR(149, 0xe6052095), /* PORT149CR */
3321
3322 PORTCR(150, 0xe6052096), /* PORT150CR */
3323 PORTCR(151, 0xe6052097), /* PORT151CR */
3324 PORTCR(152, 0xe6052098), /* PORT152CR */
3325 PORTCR(153, 0xe6052099), /* PORT153CR */
3326 PORTCR(154, 0xe605209a), /* PORT154CR */
3327 PORTCR(155, 0xe605209b), /* PORT155CR */
3328 PORTCR(156, 0xe605209c), /* PORT156CR */
3329 PORTCR(157, 0xe605209d), /* PORT157CR */
3330 PORTCR(158, 0xe605209e), /* PORT158CR */
3331 PORTCR(159, 0xe605209f), /* PORT159CR */
3332
3333 PORTCR(160, 0xe60520a0), /* PORT160CR */
3334 PORTCR(161, 0xe60520a1), /* PORT161CR */
3335 PORTCR(162, 0xe60520a2), /* PORT162CR */
3336 PORTCR(163, 0xe60520a3), /* PORT163CR */
3337 PORTCR(164, 0xe60520a4), /* PORT164CR */
3338
3339 PORTCR(192, 0xe60520c0), /* PORT192CR */
3340 PORTCR(193, 0xe60520c1), /* PORT193CR */
3341 PORTCR(194, 0xe60520c2), /* PORT194CR */
3342 PORTCR(195, 0xe60520c3), /* PORT195CR */
3343 PORTCR(196, 0xe60520c4), /* PORT196CR */
3344 PORTCR(197, 0xe60520c5), /* PORT197CR */
3345 PORTCR(198, 0xe60520c6), /* PORT198CR */
3346 PORTCR(199, 0xe60520c7), /* PORT199CR */
3347
3348 PORTCR(200, 0xe60520c8), /* PORT200CR */
3349 PORTCR(201, 0xe60520c9), /* PORT201CR */
3350 PORTCR(202, 0xe60520ca), /* PORT202CR */
3351 PORTCR(203, 0xe60520cb), /* PORT203CR */
3352 PORTCR(204, 0xe60520cc), /* PORT204CR */
3353 PORTCR(205, 0xe60520cd), /* PORT205CR */
3354 PORTCR(206, 0xe60520ce), /* PORT206CR */
3355 PORTCR(207, 0xe60520cf), /* PORT207CR */
3356 PORTCR(208, 0xe60520d0), /* PORT208CR */
3357 PORTCR(209, 0xe60520d1), /* PORT209CR */
3358
3359 PORTCR(210, 0xe60520d2), /* PORT210CR */
3360 PORTCR(211, 0xe60520d3), /* PORT211CR */
3361 PORTCR(212, 0xe60520d4), /* PORT212CR */
3362 PORTCR(213, 0xe60520d5), /* PORT213CR */
3363 PORTCR(214, 0xe60520d6), /* PORT214CR */
3364 PORTCR(215, 0xe60520d7), /* PORT215CR */
3365 PORTCR(216, 0xe60520d8), /* PORT216CR */
3366 PORTCR(217, 0xe60520d9), /* PORT217CR */
3367 PORTCR(218, 0xe60520da), /* PORT218CR */
3368 PORTCR(219, 0xe60520db), /* PORT219CR */
3369
3370 PORTCR(220, 0xe60520dc), /* PORT220CR */
3371 PORTCR(221, 0xe60520dd), /* PORT221CR */
3372 PORTCR(222, 0xe60520de), /* PORT222CR */
3373 PORTCR(223, 0xe60520df), /* PORT223CR */
3374 PORTCR(224, 0xe60530e0), /* PORT224CR */
3375 PORTCR(225, 0xe60530e1), /* PORT225CR */
3376 PORTCR(226, 0xe60530e2), /* PORT226CR */
3377 PORTCR(227, 0xe60530e3), /* PORT227CR */
3378 PORTCR(228, 0xe60530e4), /* PORT228CR */
3379 PORTCR(229, 0xe60530e5), /* PORT229CR */
3380
3381 PORTCR(230, 0xe60530e6), /* PORT230CR */
3382 PORTCR(231, 0xe60530e7), /* PORT231CR */
3383 PORTCR(232, 0xe60530e8), /* PORT232CR */
3384 PORTCR(233, 0xe60530e9), /* PORT233CR */
3385 PORTCR(234, 0xe60530ea), /* PORT234CR */
3386 PORTCR(235, 0xe60530eb), /* PORT235CR */
3387 PORTCR(236, 0xe60530ec), /* PORT236CR */
3388 PORTCR(237, 0xe60530ed), /* PORT237CR */
3389 PORTCR(238, 0xe60530ee), /* PORT238CR */
3390 PORTCR(239, 0xe60530ef), /* PORT239CR */
3391
3392 PORTCR(240, 0xe60530f0), /* PORT240CR */
3393 PORTCR(241, 0xe60530f1), /* PORT241CR */
3394 PORTCR(242, 0xe60530f2), /* PORT242CR */
3395 PORTCR(243, 0xe60530f3), /* PORT243CR */
3396 PORTCR(244, 0xe60530f4), /* PORT244CR */
3397 PORTCR(245, 0xe60530f5), /* PORT245CR */
3398 PORTCR(246, 0xe60530f6), /* PORT246CR */
3399 PORTCR(247, 0xe60530f7), /* PORT247CR */
3400 PORTCR(248, 0xe60530f8), /* PORT248CR */
3401 PORTCR(249, 0xe60530f9), /* PORT249CR */
3402
3403 PORTCR(250, 0xe60530fa), /* PORT250CR */
3404 PORTCR(251, 0xe60530fb), /* PORT251CR */
3405 PORTCR(252, 0xe60530fc), /* PORT252CR */
3406 PORTCR(253, 0xe60530fd), /* PORT253CR */
3407 PORTCR(254, 0xe60530fe), /* PORT254CR */
3408 PORTCR(255, 0xe60530ff), /* PORT255CR */
3409 PORTCR(256, 0xe6053100), /* PORT256CR */
3410 PORTCR(257, 0xe6053101), /* PORT257CR */
3411 PORTCR(258, 0xe6053102), /* PORT258CR */
3412 PORTCR(259, 0xe6053103), /* PORT259CR */
3413
3414 PORTCR(260, 0xe6053104), /* PORT260CR */
3415 PORTCR(261, 0xe6053105), /* PORT261CR */
3416 PORTCR(262, 0xe6053106), /* PORT262CR */
3417 PORTCR(263, 0xe6053107), /* PORT263CR */
3418 PORTCR(264, 0xe6053108), /* PORT264CR */
3419 PORTCR(265, 0xe6053109), /* PORT265CR */
3420 PORTCR(266, 0xe605310a), /* PORT266CR */
3421 PORTCR(267, 0xe605310b), /* PORT267CR */
3422 PORTCR(268, 0xe605310c), /* PORT268CR */
3423 PORTCR(269, 0xe605310d), /* PORT269CR */
3424
3425 PORTCR(270, 0xe605310e), /* PORT270CR */
3426 PORTCR(271, 0xe605310f), /* PORT271CR */
3427 PORTCR(272, 0xe6053110), /* PORT272CR */
3428 PORTCR(273, 0xe6053111), /* PORT273CR */
3429 PORTCR(274, 0xe6053112), /* PORT274CR */
3430 PORTCR(275, 0xe6053113), /* PORT275CR */
3431 PORTCR(276, 0xe6053114), /* PORT276CR */
3432 PORTCR(277, 0xe6053115), /* PORT277CR */
3433 PORTCR(278, 0xe6053116), /* PORT278CR */
3434 PORTCR(279, 0xe6053117), /* PORT279CR */
3435
3436 PORTCR(280, 0xe6053118), /* PORT280CR */
3437 PORTCR(281, 0xe6053119), /* PORT281CR */
3438 PORTCR(282, 0xe605311a), /* PORT282CR */
3439
3440 PORTCR(288, 0xe6052120), /* PORT288CR */
3441 PORTCR(289, 0xe6052121), /* PORT289CR */
3442
3443 PORTCR(290, 0xe6052122), /* PORT290CR */
3444 PORTCR(291, 0xe6052123), /* PORT291CR */
3445 PORTCR(292, 0xe6052124), /* PORT292CR */
3446 PORTCR(293, 0xe6052125), /* PORT293CR */
3447 PORTCR(294, 0xe6052126), /* PORT294CR */
3448 PORTCR(295, 0xe6052127), /* PORT295CR */
3449 PORTCR(296, 0xe6052128), /* PORT296CR */
3450 PORTCR(297, 0xe6052129), /* PORT297CR */
3451 PORTCR(298, 0xe605212a), /* PORT298CR */
3452 PORTCR(299, 0xe605212b), /* PORT299CR */
3453
3454 PORTCR(300, 0xe605212c), /* PORT300CR */
3455 PORTCR(301, 0xe605212d), /* PORT301CR */
3456 PORTCR(302, 0xe605212e), /* PORT302CR */
3457 PORTCR(303, 0xe605212f), /* PORT303CR */
3458 PORTCR(304, 0xe6052130), /* PORT304CR */
3459 PORTCR(305, 0xe6052131), /* PORT305CR */
3460 PORTCR(306, 0xe6052132), /* PORT306CR */
3461 PORTCR(307, 0xe6052133), /* PORT307CR */
3462 PORTCR(308, 0xe6052134), /* PORT308CR */
3463 PORTCR(309, 0xe6052135), /* PORT309CR */
3464
3465 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3466 0, 0,
3467 0, 0,
3468 0, 0,
3469 0, 0,
3470 0, 0,
3471 0, 0,
3472 0, 0,
3473 0, 0,
3474 0, 0,
3475 0, 0,
3476 0, 0,
3477 0, 0,
3478 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3479 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3480 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3481 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3482 0, 0,
3483 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3484 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3485 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3486 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3487 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3488 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3489 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3490 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3491 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3492 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
3493 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
3494 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
3495 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
3496 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
3497 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
3498 }
3499 },
3500 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3501 0, 0,
3502 0, 0,
3503 0, 0,
3504 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
3505 0, 0,
3506 0, 0,
3507 0, 0,
3508 0, 0,
3509 0, 0,
3510 0, 0,
3511 0, 0,
3512 0, 0,
3513 0, 0,
3514 0, 0,
3515 0, 0,
3516 0, 0,
3517 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
3518 0, 0,
3519 0, 0,
3520 0, 0,
3521 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
3522 0, 0,
3523 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
3524 0, 0,
3525 0, 0,
3526 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
3527 0, 0,
3528 0, 0,
3529 0, 0,
3530 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
3531 0, 0,
3532 0, 0,
3533 }
3534 },
3535 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3536 0, 0,
3537 0, 0,
3538 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
3539 0, 0,
3540 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
3541 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
3542 0, 0,
3543 0, 0,
3544 0, 0,
3545 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
3546 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
3547 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
3548 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
3549 0, 0,
3550 0, 0,
3551 0, 0,
3552 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
3553 0, 0,
3554 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
3555 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
3556 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
3557 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
3558 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
3559 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
3560 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
3561 0, 0,
3562 0, 0,
3563 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
3564 0, 0,
3565 0, 0,
3566 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
3567 0, 0,
3568 }
3569 },
3570 { },
3571};
3572
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3573static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3574 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3575 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3576 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3577 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3578 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3579 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3580 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3581 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3582 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3583 },
3584 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3585 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3586 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3587 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3588 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3589 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3590 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3591 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3592 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3593 },
3594 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
3595 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3596 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3597 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3598 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3599 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3600 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3601 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3602 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3603 },
3604 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
3605 0, 0, 0, 0,
3606 0, 0, 0, 0,
3607 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3608 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3609 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3610 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3611 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3612 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3613 },
3614 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
3615 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3616 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3617 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3618 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3619 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3620 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3621 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3622 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3623 },
3624 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
3625 0, 0, 0, 0,
3626 0, 0, 0, 0,
3627 0, 0, 0, 0,
3628 0, 0, 0, 0,
3629 0, 0, 0, 0,
3630 0, 0, 0, 0,
3631 0, 0, 0, PORT164_DATA,
3632 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3633 },
3634 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
3635 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
3636 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
3637 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
3638 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
3639 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3640 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3641 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3642 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3643 },
3644 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
3645 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
3646 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
3647 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
3648 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
3649 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
3650 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
3651 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
3652 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
3653 },
3654 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
3655 0, 0, 0, 0,
3656 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
3657 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
3658 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
3659 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
3660 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
3661 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
3662 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
3663 },
3664 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
3665 0, 0, 0, 0,
3666 0, 0, 0, 0,
3667 0, 0, PORT309_DATA, PORT308_DATA,
3668 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
3669 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
3670 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
3671 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
3672 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
3673 },
3674 { },
3675};
3676
Magnus Damm341eb542013-02-26 12:01:09 +0900[diff] [blame]3677/* External IRQ pins mapped at IRQPIN_BASE */
3678#define EXT_IRQ16L(n) irq_pin(n)
3679#define EXT_IRQ16H(n) irq_pin(n)
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3680
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3681static const struct pinmux_irq pinmux_irqs[] = {
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]3682 PINMUX_IRQ(EXT_IRQ16H(19), 9),
3683 PINMUX_IRQ(EXT_IRQ16L(1), 10),
3684 PINMUX_IRQ(EXT_IRQ16L(0), 11),
3685 PINMUX_IRQ(EXT_IRQ16H(18), 13),
3686 PINMUX_IRQ(EXT_IRQ16H(20), 14),
3687 PINMUX_IRQ(EXT_IRQ16H(21), 15),
3688 PINMUX_IRQ(EXT_IRQ16H(31), 26),
3689 PINMUX_IRQ(EXT_IRQ16H(30), 27),
3690 PINMUX_IRQ(EXT_IRQ16H(29), 28),
3691 PINMUX_IRQ(EXT_IRQ16H(22), 40),
3692 PINMUX_IRQ(EXT_IRQ16H(23), 53),
3693 PINMUX_IRQ(EXT_IRQ16L(10), 54),
3694 PINMUX_IRQ(EXT_IRQ16L(9), 56),
3695 PINMUX_IRQ(EXT_IRQ16H(26), 115),
3696 PINMUX_IRQ(EXT_IRQ16H(27), 116),
3697 PINMUX_IRQ(EXT_IRQ16H(28), 117),
3698 PINMUX_IRQ(EXT_IRQ16H(24), 118),
3699 PINMUX_IRQ(EXT_IRQ16L(6), 147),
3700 PINMUX_IRQ(EXT_IRQ16L(2), 149),
3701 PINMUX_IRQ(EXT_IRQ16L(7), 150),
3702 PINMUX_IRQ(EXT_IRQ16L(12), 156),
3703 PINMUX_IRQ(EXT_IRQ16L(4), 159),
3704 PINMUX_IRQ(EXT_IRQ16H(25), 164),
3705 PINMUX_IRQ(EXT_IRQ16L(8), 223),
3706 PINMUX_IRQ(EXT_IRQ16L(3), 224),
3707 PINMUX_IRQ(EXT_IRQ16L(5), 227),
3708 PINMUX_IRQ(EXT_IRQ16H(17), 234),
3709 PINMUX_IRQ(EXT_IRQ16L(11), 238),
3710 PINMUX_IRQ(EXT_IRQ16L(13), 239),
3711 PINMUX_IRQ(EXT_IRQ16H(16), 249),
3712 PINMUX_IRQ(EXT_IRQ16L(14), 251),
3713 PINMUX_IRQ(EXT_IRQ16L(9), 308),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3714};
3715
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]3716/* -----------------------------------------------------------------------------
3717 * VCCQ MC0 regulator
3718 */
3719
3720static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
3721{
3722 struct sh_pfc *pfc = reg->reg_data;
3723 void __iomem *addr = pfc->window[1].virt + 4;
3724 unsigned long flags;
3725 u32 value;
3726
3727 spin_lock_irqsave(&pfc->lock, flags);
3728
3729 value = ioread32(addr);
3730
3731 if (enable)
3732 value |= BIT(28);
3733 else
3734 value &= ~BIT(28);
3735
3736 iowrite32(value, addr);
3737
3738 spin_unlock_irqrestore(&pfc->lock, flags);
3739}
3740
3741static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
3742{
3743 sh73a0_vccq_mc0_endisable(reg, true);
3744 return 0;
3745}
3746
3747static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
3748{
3749 sh73a0_vccq_mc0_endisable(reg, false);
3750 return 0;
3751}
3752
3753static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
3754{
3755 struct sh_pfc *pfc = reg->reg_data;
3756 void __iomem *addr = pfc->window[1].virt + 4;
3757 unsigned long flags;
3758 u32 value;
3759
3760 spin_lock_irqsave(&pfc->lock, flags);
3761 value = ioread32(addr);
3762 spin_unlock_irqrestore(&pfc->lock, flags);
3763
3764 return !!(value & BIT(28));
3765}
3766
3767static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
3768{
3769 return 3300000;
3770}
3771
3772static struct regulator_ops sh73a0_vccq_mc0_ops = {
3773 .enable = sh73a0_vccq_mc0_enable,
3774 .disable = sh73a0_vccq_mc0_disable,
3775 .is_enabled = sh73a0_vccq_mc0_is_enabled,
3776 .get_voltage = sh73a0_vccq_mc0_get_voltage,
3777};
3778
3779static const struct regulator_desc sh73a0_vccq_mc0_desc = {
3780 .owner = THIS_MODULE,
3781 .name = "vccq_mc0",
3782 .type = REGULATOR_VOLTAGE,
3783 .ops = &sh73a0_vccq_mc0_ops,
3784};
3785
3786static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
3787 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
3788};
3789
3790static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
3791 .constraints = {
3792 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3793 },
3794 .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
3795 .consumer_supplies = sh73a0_vccq_mc0_consumers,
3796};
3797
3798/* -----------------------------------------------------------------------------
3799 * Pin bias
3800 */
3801
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]3802#define PORTnCR_PULMD_OFF (0 << 6)
3803#define PORTnCR_PULMD_DOWN (2 << 6)
3804#define PORTnCR_PULMD_UP (3 << 6)
3805#define PORTnCR_PULMD_MASK (3 << 6)
3806
3807static const unsigned int sh73a0_portcr_offsets[] = {
3808 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
3809 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
3810};
3811
3812static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3813{
3814 void __iomem *addr = pfc->window->virt
3815 + sh73a0_portcr_offsets[pin >> 5] + pin;
3816 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3817
3818 switch (value) {
3819 case PORTnCR_PULMD_UP:
3820 return PIN_CONFIG_BIAS_PULL_UP;
3821 case PORTnCR_PULMD_DOWN:
3822 return PIN_CONFIG_BIAS_PULL_DOWN;
3823 case PORTnCR_PULMD_OFF:
3824 default:
3825 return PIN_CONFIG_BIAS_DISABLE;
3826 }
3827}
3828
3829static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3830 unsigned int bias)
3831{
3832 void __iomem *addr = pfc->window->virt
3833 + sh73a0_portcr_offsets[pin >> 5] + pin;
3834 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3835
3836 switch (bias) {
3837 case PIN_CONFIG_BIAS_PULL_UP:
3838 value |= PORTnCR_PULMD_UP;
3839 break;
3840 case PIN_CONFIG_BIAS_PULL_DOWN:
3841 value |= PORTnCR_PULMD_DOWN;
3842 break;
3843 }
3844
3845 iowrite8(value, addr);
3846}
3847
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]3848/* -----------------------------------------------------------------------------
3849 * SoC information
3850 */
3851
3852struct sh73a0_pinmux_data {
3853 struct regulator_dev *vccq_mc0;
3854};
3855
3856static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3857{
3858 struct sh73a0_pinmux_data *data;
3859 struct regulator_config cfg = { };
3860 int ret;
3861
3862 data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
3863 if (data == NULL)
3864 return -ENOMEM;
3865
3866 cfg.dev = pfc->dev;
3867 cfg.init_data = &sh73a0_vccq_mc0_init_data;
3868 cfg.driver_data = pfc;
3869
3870 data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
3871 if (IS_ERR(data->vccq_mc0)) {
3872 ret = PTR_ERR(data->vccq_mc0);
3873 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
3874 ret);
3875 return ret;
3876 }
3877
3878 pfc->soc_data = data;
3879
3880 return 0;
3881}
3882
3883static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
3884{
3885 struct sh73a0_pinmux_data *data = pfc->soc_data;
3886
3887 regulator_unregister(data->vccq_mc0);
3888}
3889
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]3890static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]3891 .init = sh73a0_pinmux_soc_init,
3892 .exit = sh73a0_pinmux_soc_exit,
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]3893 .get_bias = sh73a0_pinmux_get_bias,
3894 .set_bias = sh73a0_pinmux_set_bias,
3895};
3896
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3897const struct sh_pfc_soc_info sh73a0_pinmux_info = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3898 .name = "sh73a0_pfc",
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]3899 .ops = &sh73a0_pinmux_ops,
3900
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3901 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3902 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3903 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3904
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3905 .pins = pinmux_pins,
3906 .nr_pins = ARRAY_SIZE(pinmux_pins),
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]3907 .ranges = pinmux_ranges,
3908 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3909 .groups = pinmux_groups,
3910 .nr_groups = ARRAY_SIZE(pinmux_groups),
3911 .functions = pinmux_functions,
3912 .nr_functions = ARRAY_SIZE(pinmux_functions),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3913
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3914 .cfg_regs = pinmux_config_regs,
3915 .data_regs = pinmux_data_regs,
3916
3917 .gpio_data = pinmux_data,
3918 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3919
3920 .gpio_irq = pinmux_irqs,
3921 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3922};