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Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
Charulatha V1a5d8192011-02-02 17:52:14 +05306 * Juha Yrj�l� <juha.yrjola@nokia.com>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
Russell King53741ed2012-04-23 13:51:48 +010023#define USE_DMA_ENGINE_RX
24#define USE_DMA_ENGINE_TX
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070025
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/module.h>
30#include <linux/device.h>
31#include <linux/delay.h>
32#include <linux/dma-mapping.h>
Russell King53741ed2012-04-23 13:51:48 +010033#include <linux/dmaengine.h>
34#include <linux/omap-dma.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070035#include <linux/platform_device.h>
36#include <linux/err.h>
37#include <linux/clk.h>
38#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090039#include <linux/slab.h>
Govindraj.R1f1a4382011-02-02 17:52:15 +053040#include <linux/pm_runtime.h>
Benoit Coussond5a80032012-02-15 18:37:34 +010041#include <linux/of.h>
42#include <linux/of_device.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070043
44#include <linux/spi/spi.h>
45
Tony Lindgrence491cf2009-10-20 09:40:47 -070046#include <plat/dma.h>
47#include <plat/clock.h>
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +000048#include <plat/mcspi.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070049
50#define OMAP2_MCSPI_MAX_FREQ 48000000
Shubhrajyoti D27b52842012-03-26 17:04:22 +053051#define SPI_AUTOSUSPEND_TIMEOUT 2000
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070052
53#define OMAP2_MCSPI_REVISION 0x00
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070054#define OMAP2_MCSPI_SYSSTATUS 0x14
55#define OMAP2_MCSPI_IRQSTATUS 0x18
56#define OMAP2_MCSPI_IRQENABLE 0x1c
57#define OMAP2_MCSPI_WAKEUPENABLE 0x20
58#define OMAP2_MCSPI_SYST 0x24
59#define OMAP2_MCSPI_MODULCTRL 0x28
60
61/* per-channel banks, 0x14 bytes each, first is: */
62#define OMAP2_MCSPI_CHCONF0 0x2c
63#define OMAP2_MCSPI_CHSTAT0 0x30
64#define OMAP2_MCSPI_CHCTRL0 0x34
65#define OMAP2_MCSPI_TX0 0x38
66#define OMAP2_MCSPI_RX0 0x3c
67
68/* per-register bitmasks: */
69
Jouni Hogander7a8fa722009-09-22 16:45:58 -070070#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
71#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
72#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070073
Jouni Hogander7a8fa722009-09-22 16:45:58 -070074#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
75#define OMAP2_MCSPI_CHCONF_POL BIT(1)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070076#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070077#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070078#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070079#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
80#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070081#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070082#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
83#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
84#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
85#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
86#define OMAP2_MCSPI_CHCONF_IS BIT(18)
87#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
88#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070089
Jouni Hogander7a8fa722009-09-22 16:45:58 -070090#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070093
Jouni Hogander7a8fa722009-09-22 16:45:58 -070094#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070095
Jouni Hogander7a8fa722009-09-22 16:45:58 -070096#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070097
98/* We have 2 DMA channels per CS, one for RX and one for TX */
99struct omap2_mcspi_dma {
Russell King53741ed2012-04-23 13:51:48 +0100100 struct dma_chan *dma_tx;
101 struct dma_chan *dma_rx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700102 int dma_tx_channel;
103 int dma_rx_channel;
104
105 int dma_tx_sync_dev;
106 int dma_rx_sync_dev;
107
108 struct completion dma_tx_completion;
109 struct completion dma_rx_completion;
110};
111
112/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
114 */
Roman Tereshonkov8b66c132010-04-12 09:07:54 +0000115#define DMA_MIN_BYTES 160
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700116
117
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530118/*
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
121 */
122struct omap2_mcspi_regs {
123 u32 modulctrl;
124 u32 wakeupenable;
125 struct list_head cs;
126};
127
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700128struct omap2_mcspi {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700129 struct spi_master *master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700130 /* Virtual base address of the controller */
131 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100132 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma *dma_channels;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530135 struct device *dev;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530136 struct omap2_mcspi_regs ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700137};
138
139struct omap2_mcspi_cs {
140 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100141 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700142 int word_len;
Tero Kristo89c05372009-09-22 16:46:17 -0700143 struct list_head node;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700144 /* Context save and restore shadow register */
145 u32 chconf0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700146};
147
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700148#define MOD_REG_BIT(val, mask, set) do { \
149 if (set) \
150 val |= mask; \
151 else \
152 val &= ~mask; \
153} while (0)
154
155static inline void mcspi_write_reg(struct spi_master *master,
156 int idx, u32 val)
157{
158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
159
160 __raw_writel(val, mcspi->base + idx);
161}
162
163static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
164{
165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
166
167 return __raw_readl(mcspi->base + idx);
168}
169
170static inline void mcspi_write_cs_reg(const struct spi_device *spi,
171 int idx, u32 val)
172{
173 struct omap2_mcspi_cs *cs = spi->controller_state;
174
175 __raw_writel(val, cs->base + idx);
176}
177
178static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
179{
180 struct omap2_mcspi_cs *cs = spi->controller_state;
181
182 return __raw_readl(cs->base + idx);
183}
184
Hemanth Va41ae1a2009-09-22 16:46:16 -0700185static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
186{
187 struct omap2_mcspi_cs *cs = spi->controller_state;
188
189 return cs->chconf0;
190}
191
192static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
193{
194 struct omap2_mcspi_cs *cs = spi->controller_state;
195
196 cs->chconf0 = val;
197 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
Roman Tereshonkova330ce22010-03-15 09:06:28 +0000198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700199}
200
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700201static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
202 int is_read, int enable)
203{
204 u32 l, rw;
205
Hemanth Va41ae1a2009-09-22 16:46:16 -0700206 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700207
208 if (is_read) /* 1 is read, 0 write */
209 rw = OMAP2_MCSPI_CHCONF_DMAR;
210 else
211 rw = OMAP2_MCSPI_CHCONF_DMAW;
212
213 MOD_REG_BIT(l, rw, enable);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700214 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700215}
216
217static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
218{
219 u32 l;
220
221 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
222 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000223 /* Flash post-writes */
224 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700225}
226
227static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
228{
229 u32 l;
230
Hemanth Va41ae1a2009-09-22 16:46:16 -0700231 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700232 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700233 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700234}
235
236static void omap2_mcspi_set_master_mode(struct spi_master *master)
237{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530238 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
239 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700240 u32 l;
241
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530242 /*
243 * Setup when switching from (reset default) slave mode
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700244 * to single-channel master mode
245 */
246 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
247 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
248 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
249 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
250 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700251
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530252 ctx->modulctrl = l;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700253}
254
255static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
256{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530257 struct spi_master *spi_cntrl = mcspi->master;
258 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
259 struct omap2_mcspi_cs *cs;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700260
261 /* McSPI: context restore */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530262 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
263 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700264
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530265 list_for_each_entry(cs, &ctx->cs, node)
Tero Kristo89c05372009-09-22 16:46:17 -0700266 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700267}
268static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
269{
Shubhrajyoti D27b52842012-03-26 17:04:22 +0530270 pm_runtime_mark_last_busy(mcspi->dev);
271 pm_runtime_put_autosuspend(mcspi->dev);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700272}
273
274static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
275{
Govindraj.R1f1a4382011-02-02 17:52:15 +0530276 return pm_runtime_get_sync(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700277}
278
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530279static int omap2_prepare_transfer(struct spi_master *master)
280{
281 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
282
283 pm_runtime_get_sync(mcspi->dev);
284 return 0;
285}
286
287static int omap2_unprepare_transfer(struct spi_master *master)
288{
289 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
290
291 pm_runtime_mark_last_busy(mcspi->dev);
292 pm_runtime_put_autosuspend(mcspi->dev);
293 return 0;
294}
295
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300296static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
297{
298 unsigned long timeout;
299
300 timeout = jiffies + msecs_to_jiffies(1000);
301 while (!(__raw_readl(reg) & bit)) {
302 if (time_after(jiffies, timeout))
303 return -1;
304 cpu_relax();
305 }
306 return 0;
307}
308
Russell King53741ed2012-04-23 13:51:48 +0100309static void omap2_mcspi_rx_callback(void *data)
310{
311 struct spi_device *spi = data;
312 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
313 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
314
315 complete(&mcspi_dma->dma_rx_completion);
316
317 /* We must disable the DMA RX request */
318 omap2_mcspi_set_dma_req(spi, 1, 0);
319}
320
321static void omap2_mcspi_tx_callback(void *data)
322{
323 struct spi_device *spi = data;
324 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
325 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
326
327 complete(&mcspi_dma->dma_tx_completion);
328
329 /* We must disable the DMA TX request */
330 omap2_mcspi_set_dma_req(spi, 0, 0);
331}
332
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700333static unsigned
334omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
335{
336 struct omap2_mcspi *mcspi;
337 struct omap2_mcspi_cs *cs = spi->controller_state;
338 struct omap2_mcspi_dma *mcspi_dma;
339 unsigned int count, c;
340 unsigned long base, tx_reg, rx_reg;
341 int word_len, data_type, element_count;
Govindraj.R8b20c8c2011-06-01 11:31:24 +0530342 int elements = 0;
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000343 u32 l;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700344 u8 * rx;
345 const u8 * tx;
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300346 void __iomem *chstat_reg;
Russell King53741ed2012-04-23 13:51:48 +0100347 struct dma_slave_config cfg;
348 enum dma_slave_buswidth width;
349 unsigned es;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700350
351 mcspi = spi_master_get_devdata(spi->master);
352 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000353 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700354
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300355 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
356
Russell King53741ed2012-04-23 13:51:48 +0100357 if (cs->word_len <= 8) {
358 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
359 es = 1;
360 } else if (cs->word_len <= 16) {
361 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
362 es = 2;
363 } else {
364 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
365 es = 4;
366 }
367
368 memset(&cfg, 0, sizeof(cfg));
369 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
370 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
371 cfg.src_addr_width = width;
372 cfg.dst_addr_width = width;
373 cfg.src_maxburst = 1;
374 cfg.dst_maxburst = 1;
375
376 if (xfer->tx_buf && mcspi_dma->dma_tx) {
377 struct dma_async_tx_descriptor *tx;
378 struct scatterlist sg;
379
380 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
381
382 sg_init_table(&sg, 1);
383 sg_dma_address(&sg) = xfer->tx_dma;
384 sg_dma_len(&sg) = xfer->len;
385
386 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
387 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
388 if (tx) {
389 tx->callback = omap2_mcspi_tx_callback;
390 tx->callback_param = spi;
391 dmaengine_submit(tx);
392 } else {
393 /* FIXME: fall back to PIO? */
394 }
395 }
396
397 if (xfer->rx_buf && mcspi_dma->dma_rx) {
398 struct dma_async_tx_descriptor *tx;
399 struct scatterlist sg;
400 size_t len = xfer->len - es;
401
402 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
403
404 if (l & OMAP2_MCSPI_CHCONF_TURBO)
405 len -= es;
406
407 sg_init_table(&sg, 1);
408 sg_dma_address(&sg) = xfer->rx_dma;
409 sg_dma_len(&sg) = len;
410
411 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
412 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
413 if (tx) {
414 tx->callback = omap2_mcspi_rx_callback;
415 tx->callback_param = spi;
416 dmaengine_submit(tx);
417 } else {
418 /* FIXME: fall back to PIO? */
419 }
420 }
421
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700422 count = xfer->len;
423 c = count;
424 word_len = cs->word_len;
425
Russell Kinge5480b732008-09-01 21:51:50 +0100426 base = cs->phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700427 tx_reg = base + OMAP2_MCSPI_TX0;
428 rx_reg = base + OMAP2_MCSPI_RX0;
429 rx = xfer->rx_buf;
430 tx = xfer->tx_buf;
431
432 if (word_len <= 8) {
433 data_type = OMAP_DMA_DATA_TYPE_S8;
434 element_count = count;
435 } else if (word_len <= 16) {
436 data_type = OMAP_DMA_DATA_TYPE_S16;
437 element_count = count >> 1;
438 } else /* word_len <= 32 */ {
439 data_type = OMAP_DMA_DATA_TYPE_S32;
440 element_count = count >> 2;
441 }
442
Russell King53741ed2012-04-23 13:51:48 +0100443 if (tx != NULL && mcspi_dma->dma_tx_channel != -1) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700444 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
445 data_type, element_count, 1,
446 OMAP_DMA_SYNC_ELEMENT,
447 mcspi_dma->dma_tx_sync_dev, 0);
448
449 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
450 OMAP_DMA_AMODE_CONSTANT,
451 tx_reg, 0, 0);
452
453 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
454 OMAP_DMA_AMODE_POST_INC,
455 xfer->tx_dma, 0, 0);
456 }
457
Russell King53741ed2012-04-23 13:51:48 +0100458 if (rx != NULL && mcspi_dma->dma_rx_channel != -1) {
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000459 elements = element_count - 1;
460 if (l & OMAP2_MCSPI_CHCONF_TURBO)
461 elements--;
462
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700463 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000464 data_type, elements, 1,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700465 OMAP_DMA_SYNC_ELEMENT,
466 mcspi_dma->dma_rx_sync_dev, 1);
467
468 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
469 OMAP_DMA_AMODE_CONSTANT,
470 rx_reg, 0, 0);
471
472 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
473 OMAP_DMA_AMODE_POST_INC,
474 xfer->rx_dma, 0, 0);
475 }
476
477 if (tx != NULL) {
Russell King53741ed2012-04-23 13:51:48 +0100478 if (mcspi_dma->dma_tx)
479 dma_async_issue_pending(mcspi_dma->dma_tx);
480 else
481 omap_start_dma(mcspi_dma->dma_tx_channel);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700482 omap2_mcspi_set_dma_req(spi, 0, 1);
483 }
484
485 if (rx != NULL) {
Russell King53741ed2012-04-23 13:51:48 +0100486 if (mcspi_dma->dma_rx)
487 dma_async_issue_pending(mcspi_dma->dma_rx);
488 else
489 omap_start_dma(mcspi_dma->dma_rx_channel);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700490 omap2_mcspi_set_dma_req(spi, 1, 1);
491 }
492
493 if (tx != NULL) {
494 wait_for_completion(&mcspi_dma->dma_tx_completion);
Russell King - ARM Linux07fe0352011-01-07 15:49:20 +0000495 dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300496
497 /* for TX_ONLY mode, be sure all words have shifted out */
498 if (rx == NULL) {
499 if (mcspi_wait_for_reg_bit(chstat_reg,
500 OMAP2_MCSPI_CHSTAT_TXS) < 0)
501 dev_err(&spi->dev, "TXS timed out\n");
502 else if (mcspi_wait_for_reg_bit(chstat_reg,
503 OMAP2_MCSPI_CHSTAT_EOT) < 0)
504 dev_err(&spi->dev, "EOT timed out\n");
505 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700506 }
507
508 if (rx != NULL) {
509 wait_for_completion(&mcspi_dma->dma_rx_completion);
Russell King - ARM Linux07fe0352011-01-07 15:49:20 +0000510 dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
Eero Nurkkala57c5c28d2009-07-29 15:02:12 -0700511 omap2_mcspi_set_enable(spi, 0);
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000512
Russell King53741ed2012-04-23 13:51:48 +0100513 elements = element_count - 1;
514
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000515 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
Russell King53741ed2012-04-23 13:51:48 +0100516 elements--;
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000517
518 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
519 & OMAP2_MCSPI_CHSTAT_RXS)) {
520 u32 w;
521
522 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
523 if (word_len <= 8)
524 ((u8 *)xfer->rx_buf)[elements++] = w;
525 else if (word_len <= 16)
526 ((u16 *)xfer->rx_buf)[elements++] = w;
527 else /* word_len <= 32 */
528 ((u32 *)xfer->rx_buf)[elements++] = w;
529 } else {
530 dev_err(&spi->dev,
531 "DMA RX penultimate word empty");
532 count -= (word_len <= 8) ? 2 :
533 (word_len <= 16) ? 4 :
534 /* word_len <= 32 */ 8;
535 omap2_mcspi_set_enable(spi, 1);
536 return count;
537 }
538 }
539
Eero Nurkkala57c5c28d2009-07-29 15:02:12 -0700540 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
541 & OMAP2_MCSPI_CHSTAT_RXS)) {
542 u32 w;
543
544 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
545 if (word_len <= 8)
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000546 ((u8 *)xfer->rx_buf)[elements] = w;
Eero Nurkkala57c5c28d2009-07-29 15:02:12 -0700547 else if (word_len <= 16)
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000548 ((u16 *)xfer->rx_buf)[elements] = w;
Eero Nurkkala57c5c28d2009-07-29 15:02:12 -0700549 else /* word_len <= 32 */
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000550 ((u32 *)xfer->rx_buf)[elements] = w;
Eero Nurkkala57c5c28d2009-07-29 15:02:12 -0700551 } else {
552 dev_err(&spi->dev, "DMA RX last word empty");
553 count -= (word_len <= 8) ? 1 :
554 (word_len <= 16) ? 2 :
555 /* word_len <= 32 */ 4;
556 }
557 omap2_mcspi_set_enable(spi, 1);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700558 }
559 return count;
560}
561
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700562static unsigned
563omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
564{
565 struct omap2_mcspi *mcspi;
566 struct omap2_mcspi_cs *cs = spi->controller_state;
567 unsigned int count, c;
568 u32 l;
569 void __iomem *base = cs->base;
570 void __iomem *tx_reg;
571 void __iomem *rx_reg;
572 void __iomem *chstat_reg;
573 int word_len;
574
575 mcspi = spi_master_get_devdata(spi->master);
576 count = xfer->len;
577 c = count;
578 word_len = cs->word_len;
579
Hemanth Va41ae1a2009-09-22 16:46:16 -0700580 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700581
582 /* We store the pre-calculated register addresses on stack to speed
583 * up the transfer loop. */
584 tx_reg = base + OMAP2_MCSPI_TX0;
585 rx_reg = base + OMAP2_MCSPI_RX0;
586 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
587
Michael Jonesadef6582011-02-25 16:55:11 +0100588 if (c < (word_len>>3))
589 return 0;
590
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700591 if (word_len <= 8) {
592 u8 *rx;
593 const u8 *tx;
594
595 rx = xfer->rx_buf;
596 tx = xfer->tx_buf;
597
598 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800599 c -= 1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700600 if (tx != NULL) {
601 if (mcspi_wait_for_reg_bit(chstat_reg,
602 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
603 dev_err(&spi->dev, "TXS timed out\n");
604 goto out;
605 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900606 dev_vdbg(&spi->dev, "write-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700607 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700608 __raw_writel(*tx++, tx_reg);
609 }
610 if (rx != NULL) {
611 if (mcspi_wait_for_reg_bit(chstat_reg,
612 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
613 dev_err(&spi->dev, "RXS timed out\n");
614 goto out;
615 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000616
617 if (c == 1 && tx == NULL &&
618 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
619 omap2_mcspi_set_enable(spi, 0);
620 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900621 dev_vdbg(&spi->dev, "read-%d %02x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000622 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000623 if (mcspi_wait_for_reg_bit(chstat_reg,
624 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
625 dev_err(&spi->dev,
626 "RXS timed out\n");
627 goto out;
628 }
629 c = 0;
630 } else if (c == 0 && tx == NULL) {
631 omap2_mcspi_set_enable(spi, 0);
632 }
633
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700634 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900635 dev_vdbg(&spi->dev, "read-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700636 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700637 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200638 } while (c);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700639 } else if (word_len <= 16) {
640 u16 *rx;
641 const u16 *tx;
642
643 rx = xfer->rx_buf;
644 tx = xfer->tx_buf;
645 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800646 c -= 2;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700647 if (tx != NULL) {
648 if (mcspi_wait_for_reg_bit(chstat_reg,
649 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
650 dev_err(&spi->dev, "TXS timed out\n");
651 goto out;
652 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900653 dev_vdbg(&spi->dev, "write-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700654 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700655 __raw_writel(*tx++, tx_reg);
656 }
657 if (rx != NULL) {
658 if (mcspi_wait_for_reg_bit(chstat_reg,
659 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
660 dev_err(&spi->dev, "RXS timed out\n");
661 goto out;
662 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000663
664 if (c == 2 && tx == NULL &&
665 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
666 omap2_mcspi_set_enable(spi, 0);
667 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900668 dev_vdbg(&spi->dev, "read-%d %04x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000669 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000670 if (mcspi_wait_for_reg_bit(chstat_reg,
671 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
672 dev_err(&spi->dev,
673 "RXS timed out\n");
674 goto out;
675 }
676 c = 0;
677 } else if (c == 0 && tx == NULL) {
678 omap2_mcspi_set_enable(spi, 0);
679 }
680
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700681 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900682 dev_vdbg(&spi->dev, "read-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700683 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700684 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200685 } while (c >= 2);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700686 } else if (word_len <= 32) {
687 u32 *rx;
688 const u32 *tx;
689
690 rx = xfer->rx_buf;
691 tx = xfer->tx_buf;
692 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800693 c -= 4;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700694 if (tx != NULL) {
695 if (mcspi_wait_for_reg_bit(chstat_reg,
696 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
697 dev_err(&spi->dev, "TXS timed out\n");
698 goto out;
699 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900700 dev_vdbg(&spi->dev, "write-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700701 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700702 __raw_writel(*tx++, tx_reg);
703 }
704 if (rx != NULL) {
705 if (mcspi_wait_for_reg_bit(chstat_reg,
706 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
707 dev_err(&spi->dev, "RXS timed out\n");
708 goto out;
709 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000710
711 if (c == 4 && tx == NULL &&
712 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
713 omap2_mcspi_set_enable(spi, 0);
714 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900715 dev_vdbg(&spi->dev, "read-%d %08x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000716 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000717 if (mcspi_wait_for_reg_bit(chstat_reg,
718 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
719 dev_err(&spi->dev,
720 "RXS timed out\n");
721 goto out;
722 }
723 c = 0;
724 } else if (c == 0 && tx == NULL) {
725 omap2_mcspi_set_enable(spi, 0);
726 }
727
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700728 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900729 dev_vdbg(&spi->dev, "read-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700730 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700731 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200732 } while (c >= 4);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700733 }
734
735 /* for TX_ONLY mode, be sure all words have shifted out */
736 if (xfer->rx_buf == NULL) {
737 if (mcspi_wait_for_reg_bit(chstat_reg,
738 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
739 dev_err(&spi->dev, "TXS timed out\n");
740 } else if (mcspi_wait_for_reg_bit(chstat_reg,
741 OMAP2_MCSPI_CHSTAT_EOT) < 0)
742 dev_err(&spi->dev, "EOT timed out\n");
Jason Wange1993ed2010-10-19 18:03:27 +0800743
744 /* disable chan to purge rx datas received in TX_ONLY transfer,
745 * otherwise these rx datas will affect the direct following
746 * RX_ONLY transfer.
747 */
748 omap2_mcspi_set_enable(spi, 0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700749 }
750out:
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000751 omap2_mcspi_set_enable(spi, 1);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700752 return count - c;
753}
754
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200755static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
756{
757 u32 div;
758
759 for (div = 0; div < 15; div++)
760 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
761 return div;
762
763 return 15;
764}
765
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700766/* called only when no transfer is active to this device */
767static int omap2_mcspi_setup_transfer(struct spi_device *spi,
768 struct spi_transfer *t)
769{
770 struct omap2_mcspi_cs *cs = spi->controller_state;
771 struct omap2_mcspi *mcspi;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700772 struct spi_master *spi_cntrl;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700773 u32 l = 0, div = 0;
774 u8 word_len = spi->bits_per_word;
Scott Ellis9bd45172010-03-10 14:23:13 -0700775 u32 speed_hz = spi->max_speed_hz;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700776
777 mcspi = spi_master_get_devdata(spi->master);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700778 spi_cntrl = mcspi->master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700779
780 if (t != NULL && t->bits_per_word)
781 word_len = t->bits_per_word;
782
783 cs->word_len = word_len;
784
Scott Ellis9bd45172010-03-10 14:23:13 -0700785 if (t && t->speed_hz)
786 speed_hz = t->speed_hz;
787
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200788 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
789 div = omap2_mcspi_calc_divisor(speed_hz);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700790
Hemanth Va41ae1a2009-09-22 16:46:16 -0700791 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700792
793 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
794 * REVISIT: this controller could support SPI_3WIRE mode.
795 */
796 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
797 l |= OMAP2_MCSPI_CHCONF_DPE0;
798
799 /* wordlength */
800 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
801 l |= (word_len - 1) << 7;
802
803 /* set chipselect polarity; manage with FORCE */
804 if (!(spi->mode & SPI_CS_HIGH))
805 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
806 else
807 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
808
809 /* set clock divisor */
810 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
811 l |= div << 2;
812
813 /* set SPI mode 0..3 */
814 if (spi->mode & SPI_CPOL)
815 l |= OMAP2_MCSPI_CHCONF_POL;
816 else
817 l &= ~OMAP2_MCSPI_CHCONF_POL;
818 if (spi->mode & SPI_CPHA)
819 l |= OMAP2_MCSPI_CHCONF_PHA;
820 else
821 l &= ~OMAP2_MCSPI_CHCONF_PHA;
822
Hemanth Va41ae1a2009-09-22 16:46:16 -0700823 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700824
825 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200826 OMAP2_MCSPI_MAX_FREQ >> div,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700827 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
828 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
829
830 return 0;
831}
832
833static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
834{
Russell King53741ed2012-04-23 13:51:48 +0100835 omap2_mcspi_rx_callback(data);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700836}
837
838static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
839{
Russell King53741ed2012-04-23 13:51:48 +0100840 omap2_mcspi_tx_callback(data);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700841}
842
843static int omap2_mcspi_request_dma(struct spi_device *spi)
844{
845 struct spi_master *master = spi->master;
846 struct omap2_mcspi *mcspi;
847 struct omap2_mcspi_dma *mcspi_dma;
Russell King53741ed2012-04-23 13:51:48 +0100848 dma_cap_mask_t mask;
849 unsigned sig;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700850
851 mcspi = spi_master_get_devdata(master);
852 mcspi_dma = mcspi->dma_channels + spi->chip_select;
853
Russell King53741ed2012-04-23 13:51:48 +0100854 init_completion(&mcspi_dma->dma_rx_completion);
855 init_completion(&mcspi_dma->dma_tx_completion);
856
857 dma_cap_zero(mask);
858 dma_cap_set(DMA_SLAVE, mask);
859#ifdef USE_DMA_ENGINE_RX
860 sig = mcspi_dma->dma_rx_sync_dev;
861 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
862 if (!mcspi_dma->dma_rx) {
863 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
864 return -EAGAIN;
865 }
866#else
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700867 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
868 omap2_mcspi_dma_rx_callback, spi,
869 &mcspi_dma->dma_rx_channel)) {
870 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
871 return -EAGAIN;
872 }
Russell King53741ed2012-04-23 13:51:48 +0100873#endif
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700874
Russell King53741ed2012-04-23 13:51:48 +0100875#ifdef USE_DMA_ENGINE_TX
876 sig = mcspi_dma->dma_tx_sync_dev;
877 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
878 if (!mcspi_dma->dma_tx) {
879 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
880 dma_release_channel(mcspi_dma->dma_rx);
881 mcspi_dma->dma_rx = NULL;
882 return -EAGAIN;
883 }
884#else
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700885 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
886 omap2_mcspi_dma_tx_callback, spi,
887 &mcspi_dma->dma_tx_channel)) {
888 omap_free_dma(mcspi_dma->dma_rx_channel);
889 mcspi_dma->dma_rx_channel = -1;
890 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
891 return -EAGAIN;
892 }
Russell King53741ed2012-04-23 13:51:48 +0100893#endif
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700894
895 return 0;
896}
897
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700898static int omap2_mcspi_setup(struct spi_device *spi)
899{
900 int ret;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530901 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
902 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700903 struct omap2_mcspi_dma *mcspi_dma;
904 struct omap2_mcspi_cs *cs = spi->controller_state;
905
David Brownell7d077192009-06-17 16:26:03 -0700906 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700907 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
908 spi->bits_per_word);
909 return -EINVAL;
910 }
911
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700912 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
913
914 if (!cs) {
Russell King10aa5a32012-06-18 11:27:04 +0100915 cs = kzalloc(sizeof *cs, GFP_KERNEL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700916 if (!cs)
917 return -ENOMEM;
918 cs->base = mcspi->base + spi->chip_select * 0x14;
Russell Kinge5480b732008-09-01 21:51:50 +0100919 cs->phys = mcspi->phys + spi->chip_select * 0x14;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700920 cs->chconf0 = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700921 spi->controller_state = cs;
Tero Kristo89c05372009-09-22 16:46:17 -0700922 /* Link this to context save list */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530923 list_add_tail(&cs->node, &ctx->cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700924 }
925
Russell King53741ed2012-04-23 13:51:48 +0100926 if ((!mcspi_dma->dma_rx && mcspi_dma->dma_rx_channel == -1) ||
927 (!mcspi_dma->dma_tx && mcspi_dma->dma_tx_channel == -1)) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700928 ret = omap2_mcspi_request_dma(spi);
929 if (ret < 0)
930 return ret;
931 }
932
Govindraj.R1f1a4382011-02-02 17:52:15 +0530933 ret = omap2_mcspi_enable_clocks(mcspi);
934 if (ret < 0)
935 return ret;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700936
Kyungmin Park86eeb6f2007-10-16 01:27:45 -0700937 ret = omap2_mcspi_setup_transfer(spi, NULL);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700938 omap2_mcspi_disable_clocks(mcspi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700939
940 return ret;
941}
942
943static void omap2_mcspi_cleanup(struct spi_device *spi)
944{
945 struct omap2_mcspi *mcspi;
946 struct omap2_mcspi_dma *mcspi_dma;
Tero Kristo89c05372009-09-22 16:46:17 -0700947 struct omap2_mcspi_cs *cs;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700948
949 mcspi = spi_master_get_devdata(spi->master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700950
Scott Ellis5e774942010-03-10 14:22:45 -0700951 if (spi->controller_state) {
952 /* Unlink controller state from context save list */
953 cs = spi->controller_state;
954 list_del(&cs->node);
Tero Kristo89c05372009-09-22 16:46:17 -0700955
Russell King10aa5a32012-06-18 11:27:04 +0100956 kfree(cs);
Scott Ellis5e774942010-03-10 14:22:45 -0700957 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700958
Scott Ellis99f1a432010-05-24 14:20:27 +0000959 if (spi->chip_select < spi->master->num_chipselect) {
960 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
961
Russell King53741ed2012-04-23 13:51:48 +0100962 if (mcspi_dma->dma_rx) {
963 dma_release_channel(mcspi_dma->dma_rx);
964 mcspi_dma->dma_rx = NULL;
965 }
966 if (mcspi_dma->dma_tx) {
967 dma_release_channel(mcspi_dma->dma_tx);
968 mcspi_dma->dma_tx = NULL;
969 }
Scott Ellis99f1a432010-05-24 14:20:27 +0000970 if (mcspi_dma->dma_rx_channel != -1) {
971 omap_free_dma(mcspi_dma->dma_rx_channel);
972 mcspi_dma->dma_rx_channel = -1;
973 }
974 if (mcspi_dma->dma_tx_channel != -1) {
975 omap_free_dma(mcspi_dma->dma_tx_channel);
976 mcspi_dma->dma_tx_channel = -1;
977 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700978 }
979}
980
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530981static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700982{
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700983
984 /* We only enable one channel at a time -- the one whose message is
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530985 * -- although this controller would gladly
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700986 * arbitrate among multiple channels. This corresponds to "single
987 * channel" master mode. As a side effect, we need to manage the
988 * chipselect with the FORCE bit ... CS != channel enable.
989 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700990
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530991 struct spi_device *spi;
992 struct spi_transfer *t = NULL;
993 int cs_active = 0;
994 struct omap2_mcspi_cs *cs;
995 struct omap2_mcspi_device_config *cd;
996 int par_override = 0;
997 int status = 0;
998 u32 chconf;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700999
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301000 spi = m->spi;
1001 cs = spi->controller_state;
1002 cd = spi->controller_data;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001003
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301004 omap2_mcspi_set_enable(spi, 1);
1005 list_for_each_entry(t, &m->transfers, transfer_list) {
1006 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1007 status = -EINVAL;
1008 break;
1009 }
1010 if (par_override || t->speed_hz || t->bits_per_word) {
1011 par_override = 1;
1012 status = omap2_mcspi_setup_transfer(spi, t);
1013 if (status < 0)
1014 break;
1015 if (!t->speed_hz && !t->bits_per_word)
1016 par_override = 0;
1017 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001018
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301019 if (!cs_active) {
1020 omap2_mcspi_force_cs(spi, 1);
1021 cs_active = 1;
1022 }
1023
1024 chconf = mcspi_cached_chconf0(spi);
1025 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1026 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1027
1028 if (t->tx_buf == NULL)
1029 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1030 else if (t->rx_buf == NULL)
1031 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1032
1033 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1034 /* Turbo mode is for more than one word */
1035 if (t->len > ((cs->word_len + 7) >> 3))
1036 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1037 }
1038
1039 mcspi_write_chconf0(spi, chconf);
1040
1041 if (t->len) {
1042 unsigned count;
1043
1044 /* RX_ONLY mode needs dummy data in TX reg */
1045 if (t->tx_buf == NULL)
1046 __raw_writel(0, cs->base
1047 + OMAP2_MCSPI_TX0);
1048
1049 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
1050 count = omap2_mcspi_txrx_dma(spi, t);
1051 else
1052 count = omap2_mcspi_txrx_pio(spi, t);
1053 m->actual_length += count;
1054
1055 if (count != t->len) {
1056 status = -EIO;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001057 break;
1058 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001059 }
1060
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301061 if (t->delay_usecs)
1062 udelay(t->delay_usecs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001063
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301064 /* ignore the "leave it on after last xfer" hint */
1065 if (t->cs_change) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001066 omap2_mcspi_force_cs(spi, 0);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301067 cs_active = 0;
1068 }
1069 }
1070 /* Restore defaults if they were overriden */
1071 if (par_override) {
1072 par_override = 0;
1073 status = omap2_mcspi_setup_transfer(spi, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001074 }
1075
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301076 if (cs_active)
1077 omap2_mcspi_force_cs(spi, 0);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301078
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301079 omap2_mcspi_set_enable(spi, 0);
1080
1081 m->status = status;
1082
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001083}
1084
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301085static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1086 struct spi_message *m)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001087{
1088 struct omap2_mcspi *mcspi;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001089 struct spi_transfer *t;
1090
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301091 mcspi = spi_master_get_devdata(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001092 m->actual_length = 0;
1093 m->status = 0;
1094
1095 /* reject invalid messages and transfers */
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301096 if (list_empty(&m->transfers))
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001097 return -EINVAL;
1098 list_for_each_entry(t, &m->transfers, transfer_list) {
1099 const void *tx_buf = t->tx_buf;
1100 void *rx_buf = t->rx_buf;
1101 unsigned len = t->len;
1102
1103 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1104 || (len && !(rx_buf || tx_buf))
1105 || (t->bits_per_word &&
1106 ( t->bits_per_word < 4
1107 || t->bits_per_word > 32))) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301108 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001109 t->speed_hz,
1110 len,
1111 tx_buf ? "tx" : "",
1112 rx_buf ? "rx" : "",
1113 t->bits_per_word);
1114 return -EINVAL;
1115 }
Hannu Heikkinen57d9c102011-02-24 21:31:33 +02001116 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301117 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
Hannu Heikkinen57d9c102011-02-24 21:31:33 +02001118 t->speed_hz,
1119 OMAP2_MCSPI_MAX_FREQ >> 15);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001120 return -EINVAL;
1121 }
1122
1123 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1124 continue;
1125
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001126 if (tx_buf != NULL) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301127 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001128 len, DMA_TO_DEVICE);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301129 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1130 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001131 'T', len);
1132 return -EINVAL;
1133 }
1134 }
1135 if (rx_buf != NULL) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301136 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001137 DMA_FROM_DEVICE);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301138 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1139 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001140 'R', len);
1141 if (tx_buf != NULL)
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301142 dma_unmap_single(mcspi->dev, t->tx_dma,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001143 len, DMA_TO_DEVICE);
1144 return -EINVAL;
1145 }
1146 }
1147 }
1148
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301149 omap2_mcspi_work(mcspi, m);
1150 spi_finalize_current_message(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001151 return 0;
1152}
1153
Govindraj.R1f1a4382011-02-02 17:52:15 +05301154static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001155{
1156 struct spi_master *master = mcspi->master;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301157 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301158 int ret = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001159
Govindraj.R1f1a4382011-02-02 17:52:15 +05301160 ret = omap2_mcspi_enable_clocks(mcspi);
1161 if (ret < 0)
1162 return ret;
Jouni Hoganderddb22192009-07-29 15:02:11 -07001163
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301164 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1165 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1166 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001167
1168 omap2_mcspi_set_master_mode(master);
Hemanth Va41ae1a2009-09-22 16:46:16 -07001169 omap2_mcspi_disable_clocks(mcspi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001170 return 0;
1171}
1172
Govindraj.R1f1a4382011-02-02 17:52:15 +05301173static int omap_mcspi_runtime_resume(struct device *dev)
1174{
1175 struct omap2_mcspi *mcspi;
1176 struct spi_master *master;
1177
1178 master = dev_get_drvdata(dev);
1179 mcspi = spi_master_get_devdata(master);
1180 omap2_mcspi_restore_ctx(mcspi);
1181
1182 return 0;
1183}
1184
Benoit Coussond5a80032012-02-15 18:37:34 +01001185static struct omap2_mcspi_platform_config omap2_pdata = {
1186 .regs_offset = 0,
1187};
1188
1189static struct omap2_mcspi_platform_config omap4_pdata = {
1190 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1191};
1192
1193static const struct of_device_id omap_mcspi_of_match[] = {
1194 {
1195 .compatible = "ti,omap2-mcspi",
1196 .data = &omap2_pdata,
1197 },
1198 {
1199 .compatible = "ti,omap4-mcspi",
1200 .data = &omap4_pdata,
1201 },
1202 { },
1203};
1204MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
Girishccc7bae2008-02-06 01:38:16 -08001205
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001206static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001207{
1208 struct spi_master *master;
Benoit Coussond5a80032012-02-15 18:37:34 +01001209 struct omap2_mcspi_platform_config *pdata;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001210 struct omap2_mcspi *mcspi;
1211 struct resource *r;
1212 int status = 0, i;
Benoit Coussond5a80032012-02-15 18:37:34 +01001213 u32 regs_offset = 0;
1214 static int bus_num = 1;
1215 struct device_node *node = pdev->dev.of_node;
1216 const struct of_device_id *match;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001217
1218 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1219 if (master == NULL) {
1220 dev_dbg(&pdev->dev, "master allocation failed\n");
1221 return -ENOMEM;
1222 }
1223
David Brownelle7db06b2009-06-17 16:26:04 -07001224 /* the spi->mode bits understood by this driver: */
1225 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1226
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001227 master->setup = omap2_mcspi_setup;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301228 master->prepare_transfer_hardware = omap2_prepare_transfer;
1229 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1230 master->transfer_one_message = omap2_mcspi_transfer_one_message;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001231 master->cleanup = omap2_mcspi_cleanup;
Benoit Coussond5a80032012-02-15 18:37:34 +01001232 master->dev.of_node = node;
1233
1234 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1235 if (match) {
1236 u32 num_cs = 1; /* default number of chipselect */
1237 pdata = match->data;
1238
1239 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1240 master->num_chipselect = num_cs;
1241 master->bus_num = bus_num++;
1242 } else {
1243 pdata = pdev->dev.platform_data;
1244 master->num_chipselect = pdata->num_cs;
1245 if (pdev->id != -1)
1246 master->bus_num = pdev->id;
1247 }
1248 regs_offset = pdata->regs_offset;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001249
1250 dev_set_drvdata(&pdev->dev, master);
1251
1252 mcspi = spi_master_get_devdata(master);
1253 mcspi->master = master;
1254
1255 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256 if (r == NULL) {
1257 status = -ENODEV;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301258 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001259 }
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301260
Benoit Coussond5a80032012-02-15 18:37:34 +01001261 r->start += regs_offset;
1262 r->end += regs_offset;
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301263 mcspi->phys = r->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001264
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301265 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
Russell King55c381e2008-09-04 14:07:22 +01001266 if (!mcspi->base) {
1267 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1268 status = -ENOMEM;
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301269 goto free_master;
Russell King55c381e2008-09-04 14:07:22 +01001270 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001271
Govindraj.R1f1a4382011-02-02 17:52:15 +05301272 mcspi->dev = &pdev->dev;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001273
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301274 INIT_LIST_HEAD(&mcspi->ctx.cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001275
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001276 mcspi->dma_channels = kcalloc(master->num_chipselect,
1277 sizeof(struct omap2_mcspi_dma),
1278 GFP_KERNEL);
1279
1280 if (mcspi->dma_channels == NULL)
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301281 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001282
Charulatha V1a5d8192011-02-02 17:52:14 +05301283 for (i = 0; i < master->num_chipselect; i++) {
1284 char dma_ch_name[14];
1285 struct resource *dma_res;
1286
1287 sprintf(dma_ch_name, "rx%d", i);
1288 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1289 dma_ch_name);
1290 if (!dma_res) {
1291 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1292 status = -ENODEV;
1293 break;
1294 }
1295
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001296 mcspi->dma_channels[i].dma_rx_channel = -1;
Charulatha V1a5d8192011-02-02 17:52:14 +05301297 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1298 sprintf(dma_ch_name, "tx%d", i);
1299 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1300 dma_ch_name);
1301 if (!dma_res) {
1302 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1303 status = -ENODEV;
1304 break;
1305 }
1306
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001307 mcspi->dma_channels[i].dma_tx_channel = -1;
Charulatha V1a5d8192011-02-02 17:52:14 +05301308 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001309 }
1310
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301311 if (status < 0)
1312 goto dma_chnl_free;
1313
Shubhrajyoti D27b52842012-03-26 17:04:22 +05301314 pm_runtime_use_autosuspend(&pdev->dev);
1315 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301316 pm_runtime_enable(&pdev->dev);
1317
1318 if (status || omap2_mcspi_master_setup(mcspi) < 0)
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301319 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001320
1321 status = spi_register_master(master);
1322 if (status < 0)
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301323 goto err_spi_register;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001324
1325 return status;
1326
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301327err_spi_register:
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001328 spi_master_put(master);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301329disable_pm:
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301330 pm_runtime_disable(&pdev->dev);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301331dma_chnl_free:
Govindraj.R1f1a4382011-02-02 17:52:15 +05301332 kfree(mcspi->dma_channels);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301333free_master:
1334 kfree(master);
1335 platform_set_drvdata(pdev, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001336 return status;
1337}
1338
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001339static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001340{
1341 struct spi_master *master;
1342 struct omap2_mcspi *mcspi;
1343 struct omap2_mcspi_dma *dma_channels;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001344
1345 master = dev_get_drvdata(&pdev->dev);
1346 mcspi = spi_master_get_devdata(master);
1347 dma_channels = mcspi->dma_channels;
1348
Govindraj.R1f1a4382011-02-02 17:52:15 +05301349 omap2_mcspi_disable_clocks(mcspi);
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301350 pm_runtime_disable(&pdev->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001351
1352 spi_unregister_master(master);
1353 kfree(dma_channels);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301354 platform_set_drvdata(pdev, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001355
1356 return 0;
1357}
1358
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001359/* work with hotplug and coldplug */
1360MODULE_ALIAS("platform:omap2_mcspi");
1361
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001362#ifdef CONFIG_SUSPEND
1363/*
1364 * When SPI wake up from off-mode, CS is in activate state. If it was in
1365 * unactive state when driver was suspend, then force it to unactive state at
1366 * wake up.
1367 */
1368static int omap2_mcspi_resume(struct device *dev)
1369{
1370 struct spi_master *master = dev_get_drvdata(dev);
1371 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301372 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1373 struct omap2_mcspi_cs *cs;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001374
1375 omap2_mcspi_enable_clocks(mcspi);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301376 list_for_each_entry(cs, &ctx->cs, node) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001377 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001378 /*
1379 * We need to toggle CS state for OMAP take this
1380 * change in account.
1381 */
1382 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
1383 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1384 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
1385 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1386 }
1387 }
1388 omap2_mcspi_disable_clocks(mcspi);
1389 return 0;
1390}
1391#else
1392#define omap2_mcspi_resume NULL
1393#endif
1394
1395static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1396 .resume = omap2_mcspi_resume,
Govindraj.R1f1a4382011-02-02 17:52:15 +05301397 .runtime_resume = omap_mcspi_runtime_resume,
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001398};
1399
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001400static struct platform_driver omap2_mcspi_driver = {
1401 .driver = {
1402 .name = "omap2_mcspi",
1403 .owner = THIS_MODULE,
Benoit Coussond5a80032012-02-15 18:37:34 +01001404 .pm = &omap2_mcspi_pm_ops,
1405 .of_match_table = omap_mcspi_of_match,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001406 },
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001407 .probe = omap2_mcspi_probe,
1408 .remove = __devexit_p(omap2_mcspi_remove),
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001409};
1410
Felipe Balbi9fdca9d2012-03-14 11:18:31 +02001411module_platform_driver(omap2_mcspi_driver);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001412MODULE_LICENSE("GPL");