Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2 McSPI controller driver |
| 3 | * |
| 4 | * Copyright (C) 2005, 2006 Nokia Corporation |
| 5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 23 | #define USE_DMA_ENGINE_RX |
| 24 | #define USE_DMA_ENGINE_TX |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 25 | |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/init.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/device.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/dma-mapping.h> |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 33 | #include <linux/dmaengine.h> |
| 34 | #include <linux/omap-dma.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 35 | #include <linux/platform_device.h> |
| 36 | #include <linux/err.h> |
| 37 | #include <linux/clk.h> |
| 38 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 39 | #include <linux/slab.h> |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 40 | #include <linux/pm_runtime.h> |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 41 | #include <linux/of.h> |
| 42 | #include <linux/of_device.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 43 | |
| 44 | #include <linux/spi/spi.h> |
| 45 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 46 | #include <plat/dma.h> |
| 47 | #include <plat/clock.h> |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 48 | #include <plat/mcspi.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 49 | |
| 50 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 51 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 52 | |
| 53 | #define OMAP2_MCSPI_REVISION 0x00 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 54 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
| 55 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
| 56 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
| 57 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 |
| 58 | #define OMAP2_MCSPI_SYST 0x24 |
| 59 | #define OMAP2_MCSPI_MODULCTRL 0x28 |
| 60 | |
| 61 | /* per-channel banks, 0x14 bytes each, first is: */ |
| 62 | #define OMAP2_MCSPI_CHCONF0 0x2c |
| 63 | #define OMAP2_MCSPI_CHSTAT0 0x30 |
| 64 | #define OMAP2_MCSPI_CHCTRL0 0x34 |
| 65 | #define OMAP2_MCSPI_TX0 0x38 |
| 66 | #define OMAP2_MCSPI_RX0 0x3c |
| 67 | |
| 68 | /* per-register bitmasks: */ |
| 69 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 70 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
| 71 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
| 72 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 73 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 74 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
| 75 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 76 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 77 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 78 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 79 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
| 80 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 81 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 82 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
| 83 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) |
| 84 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) |
| 85 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) |
| 86 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) |
| 87 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) |
| 88 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 89 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 90 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
| 91 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) |
| 92 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 93 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 94 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 95 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 96 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 97 | |
| 98 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 99 | struct omap2_mcspi_dma { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 100 | struct dma_chan *dma_tx; |
| 101 | struct dma_chan *dma_rx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 102 | int dma_tx_channel; |
| 103 | int dma_rx_channel; |
| 104 | |
| 105 | int dma_tx_sync_dev; |
| 106 | int dma_rx_sync_dev; |
| 107 | |
| 108 | struct completion dma_tx_completion; |
| 109 | struct completion dma_rx_completion; |
| 110 | }; |
| 111 | |
| 112 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
| 113 | * cache operations; better heuristics consider wordsize and bitrate. |
| 114 | */ |
Roman Tereshonkov | 8b66c13 | 2010-04-12 09:07:54 +0000 | [diff] [blame] | 115 | #define DMA_MIN_BYTES 160 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 116 | |
| 117 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 118 | /* |
| 119 | * Used for context save and restore, structure members to be updated whenever |
| 120 | * corresponding registers are modified. |
| 121 | */ |
| 122 | struct omap2_mcspi_regs { |
| 123 | u32 modulctrl; |
| 124 | u32 wakeupenable; |
| 125 | struct list_head cs; |
| 126 | }; |
| 127 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 128 | struct omap2_mcspi { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 129 | struct spi_master *master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 130 | /* Virtual base address of the controller */ |
| 131 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 132 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 133 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
| 134 | struct omap2_mcspi_dma *dma_channels; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 135 | struct device *dev; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 136 | struct omap2_mcspi_regs ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 137 | }; |
| 138 | |
| 139 | struct omap2_mcspi_cs { |
| 140 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 141 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 142 | int word_len; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 143 | struct list_head node; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 144 | /* Context save and restore shadow register */ |
| 145 | u32 chconf0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 146 | }; |
| 147 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 148 | #define MOD_REG_BIT(val, mask, set) do { \ |
| 149 | if (set) \ |
| 150 | val |= mask; \ |
| 151 | else \ |
| 152 | val &= ~mask; \ |
| 153 | } while (0) |
| 154 | |
| 155 | static inline void mcspi_write_reg(struct spi_master *master, |
| 156 | int idx, u32 val) |
| 157 | { |
| 158 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 159 | |
| 160 | __raw_writel(val, mcspi->base + idx); |
| 161 | } |
| 162 | |
| 163 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
| 164 | { |
| 165 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 166 | |
| 167 | return __raw_readl(mcspi->base + idx); |
| 168 | } |
| 169 | |
| 170 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
| 171 | int idx, u32 val) |
| 172 | { |
| 173 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 174 | |
| 175 | __raw_writel(val, cs->base + idx); |
| 176 | } |
| 177 | |
| 178 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
| 179 | { |
| 180 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 181 | |
| 182 | return __raw_readl(cs->base + idx); |
| 183 | } |
| 184 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 185 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
| 186 | { |
| 187 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 188 | |
| 189 | return cs->chconf0; |
| 190 | } |
| 191 | |
| 192 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) |
| 193 | { |
| 194 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 195 | |
| 196 | cs->chconf0 = val; |
| 197 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); |
Roman Tereshonkov | a330ce2 | 2010-03-15 09:06:28 +0000 | [diff] [blame] | 198 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 199 | } |
| 200 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 201 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
| 202 | int is_read, int enable) |
| 203 | { |
| 204 | u32 l, rw; |
| 205 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 206 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 207 | |
| 208 | if (is_read) /* 1 is read, 0 write */ |
| 209 | rw = OMAP2_MCSPI_CHCONF_DMAR; |
| 210 | else |
| 211 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
| 212 | |
| 213 | MOD_REG_BIT(l, rw, enable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 214 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) |
| 218 | { |
| 219 | u32 l; |
| 220 | |
| 221 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; |
| 222 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 223 | /* Flash post-writes */ |
| 224 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) |
| 228 | { |
| 229 | u32 l; |
| 230 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 231 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 232 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 233 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
| 237 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 238 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 239 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 240 | u32 l; |
| 241 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 242 | /* |
| 243 | * Setup when switching from (reset default) slave mode |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 244 | * to single-channel master mode |
| 245 | */ |
| 246 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
| 247 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); |
| 248 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); |
| 249 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); |
| 250 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 251 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 252 | ctx->modulctrl = l; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
| 256 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 257 | struct spi_master *spi_cntrl = mcspi->master; |
| 258 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 259 | struct omap2_mcspi_cs *cs; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 260 | |
| 261 | /* McSPI: context restore */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 262 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
| 263 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 264 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 265 | list_for_each_entry(cs, &ctx->cs, node) |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 266 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 267 | } |
| 268 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) |
| 269 | { |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 270 | pm_runtime_mark_last_busy(mcspi->dev); |
| 271 | pm_runtime_put_autosuspend(mcspi->dev); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
| 275 | { |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 276 | return pm_runtime_get_sync(mcspi->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 277 | } |
| 278 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 279 | static int omap2_prepare_transfer(struct spi_master *master) |
| 280 | { |
| 281 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 282 | |
| 283 | pm_runtime_get_sync(mcspi->dev); |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static int omap2_unprepare_transfer(struct spi_master *master) |
| 288 | { |
| 289 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 290 | |
| 291 | pm_runtime_mark_last_busy(mcspi->dev); |
| 292 | pm_runtime_put_autosuspend(mcspi->dev); |
| 293 | return 0; |
| 294 | } |
| 295 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 296 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
| 297 | { |
| 298 | unsigned long timeout; |
| 299 | |
| 300 | timeout = jiffies + msecs_to_jiffies(1000); |
| 301 | while (!(__raw_readl(reg) & bit)) { |
| 302 | if (time_after(jiffies, timeout)) |
| 303 | return -1; |
| 304 | cpu_relax(); |
| 305 | } |
| 306 | return 0; |
| 307 | } |
| 308 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 309 | static void omap2_mcspi_rx_callback(void *data) |
| 310 | { |
| 311 | struct spi_device *spi = data; |
| 312 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 313 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 314 | |
| 315 | complete(&mcspi_dma->dma_rx_completion); |
| 316 | |
| 317 | /* We must disable the DMA RX request */ |
| 318 | omap2_mcspi_set_dma_req(spi, 1, 0); |
| 319 | } |
| 320 | |
| 321 | static void omap2_mcspi_tx_callback(void *data) |
| 322 | { |
| 323 | struct spi_device *spi = data; |
| 324 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 325 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 326 | |
| 327 | complete(&mcspi_dma->dma_tx_completion); |
| 328 | |
| 329 | /* We must disable the DMA TX request */ |
| 330 | omap2_mcspi_set_dma_req(spi, 0, 0); |
| 331 | } |
| 332 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 333 | static unsigned |
| 334 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
| 335 | { |
| 336 | struct omap2_mcspi *mcspi; |
| 337 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 338 | struct omap2_mcspi_dma *mcspi_dma; |
| 339 | unsigned int count, c; |
| 340 | unsigned long base, tx_reg, rx_reg; |
| 341 | int word_len, data_type, element_count; |
Govindraj.R | 8b20c8c | 2011-06-01 11:31:24 +0530 | [diff] [blame] | 342 | int elements = 0; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 343 | u32 l; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 344 | u8 * rx; |
| 345 | const u8 * tx; |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 346 | void __iomem *chstat_reg; |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 347 | struct dma_slave_config cfg; |
| 348 | enum dma_slave_buswidth width; |
| 349 | unsigned es; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 350 | |
| 351 | mcspi = spi_master_get_devdata(spi->master); |
| 352 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 353 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 354 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 355 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
| 356 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 357 | if (cs->word_len <= 8) { |
| 358 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 359 | es = 1; |
| 360 | } else if (cs->word_len <= 16) { |
| 361 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 362 | es = 2; |
| 363 | } else { |
| 364 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 365 | es = 4; |
| 366 | } |
| 367 | |
| 368 | memset(&cfg, 0, sizeof(cfg)); |
| 369 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; |
| 370 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; |
| 371 | cfg.src_addr_width = width; |
| 372 | cfg.dst_addr_width = width; |
| 373 | cfg.src_maxburst = 1; |
| 374 | cfg.dst_maxburst = 1; |
| 375 | |
| 376 | if (xfer->tx_buf && mcspi_dma->dma_tx) { |
| 377 | struct dma_async_tx_descriptor *tx; |
| 378 | struct scatterlist sg; |
| 379 | |
| 380 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); |
| 381 | |
| 382 | sg_init_table(&sg, 1); |
| 383 | sg_dma_address(&sg) = xfer->tx_dma; |
| 384 | sg_dma_len(&sg) = xfer->len; |
| 385 | |
| 386 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, |
| 387 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 388 | if (tx) { |
| 389 | tx->callback = omap2_mcspi_tx_callback; |
| 390 | tx->callback_param = spi; |
| 391 | dmaengine_submit(tx); |
| 392 | } else { |
| 393 | /* FIXME: fall back to PIO? */ |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | if (xfer->rx_buf && mcspi_dma->dma_rx) { |
| 398 | struct dma_async_tx_descriptor *tx; |
| 399 | struct scatterlist sg; |
| 400 | size_t len = xfer->len - es; |
| 401 | |
| 402 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); |
| 403 | |
| 404 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
| 405 | len -= es; |
| 406 | |
| 407 | sg_init_table(&sg, 1); |
| 408 | sg_dma_address(&sg) = xfer->rx_dma; |
| 409 | sg_dma_len(&sg) = len; |
| 410 | |
| 411 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, |
| 412 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 413 | if (tx) { |
| 414 | tx->callback = omap2_mcspi_rx_callback; |
| 415 | tx->callback_param = spi; |
| 416 | dmaengine_submit(tx); |
| 417 | } else { |
| 418 | /* FIXME: fall back to PIO? */ |
| 419 | } |
| 420 | } |
| 421 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 422 | count = xfer->len; |
| 423 | c = count; |
| 424 | word_len = cs->word_len; |
| 425 | |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 426 | base = cs->phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 427 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 428 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 429 | rx = xfer->rx_buf; |
| 430 | tx = xfer->tx_buf; |
| 431 | |
| 432 | if (word_len <= 8) { |
| 433 | data_type = OMAP_DMA_DATA_TYPE_S8; |
| 434 | element_count = count; |
| 435 | } else if (word_len <= 16) { |
| 436 | data_type = OMAP_DMA_DATA_TYPE_S16; |
| 437 | element_count = count >> 1; |
| 438 | } else /* word_len <= 32 */ { |
| 439 | data_type = OMAP_DMA_DATA_TYPE_S32; |
| 440 | element_count = count >> 2; |
| 441 | } |
| 442 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 443 | if (tx != NULL && mcspi_dma->dma_tx_channel != -1) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 444 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, |
| 445 | data_type, element_count, 1, |
| 446 | OMAP_DMA_SYNC_ELEMENT, |
| 447 | mcspi_dma->dma_tx_sync_dev, 0); |
| 448 | |
| 449 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, |
| 450 | OMAP_DMA_AMODE_CONSTANT, |
| 451 | tx_reg, 0, 0); |
| 452 | |
| 453 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, |
| 454 | OMAP_DMA_AMODE_POST_INC, |
| 455 | xfer->tx_dma, 0, 0); |
| 456 | } |
| 457 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 458 | if (rx != NULL && mcspi_dma->dma_rx_channel != -1) { |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 459 | elements = element_count - 1; |
| 460 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
| 461 | elements--; |
| 462 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 463 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 464 | data_type, elements, 1, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 465 | OMAP_DMA_SYNC_ELEMENT, |
| 466 | mcspi_dma->dma_rx_sync_dev, 1); |
| 467 | |
| 468 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, |
| 469 | OMAP_DMA_AMODE_CONSTANT, |
| 470 | rx_reg, 0, 0); |
| 471 | |
| 472 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, |
| 473 | OMAP_DMA_AMODE_POST_INC, |
| 474 | xfer->rx_dma, 0, 0); |
| 475 | } |
| 476 | |
| 477 | if (tx != NULL) { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 478 | if (mcspi_dma->dma_tx) |
| 479 | dma_async_issue_pending(mcspi_dma->dma_tx); |
| 480 | else |
| 481 | omap_start_dma(mcspi_dma->dma_tx_channel); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 482 | omap2_mcspi_set_dma_req(spi, 0, 1); |
| 483 | } |
| 484 | |
| 485 | if (rx != NULL) { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 486 | if (mcspi_dma->dma_rx) |
| 487 | dma_async_issue_pending(mcspi_dma->dma_rx); |
| 488 | else |
| 489 | omap_start_dma(mcspi_dma->dma_rx_channel); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 490 | omap2_mcspi_set_dma_req(spi, 1, 1); |
| 491 | } |
| 492 | |
| 493 | if (tx != NULL) { |
| 494 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 495 | dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE); |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 496 | |
| 497 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 498 | if (rx == NULL) { |
| 499 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 500 | OMAP2_MCSPI_CHSTAT_TXS) < 0) |
| 501 | dev_err(&spi->dev, "TXS timed out\n"); |
| 502 | else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 503 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 504 | dev_err(&spi->dev, "EOT timed out\n"); |
| 505 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | if (rx != NULL) { |
| 509 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 510 | dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE); |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 511 | omap2_mcspi_set_enable(spi, 0); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 512 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 513 | elements = element_count - 1; |
| 514 | |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 515 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 516 | elements--; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 517 | |
| 518 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 519 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 520 | u32 w; |
| 521 | |
| 522 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 523 | if (word_len <= 8) |
| 524 | ((u8 *)xfer->rx_buf)[elements++] = w; |
| 525 | else if (word_len <= 16) |
| 526 | ((u16 *)xfer->rx_buf)[elements++] = w; |
| 527 | else /* word_len <= 32 */ |
| 528 | ((u32 *)xfer->rx_buf)[elements++] = w; |
| 529 | } else { |
| 530 | dev_err(&spi->dev, |
| 531 | "DMA RX penultimate word empty"); |
| 532 | count -= (word_len <= 8) ? 2 : |
| 533 | (word_len <= 16) ? 4 : |
| 534 | /* word_len <= 32 */ 8; |
| 535 | omap2_mcspi_set_enable(spi, 1); |
| 536 | return count; |
| 537 | } |
| 538 | } |
| 539 | |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 540 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 541 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 542 | u32 w; |
| 543 | |
| 544 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 545 | if (word_len <= 8) |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 546 | ((u8 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 547 | else if (word_len <= 16) |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 548 | ((u16 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 549 | else /* word_len <= 32 */ |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 550 | ((u32 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 551 | } else { |
| 552 | dev_err(&spi->dev, "DMA RX last word empty"); |
| 553 | count -= (word_len <= 8) ? 1 : |
| 554 | (word_len <= 16) ? 2 : |
| 555 | /* word_len <= 32 */ 4; |
| 556 | } |
| 557 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 558 | } |
| 559 | return count; |
| 560 | } |
| 561 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 562 | static unsigned |
| 563 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) |
| 564 | { |
| 565 | struct omap2_mcspi *mcspi; |
| 566 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 567 | unsigned int count, c; |
| 568 | u32 l; |
| 569 | void __iomem *base = cs->base; |
| 570 | void __iomem *tx_reg; |
| 571 | void __iomem *rx_reg; |
| 572 | void __iomem *chstat_reg; |
| 573 | int word_len; |
| 574 | |
| 575 | mcspi = spi_master_get_devdata(spi->master); |
| 576 | count = xfer->len; |
| 577 | c = count; |
| 578 | word_len = cs->word_len; |
| 579 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 580 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 581 | |
| 582 | /* We store the pre-calculated register addresses on stack to speed |
| 583 | * up the transfer loop. */ |
| 584 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 585 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 586 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; |
| 587 | |
Michael Jones | adef658 | 2011-02-25 16:55:11 +0100 | [diff] [blame] | 588 | if (c < (word_len>>3)) |
| 589 | return 0; |
| 590 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 591 | if (word_len <= 8) { |
| 592 | u8 *rx; |
| 593 | const u8 *tx; |
| 594 | |
| 595 | rx = xfer->rx_buf; |
| 596 | tx = xfer->tx_buf; |
| 597 | |
| 598 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 599 | c -= 1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 600 | if (tx != NULL) { |
| 601 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 602 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 603 | dev_err(&spi->dev, "TXS timed out\n"); |
| 604 | goto out; |
| 605 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 606 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 607 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 608 | __raw_writel(*tx++, tx_reg); |
| 609 | } |
| 610 | if (rx != NULL) { |
| 611 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 612 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 613 | dev_err(&spi->dev, "RXS timed out\n"); |
| 614 | goto out; |
| 615 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 616 | |
| 617 | if (c == 1 && tx == NULL && |
| 618 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 619 | omap2_mcspi_set_enable(spi, 0); |
| 620 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 621 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 622 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 623 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 624 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 625 | dev_err(&spi->dev, |
| 626 | "RXS timed out\n"); |
| 627 | goto out; |
| 628 | } |
| 629 | c = 0; |
| 630 | } else if (c == 0 && tx == NULL) { |
| 631 | omap2_mcspi_set_enable(spi, 0); |
| 632 | } |
| 633 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 634 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 635 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 636 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 637 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 638 | } while (c); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 639 | } else if (word_len <= 16) { |
| 640 | u16 *rx; |
| 641 | const u16 *tx; |
| 642 | |
| 643 | rx = xfer->rx_buf; |
| 644 | tx = xfer->tx_buf; |
| 645 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 646 | c -= 2; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 647 | if (tx != NULL) { |
| 648 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 649 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 650 | dev_err(&spi->dev, "TXS timed out\n"); |
| 651 | goto out; |
| 652 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 653 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 654 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 655 | __raw_writel(*tx++, tx_reg); |
| 656 | } |
| 657 | if (rx != NULL) { |
| 658 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 659 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 660 | dev_err(&spi->dev, "RXS timed out\n"); |
| 661 | goto out; |
| 662 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 663 | |
| 664 | if (c == 2 && tx == NULL && |
| 665 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 666 | omap2_mcspi_set_enable(spi, 0); |
| 667 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 668 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 669 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 670 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 671 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 672 | dev_err(&spi->dev, |
| 673 | "RXS timed out\n"); |
| 674 | goto out; |
| 675 | } |
| 676 | c = 0; |
| 677 | } else if (c == 0 && tx == NULL) { |
| 678 | omap2_mcspi_set_enable(spi, 0); |
| 679 | } |
| 680 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 681 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 682 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 683 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 684 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 685 | } while (c >= 2); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 686 | } else if (word_len <= 32) { |
| 687 | u32 *rx; |
| 688 | const u32 *tx; |
| 689 | |
| 690 | rx = xfer->rx_buf; |
| 691 | tx = xfer->tx_buf; |
| 692 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 693 | c -= 4; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 694 | if (tx != NULL) { |
| 695 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 696 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 697 | dev_err(&spi->dev, "TXS timed out\n"); |
| 698 | goto out; |
| 699 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 700 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 701 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 702 | __raw_writel(*tx++, tx_reg); |
| 703 | } |
| 704 | if (rx != NULL) { |
| 705 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 706 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 707 | dev_err(&spi->dev, "RXS timed out\n"); |
| 708 | goto out; |
| 709 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 710 | |
| 711 | if (c == 4 && tx == NULL && |
| 712 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 713 | omap2_mcspi_set_enable(spi, 0); |
| 714 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 715 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 716 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 717 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 718 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 719 | dev_err(&spi->dev, |
| 720 | "RXS timed out\n"); |
| 721 | goto out; |
| 722 | } |
| 723 | c = 0; |
| 724 | } else if (c == 0 && tx == NULL) { |
| 725 | omap2_mcspi_set_enable(spi, 0); |
| 726 | } |
| 727 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 728 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 729 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 730 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 731 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 732 | } while (c >= 4); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 733 | } |
| 734 | |
| 735 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 736 | if (xfer->rx_buf == NULL) { |
| 737 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 738 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 739 | dev_err(&spi->dev, "TXS timed out\n"); |
| 740 | } else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 741 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 742 | dev_err(&spi->dev, "EOT timed out\n"); |
Jason Wang | e1993ed | 2010-10-19 18:03:27 +0800 | [diff] [blame] | 743 | |
| 744 | /* disable chan to purge rx datas received in TX_ONLY transfer, |
| 745 | * otherwise these rx datas will affect the direct following |
| 746 | * RX_ONLY transfer. |
| 747 | */ |
| 748 | omap2_mcspi_set_enable(spi, 0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 749 | } |
| 750 | out: |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 751 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 752 | return count - c; |
| 753 | } |
| 754 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 755 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
| 756 | { |
| 757 | u32 div; |
| 758 | |
| 759 | for (div = 0; div < 15; div++) |
| 760 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) |
| 761 | return div; |
| 762 | |
| 763 | return 15; |
| 764 | } |
| 765 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 766 | /* called only when no transfer is active to this device */ |
| 767 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, |
| 768 | struct spi_transfer *t) |
| 769 | { |
| 770 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 771 | struct omap2_mcspi *mcspi; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 772 | struct spi_master *spi_cntrl; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 773 | u32 l = 0, div = 0; |
| 774 | u8 word_len = spi->bits_per_word; |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 775 | u32 speed_hz = spi->max_speed_hz; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 776 | |
| 777 | mcspi = spi_master_get_devdata(spi->master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 778 | spi_cntrl = mcspi->master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 779 | |
| 780 | if (t != NULL && t->bits_per_word) |
| 781 | word_len = t->bits_per_word; |
| 782 | |
| 783 | cs->word_len = word_len; |
| 784 | |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 785 | if (t && t->speed_hz) |
| 786 | speed_hz = t->speed_hz; |
| 787 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 788 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
| 789 | div = omap2_mcspi_calc_divisor(speed_hz); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 790 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 791 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 792 | |
| 793 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
| 794 | * REVISIT: this controller could support SPI_3WIRE mode. |
| 795 | */ |
| 796 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); |
| 797 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
| 798 | |
| 799 | /* wordlength */ |
| 800 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
| 801 | l |= (word_len - 1) << 7; |
| 802 | |
| 803 | /* set chipselect polarity; manage with FORCE */ |
| 804 | if (!(spi->mode & SPI_CS_HIGH)) |
| 805 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ |
| 806 | else |
| 807 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; |
| 808 | |
| 809 | /* set clock divisor */ |
| 810 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; |
| 811 | l |= div << 2; |
| 812 | |
| 813 | /* set SPI mode 0..3 */ |
| 814 | if (spi->mode & SPI_CPOL) |
| 815 | l |= OMAP2_MCSPI_CHCONF_POL; |
| 816 | else |
| 817 | l &= ~OMAP2_MCSPI_CHCONF_POL; |
| 818 | if (spi->mode & SPI_CPHA) |
| 819 | l |= OMAP2_MCSPI_CHCONF_PHA; |
| 820 | else |
| 821 | l &= ~OMAP2_MCSPI_CHCONF_PHA; |
| 822 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 823 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 824 | |
| 825 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 826 | OMAP2_MCSPI_MAX_FREQ >> div, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 827 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
| 828 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); |
| 829 | |
| 830 | return 0; |
| 831 | } |
| 832 | |
| 833 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) |
| 834 | { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 835 | omap2_mcspi_rx_callback(data); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 836 | } |
| 837 | |
| 838 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) |
| 839 | { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 840 | omap2_mcspi_tx_callback(data); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 841 | } |
| 842 | |
| 843 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
| 844 | { |
| 845 | struct spi_master *master = spi->master; |
| 846 | struct omap2_mcspi *mcspi; |
| 847 | struct omap2_mcspi_dma *mcspi_dma; |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 848 | dma_cap_mask_t mask; |
| 849 | unsigned sig; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 850 | |
| 851 | mcspi = spi_master_get_devdata(master); |
| 852 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
| 853 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 854 | init_completion(&mcspi_dma->dma_rx_completion); |
| 855 | init_completion(&mcspi_dma->dma_tx_completion); |
| 856 | |
| 857 | dma_cap_zero(mask); |
| 858 | dma_cap_set(DMA_SLAVE, mask); |
| 859 | #ifdef USE_DMA_ENGINE_RX |
| 860 | sig = mcspi_dma->dma_rx_sync_dev; |
| 861 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); |
| 862 | if (!mcspi_dma->dma_rx) { |
| 863 | dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); |
| 864 | return -EAGAIN; |
| 865 | } |
| 866 | #else |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 867 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", |
| 868 | omap2_mcspi_dma_rx_callback, spi, |
| 869 | &mcspi_dma->dma_rx_channel)) { |
| 870 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); |
| 871 | return -EAGAIN; |
| 872 | } |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 873 | #endif |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 874 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 875 | #ifdef USE_DMA_ENGINE_TX |
| 876 | sig = mcspi_dma->dma_tx_sync_dev; |
| 877 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); |
| 878 | if (!mcspi_dma->dma_tx) { |
| 879 | dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); |
| 880 | dma_release_channel(mcspi_dma->dma_rx); |
| 881 | mcspi_dma->dma_rx = NULL; |
| 882 | return -EAGAIN; |
| 883 | } |
| 884 | #else |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 885 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", |
| 886 | omap2_mcspi_dma_tx_callback, spi, |
| 887 | &mcspi_dma->dma_tx_channel)) { |
| 888 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 889 | mcspi_dma->dma_rx_channel = -1; |
| 890 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); |
| 891 | return -EAGAIN; |
| 892 | } |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 893 | #endif |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 898 | static int omap2_mcspi_setup(struct spi_device *spi) |
| 899 | { |
| 900 | int ret; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 901 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 902 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 903 | struct omap2_mcspi_dma *mcspi_dma; |
| 904 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 905 | |
David Brownell | 7d07719 | 2009-06-17 16:26:03 -0700 | [diff] [blame] | 906 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 907 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
| 908 | spi->bits_per_word); |
| 909 | return -EINVAL; |
| 910 | } |
| 911 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 912 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 913 | |
| 914 | if (!cs) { |
Russell King | 10aa5a3 | 2012-06-18 11:27:04 +0100 | [diff] [blame] | 915 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 916 | if (!cs) |
| 917 | return -ENOMEM; |
| 918 | cs->base = mcspi->base + spi->chip_select * 0x14; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 919 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 920 | cs->chconf0 = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 921 | spi->controller_state = cs; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 922 | /* Link this to context save list */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 923 | list_add_tail(&cs->node, &ctx->cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 924 | } |
| 925 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 926 | if ((!mcspi_dma->dma_rx && mcspi_dma->dma_rx_channel == -1) || |
| 927 | (!mcspi_dma->dma_tx && mcspi_dma->dma_tx_channel == -1)) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 928 | ret = omap2_mcspi_request_dma(spi); |
| 929 | if (ret < 0) |
| 930 | return ret; |
| 931 | } |
| 932 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 933 | ret = omap2_mcspi_enable_clocks(mcspi); |
| 934 | if (ret < 0) |
| 935 | return ret; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 936 | |
Kyungmin Park | 86eeb6f | 2007-10-16 01:27:45 -0700 | [diff] [blame] | 937 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 938 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 939 | |
| 940 | return ret; |
| 941 | } |
| 942 | |
| 943 | static void omap2_mcspi_cleanup(struct spi_device *spi) |
| 944 | { |
| 945 | struct omap2_mcspi *mcspi; |
| 946 | struct omap2_mcspi_dma *mcspi_dma; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 947 | struct omap2_mcspi_cs *cs; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 948 | |
| 949 | mcspi = spi_master_get_devdata(spi->master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 950 | |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 951 | if (spi->controller_state) { |
| 952 | /* Unlink controller state from context save list */ |
| 953 | cs = spi->controller_state; |
| 954 | list_del(&cs->node); |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 955 | |
Russell King | 10aa5a3 | 2012-06-18 11:27:04 +0100 | [diff] [blame] | 956 | kfree(cs); |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 957 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 958 | |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 959 | if (spi->chip_select < spi->master->num_chipselect) { |
| 960 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 961 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame^] | 962 | if (mcspi_dma->dma_rx) { |
| 963 | dma_release_channel(mcspi_dma->dma_rx); |
| 964 | mcspi_dma->dma_rx = NULL; |
| 965 | } |
| 966 | if (mcspi_dma->dma_tx) { |
| 967 | dma_release_channel(mcspi_dma->dma_tx); |
| 968 | mcspi_dma->dma_tx = NULL; |
| 969 | } |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 970 | if (mcspi_dma->dma_rx_channel != -1) { |
| 971 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 972 | mcspi_dma->dma_rx_channel = -1; |
| 973 | } |
| 974 | if (mcspi_dma->dma_tx_channel != -1) { |
| 975 | omap_free_dma(mcspi_dma->dma_tx_channel); |
| 976 | mcspi_dma->dma_tx_channel = -1; |
| 977 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 978 | } |
| 979 | } |
| 980 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 981 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 982 | { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 983 | |
| 984 | /* We only enable one channel at a time -- the one whose message is |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 985 | * -- although this controller would gladly |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 986 | * arbitrate among multiple channels. This corresponds to "single |
| 987 | * channel" master mode. As a side effect, we need to manage the |
| 988 | * chipselect with the FORCE bit ... CS != channel enable. |
| 989 | */ |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 990 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 991 | struct spi_device *spi; |
| 992 | struct spi_transfer *t = NULL; |
| 993 | int cs_active = 0; |
| 994 | struct omap2_mcspi_cs *cs; |
| 995 | struct omap2_mcspi_device_config *cd; |
| 996 | int par_override = 0; |
| 997 | int status = 0; |
| 998 | u32 chconf; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 999 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1000 | spi = m->spi; |
| 1001 | cs = spi->controller_state; |
| 1002 | cd = spi->controller_data; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1003 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1004 | omap2_mcspi_set_enable(spi, 1); |
| 1005 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 1006 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
| 1007 | status = -EINVAL; |
| 1008 | break; |
| 1009 | } |
| 1010 | if (par_override || t->speed_hz || t->bits_per_word) { |
| 1011 | par_override = 1; |
| 1012 | status = omap2_mcspi_setup_transfer(spi, t); |
| 1013 | if (status < 0) |
| 1014 | break; |
| 1015 | if (!t->speed_hz && !t->bits_per_word) |
| 1016 | par_override = 0; |
| 1017 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1018 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1019 | if (!cs_active) { |
| 1020 | omap2_mcspi_force_cs(spi, 1); |
| 1021 | cs_active = 1; |
| 1022 | } |
| 1023 | |
| 1024 | chconf = mcspi_cached_chconf0(spi); |
| 1025 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
| 1026 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
| 1027 | |
| 1028 | if (t->tx_buf == NULL) |
| 1029 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
| 1030 | else if (t->rx_buf == NULL) |
| 1031 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
| 1032 | |
| 1033 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
| 1034 | /* Turbo mode is for more than one word */ |
| 1035 | if (t->len > ((cs->word_len + 7) >> 3)) |
| 1036 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; |
| 1037 | } |
| 1038 | |
| 1039 | mcspi_write_chconf0(spi, chconf); |
| 1040 | |
| 1041 | if (t->len) { |
| 1042 | unsigned count; |
| 1043 | |
| 1044 | /* RX_ONLY mode needs dummy data in TX reg */ |
| 1045 | if (t->tx_buf == NULL) |
| 1046 | __raw_writel(0, cs->base |
| 1047 | + OMAP2_MCSPI_TX0); |
| 1048 | |
| 1049 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
| 1050 | count = omap2_mcspi_txrx_dma(spi, t); |
| 1051 | else |
| 1052 | count = omap2_mcspi_txrx_pio(spi, t); |
| 1053 | m->actual_length += count; |
| 1054 | |
| 1055 | if (count != t->len) { |
| 1056 | status = -EIO; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1057 | break; |
| 1058 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1059 | } |
| 1060 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1061 | if (t->delay_usecs) |
| 1062 | udelay(t->delay_usecs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1063 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1064 | /* ignore the "leave it on after last xfer" hint */ |
| 1065 | if (t->cs_change) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1066 | omap2_mcspi_force_cs(spi, 0); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1067 | cs_active = 0; |
| 1068 | } |
| 1069 | } |
| 1070 | /* Restore defaults if they were overriden */ |
| 1071 | if (par_override) { |
| 1072 | par_override = 0; |
| 1073 | status = omap2_mcspi_setup_transfer(spi, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1074 | } |
| 1075 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1076 | if (cs_active) |
| 1077 | omap2_mcspi_force_cs(spi, 0); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1078 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1079 | omap2_mcspi_set_enable(spi, 0); |
| 1080 | |
| 1081 | m->status = status; |
| 1082 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1083 | } |
| 1084 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1085 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
| 1086 | struct spi_message *m) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1087 | { |
| 1088 | struct omap2_mcspi *mcspi; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1089 | struct spi_transfer *t; |
| 1090 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1091 | mcspi = spi_master_get_devdata(master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1092 | m->actual_length = 0; |
| 1093 | m->status = 0; |
| 1094 | |
| 1095 | /* reject invalid messages and transfers */ |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1096 | if (list_empty(&m->transfers)) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1097 | return -EINVAL; |
| 1098 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 1099 | const void *tx_buf = t->tx_buf; |
| 1100 | void *rx_buf = t->rx_buf; |
| 1101 | unsigned len = t->len; |
| 1102 | |
| 1103 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ |
| 1104 | || (len && !(rx_buf || tx_buf)) |
| 1105 | || (t->bits_per_word && |
| 1106 | ( t->bits_per_word < 4 |
| 1107 | || t->bits_per_word > 32))) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1108 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1109 | t->speed_hz, |
| 1110 | len, |
| 1111 | tx_buf ? "tx" : "", |
| 1112 | rx_buf ? "rx" : "", |
| 1113 | t->bits_per_word); |
| 1114 | return -EINVAL; |
| 1115 | } |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 1116 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1117 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 1118 | t->speed_hz, |
| 1119 | OMAP2_MCSPI_MAX_FREQ >> 15); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1120 | return -EINVAL; |
| 1121 | } |
| 1122 | |
| 1123 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) |
| 1124 | continue; |
| 1125 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1126 | if (tx_buf != NULL) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1127 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1128 | len, DMA_TO_DEVICE); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1129 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
| 1130 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1131 | 'T', len); |
| 1132 | return -EINVAL; |
| 1133 | } |
| 1134 | } |
| 1135 | if (rx_buf != NULL) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1136 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1137 | DMA_FROM_DEVICE); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1138 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
| 1139 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1140 | 'R', len); |
| 1141 | if (tx_buf != NULL) |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1142 | dma_unmap_single(mcspi->dev, t->tx_dma, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1143 | len, DMA_TO_DEVICE); |
| 1144 | return -EINVAL; |
| 1145 | } |
| 1146 | } |
| 1147 | } |
| 1148 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1149 | omap2_mcspi_work(mcspi, m); |
| 1150 | spi_finalize_current_message(master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1151 | return 0; |
| 1152 | } |
| 1153 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1154 | static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1155 | { |
| 1156 | struct spi_master *master = mcspi->master; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1157 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1158 | int ret = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1159 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1160 | ret = omap2_mcspi_enable_clocks(mcspi); |
| 1161 | if (ret < 0) |
| 1162 | return ret; |
Jouni Hogander | ddb2219 | 2009-07-29 15:02:11 -0700 | [diff] [blame] | 1163 | |
Shubhrajyoti D | 39f8052 | 2012-03-29 22:11:07 +0530 | [diff] [blame] | 1164 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
| 1165 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
| 1166 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1167 | |
| 1168 | omap2_mcspi_set_master_mode(master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 1169 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1170 | return 0; |
| 1171 | } |
| 1172 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1173 | static int omap_mcspi_runtime_resume(struct device *dev) |
| 1174 | { |
| 1175 | struct omap2_mcspi *mcspi; |
| 1176 | struct spi_master *master; |
| 1177 | |
| 1178 | master = dev_get_drvdata(dev); |
| 1179 | mcspi = spi_master_get_devdata(master); |
| 1180 | omap2_mcspi_restore_ctx(mcspi); |
| 1181 | |
| 1182 | return 0; |
| 1183 | } |
| 1184 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1185 | static struct omap2_mcspi_platform_config omap2_pdata = { |
| 1186 | .regs_offset = 0, |
| 1187 | }; |
| 1188 | |
| 1189 | static struct omap2_mcspi_platform_config omap4_pdata = { |
| 1190 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, |
| 1191 | }; |
| 1192 | |
| 1193 | static const struct of_device_id omap_mcspi_of_match[] = { |
| 1194 | { |
| 1195 | .compatible = "ti,omap2-mcspi", |
| 1196 | .data = &omap2_pdata, |
| 1197 | }, |
| 1198 | { |
| 1199 | .compatible = "ti,omap4-mcspi", |
| 1200 | .data = &omap4_pdata, |
| 1201 | }, |
| 1202 | { }, |
| 1203 | }; |
| 1204 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); |
Girish | ccc7bae | 2008-02-06 01:38:16 -0800 | [diff] [blame] | 1205 | |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1206 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1207 | { |
| 1208 | struct spi_master *master; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1209 | struct omap2_mcspi_platform_config *pdata; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1210 | struct omap2_mcspi *mcspi; |
| 1211 | struct resource *r; |
| 1212 | int status = 0, i; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1213 | u32 regs_offset = 0; |
| 1214 | static int bus_num = 1; |
| 1215 | struct device_node *node = pdev->dev.of_node; |
| 1216 | const struct of_device_id *match; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1217 | |
| 1218 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
| 1219 | if (master == NULL) { |
| 1220 | dev_dbg(&pdev->dev, "master allocation failed\n"); |
| 1221 | return -ENOMEM; |
| 1222 | } |
| 1223 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1224 | /* the spi->mode bits understood by this driver: */ |
| 1225 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1226 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1227 | master->setup = omap2_mcspi_setup; |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1228 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
| 1229 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; |
| 1230 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1231 | master->cleanup = omap2_mcspi_cleanup; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1232 | master->dev.of_node = node; |
| 1233 | |
| 1234 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
| 1235 | if (match) { |
| 1236 | u32 num_cs = 1; /* default number of chipselect */ |
| 1237 | pdata = match->data; |
| 1238 | |
| 1239 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); |
| 1240 | master->num_chipselect = num_cs; |
| 1241 | master->bus_num = bus_num++; |
| 1242 | } else { |
| 1243 | pdata = pdev->dev.platform_data; |
| 1244 | master->num_chipselect = pdata->num_cs; |
| 1245 | if (pdev->id != -1) |
| 1246 | master->bus_num = pdev->id; |
| 1247 | } |
| 1248 | regs_offset = pdata->regs_offset; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1249 | |
| 1250 | dev_set_drvdata(&pdev->dev, master); |
| 1251 | |
| 1252 | mcspi = spi_master_get_devdata(master); |
| 1253 | mcspi->master = master; |
| 1254 | |
| 1255 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1256 | if (r == NULL) { |
| 1257 | status = -ENODEV; |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1258 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1259 | } |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1260 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1261 | r->start += regs_offset; |
| 1262 | r->end += regs_offset; |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1263 | mcspi->phys = r->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1264 | |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1265 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1266 | if (!mcspi->base) { |
| 1267 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
| 1268 | status = -ENOMEM; |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1269 | goto free_master; |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1270 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1271 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1272 | mcspi->dev = &pdev->dev; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1273 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1274 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1275 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1276 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
| 1277 | sizeof(struct omap2_mcspi_dma), |
| 1278 | GFP_KERNEL); |
| 1279 | |
| 1280 | if (mcspi->dma_channels == NULL) |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1281 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1282 | |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1283 | for (i = 0; i < master->num_chipselect; i++) { |
| 1284 | char dma_ch_name[14]; |
| 1285 | struct resource *dma_res; |
| 1286 | |
| 1287 | sprintf(dma_ch_name, "rx%d", i); |
| 1288 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
| 1289 | dma_ch_name); |
| 1290 | if (!dma_res) { |
| 1291 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); |
| 1292 | status = -ENODEV; |
| 1293 | break; |
| 1294 | } |
| 1295 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1296 | mcspi->dma_channels[i].dma_rx_channel = -1; |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1297 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
| 1298 | sprintf(dma_ch_name, "tx%d", i); |
| 1299 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
| 1300 | dma_ch_name); |
| 1301 | if (!dma_res) { |
| 1302 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); |
| 1303 | status = -ENODEV; |
| 1304 | break; |
| 1305 | } |
| 1306 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1307 | mcspi->dma_channels[i].dma_tx_channel = -1; |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1308 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1309 | } |
| 1310 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1311 | if (status < 0) |
| 1312 | goto dma_chnl_free; |
| 1313 | |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 1314 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1315 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1316 | pm_runtime_enable(&pdev->dev); |
| 1317 | |
| 1318 | if (status || omap2_mcspi_master_setup(mcspi) < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1319 | goto disable_pm; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1320 | |
| 1321 | status = spi_register_master(master); |
| 1322 | if (status < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1323 | goto err_spi_register; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1324 | |
| 1325 | return status; |
| 1326 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1327 | err_spi_register: |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1328 | spi_master_put(master); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1329 | disable_pm: |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1330 | pm_runtime_disable(&pdev->dev); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1331 | dma_chnl_free: |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1332 | kfree(mcspi->dma_channels); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1333 | free_master: |
| 1334 | kfree(master); |
| 1335 | platform_set_drvdata(pdev, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1336 | return status; |
| 1337 | } |
| 1338 | |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1339 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1340 | { |
| 1341 | struct spi_master *master; |
| 1342 | struct omap2_mcspi *mcspi; |
| 1343 | struct omap2_mcspi_dma *dma_channels; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1344 | |
| 1345 | master = dev_get_drvdata(&pdev->dev); |
| 1346 | mcspi = spi_master_get_devdata(master); |
| 1347 | dma_channels = mcspi->dma_channels; |
| 1348 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1349 | omap2_mcspi_disable_clocks(mcspi); |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1350 | pm_runtime_disable(&pdev->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1351 | |
| 1352 | spi_unregister_master(master); |
| 1353 | kfree(dma_channels); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1354 | platform_set_drvdata(pdev, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1355 | |
| 1356 | return 0; |
| 1357 | } |
| 1358 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1359 | /* work with hotplug and coldplug */ |
| 1360 | MODULE_ALIAS("platform:omap2_mcspi"); |
| 1361 | |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1362 | #ifdef CONFIG_SUSPEND |
| 1363 | /* |
| 1364 | * When SPI wake up from off-mode, CS is in activate state. If it was in |
| 1365 | * unactive state when driver was suspend, then force it to unactive state at |
| 1366 | * wake up. |
| 1367 | */ |
| 1368 | static int omap2_mcspi_resume(struct device *dev) |
| 1369 | { |
| 1370 | struct spi_master *master = dev_get_drvdata(dev); |
| 1371 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1372 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 1373 | struct omap2_mcspi_cs *cs; |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1374 | |
| 1375 | omap2_mcspi_enable_clocks(mcspi); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1376 | list_for_each_entry(cs, &ctx->cs, node) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1377 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1378 | /* |
| 1379 | * We need to toggle CS state for OMAP take this |
| 1380 | * change in account. |
| 1381 | */ |
| 1382 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); |
| 1383 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1384 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); |
| 1385 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1386 | } |
| 1387 | } |
| 1388 | omap2_mcspi_disable_clocks(mcspi); |
| 1389 | return 0; |
| 1390 | } |
| 1391 | #else |
| 1392 | #define omap2_mcspi_resume NULL |
| 1393 | #endif |
| 1394 | |
| 1395 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { |
| 1396 | .resume = omap2_mcspi_resume, |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1397 | .runtime_resume = omap_mcspi_runtime_resume, |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1398 | }; |
| 1399 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1400 | static struct platform_driver omap2_mcspi_driver = { |
| 1401 | .driver = { |
| 1402 | .name = "omap2_mcspi", |
| 1403 | .owner = THIS_MODULE, |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1404 | .pm = &omap2_mcspi_pm_ops, |
| 1405 | .of_match_table = omap_mcspi_of_match, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1406 | }, |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1407 | .probe = omap2_mcspi_probe, |
| 1408 | .remove = __devexit_p(omap2_mcspi_remove), |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1409 | }; |
| 1410 | |
Felipe Balbi | 9fdca9d | 2012-03-14 11:18:31 +0200 | [diff] [blame] | 1411 | module_platform_driver(omap2_mcspi_driver); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1412 | MODULE_LICENSE("GPL"); |