Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 12 | |
| 13 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
| 14 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 15 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 16 | #include <uapi/drm/sde_drm.h> |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 17 | |
| 18 | #include "msm_prop.h" |
| 19 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 20 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 21 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 22 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 23 | #include "sde_hw_sspp.h" |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 24 | #include "sde_trace.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 25 | |
| 26 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 27 | #define PHASE_STEP_SHIFT 21 |
| 28 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 29 | #define PHASE_RESIDUAL 15 |
| 30 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 31 | #define SHARP_STRENGTH_DEFAULT 32 |
| 32 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 33 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 34 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 35 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 36 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 37 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 38 | #define SDE_PLANE_COLOR_FILL_FLAG BIT(31) |
| 39 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 40 | /** |
| 41 | * enum sde_plane_qos - Different qos configurations for each pipe |
| 42 | * |
| 43 | * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. |
| 44 | * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. |
| 45 | * this configuration is mutually exclusive from VBLANK_CTRL. |
| 46 | * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. |
| 47 | */ |
| 48 | enum sde_plane_qos { |
| 49 | SDE_PLANE_QOS_VBLANK_CTRL = BIT(0), |
| 50 | SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), |
| 51 | SDE_PLANE_QOS_PANIC_CTRL = BIT(2), |
| 52 | }; |
| 53 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 54 | struct sde_plane { |
| 55 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 56 | |
| 57 | int mmu_id; |
| 58 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 59 | struct mutex lock; |
| 60 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 61 | enum sde_sspp pipe; |
| 62 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 63 | uint32_t nformats; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 64 | uint32_t formats[64]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 65 | |
| 66 | struct sde_hw_pipe *pipe_hw; |
| 67 | struct sde_hw_pipe_cfg pipe_cfg; |
| 68 | struct sde_hw_pixel_ext pixel_ext; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 69 | struct sde_hw_sharp_cfg sharp_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 70 | struct sde_hw_scaler3_cfg scaler3_cfg; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 71 | struct sde_hw_pipe_qos_cfg pipe_qos_cfg; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 72 | uint32_t color_fill; |
| 73 | bool is_error; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 74 | bool is_rt_pipe; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 75 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 76 | struct sde_csc_cfg csc_cfg; |
| 77 | struct sde_csc_cfg *csc_ptr; |
| 78 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 79 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 80 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 81 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 82 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 83 | struct msm_property_info property_info; |
| 84 | struct msm_property_data property_data[PLANE_PROP_COUNT]; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 85 | struct drm_property_blob *blob_info; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 86 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 87 | /* debugfs related stuff */ |
| 88 | struct dentry *debugfs_root; |
| 89 | struct sde_debugfs_regset32 debugfs_src; |
| 90 | struct sde_debugfs_regset32 debugfs_scaler; |
| 91 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 92 | }; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 93 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 94 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 95 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 96 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 97 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 98 | return state && state->fb && state->crtc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 99 | } |
| 100 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 101 | /** |
| 102 | * _sde_plane_calc_fill_level - calculate fill level of the given source format |
| 103 | * @plane: Pointer to drm plane |
| 104 | * @fmt: Pointer to source buffer format |
| 105 | * @src_wdith: width of source buffer |
| 106 | * Return: fill level corresponding to the source buffer/format or 0 if error |
| 107 | */ |
| 108 | static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, |
| 109 | const struct sde_format *fmt, u32 src_width) |
| 110 | { |
| 111 | struct sde_plane *psde; |
| 112 | u32 fixed_buff_size; |
| 113 | u32 total_fl; |
| 114 | |
| 115 | if (!plane || !fmt) { |
| 116 | SDE_ERROR("invalid arguments\n"); |
| 117 | return 0; |
| 118 | } |
| 119 | |
| 120 | psde = to_sde_plane(plane); |
| 121 | fixed_buff_size = psde->pipe_sblk->pixel_ram_size; |
| 122 | |
| 123 | if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) { |
| 124 | if (fmt->chroma_sample == SDE_CHROMA_420) { |
| 125 | /* NV12 */ |
| 126 | total_fl = (fixed_buff_size / 2) / |
| 127 | ((src_width + 32) * fmt->bpp); |
| 128 | } else { |
| 129 | /* non NV12 */ |
| 130 | total_fl = (fixed_buff_size) / |
| 131 | ((src_width + 32) * fmt->bpp); |
| 132 | } |
| 133 | } else { |
| 134 | total_fl = (fixed_buff_size * 2) / |
| 135 | ((src_width + 32) * fmt->bpp); |
| 136 | } |
| 137 | |
| 138 | SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n", |
| 139 | plane->base.id, psde->pipe - SSPP_VIG0, |
| 140 | fmt->base.pixel_format, src_width, total_fl); |
| 141 | |
| 142 | return total_fl; |
| 143 | } |
| 144 | |
| 145 | /** |
| 146 | * _sde_plane_get_qos_lut_linear - get linear LUT mapping |
| 147 | * @total_fl: fill level |
| 148 | * Return: LUT setting corresponding to the fill level |
| 149 | */ |
| 150 | static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl) |
| 151 | { |
| 152 | u32 qos_lut; |
| 153 | |
| 154 | if (total_fl <= 4) |
| 155 | qos_lut = 0x1B; |
| 156 | else if (total_fl <= 5) |
| 157 | qos_lut = 0x5B; |
| 158 | else if (total_fl <= 6) |
| 159 | qos_lut = 0x15B; |
| 160 | else if (total_fl <= 7) |
| 161 | qos_lut = 0x55B; |
| 162 | else if (total_fl <= 8) |
| 163 | qos_lut = 0x155B; |
| 164 | else if (total_fl <= 9) |
| 165 | qos_lut = 0x555B; |
| 166 | else if (total_fl <= 10) |
| 167 | qos_lut = 0x1555B; |
| 168 | else if (total_fl <= 11) |
| 169 | qos_lut = 0x5555B; |
| 170 | else if (total_fl <= 12) |
| 171 | qos_lut = 0x15555B; |
| 172 | else |
| 173 | qos_lut = 0x55555B; |
| 174 | |
| 175 | return qos_lut; |
| 176 | } |
| 177 | |
| 178 | /** |
| 179 | * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping |
| 180 | * @total_fl: fill level |
| 181 | * Return: LUT setting corresponding to the fill level |
| 182 | */ |
| 183 | static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl) |
| 184 | { |
| 185 | u32 qos_lut; |
| 186 | |
| 187 | if (total_fl <= 10) |
| 188 | qos_lut = 0x1AAff; |
| 189 | else if (total_fl <= 11) |
| 190 | qos_lut = 0x5AAFF; |
| 191 | else if (total_fl <= 12) |
| 192 | qos_lut = 0x15AAFF; |
| 193 | else |
| 194 | qos_lut = 0x55AAFF; |
| 195 | |
| 196 | return qos_lut; |
| 197 | } |
| 198 | |
| 199 | /** |
| 200 | * _sde_plane_is_rt_pipe - check if the given plane requires real-time QoS |
| 201 | * @plane: Pointer to drm plane |
| 202 | * @crtc: Pointer to drm crtc associated with the given plane |
| 203 | */ |
| 204 | static bool _sde_plane_is_rt_pipe(struct drm_plane *plane, |
| 205 | struct drm_crtc *crtc) |
| 206 | { |
| 207 | struct sde_plane *psde = to_sde_plane(plane); |
| 208 | struct drm_connector *connector; |
| 209 | bool is_rt = false; |
| 210 | |
| 211 | /* check if this plane has a physical connector interface */ |
| 212 | drm_for_each_connector(connector, plane->dev) |
| 213 | if (connector->state && |
| 214 | (connector->state->crtc == crtc) && |
| 215 | (connector->connector_type |
| 216 | != DRM_MODE_CONNECTOR_VIRTUAL)) { |
| 217 | is_rt = true; |
| 218 | break; |
| 219 | } |
| 220 | |
| 221 | SDE_DEBUG("plane%u: pnum:%d rt:%d\n", |
| 222 | plane->base.id, psde->pipe - SSPP_VIG0, is_rt); |
| 223 | |
| 224 | return is_rt; |
| 225 | } |
| 226 | |
| 227 | /** |
| 228 | * _sde_plane_set_qos_lut - set QoS LUT of the given plane |
| 229 | * @plane: Pointer to drm plane |
| 230 | * @fb: Pointer to framebuffer associated with the given plane |
| 231 | */ |
| 232 | static void _sde_plane_set_qos_lut(struct drm_plane *plane, |
| 233 | struct drm_framebuffer *fb) |
| 234 | { |
| 235 | struct sde_plane *psde; |
| 236 | const struct sde_format *fmt = NULL; |
| 237 | u32 qos_lut; |
| 238 | u32 total_fl = 0; |
| 239 | |
| 240 | if (!plane || !fb) { |
| 241 | SDE_ERROR("invalid arguments plane %d fb %d\n", |
| 242 | plane != 0, fb != 0); |
| 243 | return; |
| 244 | } |
| 245 | |
| 246 | psde = to_sde_plane(plane); |
| 247 | |
| 248 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 249 | SDE_ERROR("invalid arguments\n"); |
| 250 | return; |
| 251 | } else if (!psde->pipe_hw->ops.setup_creq_lut) { |
| 252 | return; |
| 253 | } |
| 254 | |
| 255 | if (!psde->is_rt_pipe) { |
| 256 | qos_lut = psde->pipe_sblk->creq_lut_nrt; |
| 257 | } else { |
| 258 | fmt = sde_get_sde_format_ext( |
| 259 | fb->pixel_format, |
| 260 | fb->modifier, |
| 261 | drm_format_num_planes(fb->pixel_format)); |
| 262 | total_fl = _sde_plane_calc_fill_level(plane, fmt, |
| 263 | psde->pipe_cfg.src_rect.w); |
| 264 | |
| 265 | if (SDE_FORMAT_IS_LINEAR(fmt)) |
| 266 | qos_lut = _sde_plane_get_qos_lut_linear(total_fl); |
| 267 | else |
| 268 | qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl); |
| 269 | } |
| 270 | |
| 271 | psde->pipe_qos_cfg.creq_lut = qos_lut; |
| 272 | |
| 273 | trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, |
| 274 | (fmt) ? fmt->base.pixel_format : 0, |
| 275 | psde->is_rt_pipe, total_fl, qos_lut, |
| 276 | (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0); |
| 277 | |
| 278 | SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n", |
| 279 | plane->base.id, |
| 280 | psde->pipe - SSPP_VIG0, |
| 281 | (fmt) ? fmt->base.pixel_format : 0, |
| 282 | psde->is_rt_pipe, total_fl, qos_lut); |
| 283 | |
| 284 | psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg); |
| 285 | } |
| 286 | |
| 287 | /** |
| 288 | * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane |
| 289 | * @plane: Pointer to drm plane |
| 290 | * @fb: Pointer to framebuffer associated with the given plane |
| 291 | */ |
| 292 | static void _sde_plane_set_danger_lut(struct drm_plane *plane, |
| 293 | struct drm_framebuffer *fb) |
| 294 | { |
| 295 | struct sde_plane *psde; |
| 296 | const struct sde_format *fmt = NULL; |
| 297 | u32 danger_lut, safe_lut; |
| 298 | |
| 299 | if (!plane || !fb) { |
| 300 | SDE_ERROR("invalid arguments\n"); |
| 301 | return; |
| 302 | } |
| 303 | |
| 304 | psde = to_sde_plane(plane); |
| 305 | |
| 306 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 307 | SDE_ERROR("invalid arguments\n"); |
| 308 | return; |
| 309 | } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) { |
| 310 | return; |
| 311 | } |
| 312 | |
| 313 | if (!psde->is_rt_pipe) { |
| 314 | danger_lut = psde->pipe_sblk->danger_lut_nrt; |
| 315 | safe_lut = psde->pipe_sblk->safe_lut_nrt; |
| 316 | } else { |
| 317 | fmt = sde_get_sde_format_ext( |
| 318 | fb->pixel_format, |
| 319 | fb->modifier, |
| 320 | drm_format_num_planes(fb->pixel_format)); |
| 321 | |
| 322 | if (SDE_FORMAT_IS_LINEAR(fmt)) { |
| 323 | danger_lut = psde->pipe_sblk->danger_lut_linear; |
| 324 | safe_lut = psde->pipe_sblk->safe_lut_linear; |
| 325 | } else { |
| 326 | danger_lut = psde->pipe_sblk->danger_lut_tile; |
| 327 | safe_lut = psde->pipe_sblk->safe_lut_tile; |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | psde->pipe_qos_cfg.danger_lut = danger_lut; |
| 332 | psde->pipe_qos_cfg.safe_lut = safe_lut; |
| 333 | |
| 334 | trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0, |
| 335 | (fmt) ? fmt->base.pixel_format : 0, |
| 336 | (fmt) ? fmt->fetch_mode : 0, |
| 337 | psde->pipe_qos_cfg.danger_lut, |
| 338 | psde->pipe_qos_cfg.safe_lut); |
| 339 | |
| 340 | SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n", |
| 341 | plane->base.id, |
| 342 | psde->pipe - SSPP_VIG0, |
| 343 | fmt ? fmt->base.pixel_format : 0, |
| 344 | fmt ? fmt->fetch_mode : -1, |
| 345 | psde->pipe_qos_cfg.danger_lut, |
| 346 | psde->pipe_qos_cfg.safe_lut); |
| 347 | |
| 348 | psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw, |
| 349 | &psde->pipe_qos_cfg); |
| 350 | } |
| 351 | |
| 352 | /** |
| 353 | * _sde_plane_set_qos_ctrl - set QoS control of the given plane |
| 354 | * @plane: Pointer to drm plane |
| 355 | * @enable: true to enable QoS control |
| 356 | * @flags: QoS control mode (enum sde_plane_qos) |
| 357 | */ |
| 358 | static void _sde_plane_set_qos_ctrl(struct drm_plane *plane, |
| 359 | bool enable, u32 flags) |
| 360 | { |
| 361 | struct sde_plane *psde; |
| 362 | |
| 363 | if (!plane) { |
| 364 | SDE_ERROR("invalid arguments\n"); |
| 365 | return; |
| 366 | } |
| 367 | |
| 368 | psde = to_sde_plane(plane); |
| 369 | |
| 370 | if (!psde->pipe_hw || !psde->pipe_sblk) { |
| 371 | SDE_ERROR("invalid arguments\n"); |
| 372 | return; |
| 373 | } else if (!psde->pipe_hw->ops.setup_qos_ctrl) { |
| 374 | return; |
| 375 | } |
| 376 | |
| 377 | if (flags & SDE_PLANE_QOS_VBLANK_CTRL) { |
| 378 | psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank; |
| 379 | psde->pipe_qos_cfg.danger_vblank = |
| 380 | psde->pipe_sblk->danger_vblank; |
| 381 | psde->pipe_qos_cfg.vblank_en = enable; |
| 382 | } |
| 383 | |
| 384 | if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) { |
| 385 | /* this feature overrules previous VBLANK_CTRL */ |
| 386 | psde->pipe_qos_cfg.vblank_en = false; |
| 387 | psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ |
| 388 | } |
| 389 | |
| 390 | if (flags & SDE_PLANE_QOS_PANIC_CTRL) |
| 391 | psde->pipe_qos_cfg.danger_safe_en = enable; |
| 392 | |
| 393 | if (!psde->is_rt_pipe) { |
| 394 | psde->pipe_qos_cfg.vblank_en = false; |
| 395 | psde->pipe_qos_cfg.danger_safe_en = false; |
| 396 | } |
| 397 | |
| 398 | SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x]\n", |
| 399 | plane->base.id, |
| 400 | psde->pipe - SSPP_VIG0, |
| 401 | psde->pipe_qos_cfg.danger_safe_en, |
| 402 | psde->pipe_qos_cfg.vblank_en, |
| 403 | psde->pipe_qos_cfg.creq_vblank, |
| 404 | psde->pipe_qos_cfg.danger_vblank); |
| 405 | |
| 406 | psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw, |
| 407 | &psde->pipe_qos_cfg); |
| 408 | } |
| 409 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 410 | /* helper to update a state's input fence pointer from the property */ |
| 411 | static void _sde_plane_set_input_fence(struct drm_plane *plane, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 412 | struct sde_plane_state *pstate, uint64_t fd) |
| 413 | { |
| 414 | if (!plane || !pstate) |
| 415 | return; |
| 416 | |
| 417 | /* clear previous reference */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 418 | if (pstate->input_fence) |
| 419 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 420 | |
| 421 | /* get fence pointer for later */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 422 | pstate->input_fence = sde_sync_get(fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 423 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 424 | SDE_DEBUG("0x%llX\n", fd); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 425 | } |
| 426 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 427 | int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 428 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 429 | struct sde_plane *psde; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 430 | struct sde_plane_state *pstate; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 431 | void *input_fence; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 432 | int ret = -EINVAL; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 433 | |
| 434 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 435 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 436 | } else if (!plane->state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 437 | SDE_ERROR("invalid plane state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 438 | } else { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 439 | psde = to_sde_plane(plane); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 440 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 441 | input_fence = pstate->input_fence; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 442 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 443 | if (input_fence) { |
| 444 | ret = sde_sync_wait(input_fence, wait_ms); |
| 445 | switch (ret) { |
| 446 | case 0: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 447 | SDE_DEBUG("%s signaled\n", psde->pipe_name); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 448 | break; |
| 449 | case -ETIME: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 450 | SDE_ERROR("timeout on %s, %ums\n", |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 451 | psde->pipe_name, wait_ms); |
| 452 | psde->is_error = true; |
| 453 | break; |
| 454 | default: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 455 | SDE_ERROR("error on %s, %d\n", |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 456 | psde->pipe_name, ret); |
| 457 | psde->is_error = true; |
| 458 | break; |
| 459 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 460 | } else { |
| 461 | ret = 0; |
| 462 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 463 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 464 | return ret; |
| 465 | } |
| 466 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 467 | static void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 468 | struct sde_plane_state *pstate, |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 469 | struct sde_hw_pipe_cfg *pipe_cfg, |
| 470 | struct drm_framebuffer *fb) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 471 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 472 | struct sde_plane *psde; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 473 | int ret, i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 474 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 475 | if (!plane || !pstate || !pipe_cfg || !fb) |
| 476 | return; |
| 477 | |
| 478 | psde = to_sde_plane(plane); |
| 479 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 480 | ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout); |
| 481 | if (ret) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 482 | SDE_ERROR("failed to get format layout, error: %d\n", ret); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 483 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 484 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 485 | |
| 486 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 487 | BIT(SDE_DRM_DEINTERLACE)) |
| 488 | for (i = 0; i < SDE_MAX_PLANES; ++i) |
| 489 | pipe_cfg->layout.plane_pitch[i] <<= 1; |
| 490 | |
| 491 | if (psde->pipe_hw && psde->pipe_hw->ops.setup_sourceaddress) |
| 492 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 493 | } |
| 494 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 495 | static void _sde_plane_setup_scaler3(struct sde_plane *psde, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 496 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 497 | struct sde_hw_scaler3_cfg *scale_cfg, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 498 | const struct sde_format *fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 499 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 500 | { |
| 501 | } |
| 502 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 503 | /** |
| 504 | * _sde_plane_setup_scaler2(): Determine default scaler phase steps/filter type |
| 505 | * @psde: Pointer to SDE plane object |
| 506 | * @src: Source size |
| 507 | * @dst: Destination size |
| 508 | * @phase_steps: Pointer to output array for phase steps |
| 509 | * @filter: Pointer to output array for filter type |
| 510 | * @fmt: Pointer to format definition |
| 511 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 512 | * |
| 513 | * Returns: 0 on success |
| 514 | */ |
| 515 | static int _sde_plane_setup_scaler2(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 516 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 517 | enum sde_hw_filter *filter, const struct sde_format *fmt, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 518 | uint32_t chroma_subsampling) |
| 519 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 520 | if (!psde || !phase_steps || !filter || !fmt) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 521 | SDE_ERROR("invalid arguments\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 522 | return -EINVAL; |
| 523 | } |
| 524 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 525 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 526 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 527 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 528 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 529 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 530 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 531 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 532 | |
| 533 | /* calculate scaler config, if necessary */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 534 | if (SDE_FORMAT_IS_YUV(fmt) || src != dst) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 535 | filter[SDE_SSPP_COMP_3] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 536 | (src <= dst) ? SDE_SCALE_FILTER_BIL : |
| 537 | SDE_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 538 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 539 | if (SDE_FORMAT_IS_YUV(fmt)) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 540 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 541 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 542 | } else { |
| 543 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 544 | filter[SDE_SSPP_COMP_1_2] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 545 | SDE_SCALE_FILTER_NEAREST; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 546 | } |
| 547 | } else { |
| 548 | /* disable scaler */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 549 | SDE_DEBUG("disable scaler\n"); |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 550 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX; |
| 551 | filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX; |
| 552 | filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 553 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 554 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 555 | } |
| 556 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 557 | /** |
| 558 | * _sde_plane_setup_pixel_ext - determine default pixel extension values |
| 559 | * @psde: Pointer to SDE plane object |
| 560 | * @src: Source size |
| 561 | * @dst: Destination size |
| 562 | * @decimated_src: Source size after decimation, if any |
| 563 | * @phase_steps: Pointer to output array for phase steps |
| 564 | * @out_src: Output array for pixel extension values |
| 565 | * @out_edge1: Output array for pixel extension first edge |
| 566 | * @out_edge2: Output array for pixel extension second edge |
| 567 | * @filter: Pointer to array for filter type |
| 568 | * @fmt: Pointer to format definition |
| 569 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 570 | * @post_compare: Whether to chroma subsampled source size for comparisions |
| 571 | */ |
| 572 | static void _sde_plane_setup_pixel_ext(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 573 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 574 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 575 | int *out_edge2, enum sde_hw_filter *filter, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 576 | const struct sde_format *fmt, uint32_t chroma_subsampling, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 577 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 578 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 579 | int64_t edge1, edge2, caf; |
| 580 | uint32_t src_work; |
| 581 | int i, tmp; |
| 582 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 583 | if (psde && phase_steps && out_src && out_edge1 && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 584 | out_edge2 && filter && fmt) { |
| 585 | /* handle CAF for YUV formats */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 586 | if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 587 | caf = PHASE_STEP_UNIT_SCALE; |
| 588 | else |
| 589 | caf = 0; |
| 590 | |
| 591 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 592 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 593 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 594 | src_work /= chroma_subsampling; |
| 595 | if (post_compare) |
| 596 | src = src_work; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 597 | if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 598 | /* unity */ |
| 599 | edge1 = 0; |
| 600 | edge2 = 0; |
| 601 | } else if (dst >= src) { |
| 602 | /* upscale */ |
| 603 | edge1 = (1 << PHASE_RESIDUAL); |
| 604 | edge1 -= caf; |
| 605 | edge2 = (1 << PHASE_RESIDUAL); |
| 606 | edge2 += (dst - 1) * *(phase_steps + i); |
| 607 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 608 | edge2 += caf; |
| 609 | edge2 = -(edge2); |
| 610 | } else { |
| 611 | /* downscale */ |
| 612 | edge1 = 0; |
| 613 | edge2 = (dst - 1) * *(phase_steps + i); |
| 614 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 615 | edge2 += *(phase_steps + i); |
| 616 | edge2 = -(edge2); |
| 617 | } |
| 618 | |
| 619 | /* only enable CAF for luma plane */ |
| 620 | caf = 0; |
| 621 | |
| 622 | /* populate output arrays */ |
| 623 | *(out_src + i) = src_work; |
| 624 | |
| 625 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 626 | if (edge1 >= 0) { |
| 627 | tmp = (uint32_t)edge1; |
| 628 | tmp >>= PHASE_STEP_SHIFT; |
| 629 | *(out_edge1 + i) = -tmp; |
| 630 | } else { |
| 631 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 632 | *(out_edge1 + i) = |
| 633 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 634 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 635 | } |
| 636 | if (edge2 >= 0) { |
| 637 | tmp = (uint32_t)edge2; |
| 638 | tmp >>= PHASE_STEP_SHIFT; |
| 639 | *(out_edge2 + i) = -tmp; |
| 640 | } else { |
| 641 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 642 | *(out_edge2 + i) = |
| 643 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 644 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 645 | } |
| 646 | } |
| 647 | } |
| 648 | } |
| 649 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 650 | /** |
| 651 | * _sde_plane_verify_blob - verify incoming blob is big enough to contain |
| 652 | * sub-structure |
| 653 | * @blob_ptr: Pointer to start of incoming blob data |
| 654 | * @blob_size: Size of incoming blob data, in bytes |
| 655 | * @sub_ptr: Pointer to start of desired sub-structure |
| 656 | * @sub_size: Required size of sub-structure, in bytes |
| 657 | */ |
| 658 | static int _sde_plane_verify_blob(void *blob_ptr, |
| 659 | size_t blob_size, |
| 660 | void *sub_ptr, |
| 661 | size_t sub_size) |
| 662 | { |
| 663 | /* |
| 664 | * Use the blob size provided by drm to check if there are enough |
| 665 | * bytes from the start of versioned sub-structures to the end of |
| 666 | * blob data: |
| 667 | * |
| 668 | * e.g., |
| 669 | * blob_ptr --> struct blob_data { |
| 670 | * uint32_t version; |
| 671 | * sub_ptr --> struct blob_data_v1 v1; |
| 672 | * sub_ptr + sub_size --> struct blob_stuff more_stuff; |
| 673 | * blob_ptr + blob_size --> }; |
| 674 | * |
| 675 | * It's important to check the actual number of bytes from the start |
| 676 | * of the sub-structure to the end of the blob data, and not just rely |
| 677 | * on something like, |
| 678 | * |
| 679 | * sizeof(blob) - sizeof(blob->version) >= sizeof(sub-struct) |
| 680 | * |
| 681 | * This is because the start of the sub-structure can vary based on |
| 682 | * how the compiler pads the overall structure. |
| 683 | */ |
| 684 | if (blob_ptr && sub_ptr) |
| 685 | /* return zero if end of blob >= end of sub-struct */ |
| 686 | return ((unsigned char *)blob_ptr + blob_size) < |
| 687 | ((unsigned char *)sub_ptr + sub_size); |
| 688 | return -EINVAL; |
| 689 | } |
| 690 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 691 | static void _sde_plane_setup_csc(struct sde_plane *psde, |
| 692 | struct sde_plane_state *pstate, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 693 | const struct sde_format *fmt) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 694 | { |
| 695 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 696 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 697 | /* S15.16 format */ |
| 698 | 0x00012A00, 0x00000000, 0x00019880, |
| 699 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 700 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 701 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 702 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 703 | { 0xfff0, 0xff80, 0xff80,}, |
| 704 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 705 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 706 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 707 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 708 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 709 | static const struct sde_csc_cfg sde_csc_NOP = { |
| 710 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 711 | /* identity matrix, S15.16 format */ |
| 712 | 0x10000, 0x00000, 0x00000, |
| 713 | 0x00000, 0x10000, 0x00000, |
| 714 | 0x00000, 0x00000, 0x10000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 715 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 716 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 717 | { 0x0, 0x0, 0x0,}, |
| 718 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 719 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 720 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 721 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 722 | }; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 723 | struct sde_drm_csc *csc = NULL; |
| 724 | size_t csc_size = 0; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 725 | int i; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 726 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 727 | if (!psde || !pstate || !fmt) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 728 | SDE_ERROR("invalid arguments\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 729 | return; |
| 730 | } |
| 731 | if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_csc) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 732 | return; |
| 733 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 734 | /* check for user space override */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 735 | psde->csc_ptr = NULL; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 736 | csc = msm_property_get_blob(&psde->property_info, |
| 737 | pstate->property_blobs, |
| 738 | &csc_size, |
| 739 | PLANE_PROP_CSC); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 740 | if (csc) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 741 | /* user space override */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 742 | memcpy(&psde->csc_cfg, |
| 743 | &sde_csc_NOP, |
| 744 | sizeof(struct sde_csc_cfg)); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 745 | switch (csc->version) { |
| 746 | case SDE_DRM_CSC_V1: |
| 747 | if (!_sde_plane_verify_blob(csc, |
| 748 | csc_size, |
| 749 | &csc->v1, |
| 750 | sizeof(struct sde_drm_csc_v1))) { |
| 751 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 752 | psde->csc_cfg.csc_mv[i] = |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 753 | csc->v1.ctm_coeff[i] >> 16; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 754 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 755 | psde->csc_cfg.csc_pre_bv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 756 | csc->v1.pre_bias[i]; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 757 | psde->csc_cfg.csc_post_bv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 758 | csc->v1.post_bias[i]; |
| 759 | } |
| 760 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 761 | psde->csc_cfg.csc_pre_lv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 762 | csc->v1.pre_clamp[i]; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 763 | psde->csc_cfg.csc_post_lv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 764 | csc->v1.post_clamp[i]; |
| 765 | } |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 766 | psde->csc_ptr = &psde->csc_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 767 | } |
| 768 | break; |
| 769 | default: |
| 770 | break; |
| 771 | } |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 772 | if (!psde->csc_ptr) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 773 | SDE_ERROR("invalid csc blob, v%lld\n", csc->version); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 774 | } |
| 775 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 776 | /* revert to kernel default if override not available */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 777 | if (psde->csc_ptr) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 778 | SDE_DEBUG("user blob override for csc\n"); |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame] | 779 | else if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 780 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 781 | } |
| 782 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 783 | static void _sde_plane_setup_scaler(struct sde_plane *psde, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 784 | const struct sde_format *fmt, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 785 | struct sde_plane_state *pstate) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 786 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 787 | struct sde_hw_pixel_ext *pe = NULL; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 788 | struct sde_drm_scaler *sc_u = NULL; |
| 789 | struct sde_drm_scaler_v1 *sc_u1 = NULL; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 790 | size_t sc_u_size = 0; |
| 791 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
| 792 | uint32_t tmp; |
| 793 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 794 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 795 | if (!psde || !fmt) |
| 796 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 797 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 798 | pe = &(psde->pixel_ext); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 799 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 800 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 801 | /* get scaler config from user space */ |
Clarence Ip | c3ffec1 | 2016-07-18 19:07:24 -0400 | [diff] [blame] | 802 | if (pstate) |
| 803 | sc_u = msm_property_get_blob(&psde->property_info, |
| 804 | pstate->property_blobs, |
| 805 | &sc_u_size, |
| 806 | PLANE_PROP_SCALER); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 807 | if (sc_u) { |
| 808 | switch (sc_u->version) { |
| 809 | case SDE_DRM_SCALER_V1: |
| 810 | if (!_sde_plane_verify_blob(sc_u, |
| 811 | sc_u_size, |
| 812 | &sc_u->v1, |
| 813 | sizeof(*sc_u1))) |
| 814 | sc_u1 = &sc_u->v1; |
| 815 | break; |
| 816 | default: |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 817 | SDE_DEBUG("unrecognized scaler blob v%lld\n", |
| 818 | sc_u->version); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 819 | break; |
| 820 | } |
| 821 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 822 | |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 823 | /* decimation */ |
| 824 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_DECIMATE)) { |
| 825 | psde->pipe_cfg.horz_decimation = sc_u1->horz_decimate; |
| 826 | psde->pipe_cfg.vert_decimation = sc_u1->vert_decimate; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 827 | } else { |
| 828 | psde->pipe_cfg.horz_decimation = 0; |
| 829 | psde->pipe_cfg.vert_decimation = 0; |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 830 | } |
| 831 | |
| 832 | /* don't chroma subsample if decimating */ |
| 833 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 834 | drm_format_horz_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 835 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 836 | drm_format_vert_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 837 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 838 | /* update scaler */ |
| 839 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 840 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_3)) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 841 | SDE_DEBUG("SCALER3 blob detected\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 842 | else |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 843 | _sde_plane_setup_scaler3(psde, |
| 844 | psde->pipe_cfg.src_rect.w, |
| 845 | psde->pipe_cfg.src_rect.h, |
| 846 | psde->pipe_cfg.dst_rect.w, |
| 847 | psde->pipe_cfg.dst_rect.h, |
| 848 | &psde->scaler3_cfg, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 849 | chroma_subsmpl_h, chroma_subsmpl_v); |
| 850 | } else { |
| 851 | /* always calculate basic scaler config */ |
| 852 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_2)) { |
| 853 | /* populate from user space */ |
| 854 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 855 | pe->init_phase_x[i] = sc_u1->init_phase_x[i]; |
| 856 | pe->phase_step_x[i] = sc_u1->phase_step_x[i]; |
| 857 | pe->init_phase_y[i] = sc_u1->init_phase_y[i]; |
| 858 | pe->phase_step_y[i] = sc_u1->phase_step_y[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 859 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 860 | pe->horz_filter[i] = sc_u1->horz_filter[i]; |
| 861 | pe->vert_filter[i] = sc_u1->vert_filter[i]; |
| 862 | } |
| 863 | } else { |
| 864 | /* calculate phase steps */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 865 | _sde_plane_setup_scaler2(psde, |
| 866 | psde->pipe_cfg.src_rect.w, |
| 867 | psde->pipe_cfg.dst_rect.w, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 868 | pe->phase_step_x, |
| 869 | pe->horz_filter, fmt, chroma_subsmpl_h); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 870 | _sde_plane_setup_scaler2(psde, |
| 871 | psde->pipe_cfg.src_rect.h, |
| 872 | psde->pipe_cfg.dst_rect.h, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 873 | pe->phase_step_y, |
| 874 | pe->vert_filter, fmt, chroma_subsmpl_v); |
| 875 | } |
| 876 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 877 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 878 | /* update pixel extensions */ |
| 879 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_PIX_EXT)) { |
| 880 | /* populate from user space */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 881 | SDE_DEBUG("pixel ext blob detected\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 882 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 883 | pe->num_ext_pxls_left[i] = sc_u1->lr.num_pxls_start[i]; |
| 884 | pe->num_ext_pxls_right[i] = sc_u1->lr.num_pxls_end[i]; |
| 885 | pe->left_ftch[i] = sc_u1->lr.ftch_start[i]; |
| 886 | pe->right_ftch[i] = sc_u1->lr.ftch_end[i]; |
| 887 | pe->left_rpt[i] = sc_u1->lr.rpt_start[i]; |
| 888 | pe->right_rpt[i] = sc_u1->lr.rpt_end[i]; |
| 889 | pe->roi_w[i] = sc_u1->lr.roi[i]; |
| 890 | |
| 891 | pe->num_ext_pxls_top[i] = sc_u1->tb.num_pxls_start[i]; |
| 892 | pe->num_ext_pxls_btm[i] = sc_u1->tb.num_pxls_end[i]; |
| 893 | pe->top_ftch[i] = sc_u1->tb.ftch_start[i]; |
| 894 | pe->btm_ftch[i] = sc_u1->tb.ftch_end[i]; |
| 895 | pe->top_rpt[i] = sc_u1->tb.rpt_start[i]; |
| 896 | pe->btm_rpt[i] = sc_u1->tb.rpt_end[i]; |
| 897 | pe->roi_h[i] = sc_u1->tb.roi[i]; |
| 898 | } |
| 899 | } else { |
| 900 | /* calculate left/right/top/bottom pixel extensions */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 901 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 902 | psde->pipe_cfg.horz_decimation); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 903 | if (SDE_FORMAT_IS_YUV(fmt)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 904 | tmp &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 905 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w, |
| 906 | psde->pipe_cfg.dst_rect.w, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 907 | pe->phase_step_x, |
| 908 | pe->roi_w, |
| 909 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 910 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 911 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 912 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 913 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 914 | psde->pipe_cfg.vert_decimation); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 915 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h, |
| 916 | psde->pipe_cfg.dst_rect.h, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 917 | pe->phase_step_y, |
| 918 | pe->roi_h, |
| 919 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 920 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 921 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 922 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 923 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 924 | if (pe->num_ext_pxls_left[i] >= 0) |
| 925 | pe->left_rpt[i] = |
| 926 | pe->num_ext_pxls_left[i]; |
| 927 | else |
| 928 | pe->left_ftch[i] = |
| 929 | pe->num_ext_pxls_left[i]; |
| 930 | |
| 931 | if (pe->num_ext_pxls_right[i] >= 0) |
| 932 | pe->right_rpt[i] = |
| 933 | pe->num_ext_pxls_right[i]; |
| 934 | else |
| 935 | pe->right_ftch[i] = |
| 936 | pe->num_ext_pxls_right[i]; |
| 937 | |
| 938 | if (pe->num_ext_pxls_top[i] >= 0) |
| 939 | pe->top_rpt[i] = |
| 940 | pe->num_ext_pxls_top[i]; |
| 941 | else |
| 942 | pe->top_ftch[i] = |
| 943 | pe->num_ext_pxls_top[i]; |
| 944 | |
| 945 | if (pe->num_ext_pxls_btm[i] >= 0) |
| 946 | pe->btm_rpt[i] = |
| 947 | pe->num_ext_pxls_btm[i]; |
| 948 | else |
| 949 | pe->btm_ftch[i] = |
| 950 | pe->num_ext_pxls_btm[i]; |
| 951 | } |
| 952 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 953 | } |
| 954 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 955 | /** |
| 956 | * _sde_plane_color_fill - enables color fill on plane |
| 957 | * @plane: Pointer to DRM plane object |
| 958 | * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red |
| 959 | * @alpha: 8-bit fill alpha value, 255 selects 100% alpha |
| 960 | * Returns: 0 on success |
| 961 | */ |
| 962 | static int _sde_plane_color_fill(struct drm_plane *plane, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 963 | uint32_t color, uint32_t alpha) |
| 964 | { |
| 965 | struct sde_plane *psde; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 966 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 967 | |
| 968 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 969 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 970 | return -EINVAL; |
| 971 | } |
| 972 | |
| 973 | psde = to_sde_plane(plane); |
| 974 | if (!psde->pipe_hw) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 975 | SDE_ERROR("invalid plane h/w pointer\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 976 | return -EINVAL; |
| 977 | } |
| 978 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 979 | DBG(""); |
| 980 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 981 | /* |
| 982 | * select fill format to match user property expectation, |
| 983 | * h/w only supports RGB variants |
| 984 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 985 | fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 986 | |
| 987 | /* update sspp */ |
| 988 | if (fmt && psde->pipe_hw->ops.setup_solidfill) { |
| 989 | psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw, |
| 990 | (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); |
| 991 | |
| 992 | /* override scaler/decimation if solid fill */ |
| 993 | psde->pipe_cfg.src_rect.x = 0; |
| 994 | psde->pipe_cfg.src_rect.y = 0; |
| 995 | psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w; |
| 996 | psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h; |
| 997 | |
| 998 | _sde_plane_setup_scaler(psde, fmt, 0); |
| 999 | |
| 1000 | if (psde->pipe_hw->ops.setup_format) |
| 1001 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
| 1002 | fmt, SDE_SSPP_SOLID_FILL); |
| 1003 | |
| 1004 | if (psde->pipe_hw->ops.setup_rects) |
| 1005 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 1006 | &psde->pipe_cfg, &psde->pixel_ext); |
| 1007 | } |
| 1008 | |
| 1009 | return 0; |
| 1010 | } |
| 1011 | |
| 1012 | static int _sde_plane_mode_set(struct drm_plane *plane, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1013 | struct drm_plane_state *state) |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1014 | { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1015 | uint32_t nplanes, src_flags; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1016 | struct sde_plane *psde; |
| 1017 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1018 | const struct sde_format *fmt; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1019 | struct drm_crtc *crtc; |
| 1020 | struct drm_framebuffer *fb; |
| 1021 | struct sde_rect src, dst; |
| 1022 | bool q16_data = true; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1023 | |
| 1024 | if (!plane || !plane->state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1025 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1026 | return -EINVAL; |
| 1027 | } |
| 1028 | |
| 1029 | psde = to_sde_plane(plane); |
| 1030 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1031 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1032 | crtc = state->crtc; |
| 1033 | fb = state->fb; |
| 1034 | if (!crtc || !fb) { |
| 1035 | SDE_ERROR("invalid crtc/fb\n"); |
| 1036 | return -EINVAL; |
| 1037 | } |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1038 | fmt = to_sde_format(msm_framebuffer_format(fb)); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1039 | nplanes = fmt->num_planes; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1040 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 1041 | psde->is_rt_pipe = _sde_plane_is_rt_pipe(plane, crtc); |
| 1042 | |
| 1043 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1044 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1045 | POPULATE_RECT(&src, state->src_x, state->src_y, |
| 1046 | state->src_w, state->src_h, q16_data); |
| 1047 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, |
| 1048 | state->crtc_w, state->crtc_h, !q16_data); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1049 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1050 | SDE_DEBUG("%s:FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u, %s ubwc %d\n", |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1051 | psde->pipe_name, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1052 | fb->base.id, src.x, src.y, src.w, src.h, |
| 1053 | crtc->base.id, dst.x, dst.y, dst.w, dst.h, |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1054 | drm_get_format_name(fmt->base.pixel_format), |
| 1055 | SDE_FORMAT_IS_UBWC(fmt)); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1056 | |
| 1057 | /* update format configuration */ |
| 1058 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
| 1059 | src_flags = 0; |
| 1060 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1061 | /* flags */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1062 | SDE_DEBUG("flags 0x%llX, rotation 0x%llX\n", |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1063 | sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG), |
| 1064 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 1065 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1066 | BIT(DRM_REFLECT_X)) |
| 1067 | src_flags |= SDE_SSPP_FLIP_LR; |
| 1068 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 1069 | BIT(DRM_REFLECT_Y)) |
| 1070 | src_flags |= SDE_SSPP_FLIP_UD; |
| 1071 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 1072 | BIT(SDE_DRM_DEINTERLACE)) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1073 | src.h /= 2; |
| 1074 | src.y = DIV_ROUND_UP(src.y, 2); |
| 1075 | src.y &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1076 | } |
| 1077 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1078 | psde->pipe_cfg.src_rect = src; |
| 1079 | psde->pipe_cfg.dst_rect = dst; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1080 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1081 | /* check for color fill */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1082 | psde->color_fill = (uint32_t)sde_plane_get_property(pstate, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1083 | PLANE_PROP_COLOR_FILL); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1084 | if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) |
| 1085 | /* skip remaining processing on color fill */ |
| 1086 | return 0; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1087 | |
| 1088 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 1089 | |
| 1090 | _sde_plane_setup_scaler(psde, fmt, pstate); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1091 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1092 | if (psde->pipe_hw->ops.setup_format) |
| 1093 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1094 | fmt, src_flags); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1095 | if (psde->pipe_hw->ops.setup_rects) |
| 1096 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 1097 | &psde->pipe_cfg, &psde->pixel_ext); |
| 1098 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1099 | /* update sharpening */ |
| 1100 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 1101 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 1102 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 1103 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
| 1104 | |
| 1105 | if (psde->pipe_hw->ops.setup_sharpening) |
| 1106 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
| 1107 | &psde->sharp_cfg); |
| 1108 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1109 | /* update csc */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1110 | if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1111 | _sde_plane_setup_csc(psde, pstate, fmt); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1112 | else |
| 1113 | psde->csc_ptr = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1114 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 1115 | _sde_plane_set_qos_lut(plane, fb); |
| 1116 | _sde_plane_set_danger_lut(plane, fb); |
| 1117 | |
| 1118 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
| 1119 | _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL); |
| 1120 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1121 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1122 | } |
| 1123 | |
| 1124 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
| 1125 | const struct drm_plane_state *new_state) |
| 1126 | { |
| 1127 | struct drm_framebuffer *fb = new_state->fb; |
| 1128 | struct sde_plane *psde = to_sde_plane(plane); |
| 1129 | |
| 1130 | if (!new_state->fb) |
| 1131 | return 0; |
| 1132 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1133 | SDE_DEBUG("%s: FB[%u]\n", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1134 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 1135 | } |
| 1136 | |
| 1137 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
| 1138 | const struct drm_plane_state *old_state) |
| 1139 | { |
| 1140 | struct drm_framebuffer *fb = old_state->fb; |
| 1141 | struct sde_plane *psde = to_sde_plane(plane); |
| 1142 | |
| 1143 | if (!fb) |
| 1144 | return; |
| 1145 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1146 | SDE_DEBUG("%s: FB[%u]\n", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1147 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 1148 | } |
| 1149 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1150 | static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde, |
| 1151 | struct drm_plane_state *state, |
| 1152 | struct drm_plane_state *old_state) |
| 1153 | { |
| 1154 | struct sde_plane_state *pstate = to_sde_plane_state(state); |
| 1155 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1156 | /* no need to check it again */ |
| 1157 | if (pstate->mode_changed) |
| 1158 | return; |
| 1159 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1160 | if (!(sde_plane_enabled(state) && sde_plane_enabled(old_state))) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1161 | SDE_DEBUG("%s: pipe enabling/disabling full modeset required\n", |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1162 | psde->pipe_name); |
| 1163 | pstate->mode_changed = true; |
| 1164 | } else if (to_sde_plane_state(old_state)->pending) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1165 | SDE_DEBUG("%s: still pending\n", psde->pipe_name); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1166 | pstate->mode_changed = true; |
| 1167 | } else if (state->src_w != old_state->src_w || |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1168 | state->src_h != old_state->src_h || |
| 1169 | state->src_x != old_state->src_x || |
| 1170 | state->src_y != old_state->src_y) { |
| 1171 | SDE_DEBUG("%s: src rect updated\n", psde->pipe_name); |
| 1172 | pstate->mode_changed = true; |
| 1173 | } else if (state->crtc_w != old_state->crtc_w || |
| 1174 | state->crtc_h != old_state->crtc_h || |
| 1175 | state->crtc_x != old_state->crtc_x || |
| 1176 | state->crtc_y != old_state->crtc_y) { |
| 1177 | SDE_DEBUG("%s: crtc rect updated\n", psde->pipe_name); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1178 | pstate->mode_changed = true; |
| 1179 | } else if (state->fb->pixel_format != old_state->fb->pixel_format) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1180 | SDE_DEBUG("%s: format change!\n", psde->pipe_name); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1181 | pstate->mode_changed = true; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1182 | } else { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1183 | uint64_t *new_mods = state->fb->modifier; |
| 1184 | uint64_t *old_mods = old_state->fb->modifier; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1185 | uint32_t *new_pitches = state->fb->pitches; |
| 1186 | uint32_t *old_pitches = old_state->fb->pitches; |
| 1187 | uint32_t *new_offset = state->fb->offsets; |
| 1188 | uint32_t *old_offset = old_state->fb->offsets; |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1189 | int i; |
| 1190 | |
| 1191 | for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) { |
| 1192 | if (new_mods[i] != old_mods[i]) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1193 | SDE_DEBUG("%s: format modifiers change\"\ |
| 1194 | plane:%d new_mode:%llu old_mode:%llu\n", |
| 1195 | psde->pipe_name, i, new_mods[i], |
| 1196 | old_mods[i]); |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1197 | pstate->mode_changed = true; |
| 1198 | break; |
| 1199 | } |
| 1200 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1201 | for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) { |
| 1202 | if (new_pitches[i] != old_pitches[i]) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1203 | SDE_DEBUG("%s: pitches change plane:%d\"\ |
| 1204 | old_pitches:%u new_pitches:%u\n", |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1205 | psde->pipe_name, i, old_pitches[i], |
| 1206 | new_pitches[i]); |
| 1207 | pstate->mode_changed = true; |
| 1208 | break; |
| 1209 | } |
| 1210 | } |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1211 | for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) { |
| 1212 | if (new_offset[i] != old_offset[i]) { |
| 1213 | SDE_DEBUG("%s: offset change plane:%d\"\ |
| 1214 | old_offset:%u new_offset:%u\n", |
| 1215 | psde->pipe_name, i, old_offset[i], |
| 1216 | new_offset[i]); |
| 1217 | pstate->mode_changed = true; |
| 1218 | break; |
| 1219 | } |
| 1220 | } |
Lloyd Atkinson | 3ab9ef7 | 2016-07-14 17:42:41 -0400 | [diff] [blame] | 1221 | } |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1222 | } |
| 1223 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1224 | static bool __get_scale_data(struct sde_plane *psde, |
| 1225 | struct sde_plane_state *pstate, struct sde_drm_scaler *sc_u, |
| 1226 | size_t *sc_u_size) |
| 1227 | { |
| 1228 | bool valid_flag = false; |
| 1229 | |
| 1230 | sc_u = msm_property_get_blob(&psde->property_info, |
| 1231 | pstate->property_blobs, |
| 1232 | sc_u_size, |
| 1233 | PLANE_PROP_SCALER); |
| 1234 | if (sc_u) { |
| 1235 | switch (sc_u->version) { |
| 1236 | case SDE_DRM_SCALER_V1: |
| 1237 | if (!_sde_plane_verify_blob(sc_u, *sc_u_size, |
| 1238 | &sc_u->v1, sizeof(struct sde_drm_scaler_v1))) |
| 1239 | valid_flag = true; |
| 1240 | break; |
| 1241 | default: |
| 1242 | SDE_DEBUG("unrecognized scaler blob v%lld\n", |
| 1243 | sc_u->version); |
| 1244 | break; |
| 1245 | } |
| 1246 | } |
| 1247 | |
| 1248 | return valid_flag; |
| 1249 | } |
| 1250 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1251 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 1252 | struct drm_plane_state *state) |
| 1253 | { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1254 | int ret = 0, valid_scale_data; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1255 | struct sde_plane *psde; |
| 1256 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1257 | const struct sde_format *fmt; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1258 | size_t sc_u_size = 0; |
| 1259 | struct sde_drm_scaler *sc_u = NULL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1260 | struct sde_rect src, dst; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1261 | uint32_t deci_w, deci_h, src_deci_w, src_deci_h; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1262 | uint32_t max_upscale, max_downscale, min_src_size, max_linewidth; |
| 1263 | bool q16_data = true; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1264 | |
| 1265 | if (!plane || !state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1266 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1267 | ret = -EINVAL; |
| 1268 | goto exit; |
| 1269 | } |
| 1270 | |
| 1271 | psde = to_sde_plane(plane); |
| 1272 | pstate = to_sde_plane_state(state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1273 | |
| 1274 | if (!psde->pipe_sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1275 | SDE_ERROR("invalid plane catalog\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1276 | ret = -EINVAL; |
| 1277 | goto exit; |
| 1278 | } |
| 1279 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1280 | valid_scale_data = __get_scale_data(psde, pstate, sc_u, &sc_u_size); |
| 1281 | deci_w = valid_scale_data && sc_u ? sc_u->v1.horz_decimate : 0; |
| 1282 | deci_h = valid_scale_data && sc_u ? sc_u->v1.vert_decimate : 0; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1283 | |
| 1284 | /* src values are in Q16 fixed point, convert to integer */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1285 | POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w, |
| 1286 | state->src_h, q16_data); |
| 1287 | POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w, |
| 1288 | state->crtc_h, !q16_data); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1289 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1290 | src_deci_w = DECIMATED_DIMENSION(src.w, deci_w); |
| 1291 | src_deci_h = DECIMATED_DIMENSION(src.h, deci_h); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1292 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1293 | max_upscale = psde->pipe_sblk->maxupscale; |
| 1294 | max_downscale = psde->pipe_sblk->maxdwnscale; |
| 1295 | max_linewidth = psde->pipe_sblk->maxlinewidth; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1296 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1297 | SDE_DEBUG("%s: check (%d -> %d)\n", psde->pipe_name, |
| 1298 | sde_plane_enabled(plane->state), sde_plane_enabled(state)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1299 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1300 | if (!sde_plane_enabled(state)) |
| 1301 | goto modeset_update; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1302 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1303 | fmt = to_sde_format(msm_framebuffer_format(state->fb)); |
| 1304 | |
| 1305 | min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1; |
| 1306 | |
| 1307 | if (SDE_FORMAT_IS_YUV(fmt) && |
| 1308 | (!(psde->features & SDE_SSPP_SCALER) || |
| 1309 | !(psde->features & BIT(SDE_SSPP_CSC)))) { |
| 1310 | SDE_ERROR("plane doesn't have scaler/csc capability for yuv\n"); |
| 1311 | ret = -EINVAL; |
| 1312 | |
| 1313 | /* check src bounds */ |
| 1314 | } else if (state->fb->width > MAX_IMG_WIDTH || |
| 1315 | state->fb->height > MAX_IMG_HEIGHT || |
| 1316 | src.w < min_src_size || src.h < min_src_size || |
| 1317 | CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) || |
| 1318 | CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) { |
| 1319 | SDE_ERROR("invalid source (%u, %u) -> (%u, %u)\n", |
| 1320 | src.x, src.y, src.w, src.h); |
| 1321 | ret = -E2BIG; |
| 1322 | |
| 1323 | /* valid yuv image */ |
| 1324 | } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) || |
| 1325 | (src.w & 0x1) || (src.h & 0x1))) { |
| 1326 | SDE_ERROR("invalid yuv source (%u, %u) -> (%u, %u)\n", |
| 1327 | src.x, src.y, src.w, src.h); |
| 1328 | ret = -EINVAL; |
| 1329 | |
| 1330 | /* min dst support */ |
| 1331 | } else if (dst.w < 0x1 || dst.h < 0x1) { |
| 1332 | SDE_ERROR("invalid dest rect (%u, %u) -> (%u, %u)\n", |
| 1333 | dst.x, dst.y, dst.w, dst.h); |
| 1334 | ret = -EINVAL; |
| 1335 | |
| 1336 | /* decimation validation */ |
| 1337 | } else if (deci_w || deci_h) { |
| 1338 | if ((deci_w > psde->pipe_sblk->maxhdeciexp) || |
| 1339 | (deci_h > psde->pipe_sblk->maxvdeciexp)) { |
| 1340 | SDE_ERROR("too much decimation requested\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1341 | ret = -EINVAL; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1342 | } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
| 1343 | SDE_ERROR("decimation requires linear fetch\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1344 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1345 | } |
| 1346 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1347 | } else if (!(psde->features & SDE_SSPP_SCALER) && |
| 1348 | ((src.w != dst.w) || (src.h != dst.h))) { |
| 1349 | SDE_ERROR("pipe doesn't support scaling %ux%u->%ux%u\n", |
| 1350 | src.w, src.h, dst.w, dst.h); |
| 1351 | ret = -EINVAL; |
| 1352 | |
| 1353 | /* check decimated source width */ |
| 1354 | } else if (src_deci_w > max_linewidth) { |
| 1355 | SDE_ERROR("invalid source width:%u, deci wid:%u, line wid:%u\n", |
| 1356 | src.w, src_deci_w, max_linewidth); |
| 1357 | ret = -E2BIG; |
| 1358 | |
| 1359 | /* check max scaler capability */ |
| 1360 | } else if (((src_deci_w * max_upscale) < dst.w) || |
| 1361 | ((src_deci_h * max_upscale) < dst.h) || |
| 1362 | ((dst.w * max_downscale) < src_deci_w) || |
| 1363 | ((dst.h * max_downscale) < src_deci_h)) { |
| 1364 | SDE_ERROR("too much scaling requested %ux%u -> %ux%u\n", |
| 1365 | src_deci_w, src_deci_h, dst.w, dst.h); |
| 1366 | ret = -E2BIG; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1367 | } |
| 1368 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1369 | modeset_update: |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 1370 | if (!ret) |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1371 | _sde_plane_atomic_check_mode_changed(psde, state, plane->state); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1372 | exit: |
| 1373 | return ret; |
| 1374 | } |
| 1375 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1376 | /** |
| 1377 | * sde_plane_flush - final plane operations before commit flush |
| 1378 | * @plane: Pointer to drm plane structure |
| 1379 | */ |
| 1380 | void sde_plane_flush(struct drm_plane *plane) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1381 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1382 | struct sde_plane *psde; |
| 1383 | |
| 1384 | if (!plane) |
| 1385 | return; |
| 1386 | |
| 1387 | psde = to_sde_plane(plane); |
| 1388 | |
| 1389 | /* |
| 1390 | * These updates have to be done immediately before the plane flush |
| 1391 | * timing, and may not be moved to the atomic_update/mode_set functions. |
| 1392 | */ |
| 1393 | if (psde->is_error) |
| 1394 | /* force white frame with 0% alpha pipe output on error */ |
| 1395 | _sde_plane_color_fill(plane, 0xFFFFFF, 0x0); |
| 1396 | else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) |
| 1397 | /* force 100% alpha */ |
| 1398 | _sde_plane_color_fill(plane, psde->color_fill, 0xFF); |
| 1399 | else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc) |
| 1400 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
| 1401 | |
| 1402 | /* flag h/w flush complete */ |
| 1403 | if (plane->state) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1404 | to_sde_plane_state(plane->state)->pending = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1405 | } |
| 1406 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1407 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1408 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1409 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1410 | struct sde_plane *sde_plane; |
| 1411 | struct drm_plane_state *state; |
| 1412 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1413 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1414 | if (!plane || !plane->state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1415 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1416 | return; |
| 1417 | } |
| 1418 | |
| 1419 | sde_plane = to_sde_plane(plane); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1420 | sde_plane->is_error = false; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1421 | state = plane->state; |
| 1422 | pstate = to_sde_plane_state(state); |
| 1423 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1424 | SDE_DEBUG("%s: update\n", sde_plane->pipe_name); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1425 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1426 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1427 | pstate->pending = true; |
| 1428 | } else if (pstate->mode_changed) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1429 | int ret; |
| 1430 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1431 | pstate->pending = true; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1432 | ret = _sde_plane_mode_set(plane, state); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1433 | /* atomic_check should have ensured that this doesn't fail */ |
| 1434 | WARN_ON(ret < 0); |
| 1435 | } else { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1436 | _sde_plane_set_scanout(plane, pstate, |
| 1437 | &sde_plane->pipe_cfg, state->fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1438 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1439 | } |
| 1440 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1441 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1442 | /* helper to install properties which are common to planes and crtcs */ |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1443 | static void _sde_plane_install_properties(struct drm_plane *plane, |
| 1444 | u32 max_blendstages) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1445 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1446 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 1447 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 1448 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 1449 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 1450 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 1451 | }; |
| 1452 | static const struct drm_prop_enum_list e_src_config[] = { |
| 1453 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 1454 | }; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1455 | const struct sde_format_extended *format_list; |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1456 | struct sde_kms_info *info; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1457 | struct sde_plane *psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1458 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1459 | if (!plane || !psde || !psde->pipe_hw || !psde->pipe_sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1460 | SDE_ERROR("Invalid argument(s)\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1461 | return; |
| 1462 | } |
| 1463 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1464 | msm_property_install_range(&psde->property_info, "zpos", 0x0, 0, |
| 1465 | max_blendstages, STAGE_BASE, PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1466 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1467 | msm_property_install_range(&psde->property_info, "alpha", |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1468 | 0x0, 0, 255, 255, PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1469 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1470 | /* linux default file descriptor range on each process */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1471 | msm_property_install_range(&psde->property_info, "input_fence", |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1472 | 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1473 | |
| 1474 | /* standard properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1475 | msm_property_install_rotation(&psde->property_info, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1476 | BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1477 | |
Lloyd Atkinson | 38ad8c9 | 2016-07-06 10:39:32 -0400 | [diff] [blame] | 1478 | msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0, |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1479 | e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1480 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1481 | msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1, |
| 1482 | e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG); |
| 1483 | |
| 1484 | if (psde->pipe_hw->ops.setup_solidfill) |
| 1485 | msm_property_install_range(&psde->property_info, "color_fill", |
| 1486 | 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL); |
| 1487 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1488 | if (psde->features & SDE_SSPP_SCALER) |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1489 | msm_property_install_blob(&psde->property_info, "scaler", 0, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1490 | PLANE_PROP_SCALER); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1491 | |
| 1492 | if (psde->features & BIT(SDE_SSPP_CSC)) |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1493 | msm_property_install_blob(&psde->property_info, "csc", 0, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1494 | PLANE_PROP_CSC); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1495 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1496 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
| 1497 | if (!info) |
| 1498 | return; |
| 1499 | |
| 1500 | msm_property_install_blob(&psde->property_info, "capabilities", |
| 1501 | DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO); |
| 1502 | sde_kms_info_reset(info); |
| 1503 | |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1504 | format_list = psde->pipe_sblk->format_list; |
| 1505 | if (format_list) { |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1506 | sde_kms_info_start(info, "pixel_formats"); |
| 1507 | while (format_list->fourcc_format) { |
| 1508 | sde_kms_info_append_format(info, |
| 1509 | format_list->fourcc_format, |
| 1510 | format_list->modifier); |
| 1511 | ++format_list; |
| 1512 | } |
| 1513 | sde_kms_info_stop(info); |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1514 | } |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1515 | |
| 1516 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 1517 | psde->pipe_sblk->maxlinewidth); |
| 1518 | sde_kms_info_add_keyint(info, "max_upscale", |
| 1519 | psde->pipe_sblk->maxupscale); |
| 1520 | sde_kms_info_add_keyint(info, "max_downscale", |
| 1521 | psde->pipe_sblk->maxdwnscale); |
| 1522 | sde_kms_info_add_keyint(info, "max_horizontal_deci", |
| 1523 | psde->pipe_sblk->maxhdeciexp); |
| 1524 | sde_kms_info_add_keyint(info, "max_vertical_deci", |
| 1525 | psde->pipe_sblk->maxvdeciexp); |
| 1526 | msm_property_set_blob(&psde->property_info, &psde->blob_info, |
| 1527 | info->data, info->len, PLANE_PROP_INFO); |
| 1528 | |
| 1529 | kfree(info); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1530 | } |
| 1531 | |
| 1532 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1533 | struct drm_plane_state *state, struct drm_property *property, |
| 1534 | uint64_t val) |
| 1535 | { |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1536 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1537 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1538 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1539 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1540 | DBG(""); |
| 1541 | |
| 1542 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1543 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1544 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1545 | SDE_ERROR("invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1546 | } else { |
| 1547 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1548 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1549 | ret = msm_property_atomic_set(&psde->property_info, |
| 1550 | pstate->property_values, pstate->property_blobs, |
| 1551 | property, val); |
| 1552 | if (!ret) { |
| 1553 | idx = msm_property_index(&psde->property_info, |
| 1554 | property); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1555 | if (idx == PLANE_PROP_INPUT_FENCE) |
| 1556 | _sde_plane_set_input_fence(plane, pstate, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1557 | } |
| 1558 | } |
| 1559 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1560 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1561 | } |
| 1562 | |
| 1563 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1564 | struct drm_property *property, uint64_t val) |
| 1565 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1566 | DBG(""); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1567 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1568 | return sde_plane_atomic_set_property(plane, |
| 1569 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1570 | } |
| 1571 | |
| 1572 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1573 | const struct drm_plane_state *state, |
| 1574 | struct drm_property *property, uint64_t *val) |
| 1575 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1576 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1577 | struct sde_plane_state *pstate; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1578 | int ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1579 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1580 | DBG(""); |
| 1581 | |
| 1582 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1583 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1584 | } else if (!state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1585 | SDE_ERROR("invalid state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1586 | } else { |
| 1587 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1588 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1589 | ret = msm_property_atomic_get(&psde->property_info, |
| 1590 | pstate->property_values, pstate->property_blobs, |
| 1591 | property, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1592 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1593 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1594 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1595 | } |
| 1596 | |
| 1597 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1598 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1599 | struct sde_plane *psde; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1600 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1601 | DBG(""); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1602 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1603 | if (plane) { |
| 1604 | psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1605 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame^] | 1606 | _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL); |
| 1607 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1608 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1609 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 1610 | if (psde->blob_info) |
| 1611 | drm_property_unreference_blob(psde->blob_info); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1612 | msm_property_destroy(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1613 | mutex_destroy(&psde->lock); |
| 1614 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1615 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1616 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1617 | /* this will destroy the states as well */ |
| 1618 | drm_plane_cleanup(plane); |
| 1619 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1620 | if (psde->pipe_hw) |
| 1621 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1622 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1623 | kfree(psde); |
| 1624 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1625 | } |
| 1626 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1627 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1628 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1629 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1630 | struct sde_plane *psde; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1631 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1632 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1633 | if (!plane || !state) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1634 | SDE_ERROR("invalid plane/state\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1635 | return; |
| 1636 | } |
| 1637 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1638 | psde = to_sde_plane(plane); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1639 | pstate = to_sde_plane_state(state); |
| 1640 | |
| 1641 | DBG(""); |
| 1642 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1643 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1644 | if (state->fb) |
| 1645 | drm_framebuffer_unreference(state->fb); |
| 1646 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1647 | /* remove ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1648 | if (pstate->input_fence) |
| 1649 | sde_sync_put(pstate->input_fence); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1650 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1651 | /* destroy value helper */ |
| 1652 | msm_property_destroy_state(&psde->property_info, pstate, |
| 1653 | pstate->property_values, pstate->property_blobs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1654 | } |
| 1655 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1656 | static struct drm_plane_state * |
| 1657 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1658 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1659 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1660 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1661 | struct sde_plane_state *old_state; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1662 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1663 | if (!plane || !plane->state) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1664 | return NULL; |
| 1665 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1666 | old_state = to_sde_plane_state(plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1667 | psde = to_sde_plane(plane); |
| 1668 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1669 | if (!pstate) |
| 1670 | return NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1671 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1672 | DBG(""); |
| 1673 | |
| 1674 | /* duplicate value helper */ |
| 1675 | msm_property_duplicate_state(&psde->property_info, old_state, pstate, |
| 1676 | pstate->property_values, pstate->property_blobs); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1677 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1678 | /* add ref count for frame buffer */ |
| 1679 | if (pstate->base.fb) |
| 1680 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1681 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1682 | /* add ref count for fence */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1683 | if (pstate->input_fence) { |
| 1684 | pstate->input_fence = 0; |
| 1685 | _sde_plane_set_input_fence(plane, pstate, pstate-> |
| 1686 | property_values[PLANE_PROP_INPUT_FENCE]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1687 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1688 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1689 | pstate->mode_changed = false; |
| 1690 | pstate->pending = false; |
| 1691 | |
| 1692 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1693 | } |
| 1694 | |
| 1695 | static void sde_plane_reset(struct drm_plane *plane) |
| 1696 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1697 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1698 | struct sde_plane_state *pstate; |
| 1699 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1700 | if (!plane) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1701 | SDE_ERROR("invalid plane\n"); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1702 | return; |
| 1703 | } |
| 1704 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1705 | psde = to_sde_plane(plane); |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1706 | SDE_DEBUG("%s\n", psde->pipe_name); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1707 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1708 | /* remove previous state, if present */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1709 | if (plane->state) { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1710 | sde_plane_destroy_state(plane, plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1711 | plane->state = 0; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1712 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1713 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1714 | pstate = msm_property_alloc_state(&psde->property_info); |
| 1715 | if (!pstate) |
| 1716 | return; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1717 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1718 | /* reset value helper */ |
| 1719 | msm_property_reset_state(&psde->property_info, pstate, |
| 1720 | pstate->property_values, pstate->property_blobs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1721 | |
| 1722 | pstate->base.plane = plane; |
| 1723 | |
| 1724 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1725 | } |
| 1726 | |
| 1727 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1728 | .update_plane = drm_atomic_helper_update_plane, |
| 1729 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1730 | .destroy = sde_plane_destroy, |
| 1731 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1732 | .atomic_set_property = sde_plane_atomic_set_property, |
| 1733 | .atomic_get_property = sde_plane_atomic_get_property, |
| 1734 | .reset = sde_plane_reset, |
| 1735 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 1736 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1737 | }; |
| 1738 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1739 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 1740 | .prepare_fb = sde_plane_prepare_fb, |
| 1741 | .cleanup_fb = sde_plane_cleanup_fb, |
| 1742 | .atomic_check = sde_plane_atomic_check, |
| 1743 | .atomic_update = sde_plane_atomic_update, |
| 1744 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1745 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1746 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1747 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1748 | struct sde_plane *sde_plane = to_sde_plane(plane); |
| 1749 | |
| 1750 | return sde_plane->pipe; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1751 | } |
| 1752 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1753 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 1754 | { |
| 1755 | const struct sde_sspp_sub_blks *sblk = 0; |
| 1756 | const struct sde_sspp_cfg *cfg = 0; |
| 1757 | |
| 1758 | if (psde && psde->pipe_hw) |
| 1759 | cfg = psde->pipe_hw->cap; |
| 1760 | if (cfg) |
| 1761 | sblk = cfg->sblk; |
| 1762 | |
| 1763 | if (kms && sblk) { |
| 1764 | /* create overall sub-directory for the pipe */ |
| 1765 | psde->debugfs_root = |
| 1766 | debugfs_create_dir(psde->pipe_name, |
| 1767 | sde_debugfs_get_root(kms)); |
| 1768 | if (psde->debugfs_root) { |
| 1769 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1770 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1771 | psde->debugfs_root, &psde->features); |
| 1772 | |
| 1773 | /* add register dump support */ |
| 1774 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 1775 | sblk->src_blk.base + cfg->base, |
| 1776 | sblk->src_blk.len, |
| 1777 | kms->mmio); |
| 1778 | sde_debugfs_create_regset32("src_blk", 0444, |
| 1779 | psde->debugfs_root, &psde->debugfs_src); |
| 1780 | |
| 1781 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 1782 | sblk->scaler_blk.base + cfg->base, |
| 1783 | sblk->scaler_blk.len, |
| 1784 | kms->mmio); |
| 1785 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 1786 | psde->debugfs_root, |
| 1787 | &psde->debugfs_scaler); |
| 1788 | |
| 1789 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 1790 | sblk->csc_blk.base + cfg->base, |
| 1791 | sblk->csc_blk.len, |
| 1792 | kms->mmio); |
| 1793 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 1794 | psde->debugfs_root, &psde->debugfs_csc); |
| 1795 | } |
| 1796 | } |
| 1797 | } |
| 1798 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1799 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1800 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1801 | uint32_t pipe, bool primary_plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1802 | { |
| 1803 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1804 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1805 | struct msm_drm_private *priv; |
| 1806 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1807 | enum drm_plane_type type; |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1808 | int ret = -EINVAL, max_blendstages = 255; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1809 | |
| 1810 | if (!dev) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1811 | SDE_ERROR("[%u]device is NULL\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1812 | goto exit; |
| 1813 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1814 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1815 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1816 | if (!priv) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1817 | SDE_ERROR("[%u]private data is NULL\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1818 | goto exit; |
| 1819 | } |
| 1820 | |
| 1821 | if (!priv->kms) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1822 | SDE_ERROR("[%u]invalid KMS reference\n", pipe); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1823 | goto exit; |
| 1824 | } |
| 1825 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1826 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1827 | if (!kms->catalog) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1828 | SDE_ERROR("[%u]invalid catalog reference\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1829 | goto exit; |
| 1830 | } |
| 1831 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1832 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1833 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 1834 | if (!psde) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1835 | SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1836 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1837 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1838 | } |
| 1839 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1840 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1841 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1842 | psde->pipe = pipe; |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 1843 | psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1844 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1845 | /* initialize underlying h/w driver */ |
| 1846 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 1847 | if (IS_ERR(psde->pipe_hw)) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1848 | SDE_ERROR("[%u]SSPP init failed\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1849 | ret = PTR_ERR(psde->pipe_hw); |
| 1850 | goto clean_plane; |
| 1851 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1852 | SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1853 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1854 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1855 | |
| 1856 | /* cache features mask for later */ |
| 1857 | psde->features = psde->pipe_hw->cap->features; |
| 1858 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1859 | if (!psde->pipe_sblk) { |
| 1860 | SDE_ERROR("invalid sblk on pipe %d\n", pipe); |
| 1861 | goto clean_sspp; |
| 1862 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1863 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1864 | if (kms->catalog && kms->catalog->mixer_count && kms->catalog->mixer) |
| 1865 | max_blendstages = kms->catalog->mixer[0].sblk->maxblendstages; |
| 1866 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1867 | /* add plane to DRM framework */ |
Clarence Ip | ea3d626 | 2016-07-15 16:20:11 -0400 | [diff] [blame] | 1868 | psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list, |
| 1869 | psde->formats, |
| 1870 | 0, |
| 1871 | ARRAY_SIZE(psde->formats)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1872 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1873 | if (!psde->nformats) { |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1874 | SDE_ERROR("[%u]no valid formats for plane\n", pipe); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1875 | goto clean_sspp; |
| 1876 | } |
| 1877 | |
| 1878 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 1879 | type = DRM_PLANE_TYPE_CURSOR; |
| 1880 | else if (primary_plane) |
| 1881 | type = DRM_PLANE_TYPE_PRIMARY; |
| 1882 | else |
| 1883 | type = DRM_PLANE_TYPE_OVERLAY; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1884 | ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs, |
| 1885 | psde->formats, psde->nformats, |
| 1886 | type); |
| 1887 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1888 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1889 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1890 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1891 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1892 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1893 | msm_property_init(&psde->property_info, &plane->base, dev, |
| 1894 | priv->plane_property, psde->property_data, |
| 1895 | PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT, |
| 1896 | sizeof(struct sde_plane_state)); |
| 1897 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1898 | _sde_plane_install_properties(plane, max_blendstages); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1899 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1900 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1901 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1902 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1903 | mutex_init(&psde->lock); |
| 1904 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1905 | _sde_plane_init_debugfs(psde, kms); |
| 1906 | |
Dhaval Patel | 47302cf | 2016-08-18 15:04:28 -0700 | [diff] [blame] | 1907 | DRM_INFO("[%u]successfully created %s\n", pipe, psde->pipe_name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1908 | return plane; |
| 1909 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1910 | clean_sspp: |
| 1911 | if (psde && psde->pipe_hw) |
| 1912 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1913 | clean_plane: |
| 1914 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1915 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1916 | return ERR_PTR(ret); |
| 1917 | } |