Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 12 | #include <linux/debugfs.h> |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 13 | #include <uapi/drm/sde_drm.h> |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 14 | |
| 15 | #include "msm_prop.h" |
| 16 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 17 | #include "sde_kms.h" |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 18 | #include "sde_fence.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 19 | #include "sde_formats.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 20 | #include "sde_hw_sspp.h" |
| 21 | |
| 22 | #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) |
| 23 | #define PHASE_STEP_SHIFT 21 |
| 24 | #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) |
| 25 | #define PHASE_RESIDUAL 15 |
| 26 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 27 | #define SHARP_STRENGTH_DEFAULT 32 |
| 28 | #define SHARP_EDGE_THR_DEFAULT 112 |
| 29 | #define SHARP_SMOOTH_THR_DEFAULT 8 |
| 30 | #define SHARP_NOISE_THR_DEFAULT 2 |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 31 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 32 | #define SDE_NAME_SIZE 12 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 33 | |
| 34 | struct sde_plane { |
| 35 | struct drm_plane base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 36 | |
| 37 | int mmu_id; |
| 38 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 39 | struct mutex lock; |
| 40 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 41 | enum sde_sspp pipe; |
| 42 | uint32_t features; /* capabilities from catalog */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 43 | uint32_t nformats; |
| 44 | uint32_t formats[32]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 45 | |
| 46 | struct sde_hw_pipe *pipe_hw; |
| 47 | struct sde_hw_pipe_cfg pipe_cfg; |
| 48 | struct sde_hw_pixel_ext pixel_ext; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 49 | struct sde_hw_sharp_cfg sharp_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 50 | struct sde_hw_scaler3_cfg scaler3_cfg; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 51 | |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 52 | struct sde_csc_cfg csc_cfg; |
| 53 | struct sde_csc_cfg *csc_ptr; |
| 54 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 55 | const struct sde_sspp_sub_blks *pipe_sblk; |
| 56 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 57 | char pipe_name[SDE_NAME_SIZE]; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 58 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 59 | struct msm_property_info property_info; |
| 60 | struct msm_property_data property_data[PLANE_PROP_COUNT]; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 61 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 62 | /* debugfs related stuff */ |
| 63 | struct dentry *debugfs_root; |
| 64 | struct sde_debugfs_regset32 debugfs_src; |
| 65 | struct sde_debugfs_regset32 debugfs_scaler; |
| 66 | struct sde_debugfs_regset32 debugfs_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 67 | }; |
| 68 | #define to_sde_plane(x) container_of(x, struct sde_plane, base) |
| 69 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 70 | static bool sde_plane_enabled(struct drm_plane_state *state) |
| 71 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 72 | return state && state->fb && state->crtc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 73 | } |
| 74 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 75 | /* helper to update a state's sync fence pointer from the property */ |
| 76 | static void _sde_plane_update_sync_fence(struct drm_plane *plane, |
| 77 | struct sde_plane_state *pstate, uint64_t fd) |
| 78 | { |
| 79 | if (!plane || !pstate) |
| 80 | return; |
| 81 | |
| 82 | /* clear previous reference */ |
| 83 | if (pstate->sync_fence) |
| 84 | sde_sync_put(pstate->sync_fence); |
| 85 | |
| 86 | /* get fence pointer for later */ |
| 87 | pstate->sync_fence = sde_sync_get(fd); |
| 88 | |
| 89 | DBG("0x%llX", fd); |
| 90 | } |
| 91 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 92 | int sde_plane_wait_sync_fence(struct drm_plane *plane) |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 93 | { |
| 94 | struct sde_plane_state *pstate; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 95 | void *sync_fence; |
| 96 | long wait_ms; |
| 97 | int ret = -EINVAL; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 98 | |
| 99 | if (!plane) { |
| 100 | DRM_ERROR("Invalid plane\n"); |
| 101 | } else if (!plane->state) { |
| 102 | DRM_ERROR("Invalid plane state\n"); |
| 103 | } else { |
| 104 | pstate = to_sde_plane_state(plane->state); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 105 | sync_fence = pstate->sync_fence; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 106 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 107 | if (sync_fence) { |
| 108 | wait_ms = (long)sde_plane_get_property(pstate, |
| 109 | PLANE_PROP_SYNC_FENCE_TIMEOUT); |
| 110 | |
| 111 | DBG("%s", to_sde_plane(plane)->pipe_name); |
| 112 | ret = sde_sync_wait(sync_fence, wait_ms); |
| 113 | if (!ret) |
| 114 | DBG("signaled"); |
| 115 | else if (ret == -ETIME) |
| 116 | DRM_ERROR("timeout\n"); |
| 117 | else |
| 118 | DRM_ERROR("error %d\n", ret); |
| 119 | } else { |
| 120 | ret = 0; |
| 121 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 122 | } |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 123 | return ret; |
| 124 | } |
| 125 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 126 | static void _sde_plane_set_scanout(struct drm_plane *plane, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 127 | struct sde_plane_state *pstate, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 128 | struct sde_hw_pipe_cfg *pipe_cfg, struct drm_framebuffer *fb) |
| 129 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 130 | struct sde_plane *psde; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 131 | unsigned int shift; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 132 | int i; |
| 133 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 134 | if (!plane || !pstate || !pipe_cfg || !fb) |
| 135 | return; |
| 136 | |
| 137 | psde = to_sde_plane(plane); |
| 138 | |
| 139 | if (psde->pipe_hw && psde->pipe_hw->ops.setup_sourceaddress) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 140 | /* stride */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 141 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 142 | BIT(SDE_DRM_DEINTERLACE)) |
| 143 | shift = 1; |
| 144 | else |
| 145 | shift = 0; |
| 146 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 147 | i = min_t(int, ARRAY_SIZE(fb->pitches), SDE_MAX_PLANES); |
| 148 | while (i) { |
| 149 | --i; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 150 | pipe_cfg->src.ystride[i] = fb->pitches[i] << shift; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | /* address */ |
| 154 | for (i = 0; i < ARRAY_SIZE(pipe_cfg->addr.plane); ++i) |
| 155 | pipe_cfg->addr.plane[i] = msm_framebuffer_iova(fb, |
| 156 | psde->mmu_id, i); |
| 157 | |
| 158 | /* hw driver */ |
| 159 | psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg); |
| 160 | } |
| 161 | } |
| 162 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 163 | static void _sde_plane_setup_scaler3(struct sde_plane *psde, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 164 | uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, |
| 165 | struct sde_hw_scaler3_cfg *scale_cfg, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 166 | const struct sde_format *fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 167 | uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) |
| 168 | { |
| 169 | } |
| 170 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 171 | /** |
| 172 | * _sde_plane_setup_scaler2(): Determine default scaler phase steps/filter type |
| 173 | * @psde: Pointer to SDE plane object |
| 174 | * @src: Source size |
| 175 | * @dst: Destination size |
| 176 | * @phase_steps: Pointer to output array for phase steps |
| 177 | * @filter: Pointer to output array for filter type |
| 178 | * @fmt: Pointer to format definition |
| 179 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 180 | * |
| 181 | * Returns: 0 on success |
| 182 | */ |
| 183 | static int _sde_plane_setup_scaler2(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 184 | uint32_t src, uint32_t dst, uint32_t *phase_steps, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 185 | enum sde_hw_filter *filter, const struct sde_format *fmt, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 186 | uint32_t chroma_subsampling) |
| 187 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 188 | if (!psde || !phase_steps || !filter || !fmt) { |
| 189 | DRM_ERROR("Invalid arguments\n"); |
| 190 | return -EINVAL; |
| 191 | } |
| 192 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 193 | /* calculate phase steps, leave init phase as zero */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 194 | phase_steps[SDE_SSPP_COMP_0] = |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 195 | mult_frac(1 << PHASE_STEP_SHIFT, src, dst); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 196 | phase_steps[SDE_SSPP_COMP_1_2] = |
| 197 | phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling; |
| 198 | phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2]; |
| 199 | phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 200 | |
| 201 | /* calculate scaler config, if necessary */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 202 | if (SDE_FORMAT_IS_YUV(fmt) || src != dst) { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 203 | filter[SDE_SSPP_COMP_3] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 204 | (src <= dst) ? SDE_SCALE_FILTER_BIL : |
| 205 | SDE_SCALE_FILTER_PCMN; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 206 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 207 | if (SDE_FORMAT_IS_YUV(fmt)) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 208 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 209 | filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3]; |
| 210 | } else { |
| 211 | filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3]; |
| 212 | filter[SDE_SSPP_COMP_1_2] = |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 213 | SDE_SCALE_FILTER_NEAREST; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 214 | } |
| 215 | } else { |
| 216 | /* disable scaler */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 217 | DBG("Disable scaler"); |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 218 | filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX; |
| 219 | filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX; |
| 220 | filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 221 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 222 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 223 | } |
| 224 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 225 | /** |
| 226 | * _sde_plane_setup_pixel_ext - determine default pixel extension values |
| 227 | * @psde: Pointer to SDE plane object |
| 228 | * @src: Source size |
| 229 | * @dst: Destination size |
| 230 | * @decimated_src: Source size after decimation, if any |
| 231 | * @phase_steps: Pointer to output array for phase steps |
| 232 | * @out_src: Output array for pixel extension values |
| 233 | * @out_edge1: Output array for pixel extension first edge |
| 234 | * @out_edge2: Output array for pixel extension second edge |
| 235 | * @filter: Pointer to array for filter type |
| 236 | * @fmt: Pointer to format definition |
| 237 | * @chroma_subsampling: Subsampling amount for chroma channel |
| 238 | * @post_compare: Whether to chroma subsampled source size for comparisions |
| 239 | */ |
| 240 | static void _sde_plane_setup_pixel_ext(struct sde_plane *psde, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 241 | uint32_t src, uint32_t dst, uint32_t decimated_src, |
| 242 | uint32_t *phase_steps, uint32_t *out_src, int *out_edge1, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 243 | int *out_edge2, enum sde_hw_filter *filter, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 244 | const struct sde_format *fmt, uint32_t chroma_subsampling, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 245 | bool post_compare) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 246 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 247 | int64_t edge1, edge2, caf; |
| 248 | uint32_t src_work; |
| 249 | int i, tmp; |
| 250 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 251 | if (psde && phase_steps && out_src && out_edge1 && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 252 | out_edge2 && filter && fmt) { |
| 253 | /* handle CAF for YUV formats */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 254 | if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 255 | caf = PHASE_STEP_UNIT_SCALE; |
| 256 | else |
| 257 | caf = 0; |
| 258 | |
| 259 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 260 | src_work = decimated_src; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 261 | if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 262 | src_work /= chroma_subsampling; |
| 263 | if (post_compare) |
| 264 | src = src_work; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 265 | if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 266 | /* unity */ |
| 267 | edge1 = 0; |
| 268 | edge2 = 0; |
| 269 | } else if (dst >= src) { |
| 270 | /* upscale */ |
| 271 | edge1 = (1 << PHASE_RESIDUAL); |
| 272 | edge1 -= caf; |
| 273 | edge2 = (1 << PHASE_RESIDUAL); |
| 274 | edge2 += (dst - 1) * *(phase_steps + i); |
| 275 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 276 | edge2 += caf; |
| 277 | edge2 = -(edge2); |
| 278 | } else { |
| 279 | /* downscale */ |
| 280 | edge1 = 0; |
| 281 | edge2 = (dst - 1) * *(phase_steps + i); |
| 282 | edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE; |
| 283 | edge2 += *(phase_steps + i); |
| 284 | edge2 = -(edge2); |
| 285 | } |
| 286 | |
| 287 | /* only enable CAF for luma plane */ |
| 288 | caf = 0; |
| 289 | |
| 290 | /* populate output arrays */ |
| 291 | *(out_src + i) = src_work; |
| 292 | |
| 293 | /* edge updates taken from __pxl_extn_helper */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 294 | if (edge1 >= 0) { |
| 295 | tmp = (uint32_t)edge1; |
| 296 | tmp >>= PHASE_STEP_SHIFT; |
| 297 | *(out_edge1 + i) = -tmp; |
| 298 | } else { |
| 299 | tmp = (uint32_t)(-edge1); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 300 | *(out_edge1 + i) = |
| 301 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 302 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 303 | } |
| 304 | if (edge2 >= 0) { |
| 305 | tmp = (uint32_t)edge2; |
| 306 | tmp >>= PHASE_STEP_SHIFT; |
| 307 | *(out_edge2 + i) = -tmp; |
| 308 | } else { |
| 309 | tmp = (uint32_t)(-edge2); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 310 | *(out_edge2 + i) = |
| 311 | (tmp + PHASE_STEP_UNIT_SCALE - 1) >> |
| 312 | PHASE_STEP_SHIFT; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 313 | } |
| 314 | } |
| 315 | } |
| 316 | } |
| 317 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 318 | /** |
| 319 | * _sde_plane_verify_blob - verify incoming blob is big enough to contain |
| 320 | * sub-structure |
| 321 | * @blob_ptr: Pointer to start of incoming blob data |
| 322 | * @blob_size: Size of incoming blob data, in bytes |
| 323 | * @sub_ptr: Pointer to start of desired sub-structure |
| 324 | * @sub_size: Required size of sub-structure, in bytes |
| 325 | */ |
| 326 | static int _sde_plane_verify_blob(void *blob_ptr, |
| 327 | size_t blob_size, |
| 328 | void *sub_ptr, |
| 329 | size_t sub_size) |
| 330 | { |
| 331 | /* |
| 332 | * Use the blob size provided by drm to check if there are enough |
| 333 | * bytes from the start of versioned sub-structures to the end of |
| 334 | * blob data: |
| 335 | * |
| 336 | * e.g., |
| 337 | * blob_ptr --> struct blob_data { |
| 338 | * uint32_t version; |
| 339 | * sub_ptr --> struct blob_data_v1 v1; |
| 340 | * sub_ptr + sub_size --> struct blob_stuff more_stuff; |
| 341 | * blob_ptr + blob_size --> }; |
| 342 | * |
| 343 | * It's important to check the actual number of bytes from the start |
| 344 | * of the sub-structure to the end of the blob data, and not just rely |
| 345 | * on something like, |
| 346 | * |
| 347 | * sizeof(blob) - sizeof(blob->version) >= sizeof(sub-struct) |
| 348 | * |
| 349 | * This is because the start of the sub-structure can vary based on |
| 350 | * how the compiler pads the overall structure. |
| 351 | */ |
| 352 | if (blob_ptr && sub_ptr) |
| 353 | /* return zero if end of blob >= end of sub-struct */ |
| 354 | return ((unsigned char *)blob_ptr + blob_size) < |
| 355 | ((unsigned char *)sub_ptr + sub_size); |
| 356 | return -EINVAL; |
| 357 | } |
| 358 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 359 | static void _sde_plane_setup_csc(struct sde_plane *psde, |
| 360 | struct sde_plane_state *pstate, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 361 | const struct sde_format *fmt) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 362 | { |
| 363 | static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = { |
| 364 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 365 | /* S15.16 format */ |
| 366 | 0x00012A00, 0x00000000, 0x00019880, |
| 367 | 0x00012A00, 0xFFFF9B80, 0xFFFF3000, |
| 368 | 0x00012A00, 0x00020480, 0x00000000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 369 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 370 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 371 | { 0xfff0, 0xff80, 0xff80,}, |
| 372 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 373 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 374 | { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 375 | { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 376 | }; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 377 | static const struct sde_csc_cfg sde_csc_NOP = { |
| 378 | { |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 379 | /* identity matrix, S15.16 format */ |
| 380 | 0x10000, 0x00000, 0x00000, |
| 381 | 0x00000, 0x10000, 0x00000, |
| 382 | 0x00000, 0x00000, 0x10000, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 383 | }, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 384 | /* signed bias */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 385 | { 0x0, 0x0, 0x0,}, |
| 386 | { 0x0, 0x0, 0x0,}, |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 387 | /* unsigned clamp */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 388 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 389 | { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,}, |
| 390 | }; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 391 | struct sde_drm_csc *csc = NULL; |
| 392 | size_t csc_size = 0; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 393 | int i; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 394 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 395 | if (!psde || !pstate || !fmt) { |
| 396 | DRM_ERROR("Invalid arguments\n"); |
| 397 | return; |
| 398 | } |
| 399 | if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_csc) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 400 | return; |
| 401 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 402 | /* check for user space override */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 403 | psde->csc_ptr = NULL; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 404 | csc = msm_property_get_blob(&psde->property_info, |
| 405 | pstate->property_blobs, |
| 406 | &csc_size, |
| 407 | PLANE_PROP_CSC); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 408 | if (csc) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 409 | /* user space override */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 410 | memcpy(&psde->csc_cfg, |
| 411 | &sde_csc_NOP, |
| 412 | sizeof(struct sde_csc_cfg)); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 413 | switch (csc->version) { |
| 414 | case SDE_DRM_CSC_V1: |
| 415 | if (!_sde_plane_verify_blob(csc, |
| 416 | csc_size, |
| 417 | &csc->v1, |
| 418 | sizeof(struct sde_drm_csc_v1))) { |
| 419 | for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i) |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 420 | psde->csc_cfg.csc_mv[i] = |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 421 | csc->v1.ctm_coeff[i] >> 16; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 422 | for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) { |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 423 | psde->csc_cfg.csc_pre_bv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 424 | csc->v1.pre_bias[i]; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 425 | psde->csc_cfg.csc_post_bv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 426 | csc->v1.post_bias[i]; |
| 427 | } |
| 428 | for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) { |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 429 | psde->csc_cfg.csc_pre_lv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 430 | csc->v1.pre_clamp[i]; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 431 | psde->csc_cfg.csc_post_lv[i] = |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 432 | csc->v1.post_clamp[i]; |
| 433 | } |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 434 | psde->csc_ptr = &psde->csc_cfg; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 435 | } |
| 436 | break; |
| 437 | default: |
| 438 | break; |
| 439 | } |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 440 | if (!psde->csc_ptr) |
| 441 | DRM_ERROR("invalid csc blob, v%lld\n", csc->version); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 442 | } |
| 443 | |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 444 | if (psde->csc_ptr) |
| 445 | DBG("user blob override for csc"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 446 | /* revert to kernel default */ |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 447 | else if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 448 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L; |
Clarence Ip | b493d76 | 2016-07-19 18:49:10 -0400 | [diff] [blame^] | 449 | else |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 450 | psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_NOP; |
Clarence Ip | 373f859 | 2016-05-26 00:58:42 -0400 | [diff] [blame] | 451 | |
| 452 | psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 453 | } |
| 454 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 455 | static void _sde_plane_setup_scaler(struct sde_plane *psde, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 456 | const struct sde_format *fmt, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 457 | struct sde_plane_state *pstate) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 458 | { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 459 | struct sde_hw_pixel_ext *pe = NULL; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 460 | struct sde_drm_scaler *sc_u = NULL; |
| 461 | struct sde_drm_scaler_v1 *sc_u1 = NULL; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 462 | size_t sc_u_size = 0; |
| 463 | uint32_t chroma_subsmpl_h, chroma_subsmpl_v; |
| 464 | uint32_t tmp; |
| 465 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 466 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 467 | if (!psde || !fmt) |
| 468 | return; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 469 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 470 | pe = &(psde->pixel_ext); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 471 | memset(pe, 0, sizeof(struct sde_hw_pixel_ext)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 472 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 473 | /* get scaler config from user space */ |
Clarence Ip | c3ffec1 | 2016-07-18 19:07:24 -0400 | [diff] [blame] | 474 | if (pstate) |
| 475 | sc_u = msm_property_get_blob(&psde->property_info, |
| 476 | pstate->property_blobs, |
| 477 | &sc_u_size, |
| 478 | PLANE_PROP_SCALER); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 479 | if (sc_u) { |
| 480 | switch (sc_u->version) { |
| 481 | case SDE_DRM_SCALER_V1: |
| 482 | if (!_sde_plane_verify_blob(sc_u, |
| 483 | sc_u_size, |
| 484 | &sc_u->v1, |
| 485 | sizeof(*sc_u1))) |
| 486 | sc_u1 = &sc_u->v1; |
| 487 | break; |
| 488 | default: |
| 489 | DBG("Unrecognized scaler blob v%lld", sc_u->version); |
| 490 | break; |
| 491 | } |
| 492 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 493 | |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 494 | /* decimation */ |
| 495 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_DECIMATE)) { |
| 496 | psde->pipe_cfg.horz_decimation = sc_u1->horz_decimate; |
| 497 | psde->pipe_cfg.vert_decimation = sc_u1->vert_decimate; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 498 | } else { |
| 499 | psde->pipe_cfg.horz_decimation = 0; |
| 500 | psde->pipe_cfg.vert_decimation = 0; |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | /* don't chroma subsample if decimating */ |
| 504 | chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 505 | drm_format_horz_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 506 | chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 507 | drm_format_vert_chroma_subsampling(fmt->base.pixel_format); |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 508 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 509 | /* update scaler */ |
| 510 | if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) { |
| 511 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_3)) |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 512 | DBG("SCALER3 blob detected"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 513 | else |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 514 | _sde_plane_setup_scaler3(psde, |
| 515 | psde->pipe_cfg.src_rect.w, |
| 516 | psde->pipe_cfg.src_rect.h, |
| 517 | psde->pipe_cfg.dst_rect.w, |
| 518 | psde->pipe_cfg.dst_rect.h, |
| 519 | &psde->scaler3_cfg, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 520 | chroma_subsmpl_h, chroma_subsmpl_v); |
| 521 | } else { |
| 522 | /* always calculate basic scaler config */ |
| 523 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_2)) { |
| 524 | /* populate from user space */ |
| 525 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 526 | pe->init_phase_x[i] = sc_u1->init_phase_x[i]; |
| 527 | pe->phase_step_x[i] = sc_u1->phase_step_x[i]; |
| 528 | pe->init_phase_y[i] = sc_u1->init_phase_y[i]; |
| 529 | pe->phase_step_y[i] = sc_u1->phase_step_y[i]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 530 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 531 | pe->horz_filter[i] = sc_u1->horz_filter[i]; |
| 532 | pe->vert_filter[i] = sc_u1->vert_filter[i]; |
| 533 | } |
| 534 | } else { |
| 535 | /* calculate phase steps */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 536 | _sde_plane_setup_scaler2(psde, |
| 537 | psde->pipe_cfg.src_rect.w, |
| 538 | psde->pipe_cfg.dst_rect.w, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 539 | pe->phase_step_x, |
| 540 | pe->horz_filter, fmt, chroma_subsmpl_h); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 541 | _sde_plane_setup_scaler2(psde, |
| 542 | psde->pipe_cfg.src_rect.h, |
| 543 | psde->pipe_cfg.dst_rect.h, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 544 | pe->phase_step_y, |
| 545 | pe->vert_filter, fmt, chroma_subsmpl_v); |
| 546 | } |
| 547 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 548 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 549 | /* update pixel extensions */ |
| 550 | if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_PIX_EXT)) { |
| 551 | /* populate from user space */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 552 | DBG("PIXEXT blob detected"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 553 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 554 | pe->num_ext_pxls_left[i] = sc_u1->lr.num_pxls_start[i]; |
| 555 | pe->num_ext_pxls_right[i] = sc_u1->lr.num_pxls_end[i]; |
| 556 | pe->left_ftch[i] = sc_u1->lr.ftch_start[i]; |
| 557 | pe->right_ftch[i] = sc_u1->lr.ftch_end[i]; |
| 558 | pe->left_rpt[i] = sc_u1->lr.rpt_start[i]; |
| 559 | pe->right_rpt[i] = sc_u1->lr.rpt_end[i]; |
| 560 | pe->roi_w[i] = sc_u1->lr.roi[i]; |
| 561 | |
| 562 | pe->num_ext_pxls_top[i] = sc_u1->tb.num_pxls_start[i]; |
| 563 | pe->num_ext_pxls_btm[i] = sc_u1->tb.num_pxls_end[i]; |
| 564 | pe->top_ftch[i] = sc_u1->tb.ftch_start[i]; |
| 565 | pe->btm_ftch[i] = sc_u1->tb.ftch_end[i]; |
| 566 | pe->top_rpt[i] = sc_u1->tb.rpt_start[i]; |
| 567 | pe->btm_rpt[i] = sc_u1->tb.rpt_end[i]; |
| 568 | pe->roi_h[i] = sc_u1->tb.roi[i]; |
| 569 | } |
| 570 | } else { |
| 571 | /* calculate left/right/top/bottom pixel extensions */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 572 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 573 | psde->pipe_cfg.horz_decimation); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 574 | if (SDE_FORMAT_IS_YUV(fmt)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 575 | tmp &= ~0x1; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 576 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w, |
| 577 | psde->pipe_cfg.dst_rect.w, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 578 | pe->phase_step_x, |
| 579 | pe->roi_w, |
| 580 | pe->num_ext_pxls_left, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 581 | pe->num_ext_pxls_right, pe->horz_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 582 | chroma_subsmpl_h, 0); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 583 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 584 | tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 585 | psde->pipe_cfg.vert_decimation); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 586 | _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h, |
| 587 | psde->pipe_cfg.dst_rect.h, tmp, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 588 | pe->phase_step_y, |
| 589 | pe->roi_h, |
| 590 | pe->num_ext_pxls_top, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 591 | pe->num_ext_pxls_btm, pe->vert_filter, fmt, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 592 | chroma_subsmpl_v, 1); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 593 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 594 | for (i = 0; i < SDE_MAX_PLANES; i++) { |
| 595 | if (pe->num_ext_pxls_left[i] >= 0) |
| 596 | pe->left_rpt[i] = |
| 597 | pe->num_ext_pxls_left[i]; |
| 598 | else |
| 599 | pe->left_ftch[i] = |
| 600 | pe->num_ext_pxls_left[i]; |
| 601 | |
| 602 | if (pe->num_ext_pxls_right[i] >= 0) |
| 603 | pe->right_rpt[i] = |
| 604 | pe->num_ext_pxls_right[i]; |
| 605 | else |
| 606 | pe->right_ftch[i] = |
| 607 | pe->num_ext_pxls_right[i]; |
| 608 | |
| 609 | if (pe->num_ext_pxls_top[i] >= 0) |
| 610 | pe->top_rpt[i] = |
| 611 | pe->num_ext_pxls_top[i]; |
| 612 | else |
| 613 | pe->top_ftch[i] = |
| 614 | pe->num_ext_pxls_top[i]; |
| 615 | |
| 616 | if (pe->num_ext_pxls_btm[i] >= 0) |
| 617 | pe->btm_rpt[i] = |
| 618 | pe->num_ext_pxls_btm[i]; |
| 619 | else |
| 620 | pe->btm_ftch[i] = |
| 621 | pe->num_ext_pxls_btm[i]; |
| 622 | } |
| 623 | } |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 624 | } |
| 625 | |
| 626 | int sde_plane_color_fill(struct drm_plane *plane, |
| 627 | uint32_t color, uint32_t alpha) |
| 628 | { |
| 629 | struct sde_plane *psde; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 630 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 631 | |
| 632 | if (!plane) { |
| 633 | DRM_ERROR("Invalid plane\n"); |
| 634 | return -EINVAL; |
| 635 | } |
| 636 | |
| 637 | psde = to_sde_plane(plane); |
| 638 | if (!psde->pipe_hw) { |
| 639 | DRM_ERROR("Invalid plane h/w pointer\n"); |
| 640 | return -EINVAL; |
| 641 | } |
| 642 | |
| 643 | /* |
| 644 | * select fill format to match user property expectation, |
| 645 | * h/w only supports RGB variants |
| 646 | */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 647 | fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 648 | |
| 649 | /* update sspp */ |
| 650 | if (fmt && psde->pipe_hw->ops.setup_solidfill) { |
| 651 | psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw, |
| 652 | (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); |
| 653 | |
| 654 | /* override scaler/decimation if solid fill */ |
| 655 | psde->pipe_cfg.src_rect.x = 0; |
| 656 | psde->pipe_cfg.src_rect.y = 0; |
| 657 | psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w; |
| 658 | psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h; |
| 659 | |
| 660 | _sde_plane_setup_scaler(psde, fmt, 0); |
| 661 | |
| 662 | if (psde->pipe_hw->ops.setup_format) |
| 663 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
| 664 | fmt, SDE_SSPP_SOLID_FILL); |
| 665 | |
| 666 | if (psde->pipe_hw->ops.setup_rects) |
| 667 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 668 | &psde->pipe_cfg, &psde->pixel_ext); |
| 669 | } |
| 670 | |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | static int _sde_plane_mode_set(struct drm_plane *plane, |
| 675 | struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 676 | int crtc_x, int crtc_y, |
| 677 | unsigned int crtc_w, unsigned int crtc_h, |
| 678 | uint32_t src_x, uint32_t src_y, |
| 679 | uint32_t src_w, uint32_t src_h) |
| 680 | { |
| 681 | struct sde_plane *psde; |
| 682 | struct sde_plane_state *pstate; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 683 | uint32_t nplanes, color_fill; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 684 | uint32_t src_flags; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 685 | const struct sde_format *fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 686 | |
| 687 | DBG(""); |
| 688 | |
| 689 | if (!plane || !plane->state) { |
| 690 | DRM_ERROR("Invalid plane/state\n"); |
| 691 | return -EINVAL; |
| 692 | } |
| 693 | if (!crtc || !fb) { |
| 694 | DRM_ERROR("Invalid crtc/fb\n"); |
| 695 | return -EINVAL; |
| 696 | } |
| 697 | |
| 698 | psde = to_sde_plane(plane); |
| 699 | pstate = to_sde_plane_state(plane->state); |
| 700 | nplanes = drm_format_num_planes(fb->pixel_format); |
| 701 | |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 702 | fmt = to_sde_format(msm_framebuffer_format(fb)); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 703 | |
| 704 | /* src values are in Q16 fixed point, convert to integer */ |
| 705 | src_x = src_x >> 16; |
| 706 | src_y = src_y >> 16; |
| 707 | src_w = src_w >> 16; |
| 708 | src_h = src_h >> 16; |
| 709 | |
| 710 | DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", psde->pipe_name, |
| 711 | fb->base.id, src_x, src_y, src_w, src_h, |
| 712 | crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); |
| 713 | |
| 714 | /* update format configuration */ |
| 715 | memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg)); |
| 716 | src_flags = 0; |
| 717 | |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 718 | psde->pipe_cfg.src.format = fmt; |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 719 | psde->pipe_cfg.src.width = fb->width; |
| 720 | psde->pipe_cfg.src.height = fb->height; |
| 721 | psde->pipe_cfg.src.num_planes = nplanes; |
| 722 | |
| 723 | /* flags */ |
| 724 | DBG("Flags 0x%llX, rotation 0x%llX", |
| 725 | sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG), |
| 726 | sde_plane_get_property(pstate, PLANE_PROP_ROTATION)); |
| 727 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 728 | BIT(DRM_REFLECT_X)) |
| 729 | src_flags |= SDE_SSPP_FLIP_LR; |
| 730 | if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) & |
| 731 | BIT(DRM_REFLECT_Y)) |
| 732 | src_flags |= SDE_SSPP_FLIP_UD; |
| 733 | if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) & |
| 734 | BIT(SDE_DRM_DEINTERLACE)) { |
| 735 | src_h /= 2; |
| 736 | src_y = DIV_ROUND_UP(src_y, 2); |
| 737 | src_y &= ~0x1; |
| 738 | } |
| 739 | |
| 740 | psde->pipe_cfg.src_rect.x = src_x; |
| 741 | psde->pipe_cfg.src_rect.y = src_y; |
| 742 | psde->pipe_cfg.src_rect.w = src_w; |
| 743 | psde->pipe_cfg.src_rect.h = src_h; |
| 744 | |
| 745 | psde->pipe_cfg.dst_rect.x = crtc_x; |
| 746 | psde->pipe_cfg.dst_rect.y = crtc_y; |
| 747 | psde->pipe_cfg.dst_rect.w = crtc_w; |
| 748 | psde->pipe_cfg.dst_rect.h = crtc_h; |
| 749 | |
| 750 | /* get sde pixel format definition */ |
| 751 | fmt = psde->pipe_cfg.src.format; |
| 752 | |
| 753 | /* check for color fill */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 754 | color_fill = (uint32_t)sde_plane_get_property(pstate, |
| 755 | PLANE_PROP_COLOR_FILL); |
| 756 | if (color_fill & BIT(31)) { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 757 | /* force 100% alpha, stop other processing */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 758 | return sde_plane_color_fill(plane, color_fill, 0xFF); |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb); |
| 762 | |
| 763 | _sde_plane_setup_scaler(psde, fmt, pstate); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 764 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 765 | if (psde->pipe_hw->ops.setup_format) |
| 766 | psde->pipe_hw->ops.setup_format(psde->pipe_hw, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 767 | fmt, src_flags); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 768 | if (psde->pipe_hw->ops.setup_rects) |
| 769 | psde->pipe_hw->ops.setup_rects(psde->pipe_hw, |
| 770 | &psde->pipe_cfg, &psde->pixel_ext); |
| 771 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 772 | /* update sharpening */ |
| 773 | psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT; |
| 774 | psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT; |
| 775 | psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT; |
| 776 | psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT; |
| 777 | |
| 778 | if (psde->pipe_hw->ops.setup_sharpening) |
| 779 | psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw, |
| 780 | &psde->sharp_cfg); |
| 781 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 782 | /* update csc */ |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 783 | if (SDE_FORMAT_IS_YUV(fmt)) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 784 | _sde_plane_setup_csc(psde, pstate, fmt); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 785 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 786 | return 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 787 | } |
| 788 | |
| 789 | static int sde_plane_prepare_fb(struct drm_plane *plane, |
| 790 | const struct drm_plane_state *new_state) |
| 791 | { |
| 792 | struct drm_framebuffer *fb = new_state->fb; |
| 793 | struct sde_plane *psde = to_sde_plane(plane); |
| 794 | |
| 795 | if (!new_state->fb) |
| 796 | return 0; |
| 797 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 798 | DBG("%s: FB[%u]", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 799 | return msm_framebuffer_prepare(fb, psde->mmu_id); |
| 800 | } |
| 801 | |
| 802 | static void sde_plane_cleanup_fb(struct drm_plane *plane, |
| 803 | const struct drm_plane_state *old_state) |
| 804 | { |
| 805 | struct drm_framebuffer *fb = old_state->fb; |
| 806 | struct sde_plane *psde = to_sde_plane(plane); |
| 807 | |
| 808 | if (!fb) |
| 809 | return; |
| 810 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 811 | DBG("%s: FB[%u]", psde->pipe_name, fb->base.id); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 812 | msm_framebuffer_cleanup(fb, psde->mmu_id); |
| 813 | } |
| 814 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 815 | static int _sde_plane_atomic_check_fb(struct sde_plane *psde, |
| 816 | struct sde_plane_state *pstate, |
| 817 | struct drm_framebuffer *fb) |
| 818 | { |
| 819 | return 0; |
| 820 | } |
| 821 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 822 | static int sde_plane_atomic_check(struct drm_plane *plane, |
| 823 | struct drm_plane_state *state) |
| 824 | { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 825 | struct sde_plane *psde; |
| 826 | struct sde_plane_state *pstate; |
| 827 | struct drm_plane_state *old_state; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 828 | const struct sde_format *fmt; |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 829 | size_t sc_u_size = 0; |
| 830 | struct sde_drm_scaler *sc_u = NULL; |
| 831 | int ret = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 832 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 833 | uint32_t src_x, src_y; |
| 834 | uint32_t src_w, src_h; |
| 835 | uint32_t deci_w, deci_h, src_deci_w, src_deci_h; |
| 836 | uint32_t src_max_x, src_max_y, src_max_w, src_max_h; |
| 837 | uint32_t upscale_max, downscale_max; |
| 838 | |
| 839 | DBG(); |
| 840 | |
| 841 | if (!plane || !state) { |
| 842 | DRM_ERROR("Invalid plane/state\n"); |
| 843 | ret = -EINVAL; |
| 844 | goto exit; |
| 845 | } |
| 846 | |
| 847 | psde = to_sde_plane(plane); |
| 848 | pstate = to_sde_plane_state(state); |
| 849 | old_state = plane->state; |
| 850 | |
| 851 | if (!psde->pipe_sblk) { |
| 852 | DRM_ERROR("Invalid plane catalog\n"); |
| 853 | ret = -EINVAL; |
| 854 | goto exit; |
| 855 | } |
| 856 | |
| 857 | /* get decimation config from user space */ |
| 858 | deci_w = 0; |
| 859 | deci_h = 0; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 860 | sc_u = msm_property_get_blob(&psde->property_info, |
| 861 | pstate->property_blobs, |
| 862 | &sc_u_size, |
| 863 | PLANE_PROP_SCALER); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 864 | if (sc_u) { |
| 865 | switch (sc_u->version) { |
| 866 | case SDE_DRM_SCALER_V1: |
| 867 | if (!_sde_plane_verify_blob(sc_u, |
| 868 | sc_u_size, |
| 869 | &sc_u->v1, |
| 870 | sizeof(struct sde_drm_scaler_v1))) { |
| 871 | deci_w = sc_u->v1.horz_decimate; |
| 872 | deci_h = sc_u->v1.vert_decimate; |
| 873 | } |
| 874 | break; |
| 875 | default: |
| 876 | DBG("Unrecognized scaler blob v%lld", sc_u->version); |
| 877 | break; |
| 878 | } |
| 879 | } |
| 880 | |
| 881 | /* src values are in Q16 fixed point, convert to integer */ |
| 882 | src_x = state->src_x >> 16; |
| 883 | src_y = state->src_y >> 16; |
| 884 | src_w = state->src_w >> 16; |
| 885 | src_h = state->src_h >> 16; |
| 886 | |
| 887 | src_deci_w = DECIMATED_DIMENSION(src_w, deci_w); |
| 888 | src_deci_h = DECIMATED_DIMENSION(src_h, deci_h); |
| 889 | |
| 890 | src_max_x = 0xFFFF; |
| 891 | src_max_y = 0xFFFF; |
| 892 | src_max_w = 0x3FFF; |
| 893 | src_max_h = 0x3FFF; |
| 894 | upscale_max = psde->pipe_sblk->maxupscale; |
| 895 | downscale_max = psde->pipe_sblk->maxdwnscale; |
| 896 | |
| 897 | /* |
| 898 | * Including checks from mdss |
| 899 | * - mdss_mdp_overlay_req_check() |
| 900 | */ |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 901 | DBG("%s: check (%d -> %d)", psde->pipe_name, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 902 | sde_plane_enabled(old_state), sde_plane_enabled(state)); |
| 903 | |
| 904 | if (sde_plane_enabled(state)) { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 905 | /* determine SDE format definition. State's fb is valid here. */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 906 | fmt = to_sde_format(msm_framebuffer_format(state->fb)); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 907 | |
| 908 | /* don't check for other errors after first failure */ |
| 909 | if (SDE_FORMAT_IS_YUV(fmt) && |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 910 | (!(psde->features & SDE_SSPP_SCALER) || |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 911 | !(psde->features & BIT(SDE_SSPP_CSC)))) { |
Lloyd Atkinson | d49de56 | 2016-05-30 13:23:48 -0400 | [diff] [blame] | 912 | DRM_ERROR("Pipe doesn't support YUV\n"); |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 913 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 914 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 915 | /* verify source size/region */ |
| 916 | } else if (!src_w || !src_h || |
| 917 | (src_w > src_max_w) || (src_h > src_max_h) || |
| 918 | (src_x > src_max_x) || (src_y > src_max_y) || |
| 919 | (src_x + src_w > src_max_x) || |
| 920 | (src_y + src_h > src_max_y)) { |
| 921 | DRM_ERROR("Invalid source (%u, %u) -> (%u, %u)\n", |
| 922 | src_x, src_y, src_x + src_w, |
| 923 | src_y + src_h); |
| 924 | ret = -EINVAL; |
| 925 | |
| 926 | /* require even source for YUV */ |
| 927 | } else if (SDE_FORMAT_IS_YUV(fmt) && |
| 928 | ((src_x & 0x1) || (src_y & 0x1) || |
| 929 | (src_w & 0x1) || (src_h & 0x1))) { |
| 930 | DRM_ERROR("Invalid odd src res/pos for YUV\n"); |
| 931 | ret = -EINVAL; |
| 932 | |
| 933 | /* verify scaler requirements */ |
| 934 | } else if (!(psde->features & SDE_SSPP_SCALER) && |
| 935 | ((src_w != state->crtc_w) || |
| 936 | (src_h != state->crtc_h))) { |
| 937 | DRM_ERROR("Pipe doesn't support scaling %ux%u->%ux%u\n", |
| 938 | src_w, src_h, state->crtc_w, |
| 939 | state->crtc_h); |
| 940 | ret = -EINVAL; |
| 941 | |
| 942 | /* check decimated source width */ |
| 943 | } else if (src_deci_w > psde->pipe_sblk->maxlinewidth) { |
| 944 | DRM_ERROR("Invalid source [W:%u, Wd:%u] > %u\n", |
| 945 | src_w, src_deci_w, |
| 946 | psde->pipe_sblk->maxlinewidth); |
| 947 | ret = -EINVAL; |
| 948 | |
| 949 | /* check max scaler capability */ |
| 950 | } else if (((src_deci_w * upscale_max) < state->crtc_w) || |
| 951 | ((src_deci_h * upscale_max) < state->crtc_h) || |
| 952 | ((state->crtc_w * downscale_max) < src_deci_w) || |
| 953 | ((state->crtc_h * downscale_max) < src_deci_h)) { |
| 954 | DRM_ERROR("Too much scaling requested %ux%u -> %ux%u\n", |
| 955 | src_deci_w, src_deci_h, |
| 956 | state->crtc_w, state->crtc_h); |
| 957 | ret = -EINVAL; |
| 958 | |
| 959 | /* check frame buffer */ |
| 960 | } else if (_sde_plane_atomic_check_fb( |
| 961 | psde, pstate, state->fb)) { |
| 962 | ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 963 | } |
| 964 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 965 | /* check decimation (and bwc/fetch mode) */ |
| 966 | if (!ret && (deci_w || deci_h)) { |
| 967 | if (SDE_FORMAT_IS_UBWC(fmt)) { |
| 968 | DRM_ERROR("No decimation with BWC\n"); |
| 969 | ret = -EINVAL; |
| 970 | } else if ((deci_w > psde->pipe_sblk->maxhdeciexp) || |
| 971 | (deci_h > psde->pipe_sblk->maxvdeciexp)) { |
| 972 | DRM_ERROR("Too much decimation requested\n"); |
| 973 | ret = -EINVAL; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 974 | } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 975 | DRM_ERROR("Decimation requires linear fetch\n"); |
| 976 | ret = -EINVAL; |
| 977 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 978 | } |
| 979 | } |
| 980 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 981 | if (!ret) { |
| 982 | if (sde_plane_enabled(state) && |
| 983 | sde_plane_enabled(old_state)) { |
| 984 | bool full_modeset = false; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 985 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 986 | if (state->fb->pixel_format != |
| 987 | old_state->fb->pixel_format) { |
| 988 | DBG("%s: format change!", psde->pipe_name); |
| 989 | full_modeset = true; |
| 990 | } |
| 991 | if (state->src_w != old_state->src_w || |
| 992 | state->src_h != old_state->src_h) { |
| 993 | DBG("%s: src_w change!", psde->pipe_name); |
| 994 | full_modeset = true; |
| 995 | } |
| 996 | if (to_sde_plane_state(old_state)->pending) { |
| 997 | DBG("%s: still pending!", psde->pipe_name); |
| 998 | full_modeset = true; |
| 999 | } |
Lloyd Atkinson | 6635890 | 2016-03-23 11:58:23 -0400 | [diff] [blame] | 1000 | if (full_modeset) |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1001 | to_sde_plane_state(state)->mode_changed = true; |
Lloyd Atkinson | 6635890 | 2016-03-23 11:58:23 -0400 | [diff] [blame] | 1002 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1003 | } else { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1004 | to_sde_plane_state(state)->mode_changed = true; |
| 1005 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1006 | } |
| 1007 | |
Clarence Ip | dbde983 | 2016-06-26 09:48:36 -0400 | [diff] [blame] | 1008 | exit: |
| 1009 | return ret; |
| 1010 | } |
| 1011 | |
| 1012 | void sde_plane_complete_flip(struct drm_plane *plane) |
| 1013 | { |
| 1014 | if (plane && plane->state) |
| 1015 | to_sde_plane_state(plane->state)->pending = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1016 | } |
| 1017 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1018 | static void sde_plane_atomic_update(struct drm_plane *plane, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1019 | struct drm_plane_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1020 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1021 | struct sde_plane *sde_plane; |
| 1022 | struct drm_plane_state *state; |
| 1023 | struct sde_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1024 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1025 | if (!plane || !plane->state) { |
| 1026 | DRM_ERROR("Invalid plane/state\n"); |
| 1027 | return; |
| 1028 | } |
| 1029 | |
| 1030 | sde_plane = to_sde_plane(plane); |
| 1031 | state = plane->state; |
| 1032 | pstate = to_sde_plane_state(state); |
| 1033 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1034 | DBG("%s: update", sde_plane->pipe_name); |
| 1035 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1036 | if (!sde_plane_enabled(state)) { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1037 | pstate->pending = true; |
| 1038 | } else if (pstate->mode_changed) { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1039 | int ret; |
| 1040 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1041 | pstate->pending = true; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1042 | ret = _sde_plane_mode_set(plane, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1043 | state->crtc, state->fb, |
| 1044 | state->crtc_x, state->crtc_y, |
| 1045 | state->crtc_w, state->crtc_h, |
| 1046 | state->src_x, state->src_y, |
| 1047 | state->src_w, state->src_h); |
| 1048 | /* atomic_check should have ensured that this doesn't fail */ |
| 1049 | WARN_ON(ret < 0); |
| 1050 | } else { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1051 | _sde_plane_set_scanout(plane, pstate, |
| 1052 | &sde_plane->pipe_cfg, state->fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1053 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1054 | } |
| 1055 | |
| 1056 | /* helper to install properties which are common to planes and crtcs */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1057 | static void _sde_plane_install_properties(struct drm_plane *plane) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1058 | { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1059 | static const struct drm_prop_enum_list e_blend_op[] = { |
| 1060 | {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"}, |
| 1061 | {SDE_DRM_BLEND_OP_OPAQUE, "opaque"}, |
| 1062 | {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"}, |
| 1063 | {SDE_DRM_BLEND_OP_COVERAGE, "coverage"} |
| 1064 | }; |
| 1065 | static const struct drm_prop_enum_list e_src_config[] = { |
| 1066 | {SDE_DRM_DEINTERLACE, "deinterlace"} |
| 1067 | }; |
| 1068 | struct sde_plane *psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1069 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1070 | DBG(""); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1071 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1072 | if (!plane || !psde || !psde->pipe_hw || !psde->pipe_sblk) { |
| 1073 | DRM_ERROR("Invalid argument(s)\n"); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1074 | return; |
| 1075 | } |
| 1076 | |
| 1077 | /* range properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1078 | msm_property_install_range(&psde->property_info, "zpos", 0, 255, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1079 | plane->type == DRM_PLANE_TYPE_PRIMARY ? |
| 1080 | STAGE_BASE : STAGE0 + drm_plane_index(plane), |
| 1081 | PLANE_PROP_ZPOS); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1082 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1083 | msm_property_install_range(&psde->property_info, "alpha", 0, 255, 255, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1084 | PLANE_PROP_ALPHA); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1085 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1086 | if (psde->pipe_hw->ops.setup_solidfill) |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1087 | msm_property_install_range(&psde->property_info, "color_fill", |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1088 | 0, 0xFFFFFFFF, 0, |
| 1089 | PLANE_PROP_COLOR_FILL); |
| 1090 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1091 | msm_property_install_range(&psde->property_info, "sync_fence", |
| 1092 | 0, ~0, ~0, PLANE_PROP_SYNC_FENCE); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1093 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1094 | msm_property_install_range(&psde->property_info, "sync_fence_timeout", |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 1095 | 0, ~0, 10000, |
| 1096 | PLANE_PROP_SYNC_FENCE_TIMEOUT); |
| 1097 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1098 | /* standard properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1099 | msm_property_install_rotation(&psde->property_info, |
| 1100 | BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), |
| 1101 | PLANE_PROP_ROTATION); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1102 | |
Clarence Ip | 04ec67d | 2016-05-26 01:16:15 -0400 | [diff] [blame] | 1103 | /* enum/bitmask properties */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1104 | msm_property_install_enum(&psde->property_info, "blend_op", 0, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1105 | e_blend_op, ARRAY_SIZE(e_blend_op), |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1106 | PLANE_PROP_BLEND_OP); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1107 | msm_property_install_enum(&psde->property_info, "src_config", 1, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1108 | e_src_config, ARRAY_SIZE(e_src_config), |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1109 | PLANE_PROP_SRC_CONFIG); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1110 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1111 | /* blob properties */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1112 | if (psde->features & SDE_SSPP_SCALER) |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1113 | msm_property_install_blob(&psde->property_info, "scaler", 0, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1114 | PLANE_PROP_SCALER); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1115 | if (psde->features & BIT(SDE_SSPP_CSC)) { |
| 1116 | msm_property_install_blob(&psde->property_info, "csc", 0, |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1117 | PLANE_PROP_CSC); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1118 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1119 | } |
| 1120 | |
| 1121 | static int sde_plane_atomic_set_property(struct drm_plane *plane, |
| 1122 | struct drm_plane_state *state, struct drm_property *property, |
| 1123 | uint64_t val) |
| 1124 | { |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1125 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1126 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1127 | int idx, ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1128 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1129 | DBG(""); |
| 1130 | |
| 1131 | if (!plane) { |
| 1132 | DRM_ERROR("Invalid plane\n"); |
| 1133 | } else if (!state) { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1134 | DRM_ERROR("Invalid state\n"); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1135 | } else { |
| 1136 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1137 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1138 | ret = msm_property_atomic_set(&psde->property_info, |
| 1139 | pstate->property_values, pstate->property_blobs, |
| 1140 | property, val); |
| 1141 | if (!ret) { |
| 1142 | idx = msm_property_index(&psde->property_info, |
| 1143 | property); |
| 1144 | if (idx == PLANE_PROP_SYNC_FENCE) |
| 1145 | _sde_plane_update_sync_fence(plane, |
| 1146 | pstate, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1147 | } |
| 1148 | } |
| 1149 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1150 | return ret; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | static int sde_plane_set_property(struct drm_plane *plane, |
| 1154 | struct drm_property *property, uint64_t val) |
| 1155 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1156 | DBG(""); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1157 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1158 | return sde_plane_atomic_set_property(plane, |
| 1159 | plane->state, property, val); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1160 | } |
| 1161 | |
| 1162 | static int sde_plane_atomic_get_property(struct drm_plane *plane, |
| 1163 | const struct drm_plane_state *state, |
| 1164 | struct drm_property *property, uint64_t *val) |
| 1165 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1166 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1167 | struct sde_plane_state *pstate; |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1168 | int ret = -EINVAL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1169 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1170 | DBG(""); |
| 1171 | |
| 1172 | if (!plane) { |
| 1173 | DRM_ERROR("Invalid plane\n"); |
| 1174 | } else if (!state) { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1175 | DRM_ERROR("Invalid state\n"); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1176 | } else { |
| 1177 | psde = to_sde_plane(plane); |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1178 | pstate = to_sde_plane_state(state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1179 | ret = msm_property_atomic_get(&psde->property_info, |
| 1180 | pstate->property_values, pstate->property_blobs, |
| 1181 | property, val); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1182 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1183 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1184 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1185 | } |
| 1186 | |
| 1187 | static void sde_plane_destroy(struct drm_plane *plane) |
| 1188 | { |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1189 | struct sde_plane *psde; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1190 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1191 | DBG(""); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1192 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1193 | if (plane) { |
| 1194 | psde = to_sde_plane(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1195 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1196 | debugfs_remove_recursive(psde->debugfs_root); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1197 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1198 | msm_property_destroy(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1199 | mutex_destroy(&psde->lock); |
| 1200 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1201 | drm_plane_helper_disable(plane); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1202 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1203 | /* this will destroy the states as well */ |
| 1204 | drm_plane_cleanup(plane); |
| 1205 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1206 | if (psde->pipe_hw) |
| 1207 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1208 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1209 | kfree(psde); |
| 1210 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1211 | } |
| 1212 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1213 | static void sde_plane_destroy_state(struct drm_plane *plane, |
| 1214 | struct drm_plane_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1215 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1216 | struct sde_plane *psde; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1217 | struct sde_plane_state *pstate; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1218 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1219 | if (!plane || !state) { |
| 1220 | DRM_ERROR("Invalid plane/state\n"); |
| 1221 | return; |
| 1222 | } |
| 1223 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1224 | psde = to_sde_plane(plane); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1225 | pstate = to_sde_plane_state(state); |
| 1226 | |
| 1227 | DBG(""); |
| 1228 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1229 | /* remove ref count for frame buffers */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1230 | if (state->fb) |
| 1231 | drm_framebuffer_unreference(state->fb); |
| 1232 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1233 | /* remove ref count for fence */ |
| 1234 | if (pstate->sync_fence) |
| 1235 | sde_sync_put(pstate->sync_fence); |
| 1236 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1237 | /* destroy value helper */ |
| 1238 | msm_property_destroy_state(&psde->property_info, pstate, |
| 1239 | pstate->property_values, pstate->property_blobs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1240 | } |
| 1241 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1242 | static struct drm_plane_state * |
| 1243 | sde_plane_duplicate_state(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1244 | { |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1245 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1246 | struct sde_plane_state *pstate; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1247 | struct sde_plane_state *old_state; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1248 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1249 | if (!plane || !plane->state) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1250 | return NULL; |
| 1251 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1252 | old_state = to_sde_plane_state(plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1253 | psde = to_sde_plane(plane); |
| 1254 | pstate = msm_property_alloc_state(&psde->property_info); |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1255 | if (!pstate) |
| 1256 | return NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1257 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1258 | DBG(""); |
| 1259 | |
| 1260 | /* duplicate value helper */ |
| 1261 | msm_property_duplicate_state(&psde->property_info, old_state, pstate, |
| 1262 | pstate->property_values, pstate->property_blobs); |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1263 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1264 | /* add ref count for frame buffer */ |
| 1265 | if (pstate->base.fb) |
| 1266 | drm_framebuffer_reference(pstate->base.fb); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1267 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1268 | /* add ref count for fence */ |
| 1269 | if (pstate->sync_fence) { |
| 1270 | pstate->sync_fence = 0; |
| 1271 | _sde_plane_update_sync_fence(plane, pstate, pstate-> |
| 1272 | property_values[PLANE_PROP_SYNC_FENCE]); |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1273 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1274 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1275 | pstate->mode_changed = false; |
| 1276 | pstate->pending = false; |
| 1277 | |
| 1278 | return &pstate->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1279 | } |
| 1280 | |
| 1281 | static void sde_plane_reset(struct drm_plane *plane) |
| 1282 | { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1283 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1284 | struct sde_plane_state *pstate; |
| 1285 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1286 | if (!plane) { |
| 1287 | DRM_ERROR("Invalid plane\n"); |
| 1288 | return; |
| 1289 | } |
| 1290 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1291 | psde = to_sde_plane(plane); |
| 1292 | DBG("%s", psde->pipe_name); |
| 1293 | |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1294 | /* remove previous state, if present */ |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1295 | if (plane->state) { |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1296 | sde_plane_destroy_state(plane, plane->state); |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1297 | plane->state = 0; |
Clarence Ip | ae4e60c | 2016-06-26 22:44:04 -0400 | [diff] [blame] | 1298 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1299 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1300 | pstate = msm_property_alloc_state(&psde->property_info); |
| 1301 | if (!pstate) |
| 1302 | return; |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1303 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1304 | /* reset value helper */ |
| 1305 | msm_property_reset_state(&psde->property_info, pstate, |
| 1306 | pstate->property_values, pstate->property_blobs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1307 | |
| 1308 | pstate->base.plane = plane; |
| 1309 | |
| 1310 | plane->state = &pstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1311 | } |
| 1312 | |
| 1313 | static const struct drm_plane_funcs sde_plane_funcs = { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1314 | .update_plane = drm_atomic_helper_update_plane, |
| 1315 | .disable_plane = drm_atomic_helper_disable_plane, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1316 | .destroy = sde_plane_destroy, |
| 1317 | .set_property = sde_plane_set_property, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1318 | .atomic_set_property = sde_plane_atomic_set_property, |
| 1319 | .atomic_get_property = sde_plane_atomic_get_property, |
| 1320 | .reset = sde_plane_reset, |
| 1321 | .atomic_duplicate_state = sde_plane_duplicate_state, |
| 1322 | .atomic_destroy_state = sde_plane_destroy_state, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1323 | }; |
| 1324 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1325 | static const struct drm_plane_helper_funcs sde_plane_helper_funcs = { |
| 1326 | .prepare_fb = sde_plane_prepare_fb, |
| 1327 | .cleanup_fb = sde_plane_cleanup_fb, |
| 1328 | .atomic_check = sde_plane_atomic_check, |
| 1329 | .atomic_update = sde_plane_atomic_update, |
| 1330 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1331 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1332 | enum sde_sspp sde_plane_pipe(struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1333 | { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1334 | struct sde_plane *sde_plane = to_sde_plane(plane); |
| 1335 | |
| 1336 | return sde_plane->pipe; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1337 | } |
| 1338 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1339 | static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms) |
| 1340 | { |
| 1341 | const struct sde_sspp_sub_blks *sblk = 0; |
| 1342 | const struct sde_sspp_cfg *cfg = 0; |
| 1343 | |
| 1344 | if (psde && psde->pipe_hw) |
| 1345 | cfg = psde->pipe_hw->cap; |
| 1346 | if (cfg) |
| 1347 | sblk = cfg->sblk; |
| 1348 | |
| 1349 | if (kms && sblk) { |
| 1350 | /* create overall sub-directory for the pipe */ |
| 1351 | psde->debugfs_root = |
| 1352 | debugfs_create_dir(psde->pipe_name, |
| 1353 | sde_debugfs_get_root(kms)); |
| 1354 | if (psde->debugfs_root) { |
| 1355 | /* don't error check these */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1356 | debugfs_create_x32("features", 0644, |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1357 | psde->debugfs_root, &psde->features); |
| 1358 | |
| 1359 | /* add register dump support */ |
| 1360 | sde_debugfs_setup_regset32(&psde->debugfs_src, |
| 1361 | sblk->src_blk.base + cfg->base, |
| 1362 | sblk->src_blk.len, |
| 1363 | kms->mmio); |
| 1364 | sde_debugfs_create_regset32("src_blk", 0444, |
| 1365 | psde->debugfs_root, &psde->debugfs_src); |
| 1366 | |
| 1367 | sde_debugfs_setup_regset32(&psde->debugfs_scaler, |
| 1368 | sblk->scaler_blk.base + cfg->base, |
| 1369 | sblk->scaler_blk.len, |
| 1370 | kms->mmio); |
| 1371 | sde_debugfs_create_regset32("scaler_blk", 0444, |
| 1372 | psde->debugfs_root, |
| 1373 | &psde->debugfs_scaler); |
| 1374 | |
| 1375 | sde_debugfs_setup_regset32(&psde->debugfs_csc, |
| 1376 | sblk->csc_blk.base + cfg->base, |
| 1377 | sblk->csc_blk.len, |
| 1378 | kms->mmio); |
| 1379 | sde_debugfs_create_regset32("csc_blk", 0444, |
| 1380 | psde->debugfs_root, &psde->debugfs_csc); |
| 1381 | } |
| 1382 | } |
| 1383 | } |
| 1384 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1385 | /* initialize plane */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1386 | struct drm_plane *sde_plane_init(struct drm_device *dev, |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1387 | uint32_t pipe, bool primary_plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1388 | { |
| 1389 | struct drm_plane *plane = NULL; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1390 | struct sde_plane *psde; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1391 | struct msm_drm_private *priv; |
| 1392 | struct sde_kms *kms; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1393 | enum drm_plane_type type; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1394 | int ret = -EINVAL; |
| 1395 | |
| 1396 | if (!dev) { |
| 1397 | DRM_ERROR("[%u]Device is NULL\n", pipe); |
| 1398 | goto exit; |
| 1399 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1400 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1401 | priv = dev->dev_private; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1402 | if (!priv) { |
| 1403 | DRM_ERROR("[%u]Private data is NULL\n", pipe); |
| 1404 | goto exit; |
| 1405 | } |
| 1406 | |
| 1407 | if (!priv->kms) { |
| 1408 | DRM_ERROR("[%u]Invalid KMS reference\n", pipe); |
| 1409 | goto exit; |
| 1410 | } |
| 1411 | kms = to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1412 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1413 | if (!kms->catalog) { |
| 1414 | DRM_ERROR("[%u]Invalid catalog reference\n", pipe); |
| 1415 | goto exit; |
| 1416 | } |
| 1417 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1418 | /* create and zero local structure */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1419 | psde = kzalloc(sizeof(*psde), GFP_KERNEL); |
| 1420 | if (!psde) { |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1421 | DRM_ERROR("[%u]Failed to allocate local plane struct\n", pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1422 | ret = -ENOMEM; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1423 | goto exit; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1424 | } |
| 1425 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1426 | /* cache local stuff for later */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1427 | plane = &psde->base; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1428 | psde->pipe = pipe; |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1429 | psde->mmu_id = kms->mmu_id; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1430 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1431 | /* initialize underlying h/w driver */ |
| 1432 | psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog); |
| 1433 | if (IS_ERR(psde->pipe_hw)) { |
| 1434 | DRM_ERROR("[%u]SSPP init failed\n", pipe); |
| 1435 | ret = PTR_ERR(psde->pipe_hw); |
| 1436 | goto clean_plane; |
| 1437 | } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) { |
| 1438 | DRM_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); |
| 1439 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1440 | } |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1441 | |
| 1442 | /* cache features mask for later */ |
| 1443 | psde->features = psde->pipe_hw->cap->features; |
| 1444 | psde->pipe_sblk = psde->pipe_hw->cap->sblk; |
| 1445 | |
| 1446 | /* add plane to DRM framework */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 1447 | psde->nformats = sde_populate_formats(psde->formats, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1448 | ARRAY_SIZE(psde->formats), |
| 1449 | !(psde->features & BIT(SDE_SSPP_CSC)) || |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1450 | !(psde->features & SDE_SSPP_SCALER)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1451 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1452 | if (!psde->nformats) { |
| 1453 | DRM_ERROR("[%u]No valid formats for plane\n", pipe); |
| 1454 | goto clean_sspp; |
| 1455 | } |
| 1456 | |
| 1457 | if (psde->features & BIT(SDE_SSPP_CURSOR)) |
| 1458 | type = DRM_PLANE_TYPE_CURSOR; |
| 1459 | else if (primary_plane) |
| 1460 | type = DRM_PLANE_TYPE_PRIMARY; |
| 1461 | else |
| 1462 | type = DRM_PLANE_TYPE_OVERLAY; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1463 | ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs, |
| 1464 | psde->formats, psde->nformats, |
| 1465 | type); |
| 1466 | if (ret) |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1467 | goto clean_sspp; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1468 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1469 | /* success! finalize initialization */ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1470 | drm_plane_helper_add(plane, &sde_plane_helper_funcs); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1471 | |
Clarence Ip | aa0faf4 | 2016-05-30 12:07:48 -0400 | [diff] [blame] | 1472 | msm_property_init(&psde->property_info, &plane->base, dev, |
| 1473 | priv->plane_property, psde->property_data, |
| 1474 | PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT, |
| 1475 | sizeof(struct sde_plane_state)); |
| 1476 | |
| 1477 | _sde_plane_install_properties(plane); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1478 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1479 | /* save user friendly pipe name for later */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 1480 | snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id); |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1481 | |
Clarence Ip | 730e719 | 2016-06-26 22:45:09 -0400 | [diff] [blame] | 1482 | mutex_init(&psde->lock); |
| 1483 | |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1484 | _sde_plane_init_debugfs(psde, kms); |
| 1485 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1486 | DRM_INFO("[%u]Successfully created %s\n", pipe, psde->pipe_name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1487 | return plane; |
| 1488 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 1489 | clean_sspp: |
| 1490 | if (psde && psde->pipe_hw) |
| 1491 | sde_hw_sspp_destroy(psde->pipe_hw); |
| 1492 | clean_plane: |
| 1493 | kfree(psde); |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 1494 | exit: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1495 | return ERR_PTR(ret); |
| 1496 | } |