blob: 424d88d91acc9688f564ae05807bf1943b7ae4c1 [file] [log] [blame]
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Clarence Ip4ce59322016-06-26 22:27:51 -040012#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040013#include <uapi/drm/sde_drm.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040014
15#include "msm_prop.h"
16
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070017#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040018#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040019#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040020#include "sde_hw_sspp.h"
21
22#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
23#define PHASE_STEP_SHIFT 21
24#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
25#define PHASE_RESIDUAL 15
26
Clarence Ipe78efb72016-06-24 18:35:21 -040027#define SHARP_STRENGTH_DEFAULT 32
28#define SHARP_EDGE_THR_DEFAULT 112
29#define SHARP_SMOOTH_THR_DEFAULT 8
30#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040031
Clarence Ip5e2a9222016-06-26 22:38:24 -040032#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070033
34struct sde_plane {
35 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040036
37 int mmu_id;
38
Clarence Ip730e7192016-06-26 22:45:09 -040039 struct mutex lock;
40
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040041 enum sde_sspp pipe;
42 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070043 uint32_t nformats;
44 uint32_t formats[32];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040045
46 struct sde_hw_pipe *pipe_hw;
47 struct sde_hw_pipe_cfg pipe_cfg;
48 struct sde_hw_pixel_ext pixel_ext;
Clarence Ipe78efb72016-06-24 18:35:21 -040049 struct sde_hw_sharp_cfg sharp_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -040050 struct sde_hw_scaler3_cfg scaler3_cfg;
Clarence Ip4ce59322016-06-26 22:27:51 -040051
Clarence Ip373f8592016-05-26 00:58:42 -040052 struct sde_csc_cfg csc_cfg;
53 struct sde_csc_cfg *csc_ptr;
54
Clarence Ip4c1d9772016-06-26 09:35:38 -040055 const struct sde_sspp_sub_blks *pipe_sblk;
56
Clarence Ip5e2a9222016-06-26 22:38:24 -040057 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -040058
Clarence Ipaa0faf42016-05-30 12:07:48 -040059 struct msm_property_info property_info;
60 struct msm_property_data property_data[PLANE_PROP_COUNT];
Clarence Ip730e7192016-06-26 22:45:09 -040061
Clarence Ip4ce59322016-06-26 22:27:51 -040062 /* debugfs related stuff */
63 struct dentry *debugfs_root;
64 struct sde_debugfs_regset32 debugfs_src;
65 struct sde_debugfs_regset32 debugfs_scaler;
66 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070067};
68#define to_sde_plane(x) container_of(x, struct sde_plane, base)
69
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040070static bool sde_plane_enabled(struct drm_plane_state *state)
71{
Clarence Ipdbde9832016-06-26 09:48:36 -040072 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040073}
74
Clarence Ipae4e60c2016-06-26 22:44:04 -040075/* helper to update a state's sync fence pointer from the property */
76static void _sde_plane_update_sync_fence(struct drm_plane *plane,
77 struct sde_plane_state *pstate, uint64_t fd)
78{
79 if (!plane || !pstate)
80 return;
81
82 /* clear previous reference */
83 if (pstate->sync_fence)
84 sde_sync_put(pstate->sync_fence);
85
86 /* get fence pointer for later */
87 pstate->sync_fence = sde_sync_get(fd);
88
89 DBG("0x%llX", fd);
90}
91
Clarence Ipcb410d42016-06-26 22:52:33 -040092int sde_plane_wait_sync_fence(struct drm_plane *plane)
Clarence Ipae4e60c2016-06-26 22:44:04 -040093{
94 struct sde_plane_state *pstate;
Clarence Ipcb410d42016-06-26 22:52:33 -040095 void *sync_fence;
96 long wait_ms;
97 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -040098
99 if (!plane) {
100 DRM_ERROR("Invalid plane\n");
101 } else if (!plane->state) {
102 DRM_ERROR("Invalid plane state\n");
103 } else {
104 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -0400105 sync_fence = pstate->sync_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400106
Clarence Ipcb410d42016-06-26 22:52:33 -0400107 if (sync_fence) {
108 wait_ms = (long)sde_plane_get_property(pstate,
109 PLANE_PROP_SYNC_FENCE_TIMEOUT);
110
111 DBG("%s", to_sde_plane(plane)->pipe_name);
112 ret = sde_sync_wait(sync_fence, wait_ms);
113 if (!ret)
114 DBG("signaled");
115 else if (ret == -ETIME)
116 DRM_ERROR("timeout\n");
117 else
118 DRM_ERROR("error %d\n", ret);
119 } else {
120 ret = 0;
121 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400122 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400123 return ret;
124}
125
Clarence Ipe78efb72016-06-24 18:35:21 -0400126static void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400127 struct sde_plane_state *pstate,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400128 struct sde_hw_pipe_cfg *pipe_cfg, struct drm_framebuffer *fb)
129{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400130 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400131 unsigned int shift;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400132 int i;
133
Clarence Ipae4e60c2016-06-26 22:44:04 -0400134 if (!plane || !pstate || !pipe_cfg || !fb)
135 return;
136
137 psde = to_sde_plane(plane);
138
139 if (psde->pipe_hw && psde->pipe_hw->ops.setup_sourceaddress) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400140 /* stride */
Clarence Ip4c1d9772016-06-26 09:35:38 -0400141 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
Clarence Ip5e2a9222016-06-26 22:38:24 -0400142 BIT(SDE_DRM_DEINTERLACE))
143 shift = 1;
144 else
145 shift = 0;
146
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400147 i = min_t(int, ARRAY_SIZE(fb->pitches), SDE_MAX_PLANES);
148 while (i) {
149 --i;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400150 pipe_cfg->src.ystride[i] = fb->pitches[i] << shift;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400151 }
152
153 /* address */
154 for (i = 0; i < ARRAY_SIZE(pipe_cfg->addr.plane); ++i)
155 pipe_cfg->addr.plane[i] = msm_framebuffer_iova(fb,
156 psde->mmu_id, i);
157
158 /* hw driver */
159 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
160 }
161}
162
Clarence Ipcb410d42016-06-26 22:52:33 -0400163static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400164 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
165 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400166 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400167 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
168{
169}
170
Clarence Ipcb410d42016-06-26 22:52:33 -0400171/**
172 * _sde_plane_setup_scaler2(): Determine default scaler phase steps/filter type
173 * @psde: Pointer to SDE plane object
174 * @src: Source size
175 * @dst: Destination size
176 * @phase_steps: Pointer to output array for phase steps
177 * @filter: Pointer to output array for filter type
178 * @fmt: Pointer to format definition
179 * @chroma_subsampling: Subsampling amount for chroma channel
180 *
181 * Returns: 0 on success
182 */
183static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400184 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400185 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400186 uint32_t chroma_subsampling)
187{
Clarence Ipcb410d42016-06-26 22:52:33 -0400188 if (!psde || !phase_steps || !filter || !fmt) {
189 DRM_ERROR("Invalid arguments\n");
190 return -EINVAL;
191 }
192
Clarence Ip4c1d9772016-06-26 09:35:38 -0400193 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400194 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400195 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400196 phase_steps[SDE_SSPP_COMP_1_2] =
197 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
198 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
199 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400200
201 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400202 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400203 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400204 (src <= dst) ? SDE_SCALE_FILTER_BIL :
205 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400206
Clarence Ipdbde9832016-06-26 09:48:36 -0400207 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400208 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400209 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
210 } else {
211 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
212 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400213 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400214 }
215 } else {
216 /* disable scaler */
Clarence Ipcb410d42016-06-26 22:52:33 -0400217 DBG("Disable scaler");
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400218 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
219 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
220 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400221 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400222 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400223}
224
Clarence Ipcb410d42016-06-26 22:52:33 -0400225/**
226 * _sde_plane_setup_pixel_ext - determine default pixel extension values
227 * @psde: Pointer to SDE plane object
228 * @src: Source size
229 * @dst: Destination size
230 * @decimated_src: Source size after decimation, if any
231 * @phase_steps: Pointer to output array for phase steps
232 * @out_src: Output array for pixel extension values
233 * @out_edge1: Output array for pixel extension first edge
234 * @out_edge2: Output array for pixel extension second edge
235 * @filter: Pointer to array for filter type
236 * @fmt: Pointer to format definition
237 * @chroma_subsampling: Subsampling amount for chroma channel
238 * @post_compare: Whether to chroma subsampled source size for comparisions
239 */
240static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400241 uint32_t src, uint32_t dst, uint32_t decimated_src,
242 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400243 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400244 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400245 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400246{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400247 int64_t edge1, edge2, caf;
248 uint32_t src_work;
249 int i, tmp;
250
Clarence Ipcb410d42016-06-26 22:52:33 -0400251 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400252 out_edge2 && filter && fmt) {
253 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400254 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400255 caf = PHASE_STEP_UNIT_SCALE;
256 else
257 caf = 0;
258
259 for (i = 0; i < SDE_MAX_PLANES; i++) {
260 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400261 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400262 src_work /= chroma_subsampling;
263 if (post_compare)
264 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400265 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400266 /* unity */
267 edge1 = 0;
268 edge2 = 0;
269 } else if (dst >= src) {
270 /* upscale */
271 edge1 = (1 << PHASE_RESIDUAL);
272 edge1 -= caf;
273 edge2 = (1 << PHASE_RESIDUAL);
274 edge2 += (dst - 1) * *(phase_steps + i);
275 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
276 edge2 += caf;
277 edge2 = -(edge2);
278 } else {
279 /* downscale */
280 edge1 = 0;
281 edge2 = (dst - 1) * *(phase_steps + i);
282 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
283 edge2 += *(phase_steps + i);
284 edge2 = -(edge2);
285 }
286
287 /* only enable CAF for luma plane */
288 caf = 0;
289
290 /* populate output arrays */
291 *(out_src + i) = src_work;
292
293 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400294 if (edge1 >= 0) {
295 tmp = (uint32_t)edge1;
296 tmp >>= PHASE_STEP_SHIFT;
297 *(out_edge1 + i) = -tmp;
298 } else {
299 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400300 *(out_edge1 + i) =
301 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
302 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400303 }
304 if (edge2 >= 0) {
305 tmp = (uint32_t)edge2;
306 tmp >>= PHASE_STEP_SHIFT;
307 *(out_edge2 + i) = -tmp;
308 } else {
309 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400310 *(out_edge2 + i) =
311 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
312 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400313 }
314 }
315 }
316}
317
Clarence Ip5e2a9222016-06-26 22:38:24 -0400318/**
319 * _sde_plane_verify_blob - verify incoming blob is big enough to contain
320 * sub-structure
321 * @blob_ptr: Pointer to start of incoming blob data
322 * @blob_size: Size of incoming blob data, in bytes
323 * @sub_ptr: Pointer to start of desired sub-structure
324 * @sub_size: Required size of sub-structure, in bytes
325 */
326static int _sde_plane_verify_blob(void *blob_ptr,
327 size_t blob_size,
328 void *sub_ptr,
329 size_t sub_size)
330{
331 /*
332 * Use the blob size provided by drm to check if there are enough
333 * bytes from the start of versioned sub-structures to the end of
334 * blob data:
335 *
336 * e.g.,
337 * blob_ptr --> struct blob_data {
338 * uint32_t version;
339 * sub_ptr --> struct blob_data_v1 v1;
340 * sub_ptr + sub_size --> struct blob_stuff more_stuff;
341 * blob_ptr + blob_size --> };
342 *
343 * It's important to check the actual number of bytes from the start
344 * of the sub-structure to the end of the blob data, and not just rely
345 * on something like,
346 *
347 * sizeof(blob) - sizeof(blob->version) >= sizeof(sub-struct)
348 *
349 * This is because the start of the sub-structure can vary based on
350 * how the compiler pads the overall structure.
351 */
352 if (blob_ptr && sub_ptr)
353 /* return zero if end of blob >= end of sub-struct */
354 return ((unsigned char *)blob_ptr + blob_size) <
355 ((unsigned char *)sub_ptr + sub_size);
356 return -EINVAL;
357}
358
Clarence Ipe78efb72016-06-24 18:35:21 -0400359static void _sde_plane_setup_csc(struct sde_plane *psde,
360 struct sde_plane_state *pstate,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400361 const struct sde_format *fmt)
Clarence Ipe78efb72016-06-24 18:35:21 -0400362{
363 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
364 {
Clarence Ip373f8592016-05-26 00:58:42 -0400365 /* S15.16 format */
366 0x00012A00, 0x00000000, 0x00019880,
367 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
368 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400369 },
Clarence Ip373f8592016-05-26 00:58:42 -0400370 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400371 { 0xfff0, 0xff80, 0xff80,},
372 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400373 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400374 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400375 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400376 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400377 static const struct sde_csc_cfg sde_csc_NOP = {
378 {
Clarence Ip373f8592016-05-26 00:58:42 -0400379 /* identity matrix, S15.16 format */
380 0x10000, 0x00000, 0x00000,
381 0x00000, 0x10000, 0x00000,
382 0x00000, 0x00000, 0x10000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400383 },
Clarence Ip373f8592016-05-26 00:58:42 -0400384 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400385 { 0x0, 0x0, 0x0,},
386 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400387 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400388 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,},
389 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,},
390 };
Clarence Ip5e2a9222016-06-26 22:38:24 -0400391 struct sde_drm_csc *csc = NULL;
392 size_t csc_size = 0;
Clarence Ipb493d762016-07-19 18:49:10 -0400393 int i;
Clarence Ipe78efb72016-06-24 18:35:21 -0400394
Clarence Ipaa0faf42016-05-30 12:07:48 -0400395 if (!psde || !pstate || !fmt) {
396 DRM_ERROR("Invalid arguments\n");
397 return;
398 }
399 if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_csc)
Clarence Ipe78efb72016-06-24 18:35:21 -0400400 return;
401
Clarence Ip5e2a9222016-06-26 22:38:24 -0400402 /* check for user space override */
Clarence Ipb493d762016-07-19 18:49:10 -0400403 psde->csc_ptr = NULL;
Clarence Ipaa0faf42016-05-30 12:07:48 -0400404 csc = msm_property_get_blob(&psde->property_info,
405 pstate->property_blobs,
406 &csc_size,
407 PLANE_PROP_CSC);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400408 if (csc) {
Clarence Ip5e2a9222016-06-26 22:38:24 -0400409 /* user space override */
Clarence Ipb493d762016-07-19 18:49:10 -0400410 memcpy(&psde->csc_cfg,
411 &sde_csc_NOP,
412 sizeof(struct sde_csc_cfg));
Clarence Ip5e2a9222016-06-26 22:38:24 -0400413 switch (csc->version) {
414 case SDE_DRM_CSC_V1:
415 if (!_sde_plane_verify_blob(csc,
416 csc_size,
417 &csc->v1,
418 sizeof(struct sde_drm_csc_v1))) {
419 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
Clarence Ipb493d762016-07-19 18:49:10 -0400420 psde->csc_cfg.csc_mv[i] =
Clarence Ip373f8592016-05-26 00:58:42 -0400421 csc->v1.ctm_coeff[i] >> 16;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400422 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
Clarence Ipb493d762016-07-19 18:49:10 -0400423 psde->csc_cfg.csc_pre_bv[i] =
Clarence Ip5e2a9222016-06-26 22:38:24 -0400424 csc->v1.pre_bias[i];
Clarence Ipb493d762016-07-19 18:49:10 -0400425 psde->csc_cfg.csc_post_bv[i] =
Clarence Ip5e2a9222016-06-26 22:38:24 -0400426 csc->v1.post_bias[i];
427 }
428 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
Clarence Ipb493d762016-07-19 18:49:10 -0400429 psde->csc_cfg.csc_pre_lv[i] =
Clarence Ip5e2a9222016-06-26 22:38:24 -0400430 csc->v1.pre_clamp[i];
Clarence Ipb493d762016-07-19 18:49:10 -0400431 psde->csc_cfg.csc_post_lv[i] =
Clarence Ip5e2a9222016-06-26 22:38:24 -0400432 csc->v1.post_clamp[i];
433 }
Clarence Ipb493d762016-07-19 18:49:10 -0400434 psde->csc_ptr = &psde->csc_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400435 }
436 break;
437 default:
438 break;
439 }
Clarence Ipb493d762016-07-19 18:49:10 -0400440 if (!psde->csc_ptr)
441 DRM_ERROR("invalid csc blob, v%lld\n", csc->version);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400442 }
443
Clarence Ipb493d762016-07-19 18:49:10 -0400444 if (psde->csc_ptr)
445 DBG("user blob override for csc");
Clarence Ip5e2a9222016-06-26 22:38:24 -0400446 /* revert to kernel default */
Clarence Ipb493d762016-07-19 18:49:10 -0400447 else if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip373f8592016-05-26 00:58:42 -0400448 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ipb493d762016-07-19 18:49:10 -0400449 else
Clarence Ip373f8592016-05-26 00:58:42 -0400450 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_NOP;
Clarence Ip373f8592016-05-26 00:58:42 -0400451
452 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
Clarence Ipe78efb72016-06-24 18:35:21 -0400453}
454
Clarence Ipcb410d42016-06-26 22:52:33 -0400455static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400456 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400457 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700458{
Clarence Ipcb410d42016-06-26 22:52:33 -0400459 struct sde_hw_pixel_ext *pe = NULL;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400460 struct sde_drm_scaler *sc_u = NULL;
461 struct sde_drm_scaler_v1 *sc_u1 = NULL;
Clarence Ipcb410d42016-06-26 22:52:33 -0400462 size_t sc_u_size = 0;
463 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
464 uint32_t tmp;
465 int i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400466
Clarence Ipcb410d42016-06-26 22:52:33 -0400467 if (!psde || !fmt)
468 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400469
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400470 pe = &(psde->pixel_ext);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400471 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400472
Clarence Ip5e2a9222016-06-26 22:38:24 -0400473 /* get scaler config from user space */
Clarence Ipc3ffec12016-07-18 19:07:24 -0400474 if (pstate)
475 sc_u = msm_property_get_blob(&psde->property_info,
476 pstate->property_blobs,
477 &sc_u_size,
478 PLANE_PROP_SCALER);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400479 if (sc_u) {
480 switch (sc_u->version) {
481 case SDE_DRM_SCALER_V1:
482 if (!_sde_plane_verify_blob(sc_u,
483 sc_u_size,
484 &sc_u->v1,
485 sizeof(*sc_u1)))
486 sc_u1 = &sc_u->v1;
487 break;
488 default:
489 DBG("Unrecognized scaler blob v%lld", sc_u->version);
490 break;
491 }
492 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400493
Clarence Ip04ec67d2016-05-26 01:16:15 -0400494 /* decimation */
495 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_DECIMATE)) {
496 psde->pipe_cfg.horz_decimation = sc_u1->horz_decimate;
497 psde->pipe_cfg.vert_decimation = sc_u1->vert_decimate;
Clarence Ipcb410d42016-06-26 22:52:33 -0400498 } else {
499 psde->pipe_cfg.horz_decimation = 0;
500 psde->pipe_cfg.vert_decimation = 0;
Clarence Ip04ec67d2016-05-26 01:16:15 -0400501 }
502
503 /* don't chroma subsample if decimating */
504 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400505 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400506 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400507 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400508
Clarence Ip5e2a9222016-06-26 22:38:24 -0400509 /* update scaler */
510 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
511 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_3))
Clarence Ipcb410d42016-06-26 22:52:33 -0400512 DBG("SCALER3 blob detected");
Clarence Ip5e2a9222016-06-26 22:38:24 -0400513 else
Clarence Ipcb410d42016-06-26 22:52:33 -0400514 _sde_plane_setup_scaler3(psde,
515 psde->pipe_cfg.src_rect.w,
516 psde->pipe_cfg.src_rect.h,
517 psde->pipe_cfg.dst_rect.w,
518 psde->pipe_cfg.dst_rect.h,
519 &psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400520 chroma_subsmpl_h, chroma_subsmpl_v);
521 } else {
522 /* always calculate basic scaler config */
523 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_2)) {
524 /* populate from user space */
525 for (i = 0; i < SDE_MAX_PLANES; i++) {
526 pe->init_phase_x[i] = sc_u1->init_phase_x[i];
527 pe->phase_step_x[i] = sc_u1->phase_step_x[i];
528 pe->init_phase_y[i] = sc_u1->init_phase_y[i];
529 pe->phase_step_y[i] = sc_u1->phase_step_y[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400530
Clarence Ip5e2a9222016-06-26 22:38:24 -0400531 pe->horz_filter[i] = sc_u1->horz_filter[i];
532 pe->vert_filter[i] = sc_u1->vert_filter[i];
533 }
534 } else {
535 /* calculate phase steps */
Clarence Ipcb410d42016-06-26 22:52:33 -0400536 _sde_plane_setup_scaler2(psde,
537 psde->pipe_cfg.src_rect.w,
538 psde->pipe_cfg.dst_rect.w,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400539 pe->phase_step_x,
540 pe->horz_filter, fmt, chroma_subsmpl_h);
Clarence Ipcb410d42016-06-26 22:52:33 -0400541 _sde_plane_setup_scaler2(psde,
542 psde->pipe_cfg.src_rect.h,
543 psde->pipe_cfg.dst_rect.h,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400544 pe->phase_step_y,
545 pe->vert_filter, fmt, chroma_subsmpl_v);
546 }
547 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400548
Clarence Ip5e2a9222016-06-26 22:38:24 -0400549 /* update pixel extensions */
550 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_PIX_EXT)) {
551 /* populate from user space */
Clarence Ipcb410d42016-06-26 22:52:33 -0400552 DBG("PIXEXT blob detected");
Clarence Ip5e2a9222016-06-26 22:38:24 -0400553 for (i = 0; i < SDE_MAX_PLANES; i++) {
554 pe->num_ext_pxls_left[i] = sc_u1->lr.num_pxls_start[i];
555 pe->num_ext_pxls_right[i] = sc_u1->lr.num_pxls_end[i];
556 pe->left_ftch[i] = sc_u1->lr.ftch_start[i];
557 pe->right_ftch[i] = sc_u1->lr.ftch_end[i];
558 pe->left_rpt[i] = sc_u1->lr.rpt_start[i];
559 pe->right_rpt[i] = sc_u1->lr.rpt_end[i];
560 pe->roi_w[i] = sc_u1->lr.roi[i];
561
562 pe->num_ext_pxls_top[i] = sc_u1->tb.num_pxls_start[i];
563 pe->num_ext_pxls_btm[i] = sc_u1->tb.num_pxls_end[i];
564 pe->top_ftch[i] = sc_u1->tb.ftch_start[i];
565 pe->btm_ftch[i] = sc_u1->tb.ftch_end[i];
566 pe->top_rpt[i] = sc_u1->tb.rpt_start[i];
567 pe->btm_rpt[i] = sc_u1->tb.rpt_end[i];
568 pe->roi_h[i] = sc_u1->tb.roi[i];
569 }
570 } else {
571 /* calculate left/right/top/bottom pixel extensions */
Clarence Ipcb410d42016-06-26 22:52:33 -0400572 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400573 psde->pipe_cfg.horz_decimation);
Clarence Ipdbde9832016-06-26 09:48:36 -0400574 if (SDE_FORMAT_IS_YUV(fmt))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400575 tmp &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400576 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
577 psde->pipe_cfg.dst_rect.w, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400578 pe->phase_step_x,
579 pe->roi_w,
580 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400581 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400582 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400583
Clarence Ipcb410d42016-06-26 22:52:33 -0400584 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400585 psde->pipe_cfg.vert_decimation);
Clarence Ipcb410d42016-06-26 22:52:33 -0400586 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
587 psde->pipe_cfg.dst_rect.h, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400588 pe->phase_step_y,
589 pe->roi_h,
590 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400591 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400592 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400593
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400594 for (i = 0; i < SDE_MAX_PLANES; i++) {
595 if (pe->num_ext_pxls_left[i] >= 0)
596 pe->left_rpt[i] =
597 pe->num_ext_pxls_left[i];
598 else
599 pe->left_ftch[i] =
600 pe->num_ext_pxls_left[i];
601
602 if (pe->num_ext_pxls_right[i] >= 0)
603 pe->right_rpt[i] =
604 pe->num_ext_pxls_right[i];
605 else
606 pe->right_ftch[i] =
607 pe->num_ext_pxls_right[i];
608
609 if (pe->num_ext_pxls_top[i] >= 0)
610 pe->top_rpt[i] =
611 pe->num_ext_pxls_top[i];
612 else
613 pe->top_ftch[i] =
614 pe->num_ext_pxls_top[i];
615
616 if (pe->num_ext_pxls_btm[i] >= 0)
617 pe->btm_rpt[i] =
618 pe->num_ext_pxls_btm[i];
619 else
620 pe->btm_ftch[i] =
621 pe->num_ext_pxls_btm[i];
622 }
623 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400624}
625
626int sde_plane_color_fill(struct drm_plane *plane,
627 uint32_t color, uint32_t alpha)
628{
629 struct sde_plane *psde;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400630 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400631
632 if (!plane) {
633 DRM_ERROR("Invalid plane\n");
634 return -EINVAL;
635 }
636
637 psde = to_sde_plane(plane);
638 if (!psde->pipe_hw) {
639 DRM_ERROR("Invalid plane h/w pointer\n");
640 return -EINVAL;
641 }
642
643 /*
644 * select fill format to match user property expectation,
645 * h/w only supports RGB variants
646 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400647 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400648
649 /* update sspp */
650 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
651 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
652 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
653
654 /* override scaler/decimation if solid fill */
655 psde->pipe_cfg.src_rect.x = 0;
656 psde->pipe_cfg.src_rect.y = 0;
657 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
658 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
659
660 _sde_plane_setup_scaler(psde, fmt, 0);
661
662 if (psde->pipe_hw->ops.setup_format)
663 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
664 fmt, SDE_SSPP_SOLID_FILL);
665
666 if (psde->pipe_hw->ops.setup_rects)
667 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
668 &psde->pipe_cfg, &psde->pixel_ext);
669 }
670
671 return 0;
672}
673
674static int _sde_plane_mode_set(struct drm_plane *plane,
675 struct drm_crtc *crtc, struct drm_framebuffer *fb,
676 int crtc_x, int crtc_y,
677 unsigned int crtc_w, unsigned int crtc_h,
678 uint32_t src_x, uint32_t src_y,
679 uint32_t src_w, uint32_t src_h)
680{
681 struct sde_plane *psde;
682 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400683 uint32_t nplanes, color_fill;
Clarence Ipcb410d42016-06-26 22:52:33 -0400684 uint32_t src_flags;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400685 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400686
687 DBG("");
688
689 if (!plane || !plane->state) {
690 DRM_ERROR("Invalid plane/state\n");
691 return -EINVAL;
692 }
693 if (!crtc || !fb) {
694 DRM_ERROR("Invalid crtc/fb\n");
695 return -EINVAL;
696 }
697
698 psde = to_sde_plane(plane);
699 pstate = to_sde_plane_state(plane->state);
700 nplanes = drm_format_num_planes(fb->pixel_format);
701
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400702 fmt = to_sde_format(msm_framebuffer_format(fb));
Clarence Ipcb410d42016-06-26 22:52:33 -0400703
704 /* src values are in Q16 fixed point, convert to integer */
705 src_x = src_x >> 16;
706 src_y = src_y >> 16;
707 src_w = src_w >> 16;
708 src_h = src_h >> 16;
709
710 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", psde->pipe_name,
711 fb->base.id, src_x, src_y, src_w, src_h,
712 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
713
714 /* update format configuration */
715 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
716 src_flags = 0;
717
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400718 psde->pipe_cfg.src.format = fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400719 psde->pipe_cfg.src.width = fb->width;
720 psde->pipe_cfg.src.height = fb->height;
721 psde->pipe_cfg.src.num_planes = nplanes;
722
723 /* flags */
724 DBG("Flags 0x%llX, rotation 0x%llX",
725 sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG),
726 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
727 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
728 BIT(DRM_REFLECT_X))
729 src_flags |= SDE_SSPP_FLIP_LR;
730 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
731 BIT(DRM_REFLECT_Y))
732 src_flags |= SDE_SSPP_FLIP_UD;
733 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
734 BIT(SDE_DRM_DEINTERLACE)) {
735 src_h /= 2;
736 src_y = DIV_ROUND_UP(src_y, 2);
737 src_y &= ~0x1;
738 }
739
740 psde->pipe_cfg.src_rect.x = src_x;
741 psde->pipe_cfg.src_rect.y = src_y;
742 psde->pipe_cfg.src_rect.w = src_w;
743 psde->pipe_cfg.src_rect.h = src_h;
744
745 psde->pipe_cfg.dst_rect.x = crtc_x;
746 psde->pipe_cfg.dst_rect.y = crtc_y;
747 psde->pipe_cfg.dst_rect.w = crtc_w;
748 psde->pipe_cfg.dst_rect.h = crtc_h;
749
750 /* get sde pixel format definition */
751 fmt = psde->pipe_cfg.src.format;
752
753 /* check for color fill */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400754 color_fill = (uint32_t)sde_plane_get_property(pstate,
755 PLANE_PROP_COLOR_FILL);
756 if (color_fill & BIT(31)) {
Clarence Ipcb410d42016-06-26 22:52:33 -0400757 /* force 100% alpha, stop other processing */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400758 return sde_plane_color_fill(plane, color_fill, 0xFF);
Clarence Ipcb410d42016-06-26 22:52:33 -0400759 }
760
761 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
762
763 _sde_plane_setup_scaler(psde, fmt, pstate);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400764
Clarence Ip4c1d9772016-06-26 09:35:38 -0400765 if (psde->pipe_hw->ops.setup_format)
766 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
Clarence Ipcb410d42016-06-26 22:52:33 -0400767 fmt, src_flags);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400768 if (psde->pipe_hw->ops.setup_rects)
769 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
770 &psde->pipe_cfg, &psde->pixel_ext);
771
Clarence Ipe78efb72016-06-24 18:35:21 -0400772 /* update sharpening */
773 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
774 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
775 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
776 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
777
778 if (psde->pipe_hw->ops.setup_sharpening)
779 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
780 &psde->sharp_cfg);
781
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400782 /* update csc */
Clarence Ipdbde9832016-06-26 09:48:36 -0400783 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ipe78efb72016-06-24 18:35:21 -0400784 _sde_plane_setup_csc(psde, pstate, fmt);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400785
Clarence Ip5e2a9222016-06-26 22:38:24 -0400786 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400787}
788
789static int sde_plane_prepare_fb(struct drm_plane *plane,
790 const struct drm_plane_state *new_state)
791{
792 struct drm_framebuffer *fb = new_state->fb;
793 struct sde_plane *psde = to_sde_plane(plane);
794
795 if (!new_state->fb)
796 return 0;
797
Clarence Ipae4e60c2016-06-26 22:44:04 -0400798 DBG("%s: FB[%u]", psde->pipe_name, fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400799 return msm_framebuffer_prepare(fb, psde->mmu_id);
800}
801
802static void sde_plane_cleanup_fb(struct drm_plane *plane,
803 const struct drm_plane_state *old_state)
804{
805 struct drm_framebuffer *fb = old_state->fb;
806 struct sde_plane *psde = to_sde_plane(plane);
807
808 if (!fb)
809 return;
810
Clarence Ipae4e60c2016-06-26 22:44:04 -0400811 DBG("%s: FB[%u]", psde->pipe_name, fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400812 msm_framebuffer_cleanup(fb, psde->mmu_id);
813}
814
Clarence Ipdbde9832016-06-26 09:48:36 -0400815static int _sde_plane_atomic_check_fb(struct sde_plane *psde,
816 struct sde_plane_state *pstate,
817 struct drm_framebuffer *fb)
818{
819 return 0;
820}
821
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400822static int sde_plane_atomic_check(struct drm_plane *plane,
823 struct drm_plane_state *state)
824{
Clarence Ipdbde9832016-06-26 09:48:36 -0400825 struct sde_plane *psde;
826 struct sde_plane_state *pstate;
827 struct drm_plane_state *old_state;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400828 const struct sde_format *fmt;
Clarence Ipdbde9832016-06-26 09:48:36 -0400829 size_t sc_u_size = 0;
830 struct sde_drm_scaler *sc_u = NULL;
831 int ret = 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400832
Clarence Ipdbde9832016-06-26 09:48:36 -0400833 uint32_t src_x, src_y;
834 uint32_t src_w, src_h;
835 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
836 uint32_t src_max_x, src_max_y, src_max_w, src_max_h;
837 uint32_t upscale_max, downscale_max;
838
839 DBG();
840
841 if (!plane || !state) {
842 DRM_ERROR("Invalid plane/state\n");
843 ret = -EINVAL;
844 goto exit;
845 }
846
847 psde = to_sde_plane(plane);
848 pstate = to_sde_plane_state(state);
849 old_state = plane->state;
850
851 if (!psde->pipe_sblk) {
852 DRM_ERROR("Invalid plane catalog\n");
853 ret = -EINVAL;
854 goto exit;
855 }
856
857 /* get decimation config from user space */
858 deci_w = 0;
859 deci_h = 0;
Clarence Ipaa0faf42016-05-30 12:07:48 -0400860 sc_u = msm_property_get_blob(&psde->property_info,
861 pstate->property_blobs,
862 &sc_u_size,
863 PLANE_PROP_SCALER);
Clarence Ipdbde9832016-06-26 09:48:36 -0400864 if (sc_u) {
865 switch (sc_u->version) {
866 case SDE_DRM_SCALER_V1:
867 if (!_sde_plane_verify_blob(sc_u,
868 sc_u_size,
869 &sc_u->v1,
870 sizeof(struct sde_drm_scaler_v1))) {
871 deci_w = sc_u->v1.horz_decimate;
872 deci_h = sc_u->v1.vert_decimate;
873 }
874 break;
875 default:
876 DBG("Unrecognized scaler blob v%lld", sc_u->version);
877 break;
878 }
879 }
880
881 /* src values are in Q16 fixed point, convert to integer */
882 src_x = state->src_x >> 16;
883 src_y = state->src_y >> 16;
884 src_w = state->src_w >> 16;
885 src_h = state->src_h >> 16;
886
887 src_deci_w = DECIMATED_DIMENSION(src_w, deci_w);
888 src_deci_h = DECIMATED_DIMENSION(src_h, deci_h);
889
890 src_max_x = 0xFFFF;
891 src_max_y = 0xFFFF;
892 src_max_w = 0x3FFF;
893 src_max_h = 0x3FFF;
894 upscale_max = psde->pipe_sblk->maxupscale;
895 downscale_max = psde->pipe_sblk->maxdwnscale;
896
897 /*
898 * Including checks from mdss
899 * - mdss_mdp_overlay_req_check()
900 */
Clarence Ip4ce59322016-06-26 22:27:51 -0400901 DBG("%s: check (%d -> %d)", psde->pipe_name,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400902 sde_plane_enabled(old_state), sde_plane_enabled(state));
903
904 if (sde_plane_enabled(state)) {
Clarence Ipdbde9832016-06-26 09:48:36 -0400905 /* determine SDE format definition. State's fb is valid here. */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400906 fmt = to_sde_format(msm_framebuffer_format(state->fb));
Clarence Ipdbde9832016-06-26 09:48:36 -0400907
908 /* don't check for other errors after first failure */
909 if (SDE_FORMAT_IS_YUV(fmt) &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400910 (!(psde->features & SDE_SSPP_SCALER) ||
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400911 !(psde->features & BIT(SDE_SSPP_CSC)))) {
Lloyd Atkinsond49de562016-05-30 13:23:48 -0400912 DRM_ERROR("Pipe doesn't support YUV\n");
Clarence Ipdbde9832016-06-26 09:48:36 -0400913 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400914
Clarence Ipdbde9832016-06-26 09:48:36 -0400915 /* verify source size/region */
916 } else if (!src_w || !src_h ||
917 (src_w > src_max_w) || (src_h > src_max_h) ||
918 (src_x > src_max_x) || (src_y > src_max_y) ||
919 (src_x + src_w > src_max_x) ||
920 (src_y + src_h > src_max_y)) {
921 DRM_ERROR("Invalid source (%u, %u) -> (%u, %u)\n",
922 src_x, src_y, src_x + src_w,
923 src_y + src_h);
924 ret = -EINVAL;
925
926 /* require even source for YUV */
927 } else if (SDE_FORMAT_IS_YUV(fmt) &&
928 ((src_x & 0x1) || (src_y & 0x1) ||
929 (src_w & 0x1) || (src_h & 0x1))) {
930 DRM_ERROR("Invalid odd src res/pos for YUV\n");
931 ret = -EINVAL;
932
933 /* verify scaler requirements */
934 } else if (!(psde->features & SDE_SSPP_SCALER) &&
935 ((src_w != state->crtc_w) ||
936 (src_h != state->crtc_h))) {
937 DRM_ERROR("Pipe doesn't support scaling %ux%u->%ux%u\n",
938 src_w, src_h, state->crtc_w,
939 state->crtc_h);
940 ret = -EINVAL;
941
942 /* check decimated source width */
943 } else if (src_deci_w > psde->pipe_sblk->maxlinewidth) {
944 DRM_ERROR("Invalid source [W:%u, Wd:%u] > %u\n",
945 src_w, src_deci_w,
946 psde->pipe_sblk->maxlinewidth);
947 ret = -EINVAL;
948
949 /* check max scaler capability */
950 } else if (((src_deci_w * upscale_max) < state->crtc_w) ||
951 ((src_deci_h * upscale_max) < state->crtc_h) ||
952 ((state->crtc_w * downscale_max) < src_deci_w) ||
953 ((state->crtc_h * downscale_max) < src_deci_h)) {
954 DRM_ERROR("Too much scaling requested %ux%u -> %ux%u\n",
955 src_deci_w, src_deci_h,
956 state->crtc_w, state->crtc_h);
957 ret = -EINVAL;
958
959 /* check frame buffer */
960 } else if (_sde_plane_atomic_check_fb(
961 psde, pstate, state->fb)) {
962 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400963 }
964
Clarence Ipdbde9832016-06-26 09:48:36 -0400965 /* check decimation (and bwc/fetch mode) */
966 if (!ret && (deci_w || deci_h)) {
967 if (SDE_FORMAT_IS_UBWC(fmt)) {
968 DRM_ERROR("No decimation with BWC\n");
969 ret = -EINVAL;
970 } else if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
971 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
972 DRM_ERROR("Too much decimation requested\n");
973 ret = -EINVAL;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400974 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ipdbde9832016-06-26 09:48:36 -0400975 DRM_ERROR("Decimation requires linear fetch\n");
976 ret = -EINVAL;
977 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400978 }
979 }
980
Clarence Ipdbde9832016-06-26 09:48:36 -0400981 if (!ret) {
982 if (sde_plane_enabled(state) &&
983 sde_plane_enabled(old_state)) {
984 bool full_modeset = false;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400985
Clarence Ipdbde9832016-06-26 09:48:36 -0400986 if (state->fb->pixel_format !=
987 old_state->fb->pixel_format) {
988 DBG("%s: format change!", psde->pipe_name);
989 full_modeset = true;
990 }
991 if (state->src_w != old_state->src_w ||
992 state->src_h != old_state->src_h) {
993 DBG("%s: src_w change!", psde->pipe_name);
994 full_modeset = true;
995 }
996 if (to_sde_plane_state(old_state)->pending) {
997 DBG("%s: still pending!", psde->pipe_name);
998 full_modeset = true;
999 }
Lloyd Atkinson66358902016-03-23 11:58:23 -04001000 if (full_modeset)
Clarence Ipdbde9832016-06-26 09:48:36 -04001001 to_sde_plane_state(state)->mode_changed = true;
Lloyd Atkinson66358902016-03-23 11:58:23 -04001002
Clarence Ipdbde9832016-06-26 09:48:36 -04001003 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001004 to_sde_plane_state(state)->mode_changed = true;
1005 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001006 }
1007
Clarence Ipdbde9832016-06-26 09:48:36 -04001008exit:
1009 return ret;
1010}
1011
1012void sde_plane_complete_flip(struct drm_plane *plane)
1013{
1014 if (plane && plane->state)
1015 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001016}
1017
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001018static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001019 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001020{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001021 struct sde_plane *sde_plane;
1022 struct drm_plane_state *state;
1023 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001024
Clarence Ip5e2a9222016-06-26 22:38:24 -04001025 if (!plane || !plane->state) {
1026 DRM_ERROR("Invalid plane/state\n");
1027 return;
1028 }
1029
1030 sde_plane = to_sde_plane(plane);
1031 state = plane->state;
1032 pstate = to_sde_plane_state(state);
1033
Clarence Ipae4e60c2016-06-26 22:44:04 -04001034 DBG("%s: update", sde_plane->pipe_name);
1035
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001036 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001037 pstate->pending = true;
1038 } else if (pstate->mode_changed) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001039 int ret;
1040
Clarence Ip5e2a9222016-06-26 22:38:24 -04001041 pstate->pending = true;
Clarence Ipe78efb72016-06-24 18:35:21 -04001042 ret = _sde_plane_mode_set(plane,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001043 state->crtc, state->fb,
1044 state->crtc_x, state->crtc_y,
1045 state->crtc_w, state->crtc_h,
1046 state->src_x, state->src_y,
1047 state->src_w, state->src_h);
1048 /* atomic_check should have ensured that this doesn't fail */
1049 WARN_ON(ret < 0);
1050 } else {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001051 _sde_plane_set_scanout(plane, pstate,
1052 &sde_plane->pipe_cfg, state->fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001053 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001054}
1055
1056/* helper to install properties which are common to planes and crtcs */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001057static void _sde_plane_install_properties(struct drm_plane *plane)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001058{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001059 static const struct drm_prop_enum_list e_blend_op[] = {
1060 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1061 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1062 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1063 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1064 };
1065 static const struct drm_prop_enum_list e_src_config[] = {
1066 {SDE_DRM_DEINTERLACE, "deinterlace"}
1067 };
1068 struct sde_plane *psde = to_sde_plane(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001069
Clarence Ip4ce59322016-06-26 22:27:51 -04001070 DBG("");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001071
Clarence Ipaa0faf42016-05-30 12:07:48 -04001072 if (!plane || !psde || !psde->pipe_hw || !psde->pipe_sblk) {
1073 DRM_ERROR("Invalid argument(s)\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001074 return;
1075 }
1076
1077 /* range properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001078 msm_property_install_range(&psde->property_info, "zpos", 0, 255,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001079 plane->type == DRM_PLANE_TYPE_PRIMARY ?
1080 STAGE_BASE : STAGE0 + drm_plane_index(plane),
1081 PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001082
Clarence Ipaa0faf42016-05-30 12:07:48 -04001083 msm_property_install_range(&psde->property_info, "alpha", 0, 255, 255,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001084 PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001085
Clarence Ipcb410d42016-06-26 22:52:33 -04001086 if (psde->pipe_hw->ops.setup_solidfill)
Clarence Ipaa0faf42016-05-30 12:07:48 -04001087 msm_property_install_range(&psde->property_info, "color_fill",
Clarence Ipcb410d42016-06-26 22:52:33 -04001088 0, 0xFFFFFFFF, 0,
1089 PLANE_PROP_COLOR_FILL);
1090
Clarence Ipaa0faf42016-05-30 12:07:48 -04001091 msm_property_install_range(&psde->property_info, "sync_fence",
1092 0, ~0, ~0, PLANE_PROP_SYNC_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001093
Clarence Ipaa0faf42016-05-30 12:07:48 -04001094 msm_property_install_range(&psde->property_info, "sync_fence_timeout",
Clarence Ipcb410d42016-06-26 22:52:33 -04001095 0, ~0, 10000,
1096 PLANE_PROP_SYNC_FENCE_TIMEOUT);
1097
Clarence Ip5e2a9222016-06-26 22:38:24 -04001098 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001099 msm_property_install_rotation(&psde->property_info,
1100 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y),
1101 PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001102
Clarence Ip04ec67d2016-05-26 01:16:15 -04001103 /* enum/bitmask properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001104 msm_property_install_enum(&psde->property_info, "blend_op", 0,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001105 e_blend_op, ARRAY_SIZE(e_blend_op),
Clarence Ipae4e60c2016-06-26 22:44:04 -04001106 PLANE_PROP_BLEND_OP);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001107 msm_property_install_enum(&psde->property_info, "src_config", 1,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001108 e_src_config, ARRAY_SIZE(e_src_config),
Clarence Ipae4e60c2016-06-26 22:44:04 -04001109 PLANE_PROP_SRC_CONFIG);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001110
Clarence Ipe78efb72016-06-24 18:35:21 -04001111 /* blob properties */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001112 if (psde->features & SDE_SSPP_SCALER)
Clarence Ipaa0faf42016-05-30 12:07:48 -04001113 msm_property_install_blob(&psde->property_info, "scaler", 0,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001114 PLANE_PROP_SCALER);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001115 if (psde->features & BIT(SDE_SSPP_CSC)) {
1116 msm_property_install_blob(&psde->property_info, "csc", 0,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001117 PLANE_PROP_CSC);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001118 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001119}
1120
1121static int sde_plane_atomic_set_property(struct drm_plane *plane,
1122 struct drm_plane_state *state, struct drm_property *property,
1123 uint64_t val)
1124{
Clarence Ip730e7192016-06-26 22:45:09 -04001125 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001126 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001127 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001128
Clarence Ipaa0faf42016-05-30 12:07:48 -04001129 DBG("");
1130
1131 if (!plane) {
1132 DRM_ERROR("Invalid plane\n");
1133 } else if (!state) {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001134 DRM_ERROR("Invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001135 } else {
1136 psde = to_sde_plane(plane);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001137 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001138 ret = msm_property_atomic_set(&psde->property_info,
1139 pstate->property_values, pstate->property_blobs,
1140 property, val);
1141 if (!ret) {
1142 idx = msm_property_index(&psde->property_info,
1143 property);
1144 if (idx == PLANE_PROP_SYNC_FENCE)
1145 _sde_plane_update_sync_fence(plane,
1146 pstate, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001147 }
1148 }
1149
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001150 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001151}
1152
1153static int sde_plane_set_property(struct drm_plane *plane,
1154 struct drm_property *property, uint64_t val)
1155{
Clarence Ip4ce59322016-06-26 22:27:51 -04001156 DBG("");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001157
Clarence Ipae4e60c2016-06-26 22:44:04 -04001158 return sde_plane_atomic_set_property(plane,
1159 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001160}
1161
1162static int sde_plane_atomic_get_property(struct drm_plane *plane,
1163 const struct drm_plane_state *state,
1164 struct drm_property *property, uint64_t *val)
1165{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001166 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001167 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001168 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001169
Clarence Ipaa0faf42016-05-30 12:07:48 -04001170 DBG("");
1171
1172 if (!plane) {
1173 DRM_ERROR("Invalid plane\n");
1174 } else if (!state) {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001175 DRM_ERROR("Invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001176 } else {
1177 psde = to_sde_plane(plane);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001178 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001179 ret = msm_property_atomic_get(&psde->property_info,
1180 pstate->property_values, pstate->property_blobs,
1181 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001182 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001183
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001184 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001185}
1186
1187static void sde_plane_destroy(struct drm_plane *plane)
1188{
Clarence Ip4ce59322016-06-26 22:27:51 -04001189 struct sde_plane *psde;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001190
Clarence Ip4ce59322016-06-26 22:27:51 -04001191 DBG("");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001192
Clarence Ip4ce59322016-06-26 22:27:51 -04001193 if (plane) {
1194 psde = to_sde_plane(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001195
Clarence Ip4ce59322016-06-26 22:27:51 -04001196 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001197
Clarence Ipaa0faf42016-05-30 12:07:48 -04001198 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001199 mutex_destroy(&psde->lock);
1200
Clarence Ip4ce59322016-06-26 22:27:51 -04001201 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001202
Clarence Ip4ce59322016-06-26 22:27:51 -04001203 /* this will destroy the states as well */
1204 drm_plane_cleanup(plane);
1205
Clarence Ip4c1d9772016-06-26 09:35:38 -04001206 if (psde->pipe_hw)
1207 sde_hw_sspp_destroy(psde->pipe_hw);
1208
Clarence Ip4ce59322016-06-26 22:27:51 -04001209 kfree(psde);
1210 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001211}
1212
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001213static void sde_plane_destroy_state(struct drm_plane *plane,
1214 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001215{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001216 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001217 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001218
Clarence Ipae4e60c2016-06-26 22:44:04 -04001219 if (!plane || !state) {
1220 DRM_ERROR("Invalid plane/state\n");
1221 return;
1222 }
1223
Clarence Ipaa0faf42016-05-30 12:07:48 -04001224 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001225 pstate = to_sde_plane_state(state);
1226
1227 DBG("");
1228
Clarence Ipe78efb72016-06-24 18:35:21 -04001229 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001230 if (state->fb)
1231 drm_framebuffer_unreference(state->fb);
1232
Clarence Ipae4e60c2016-06-26 22:44:04 -04001233 /* remove ref count for fence */
1234 if (pstate->sync_fence)
1235 sde_sync_put(pstate->sync_fence);
1236
Clarence Ipaa0faf42016-05-30 12:07:48 -04001237 /* destroy value helper */
1238 msm_property_destroy_state(&psde->property_info, pstate,
1239 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001240}
1241
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001242static struct drm_plane_state *
1243sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001244{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001245 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001246 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001247 struct sde_plane_state *old_state;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001248
Clarence Ip730e7192016-06-26 22:45:09 -04001249 if (!plane || !plane->state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001250 return NULL;
1251
Clarence Ip730e7192016-06-26 22:45:09 -04001252 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001253 psde = to_sde_plane(plane);
1254 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001255 if (!pstate)
1256 return NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001257
Clarence Ipaa0faf42016-05-30 12:07:48 -04001258 DBG("");
1259
1260 /* duplicate value helper */
1261 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
1262 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001263
Clarence Ip730e7192016-06-26 22:45:09 -04001264 /* add ref count for frame buffer */
1265 if (pstate->base.fb)
1266 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001267
Clarence Ip730e7192016-06-26 22:45:09 -04001268 /* add ref count for fence */
1269 if (pstate->sync_fence) {
1270 pstate->sync_fence = 0;
1271 _sde_plane_update_sync_fence(plane, pstate, pstate->
1272 property_values[PLANE_PROP_SYNC_FENCE]);
Clarence Ipe78efb72016-06-24 18:35:21 -04001273 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001274
Clarence Ip730e7192016-06-26 22:45:09 -04001275 pstate->mode_changed = false;
1276 pstate->pending = false;
1277
1278 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001279}
1280
1281static void sde_plane_reset(struct drm_plane *plane)
1282{
Clarence Ipae4e60c2016-06-26 22:44:04 -04001283 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001284 struct sde_plane_state *pstate;
1285
Clarence Ipae4e60c2016-06-26 22:44:04 -04001286 if (!plane) {
1287 DRM_ERROR("Invalid plane\n");
1288 return;
1289 }
1290
Clarence Ip730e7192016-06-26 22:45:09 -04001291 psde = to_sde_plane(plane);
1292 DBG("%s", psde->pipe_name);
1293
Clarence Ipae4e60c2016-06-26 22:44:04 -04001294 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001295 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04001296 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001297 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04001298 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001299
Clarence Ipaa0faf42016-05-30 12:07:48 -04001300 pstate = msm_property_alloc_state(&psde->property_info);
1301 if (!pstate)
1302 return;
Clarence Ip730e7192016-06-26 22:45:09 -04001303
Clarence Ipaa0faf42016-05-30 12:07:48 -04001304 /* reset value helper */
1305 msm_property_reset_state(&psde->property_info, pstate,
1306 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001307
1308 pstate->base.plane = plane;
1309
1310 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001311}
1312
1313static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001314 .update_plane = drm_atomic_helper_update_plane,
1315 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001316 .destroy = sde_plane_destroy,
1317 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001318 .atomic_set_property = sde_plane_atomic_set_property,
1319 .atomic_get_property = sde_plane_atomic_get_property,
1320 .reset = sde_plane_reset,
1321 .atomic_duplicate_state = sde_plane_duplicate_state,
1322 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001323};
1324
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001325static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
1326 .prepare_fb = sde_plane_prepare_fb,
1327 .cleanup_fb = sde_plane_cleanup_fb,
1328 .atomic_check = sde_plane_atomic_check,
1329 .atomic_update = sde_plane_atomic_update,
1330};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001331
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001332enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001333{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001334 struct sde_plane *sde_plane = to_sde_plane(plane);
1335
1336 return sde_plane->pipe;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001337}
1338
Clarence Ip4ce59322016-06-26 22:27:51 -04001339static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
1340{
1341 const struct sde_sspp_sub_blks *sblk = 0;
1342 const struct sde_sspp_cfg *cfg = 0;
1343
1344 if (psde && psde->pipe_hw)
1345 cfg = psde->pipe_hw->cap;
1346 if (cfg)
1347 sblk = cfg->sblk;
1348
1349 if (kms && sblk) {
1350 /* create overall sub-directory for the pipe */
1351 psde->debugfs_root =
1352 debugfs_create_dir(psde->pipe_name,
1353 sde_debugfs_get_root(kms));
1354 if (psde->debugfs_root) {
1355 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001356 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04001357 psde->debugfs_root, &psde->features);
1358
1359 /* add register dump support */
1360 sde_debugfs_setup_regset32(&psde->debugfs_src,
1361 sblk->src_blk.base + cfg->base,
1362 sblk->src_blk.len,
1363 kms->mmio);
1364 sde_debugfs_create_regset32("src_blk", 0444,
1365 psde->debugfs_root, &psde->debugfs_src);
1366
1367 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
1368 sblk->scaler_blk.base + cfg->base,
1369 sblk->scaler_blk.len,
1370 kms->mmio);
1371 sde_debugfs_create_regset32("scaler_blk", 0444,
1372 psde->debugfs_root,
1373 &psde->debugfs_scaler);
1374
1375 sde_debugfs_setup_regset32(&psde->debugfs_csc,
1376 sblk->csc_blk.base + cfg->base,
1377 sblk->csc_blk.len,
1378 kms->mmio);
1379 sde_debugfs_create_regset32("csc_blk", 0444,
1380 psde->debugfs_root, &psde->debugfs_csc);
1381 }
1382 }
1383}
1384
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001385/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04001386struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip4c1d9772016-06-26 09:35:38 -04001387 uint32_t pipe, bool primary_plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001388{
1389 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001390 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001391 struct msm_drm_private *priv;
1392 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001393 enum drm_plane_type type;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001394 int ret = -EINVAL;
1395
1396 if (!dev) {
1397 DRM_ERROR("[%u]Device is NULL\n", pipe);
1398 goto exit;
1399 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001400
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001401 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04001402 if (!priv) {
1403 DRM_ERROR("[%u]Private data is NULL\n", pipe);
1404 goto exit;
1405 }
1406
1407 if (!priv->kms) {
1408 DRM_ERROR("[%u]Invalid KMS reference\n", pipe);
1409 goto exit;
1410 }
1411 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001412
Clarence Ip4c1d9772016-06-26 09:35:38 -04001413 if (!kms->catalog) {
1414 DRM_ERROR("[%u]Invalid catalog reference\n", pipe);
1415 goto exit;
1416 }
1417
Clarence Ip4ce59322016-06-26 22:27:51 -04001418 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001419 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
1420 if (!psde) {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001421 DRM_ERROR("[%u]Failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001422 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001423 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001424 }
1425
Clarence Ip4c1d9772016-06-26 09:35:38 -04001426 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001427 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001428 psde->pipe = pipe;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001429 psde->mmu_id = kms->mmu_id;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001430
Clarence Ip4c1d9772016-06-26 09:35:38 -04001431 /* initialize underlying h/w driver */
1432 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
1433 if (IS_ERR(psde->pipe_hw)) {
1434 DRM_ERROR("[%u]SSPP init failed\n", pipe);
1435 ret = PTR_ERR(psde->pipe_hw);
1436 goto clean_plane;
1437 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
1438 DRM_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1439 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001440 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001441
1442 /* cache features mask for later */
1443 psde->features = psde->pipe_hw->cap->features;
1444 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
1445
1446 /* add plane to DRM framework */
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001447 psde->nformats = sde_populate_formats(psde->formats,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001448 ARRAY_SIZE(psde->formats),
1449 !(psde->features & BIT(SDE_SSPP_CSC)) ||
Clarence Ipe78efb72016-06-24 18:35:21 -04001450 !(psde->features & SDE_SSPP_SCALER));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001451
Clarence Ip4c1d9772016-06-26 09:35:38 -04001452 if (!psde->nformats) {
1453 DRM_ERROR("[%u]No valid formats for plane\n", pipe);
1454 goto clean_sspp;
1455 }
1456
1457 if (psde->features & BIT(SDE_SSPP_CURSOR))
1458 type = DRM_PLANE_TYPE_CURSOR;
1459 else if (primary_plane)
1460 type = DRM_PLANE_TYPE_PRIMARY;
1461 else
1462 type = DRM_PLANE_TYPE_OVERLAY;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001463 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
1464 psde->formats, psde->nformats,
1465 type);
1466 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04001467 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001468
Clarence Ip4c1d9772016-06-26 09:35:38 -04001469 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001470 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001471
Clarence Ipaa0faf42016-05-30 12:07:48 -04001472 msm_property_init(&psde->property_info, &plane->base, dev,
1473 priv->plane_property, psde->property_data,
1474 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
1475 sizeof(struct sde_plane_state));
1476
1477 _sde_plane_install_properties(plane);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001478
Clarence Ip4ce59322016-06-26 22:27:51 -04001479 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04001480 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04001481
Clarence Ip730e7192016-06-26 22:45:09 -04001482 mutex_init(&psde->lock);
1483
Clarence Ip4ce59322016-06-26 22:27:51 -04001484 _sde_plane_init_debugfs(psde, kms);
1485
Clarence Ip4c1d9772016-06-26 09:35:38 -04001486 DRM_INFO("[%u]Successfully created %s\n", pipe, psde->pipe_name);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001487 return plane;
1488
Clarence Ip4c1d9772016-06-26 09:35:38 -04001489clean_sspp:
1490 if (psde && psde->pipe_hw)
1491 sde_hw_sspp_destroy(psde->pipe_hw);
1492clean_plane:
1493 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04001494exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001495 return ERR_PTR(ret);
1496}