Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> |
| 7 | * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/module.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 14 | #include <linux/irq.h> |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 15 | #include <linux/spinlock.h> |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 16 | #include <asm/irq_cpu.h> |
| 17 | #include <asm/mipsregs.h> |
| 18 | #include <bcm63xx_cpu.h> |
| 19 | #include <bcm63xx_regs.h> |
| 20 | #include <bcm63xx_io.h> |
| 21 | #include <bcm63xx_irq.h> |
| 22 | |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 23 | |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 24 | static DEFINE_SPINLOCK(ipic_lock); |
| 25 | static DEFINE_SPINLOCK(epic_lock); |
| 26 | |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 27 | static u32 irq_stat_addr[2]; |
| 28 | static u32 irq_mask_addr[2]; |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 29 | static void (*dispatch_internal)(int cpu); |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 30 | static int is_ext_irq_cascaded; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 31 | static unsigned int ext_irq_count; |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 32 | static unsigned int ext_irq_start, ext_irq_end; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 33 | static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; |
Jonas Gorski | 553e25b | 2014-07-12 12:49:41 +0200 | [diff] [blame] | 34 | static void (*internal_irq_mask)(struct irq_data *d); |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 35 | static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m); |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 36 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 37 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 38 | static inline u32 get_ext_irq_perf_reg(int irq) |
| 39 | { |
| 40 | if (irq < 4) |
| 41 | return ext_irq_cfg_reg1; |
| 42 | return ext_irq_cfg_reg2; |
| 43 | } |
| 44 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 45 | static inline void handle_internal(int intbit) |
| 46 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 47 | if (is_ext_irq_cascaded && |
| 48 | intbit >= ext_irq_start && intbit <= ext_irq_end) |
| 49 | do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE); |
| 50 | else |
| 51 | do_IRQ(intbit + IRQ_INTERNAL_BASE); |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 52 | } |
| 53 | |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 54 | static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, |
| 55 | const struct cpumask *m) |
| 56 | { |
| 57 | bool enable = cpu_online(cpu); |
| 58 | |
| 59 | #ifdef CONFIG_SMP |
| 60 | if (m) |
Rusty Russell | 8dd9289 | 2015-03-05 10:49:17 +1030 | [diff] [blame] | 61 | enable &= cpumask_test_cpu(cpu, m); |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 62 | else if (irqd_affinity_was_set(d)) |
Jiang Liu | 5c15942 | 2015-07-13 20:45:59 +0000 | [diff] [blame] | 63 | enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d)); |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 64 | #endif |
| 65 | return enable; |
| 66 | } |
| 67 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 68 | /* |
| 69 | * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not |
| 70 | * prioritize any interrupt relatively to another. the static counter |
| 71 | * will resume the loop where it ended the last time we left this |
| 72 | * function. |
| 73 | */ |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 74 | |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 75 | #define BUILD_IPIC_INTERNAL(width) \ |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 76 | void __dispatch_internal_##width(int cpu) \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 77 | { \ |
| 78 | u32 pending[width / 32]; \ |
| 79 | unsigned int src, tgt; \ |
| 80 | bool irqs_pending = false; \ |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 81 | static unsigned int i[2]; \ |
| 82 | unsigned int *next = &i[cpu]; \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 83 | unsigned long flags; \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 84 | \ |
| 85 | /* read registers in reverse order */ \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 86 | spin_lock_irqsave(&ipic_lock, flags); \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 87 | for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ |
| 88 | u32 val; \ |
| 89 | \ |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 90 | val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ |
| 91 | val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 92 | pending[--tgt] = val; \ |
| 93 | \ |
| 94 | if (val) \ |
| 95 | irqs_pending = true; \ |
| 96 | } \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 97 | spin_unlock_irqrestore(&ipic_lock, flags); \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 98 | \ |
| 99 | if (!irqs_pending) \ |
| 100 | return; \ |
| 101 | \ |
| 102 | while (1) { \ |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 103 | unsigned int to_call = *next; \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 104 | \ |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 105 | *next = (*next + 1) & (width - 1); \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 106 | if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ |
| 107 | handle_internal(to_call); \ |
| 108 | break; \ |
| 109 | } \ |
| 110 | } \ |
| 111 | } \ |
| 112 | \ |
Jonas Gorski | 553e25b | 2014-07-12 12:49:41 +0200 | [diff] [blame] | 113 | static void __internal_irq_mask_##width(struct irq_data *d) \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 114 | { \ |
| 115 | u32 val; \ |
Jonas Gorski | 553e25b | 2014-07-12 12:49:41 +0200 | [diff] [blame] | 116 | unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 117 | unsigned reg = (irq / 32) ^ (width/32 - 1); \ |
| 118 | unsigned bit = irq & 0x1f; \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 119 | unsigned long flags; \ |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 120 | int cpu; \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 121 | \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 122 | spin_lock_irqsave(&ipic_lock, flags); \ |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 123 | for_each_present_cpu(cpu) { \ |
| 124 | if (!irq_mask_addr[cpu]) \ |
| 125 | break; \ |
| 126 | \ |
| 127 | val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ |
| 128 | val &= ~(1 << bit); \ |
| 129 | bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ |
| 130 | } \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 131 | spin_unlock_irqrestore(&ipic_lock, flags); \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 132 | } \ |
| 133 | \ |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 134 | static void __internal_irq_unmask_##width(struct irq_data *d, \ |
| 135 | const struct cpumask *m) \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 136 | { \ |
| 137 | u32 val; \ |
Jonas Gorski | 553e25b | 2014-07-12 12:49:41 +0200 | [diff] [blame] | 138 | unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 139 | unsigned reg = (irq / 32) ^ (width/32 - 1); \ |
| 140 | unsigned bit = irq & 0x1f; \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 141 | unsigned long flags; \ |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 142 | int cpu; \ |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 143 | \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 144 | spin_lock_irqsave(&ipic_lock, flags); \ |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 145 | for_each_present_cpu(cpu) { \ |
| 146 | if (!irq_mask_addr[cpu]) \ |
| 147 | break; \ |
| 148 | \ |
| 149 | val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 150 | if (enable_irq_for_cpu(cpu, d, m)) \ |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 151 | val |= (1 << bit); \ |
| 152 | else \ |
| 153 | val &= ~(1 << bit); \ |
| 154 | bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ |
| 155 | } \ |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 156 | spin_unlock_irqrestore(&ipic_lock, flags); \ |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 157 | } |
| 158 | |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame] | 159 | BUILD_IPIC_INTERNAL(32); |
| 160 | BUILD_IPIC_INTERNAL(64); |
Maxime Bizon | 71a4392 | 2011-11-04 19:09:33 +0100 | [diff] [blame] | 161 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 162 | asmlinkage void plat_irq_dispatch(void) |
| 163 | { |
| 164 | u32 cause; |
| 165 | |
| 166 | do { |
| 167 | cause = read_c0_cause() & read_c0_status() & ST0_IM; |
| 168 | |
| 169 | if (!cause) |
| 170 | break; |
| 171 | |
| 172 | if (cause & CAUSEF_IP7) |
| 173 | do_IRQ(7); |
Kevin Cernekee | 937ad10 | 2013-06-03 14:39:34 +0000 | [diff] [blame] | 174 | if (cause & CAUSEF_IP0) |
| 175 | do_IRQ(0); |
| 176 | if (cause & CAUSEF_IP1) |
| 177 | do_IRQ(1); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 178 | if (cause & CAUSEF_IP2) |
Jonas Gorski | 7a9fd14 | 2014-07-12 12:49:38 +0200 | [diff] [blame] | 179 | dispatch_internal(0); |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 180 | if (is_ext_irq_cascaded) { |
| 181 | if (cause & CAUSEF_IP3) |
| 182 | dispatch_internal(1); |
| 183 | } else { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 184 | if (cause & CAUSEF_IP3) |
| 185 | do_IRQ(IRQ_EXT_0); |
| 186 | if (cause & CAUSEF_IP4) |
| 187 | do_IRQ(IRQ_EXT_1); |
| 188 | if (cause & CAUSEF_IP5) |
| 189 | do_IRQ(IRQ_EXT_2); |
| 190 | if (cause & CAUSEF_IP6) |
| 191 | do_IRQ(IRQ_EXT_3); |
| 192 | } |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 193 | } while (1); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * internal IRQs operations: only mask/unmask on PERF irq mask |
| 198 | * register. |
| 199 | */ |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 200 | static void bcm63xx_internal_irq_mask(struct irq_data *d) |
| 201 | { |
Jonas Gorski | 553e25b | 2014-07-12 12:49:41 +0200 | [diff] [blame] | 202 | internal_irq_mask(d); |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | static void bcm63xx_internal_irq_unmask(struct irq_data *d) |
| 206 | { |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 207 | internal_irq_unmask(d, NULL); |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 208 | } |
| 209 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 210 | /* |
| 211 | * external IRQs operations: mask/unmask and clear on PERF external |
| 212 | * irq control register. |
| 213 | */ |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 214 | static void bcm63xx_external_irq_mask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 215 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 216 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 217 | u32 reg, regaddr; |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 218 | unsigned long flags; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 219 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 220 | regaddr = get_ext_irq_perf_reg(irq); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 221 | spin_lock_irqsave(&epic_lock, flags); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 222 | reg = bcm_perf_readl(regaddr); |
| 223 | |
| 224 | if (BCMCPU_IS_6348()) |
| 225 | reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); |
| 226 | else |
| 227 | reg &= ~EXTIRQ_CFG_MASK(irq % 4); |
| 228 | |
| 229 | bcm_perf_writel(reg, regaddr); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 230 | spin_unlock_irqrestore(&epic_lock, flags); |
| 231 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 232 | if (is_ext_irq_cascaded) |
Jonas Gorski | 553e25b | 2014-07-12 12:49:41 +0200 | [diff] [blame] | 233 | internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 234 | } |
| 235 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 236 | static void bcm63xx_external_irq_unmask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 237 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 238 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 239 | u32 reg, regaddr; |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 240 | unsigned long flags; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 241 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 242 | regaddr = get_ext_irq_perf_reg(irq); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 243 | spin_lock_irqsave(&epic_lock, flags); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 244 | reg = bcm_perf_readl(regaddr); |
| 245 | |
| 246 | if (BCMCPU_IS_6348()) |
| 247 | reg |= EXTIRQ_CFG_MASK_6348(irq % 4); |
| 248 | else |
| 249 | reg |= EXTIRQ_CFG_MASK(irq % 4); |
| 250 | |
| 251 | bcm_perf_writel(reg, regaddr); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 252 | spin_unlock_irqrestore(&epic_lock, flags); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 253 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 254 | if (is_ext_irq_cascaded) |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 255 | internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start), |
| 256 | NULL); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 257 | } |
| 258 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 259 | static void bcm63xx_external_irq_clear(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 260 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 261 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 262 | u32 reg, regaddr; |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 263 | unsigned long flags; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 264 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 265 | regaddr = get_ext_irq_perf_reg(irq); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 266 | spin_lock_irqsave(&epic_lock, flags); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 267 | reg = bcm_perf_readl(regaddr); |
| 268 | |
| 269 | if (BCMCPU_IS_6348()) |
| 270 | reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); |
| 271 | else |
| 272 | reg |= EXTIRQ_CFG_CLEAR(irq % 4); |
| 273 | |
| 274 | bcm_perf_writel(reg, regaddr); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 275 | spin_unlock_irqrestore(&epic_lock, flags); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 276 | } |
| 277 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 278 | static int bcm63xx_external_irq_set_type(struct irq_data *d, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 279 | unsigned int flow_type) |
| 280 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 281 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 282 | u32 reg, regaddr; |
| 283 | int levelsense, sense, bothedge; |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 284 | unsigned long flags; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 285 | |
| 286 | flow_type &= IRQ_TYPE_SENSE_MASK; |
| 287 | |
| 288 | if (flow_type == IRQ_TYPE_NONE) |
| 289 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 290 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 291 | levelsense = sense = bothedge = 0; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 292 | switch (flow_type) { |
| 293 | case IRQ_TYPE_EDGE_BOTH: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 294 | bothedge = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 295 | break; |
| 296 | |
| 297 | case IRQ_TYPE_EDGE_RISING: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 298 | sense = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 299 | break; |
| 300 | |
| 301 | case IRQ_TYPE_EDGE_FALLING: |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 302 | break; |
| 303 | |
| 304 | case IRQ_TYPE_LEVEL_HIGH: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 305 | levelsense = 1; |
| 306 | sense = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 307 | break; |
| 308 | |
| 309 | case IRQ_TYPE_LEVEL_LOW: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 310 | levelsense = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 311 | break; |
| 312 | |
| 313 | default: |
Gregory Fong | 63893ea | 2015-10-14 04:27:38 -0700 | [diff] [blame] | 314 | pr_err("bogus flow type combination given !\n"); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 315 | return -EINVAL; |
| 316 | } |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 317 | |
| 318 | regaddr = get_ext_irq_perf_reg(irq); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 319 | spin_lock_irqsave(&epic_lock, flags); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 320 | reg = bcm_perf_readl(regaddr); |
| 321 | irq %= 4; |
| 322 | |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 323 | switch (bcm63xx_get_cpu_id()) { |
| 324 | case BCM6348_CPU_ID: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 325 | if (levelsense) |
| 326 | reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); |
| 327 | else |
| 328 | reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); |
| 329 | if (sense) |
| 330 | reg |= EXTIRQ_CFG_SENSE_6348(irq); |
| 331 | else |
| 332 | reg &= ~EXTIRQ_CFG_SENSE_6348(irq); |
| 333 | if (bothedge) |
| 334 | reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); |
| 335 | else |
| 336 | reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 337 | break; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 338 | |
Florian Fainelli | 7b93342 | 2013-06-18 16:55:40 +0000 | [diff] [blame] | 339 | case BCM3368_CPU_ID: |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 340 | case BCM6328_CPU_ID: |
| 341 | case BCM6338_CPU_ID: |
| 342 | case BCM6345_CPU_ID: |
| 343 | case BCM6358_CPU_ID: |
Jonas Gorski | 2c8aaf7 | 2013-03-21 14:03:17 +0000 | [diff] [blame] | 344 | case BCM6362_CPU_ID: |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 345 | case BCM6368_CPU_ID: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 346 | if (levelsense) |
| 347 | reg |= EXTIRQ_CFG_LEVELSENSE(irq); |
| 348 | else |
| 349 | reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); |
| 350 | if (sense) |
| 351 | reg |= EXTIRQ_CFG_SENSE(irq); |
| 352 | else |
| 353 | reg &= ~EXTIRQ_CFG_SENSE(irq); |
| 354 | if (bothedge) |
| 355 | reg |= EXTIRQ_CFG_BOTHEDGE(irq); |
| 356 | else |
| 357 | reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 358 | break; |
| 359 | default: |
| 360 | BUG(); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | bcm_perf_writel(reg, regaddr); |
Jonas Gorski | 74b8ca3 | 2014-07-12 12:49:39 +0200 | [diff] [blame] | 364 | spin_unlock_irqrestore(&epic_lock, flags); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 365 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 366 | irqd_set_trigger_type(d, flow_type); |
| 367 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
Thomas Gleixner | 9154566 | 2015-07-13 20:46:02 +0000 | [diff] [blame] | 368 | irq_set_handler_locked(d, handle_level_irq); |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 369 | else |
Thomas Gleixner | 9154566 | 2015-07-13 20:46:02 +0000 | [diff] [blame] | 370 | irq_set_handler_locked(d, handle_edge_irq); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 371 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 372 | return IRQ_SET_MASK_OK_NOCOPY; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 373 | } |
| 374 | |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 375 | #ifdef CONFIG_SMP |
| 376 | static int bcm63xx_internal_set_affinity(struct irq_data *data, |
| 377 | const struct cpumask *dest, |
| 378 | bool force) |
| 379 | { |
| 380 | if (!irqd_irq_disabled(data)) |
| 381 | internal_irq_unmask(data, dest); |
| 382 | |
| 383 | return 0; |
| 384 | } |
| 385 | #endif |
| 386 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 387 | static struct irq_chip bcm63xx_internal_irq_chip = { |
| 388 | .name = "bcm63xx_ipic", |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 389 | .irq_mask = bcm63xx_internal_irq_mask, |
| 390 | .irq_unmask = bcm63xx_internal_irq_unmask, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | static struct irq_chip bcm63xx_external_irq_chip = { |
| 394 | .name = "bcm63xx_epic", |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 395 | .irq_ack = bcm63xx_external_irq_clear, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 396 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 397 | .irq_mask = bcm63xx_external_irq_mask, |
| 398 | .irq_unmask = bcm63xx_external_irq_unmask, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 399 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 400 | .irq_set_type = bcm63xx_external_irq_set_type, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 401 | }; |
| 402 | |
| 403 | static struct irqaction cpu_ip2_cascade_action = { |
| 404 | .handler = no_action, |
| 405 | .name = "cascade_ip2", |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 406 | .flags = IRQF_NO_THREAD, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 407 | }; |
| 408 | |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 409 | #ifdef CONFIG_SMP |
| 410 | static struct irqaction cpu_ip3_cascade_action = { |
| 411 | .handler = no_action, |
| 412 | .name = "cascade_ip3", |
| 413 | .flags = IRQF_NO_THREAD, |
| 414 | }; |
| 415 | #endif |
| 416 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 417 | static struct irqaction cpu_ext_cascade_action = { |
| 418 | .handler = no_action, |
| 419 | .name = "cascade_extirq", |
| 420 | .flags = IRQF_NO_THREAD, |
| 421 | }; |
| 422 | |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 423 | static void bcm63xx_init_irq(void) |
| 424 | { |
| 425 | int irq_bits; |
| 426 | |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 427 | irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); |
| 428 | irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 429 | irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); |
| 430 | irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 431 | |
| 432 | switch (bcm63xx_get_cpu_id()) { |
| 433 | case BCM3368_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 434 | irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; |
| 435 | irq_mask_addr[0] += PERF_IRQMASK_3368_REG; |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 436 | irq_stat_addr[1] = 0; |
Julia Lawall | bbc5367 | 2014-08-23 20:33:25 +0200 | [diff] [blame] | 437 | irq_mask_addr[1] = 0; |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 438 | irq_bits = 32; |
| 439 | ext_irq_count = 4; |
| 440 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; |
| 441 | break; |
| 442 | case BCM6328_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 443 | irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); |
| 444 | irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 445 | irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); |
Julia Lawall | bbc5367 | 2014-08-23 20:33:25 +0200 | [diff] [blame] | 446 | irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1); |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 447 | irq_bits = 64; |
| 448 | ext_irq_count = 4; |
| 449 | is_ext_irq_cascaded = 1; |
| 450 | ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 451 | ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
| 452 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; |
| 453 | break; |
| 454 | case BCM6338_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 455 | irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; |
| 456 | irq_mask_addr[0] += PERF_IRQMASK_6338_REG; |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 457 | irq_stat_addr[1] = 0; |
| 458 | irq_mask_addr[1] = 0; |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 459 | irq_bits = 32; |
| 460 | ext_irq_count = 4; |
| 461 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; |
| 462 | break; |
| 463 | case BCM6345_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 464 | irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; |
| 465 | irq_mask_addr[0] += PERF_IRQMASK_6345_REG; |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 466 | irq_stat_addr[1] = 0; |
| 467 | irq_mask_addr[1] = 0; |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 468 | irq_bits = 32; |
| 469 | ext_irq_count = 4; |
| 470 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; |
| 471 | break; |
| 472 | case BCM6348_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 473 | irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; |
| 474 | irq_mask_addr[0] += PERF_IRQMASK_6348_REG; |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 475 | irq_stat_addr[1] = 0; |
| 476 | irq_mask_addr[1] = 0; |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 477 | irq_bits = 32; |
| 478 | ext_irq_count = 4; |
| 479 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; |
| 480 | break; |
| 481 | case BCM6358_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 482 | irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); |
| 483 | irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 484 | irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); |
| 485 | irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 486 | irq_bits = 32; |
| 487 | ext_irq_count = 4; |
| 488 | is_ext_irq_cascaded = 1; |
| 489 | ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 490 | ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
| 491 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; |
| 492 | break; |
| 493 | case BCM6362_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 494 | irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); |
| 495 | irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 496 | irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); |
| 497 | irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 498 | irq_bits = 64; |
| 499 | ext_irq_count = 4; |
| 500 | is_ext_irq_cascaded = 1; |
| 501 | ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 502 | ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
| 503 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; |
| 504 | break; |
| 505 | case BCM6368_CPU_ID: |
Jonas Gorski | cc81d7f | 2014-07-12 12:49:36 +0200 | [diff] [blame] | 506 | irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); |
| 507 | irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); |
Jonas Gorski | 3534b5c | 2014-07-12 12:49:37 +0200 | [diff] [blame] | 508 | irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); |
| 509 | irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 510 | irq_bits = 64; |
| 511 | ext_irq_count = 6; |
| 512 | is_ext_irq_cascaded = 1; |
| 513 | ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 514 | ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; |
| 515 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; |
| 516 | ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; |
| 517 | break; |
| 518 | default: |
| 519 | BUG(); |
| 520 | } |
| 521 | |
| 522 | if (irq_bits == 32) { |
| 523 | dispatch_internal = __dispatch_internal_32; |
| 524 | internal_irq_mask = __internal_irq_mask_32; |
| 525 | internal_irq_unmask = __internal_irq_unmask_32; |
| 526 | } else { |
| 527 | dispatch_internal = __dispatch_internal_64; |
| 528 | internal_irq_mask = __internal_irq_mask_64; |
| 529 | internal_irq_unmask = __internal_irq_unmask_64; |
| 530 | } |
| 531 | } |
| 532 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 533 | void __init arch_init_irq(void) |
| 534 | { |
| 535 | int i; |
| 536 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 537 | bcm63xx_init_irq(); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 538 | mips_cpu_irq_init(); |
| 539 | for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 540 | irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 541 | handle_level_irq); |
| 542 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 543 | for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 544 | irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 545 | handle_edge_irq); |
| 546 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 547 | if (!is_ext_irq_cascaded) { |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 548 | for (i = 3; i < 3 + ext_irq_count; ++i) |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 549 | setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); |
| 550 | } |
| 551 | |
| 552 | setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 553 | #ifdef CONFIG_SMP |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 554 | if (is_ext_irq_cascaded) { |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 555 | setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); |
Jonas Gorski | b37f0f6 | 2014-07-12 12:49:42 +0200 | [diff] [blame] | 556 | bcm63xx_internal_irq_chip.irq_set_affinity = |
| 557 | bcm63xx_internal_set_affinity; |
| 558 | |
| 559 | cpumask_clear(irq_default_affinity); |
| 560 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); |
| 561 | } |
Jonas Gorski | 56d53ea | 2014-07-12 12:49:40 +0200 | [diff] [blame] | 562 | #endif |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 563 | } |