blob: c96139097ae270c9fbf6252d086611159bd6503d [file] [log] [blame]
Maxime Bizone7300d02009-08-18 13:23:37 +01001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
David Howellsca4d3e672010-10-07 14:08:54 +010014#include <linux/irq.h>
Jonas Gorski74b8ca32014-07-12 12:49:39 +020015#include <linux/spinlock.h>
Maxime Bizone7300d02009-08-18 13:23:37 +010016#include <asm/irq_cpu.h>
17#include <asm/mipsregs.h>
18#include <bcm63xx_cpu.h>
19#include <bcm63xx_regs.h>
20#include <bcm63xx_io.h>
21#include <bcm63xx_irq.h>
22
Jonas Gorski7a9fd142014-07-12 12:49:38 +020023
Jonas Gorski74b8ca32014-07-12 12:49:39 +020024static DEFINE_SPINLOCK(ipic_lock);
25static DEFINE_SPINLOCK(epic_lock);
26
Jonas Gorskicc81d7f2014-07-12 12:49:36 +020027static u32 irq_stat_addr[2];
28static u32 irq_mask_addr[2];
Jonas Gorski7a9fd142014-07-12 12:49:38 +020029static void (*dispatch_internal)(int cpu);
Maxime Bizon37c42a72011-11-04 19:09:32 +010030static int is_ext_irq_cascaded;
Maxime Bizon62248922011-11-04 19:09:34 +010031static unsigned int ext_irq_count;
Maxime Bizon37c42a72011-11-04 19:09:32 +010032static unsigned int ext_irq_start, ext_irq_end;
Maxime Bizon62248922011-11-04 19:09:34 +010033static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
Jonas Gorski553e25b2014-07-12 12:49:41 +020034static void (*internal_irq_mask)(struct irq_data *d);
Jonas Gorskib37f0f62014-07-12 12:49:42 +020035static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
Maxime Bizonf61cced2011-11-04 19:09:31 +010036
Maxime Bizonf61cced2011-11-04 19:09:31 +010037
Maxime Bizon62248922011-11-04 19:09:34 +010038static inline u32 get_ext_irq_perf_reg(int irq)
39{
40 if (irq < 4)
41 return ext_irq_cfg_reg1;
42 return ext_irq_cfg_reg2;
43}
44
Maxime Bizonf61cced2011-11-04 19:09:31 +010045static inline void handle_internal(int intbit)
46{
Maxime Bizon37c42a72011-11-04 19:09:32 +010047 if (is_ext_irq_cascaded &&
48 intbit >= ext_irq_start && intbit <= ext_irq_end)
49 do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
50 else
51 do_IRQ(intbit + IRQ_INTERNAL_BASE);
Maxime Bizonf61cced2011-11-04 19:09:31 +010052}
53
Jonas Gorskib37f0f62014-07-12 12:49:42 +020054static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
55 const struct cpumask *m)
56{
57 bool enable = cpu_online(cpu);
58
59#ifdef CONFIG_SMP
60 if (m)
Rusty Russell8dd92892015-03-05 10:49:17 +103061 enable &= cpumask_test_cpu(cpu, m);
Jonas Gorskib37f0f62014-07-12 12:49:42 +020062 else if (irqd_affinity_was_set(d))
Jiang Liu5c159422015-07-13 20:45:59 +000063 enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d));
Jonas Gorskib37f0f62014-07-12 12:49:42 +020064#endif
65 return enable;
66}
67
Maxime Bizone7300d02009-08-18 13:23:37 +010068/*
69 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
70 * prioritize any interrupt relatively to another. the static counter
71 * will resume the loop where it ended the last time we left this
72 * function.
73 */
Maxime Bizone7300d02009-08-18 13:23:37 +010074
Jonas Gorski86ee4332014-07-12 12:49:35 +020075#define BUILD_IPIC_INTERNAL(width) \
Jonas Gorski7a9fd142014-07-12 12:49:38 +020076void __dispatch_internal_##width(int cpu) \
Jonas Gorski86ee4332014-07-12 12:49:35 +020077{ \
78 u32 pending[width / 32]; \
79 unsigned int src, tgt; \
80 bool irqs_pending = false; \
Jonas Gorski7a9fd142014-07-12 12:49:38 +020081 static unsigned int i[2]; \
82 unsigned int *next = &i[cpu]; \
Jonas Gorski74b8ca32014-07-12 12:49:39 +020083 unsigned long flags; \
Jonas Gorski86ee4332014-07-12 12:49:35 +020084 \
85 /* read registers in reverse order */ \
Jonas Gorski74b8ca32014-07-12 12:49:39 +020086 spin_lock_irqsave(&ipic_lock, flags); \
Jonas Gorski86ee4332014-07-12 12:49:35 +020087 for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
88 u32 val; \
89 \
Jonas Gorski7a9fd142014-07-12 12:49:38 +020090 val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
91 val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
Jonas Gorski86ee4332014-07-12 12:49:35 +020092 pending[--tgt] = val; \
93 \
94 if (val) \
95 irqs_pending = true; \
96 } \
Jonas Gorski74b8ca32014-07-12 12:49:39 +020097 spin_unlock_irqrestore(&ipic_lock, flags); \
Jonas Gorski86ee4332014-07-12 12:49:35 +020098 \
99 if (!irqs_pending) \
100 return; \
101 \
102 while (1) { \
Jonas Gorski7a9fd142014-07-12 12:49:38 +0200103 unsigned int to_call = *next; \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200104 \
Jonas Gorski7a9fd142014-07-12 12:49:38 +0200105 *next = (*next + 1) & (width - 1); \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200106 if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
107 handle_internal(to_call); \
108 break; \
109 } \
110 } \
111} \
112 \
Jonas Gorski553e25b2014-07-12 12:49:41 +0200113static void __internal_irq_mask_##width(struct irq_data *d) \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200114{ \
115 u32 val; \
Jonas Gorski553e25b2014-07-12 12:49:41 +0200116 unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200117 unsigned reg = (irq / 32) ^ (width/32 - 1); \
118 unsigned bit = irq & 0x1f; \
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200119 unsigned long flags; \
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200120 int cpu; \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200121 \
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200122 spin_lock_irqsave(&ipic_lock, flags); \
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200123 for_each_present_cpu(cpu) { \
124 if (!irq_mask_addr[cpu]) \
125 break; \
126 \
127 val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
128 val &= ~(1 << bit); \
129 bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
130 } \
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200131 spin_unlock_irqrestore(&ipic_lock, flags); \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200132} \
133 \
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200134static void __internal_irq_unmask_##width(struct irq_data *d, \
135 const struct cpumask *m) \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200136{ \
137 u32 val; \
Jonas Gorski553e25b2014-07-12 12:49:41 +0200138 unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200139 unsigned reg = (irq / 32) ^ (width/32 - 1); \
140 unsigned bit = irq & 0x1f; \
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200141 unsigned long flags; \
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200142 int cpu; \
Jonas Gorski86ee4332014-07-12 12:49:35 +0200143 \
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200144 spin_lock_irqsave(&ipic_lock, flags); \
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200145 for_each_present_cpu(cpu) { \
146 if (!irq_mask_addr[cpu]) \
147 break; \
148 \
149 val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200150 if (enable_irq_for_cpu(cpu, d, m)) \
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200151 val |= (1 << bit); \
152 else \
153 val &= ~(1 << bit); \
154 bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
155 } \
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200156 spin_unlock_irqrestore(&ipic_lock, flags); \
Maxime Bizone7300d02009-08-18 13:23:37 +0100157}
158
Jonas Gorski86ee4332014-07-12 12:49:35 +0200159BUILD_IPIC_INTERNAL(32);
160BUILD_IPIC_INTERNAL(64);
Maxime Bizon71a43922011-11-04 19:09:33 +0100161
Maxime Bizone7300d02009-08-18 13:23:37 +0100162asmlinkage void plat_irq_dispatch(void)
163{
164 u32 cause;
165
166 do {
167 cause = read_c0_cause() & read_c0_status() & ST0_IM;
168
169 if (!cause)
170 break;
171
172 if (cause & CAUSEF_IP7)
173 do_IRQ(7);
Kevin Cernekee937ad102013-06-03 14:39:34 +0000174 if (cause & CAUSEF_IP0)
175 do_IRQ(0);
176 if (cause & CAUSEF_IP1)
177 do_IRQ(1);
Maxime Bizone7300d02009-08-18 13:23:37 +0100178 if (cause & CAUSEF_IP2)
Jonas Gorski7a9fd142014-07-12 12:49:38 +0200179 dispatch_internal(0);
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200180 if (is_ext_irq_cascaded) {
181 if (cause & CAUSEF_IP3)
182 dispatch_internal(1);
183 } else {
Maxime Bizon37c42a72011-11-04 19:09:32 +0100184 if (cause & CAUSEF_IP3)
185 do_IRQ(IRQ_EXT_0);
186 if (cause & CAUSEF_IP4)
187 do_IRQ(IRQ_EXT_1);
188 if (cause & CAUSEF_IP5)
189 do_IRQ(IRQ_EXT_2);
190 if (cause & CAUSEF_IP6)
191 do_IRQ(IRQ_EXT_3);
192 }
Maxime Bizone7300d02009-08-18 13:23:37 +0100193 } while (1);
194}
195
196/*
197 * internal IRQs operations: only mask/unmask on PERF irq mask
198 * register.
199 */
Maxime Bizon37c42a72011-11-04 19:09:32 +0100200static void bcm63xx_internal_irq_mask(struct irq_data *d)
201{
Jonas Gorski553e25b2014-07-12 12:49:41 +0200202 internal_irq_mask(d);
Maxime Bizon37c42a72011-11-04 19:09:32 +0100203}
204
205static void bcm63xx_internal_irq_unmask(struct irq_data *d)
206{
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200207 internal_irq_unmask(d, NULL);
Maxime Bizon37c42a72011-11-04 19:09:32 +0100208}
209
Maxime Bizone7300d02009-08-18 13:23:37 +0100210/*
211 * external IRQs operations: mask/unmask and clear on PERF external
212 * irq control register.
213 */
Thomas Gleixner93f29362011-03-23 21:08:47 +0000214static void bcm63xx_external_irq_mask(struct irq_data *d)
Maxime Bizone7300d02009-08-18 13:23:37 +0100215{
Maxime Bizon37c42a72011-11-04 19:09:32 +0100216 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
Maxime Bizon62248922011-11-04 19:09:34 +0100217 u32 reg, regaddr;
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200218 unsigned long flags;
Maxime Bizone7300d02009-08-18 13:23:37 +0100219
Maxime Bizon62248922011-11-04 19:09:34 +0100220 regaddr = get_ext_irq_perf_reg(irq);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200221 spin_lock_irqsave(&epic_lock, flags);
Maxime Bizon62248922011-11-04 19:09:34 +0100222 reg = bcm_perf_readl(regaddr);
223
224 if (BCMCPU_IS_6348())
225 reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
226 else
227 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
228
229 bcm_perf_writel(reg, regaddr);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200230 spin_unlock_irqrestore(&epic_lock, flags);
231
Maxime Bizon37c42a72011-11-04 19:09:32 +0100232 if (is_ext_irq_cascaded)
Jonas Gorski553e25b2014-07-12 12:49:41 +0200233 internal_irq_mask(irq_get_irq_data(irq + ext_irq_start));
Maxime Bizone7300d02009-08-18 13:23:37 +0100234}
235
Thomas Gleixner93f29362011-03-23 21:08:47 +0000236static void bcm63xx_external_irq_unmask(struct irq_data *d)
Maxime Bizone7300d02009-08-18 13:23:37 +0100237{
Maxime Bizon37c42a72011-11-04 19:09:32 +0100238 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
Maxime Bizon62248922011-11-04 19:09:34 +0100239 u32 reg, regaddr;
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200240 unsigned long flags;
Maxime Bizone7300d02009-08-18 13:23:37 +0100241
Maxime Bizon62248922011-11-04 19:09:34 +0100242 regaddr = get_ext_irq_perf_reg(irq);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200243 spin_lock_irqsave(&epic_lock, flags);
Maxime Bizon62248922011-11-04 19:09:34 +0100244 reg = bcm_perf_readl(regaddr);
245
246 if (BCMCPU_IS_6348())
247 reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
248 else
249 reg |= EXTIRQ_CFG_MASK(irq % 4);
250
251 bcm_perf_writel(reg, regaddr);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200252 spin_unlock_irqrestore(&epic_lock, flags);
Maxime Bizon62248922011-11-04 19:09:34 +0100253
Maxime Bizon37c42a72011-11-04 19:09:32 +0100254 if (is_ext_irq_cascaded)
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200255 internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
256 NULL);
Maxime Bizone7300d02009-08-18 13:23:37 +0100257}
258
Thomas Gleixner93f29362011-03-23 21:08:47 +0000259static void bcm63xx_external_irq_clear(struct irq_data *d)
Maxime Bizone7300d02009-08-18 13:23:37 +0100260{
Maxime Bizon37c42a72011-11-04 19:09:32 +0100261 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
Maxime Bizon62248922011-11-04 19:09:34 +0100262 u32 reg, regaddr;
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200263 unsigned long flags;
Maxime Bizone7300d02009-08-18 13:23:37 +0100264
Maxime Bizon62248922011-11-04 19:09:34 +0100265 regaddr = get_ext_irq_perf_reg(irq);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200266 spin_lock_irqsave(&epic_lock, flags);
Maxime Bizon62248922011-11-04 19:09:34 +0100267 reg = bcm_perf_readl(regaddr);
268
269 if (BCMCPU_IS_6348())
270 reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
271 else
272 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
273
274 bcm_perf_writel(reg, regaddr);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200275 spin_unlock_irqrestore(&epic_lock, flags);
Maxime Bizone7300d02009-08-18 13:23:37 +0100276}
277
Thomas Gleixner93f29362011-03-23 21:08:47 +0000278static int bcm63xx_external_irq_set_type(struct irq_data *d,
Maxime Bizone7300d02009-08-18 13:23:37 +0100279 unsigned int flow_type)
280{
Maxime Bizon37c42a72011-11-04 19:09:32 +0100281 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
Maxime Bizon62248922011-11-04 19:09:34 +0100282 u32 reg, regaddr;
283 int levelsense, sense, bothedge;
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200284 unsigned long flags;
Maxime Bizone7300d02009-08-18 13:23:37 +0100285
286 flow_type &= IRQ_TYPE_SENSE_MASK;
287
288 if (flow_type == IRQ_TYPE_NONE)
289 flow_type = IRQ_TYPE_LEVEL_LOW;
290
Maxime Bizon62248922011-11-04 19:09:34 +0100291 levelsense = sense = bothedge = 0;
Maxime Bizone7300d02009-08-18 13:23:37 +0100292 switch (flow_type) {
293 case IRQ_TYPE_EDGE_BOTH:
Maxime Bizon62248922011-11-04 19:09:34 +0100294 bothedge = 1;
Maxime Bizone7300d02009-08-18 13:23:37 +0100295 break;
296
297 case IRQ_TYPE_EDGE_RISING:
Maxime Bizon62248922011-11-04 19:09:34 +0100298 sense = 1;
Maxime Bizone7300d02009-08-18 13:23:37 +0100299 break;
300
301 case IRQ_TYPE_EDGE_FALLING:
Maxime Bizone7300d02009-08-18 13:23:37 +0100302 break;
303
304 case IRQ_TYPE_LEVEL_HIGH:
Maxime Bizon62248922011-11-04 19:09:34 +0100305 levelsense = 1;
306 sense = 1;
Maxime Bizone7300d02009-08-18 13:23:37 +0100307 break;
308
309 case IRQ_TYPE_LEVEL_LOW:
Maxime Bizon62248922011-11-04 19:09:34 +0100310 levelsense = 1;
Maxime Bizone7300d02009-08-18 13:23:37 +0100311 break;
312
313 default:
Gregory Fong63893ea2015-10-14 04:27:38 -0700314 pr_err("bogus flow type combination given !\n");
Maxime Bizone7300d02009-08-18 13:23:37 +0100315 return -EINVAL;
316 }
Maxime Bizon62248922011-11-04 19:09:34 +0100317
318 regaddr = get_ext_irq_perf_reg(irq);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200319 spin_lock_irqsave(&epic_lock, flags);
Maxime Bizon62248922011-11-04 19:09:34 +0100320 reg = bcm_perf_readl(regaddr);
321 irq %= 4;
322
Maxime Bizon58e380a2012-07-13 07:46:05 +0000323 switch (bcm63xx_get_cpu_id()) {
324 case BCM6348_CPU_ID:
Maxime Bizon62248922011-11-04 19:09:34 +0100325 if (levelsense)
326 reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
327 else
328 reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
329 if (sense)
330 reg |= EXTIRQ_CFG_SENSE_6348(irq);
331 else
332 reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
333 if (bothedge)
334 reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
335 else
336 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
Maxime Bizon58e380a2012-07-13 07:46:05 +0000337 break;
Maxime Bizon62248922011-11-04 19:09:34 +0100338
Florian Fainelli7b933422013-06-18 16:55:40 +0000339 case BCM3368_CPU_ID:
Maxime Bizon58e380a2012-07-13 07:46:05 +0000340 case BCM6328_CPU_ID:
341 case BCM6338_CPU_ID:
342 case BCM6345_CPU_ID:
343 case BCM6358_CPU_ID:
Jonas Gorski2c8aaf72013-03-21 14:03:17 +0000344 case BCM6362_CPU_ID:
Maxime Bizon58e380a2012-07-13 07:46:05 +0000345 case BCM6368_CPU_ID:
Maxime Bizon62248922011-11-04 19:09:34 +0100346 if (levelsense)
347 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
348 else
349 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
350 if (sense)
351 reg |= EXTIRQ_CFG_SENSE(irq);
352 else
353 reg &= ~EXTIRQ_CFG_SENSE(irq);
354 if (bothedge)
355 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
356 else
357 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
Maxime Bizon58e380a2012-07-13 07:46:05 +0000358 break;
359 default:
360 BUG();
Maxime Bizon62248922011-11-04 19:09:34 +0100361 }
362
363 bcm_perf_writel(reg, regaddr);
Jonas Gorski74b8ca32014-07-12 12:49:39 +0200364 spin_unlock_irqrestore(&epic_lock, flags);
Maxime Bizone7300d02009-08-18 13:23:37 +0100365
Thomas Gleixner93f29362011-03-23 21:08:47 +0000366 irqd_set_trigger_type(d, flow_type);
367 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixner91545662015-07-13 20:46:02 +0000368 irq_set_handler_locked(d, handle_level_irq);
Thomas Gleixner93f29362011-03-23 21:08:47 +0000369 else
Thomas Gleixner91545662015-07-13 20:46:02 +0000370 irq_set_handler_locked(d, handle_edge_irq);
Maxime Bizone7300d02009-08-18 13:23:37 +0100371
Thomas Gleixner93f29362011-03-23 21:08:47 +0000372 return IRQ_SET_MASK_OK_NOCOPY;
Maxime Bizone7300d02009-08-18 13:23:37 +0100373}
374
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200375#ifdef CONFIG_SMP
376static int bcm63xx_internal_set_affinity(struct irq_data *data,
377 const struct cpumask *dest,
378 bool force)
379{
380 if (!irqd_irq_disabled(data))
381 internal_irq_unmask(data, dest);
382
383 return 0;
384}
385#endif
386
Maxime Bizone7300d02009-08-18 13:23:37 +0100387static struct irq_chip bcm63xx_internal_irq_chip = {
388 .name = "bcm63xx_ipic",
Thomas Gleixner93f29362011-03-23 21:08:47 +0000389 .irq_mask = bcm63xx_internal_irq_mask,
390 .irq_unmask = bcm63xx_internal_irq_unmask,
Maxime Bizone7300d02009-08-18 13:23:37 +0100391};
392
393static struct irq_chip bcm63xx_external_irq_chip = {
394 .name = "bcm63xx_epic",
Thomas Gleixner93f29362011-03-23 21:08:47 +0000395 .irq_ack = bcm63xx_external_irq_clear,
Maxime Bizone7300d02009-08-18 13:23:37 +0100396
Thomas Gleixner93f29362011-03-23 21:08:47 +0000397 .irq_mask = bcm63xx_external_irq_mask,
398 .irq_unmask = bcm63xx_external_irq_unmask,
Maxime Bizone7300d02009-08-18 13:23:37 +0100399
Thomas Gleixner93f29362011-03-23 21:08:47 +0000400 .irq_set_type = bcm63xx_external_irq_set_type,
Maxime Bizone7300d02009-08-18 13:23:37 +0100401};
402
403static struct irqaction cpu_ip2_cascade_action = {
404 .handler = no_action,
405 .name = "cascade_ip2",
Wu Zhangjin5a4a4ad2011-07-23 12:41:24 +0000406 .flags = IRQF_NO_THREAD,
Maxime Bizone7300d02009-08-18 13:23:37 +0100407};
408
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200409#ifdef CONFIG_SMP
410static struct irqaction cpu_ip3_cascade_action = {
411 .handler = no_action,
412 .name = "cascade_ip3",
413 .flags = IRQF_NO_THREAD,
414};
415#endif
416
Maxime Bizon37c42a72011-11-04 19:09:32 +0100417static struct irqaction cpu_ext_cascade_action = {
418 .handler = no_action,
419 .name = "cascade_extirq",
420 .flags = IRQF_NO_THREAD,
421};
422
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200423static void bcm63xx_init_irq(void)
424{
425 int irq_bits;
426
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200427 irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
428 irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200429 irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
430 irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200431
432 switch (bcm63xx_get_cpu_id()) {
433 case BCM3368_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200434 irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
435 irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200436 irq_stat_addr[1] = 0;
Julia Lawallbbc53672014-08-23 20:33:25 +0200437 irq_mask_addr[1] = 0;
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200438 irq_bits = 32;
439 ext_irq_count = 4;
440 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
441 break;
442 case BCM6328_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200443 irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
444 irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200445 irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
Julia Lawallbbc53672014-08-23 20:33:25 +0200446 irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200447 irq_bits = 64;
448 ext_irq_count = 4;
449 is_ext_irq_cascaded = 1;
450 ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
451 ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
452 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
453 break;
454 case BCM6338_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200455 irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
456 irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200457 irq_stat_addr[1] = 0;
458 irq_mask_addr[1] = 0;
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200459 irq_bits = 32;
460 ext_irq_count = 4;
461 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
462 break;
463 case BCM6345_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200464 irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
465 irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200466 irq_stat_addr[1] = 0;
467 irq_mask_addr[1] = 0;
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200468 irq_bits = 32;
469 ext_irq_count = 4;
470 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
471 break;
472 case BCM6348_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200473 irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
474 irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200475 irq_stat_addr[1] = 0;
476 irq_mask_addr[1] = 0;
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200477 irq_bits = 32;
478 ext_irq_count = 4;
479 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
480 break;
481 case BCM6358_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200482 irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
483 irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200484 irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
485 irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200486 irq_bits = 32;
487 ext_irq_count = 4;
488 is_ext_irq_cascaded = 1;
489 ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
490 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
491 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
492 break;
493 case BCM6362_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200494 irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
495 irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200496 irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
497 irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200498 irq_bits = 64;
499 ext_irq_count = 4;
500 is_ext_irq_cascaded = 1;
501 ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
502 ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
503 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
504 break;
505 case BCM6368_CPU_ID:
Jonas Gorskicc81d7f2014-07-12 12:49:36 +0200506 irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
507 irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
Jonas Gorski3534b5c2014-07-12 12:49:37 +0200508 irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
509 irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
Jonas Gorskia6dfde82014-07-12 12:49:34 +0200510 irq_bits = 64;
511 ext_irq_count = 6;
512 is_ext_irq_cascaded = 1;
513 ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
514 ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
515 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
516 ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
517 break;
518 default:
519 BUG();
520 }
521
522 if (irq_bits == 32) {
523 dispatch_internal = __dispatch_internal_32;
524 internal_irq_mask = __internal_irq_mask_32;
525 internal_irq_unmask = __internal_irq_unmask_32;
526 } else {
527 dispatch_internal = __dispatch_internal_64;
528 internal_irq_mask = __internal_irq_mask_64;
529 internal_irq_unmask = __internal_irq_unmask_64;
530 }
531}
532
Maxime Bizone7300d02009-08-18 13:23:37 +0100533void __init arch_init_irq(void)
534{
535 int i;
536
Maxime Bizonf61cced2011-11-04 19:09:31 +0100537 bcm63xx_init_irq();
Maxime Bizone7300d02009-08-18 13:23:37 +0100538 mips_cpu_irq_init();
539 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200540 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
Maxime Bizone7300d02009-08-18 13:23:37 +0100541 handle_level_irq);
542
Maxime Bizon62248922011-11-04 19:09:34 +0100543 for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200544 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
Maxime Bizone7300d02009-08-18 13:23:37 +0100545 handle_edge_irq);
546
Maxime Bizon37c42a72011-11-04 19:09:32 +0100547 if (!is_ext_irq_cascaded) {
Maxime Bizon62248922011-11-04 19:09:34 +0100548 for (i = 3; i < 3 + ext_irq_count; ++i)
Maxime Bizon37c42a72011-11-04 19:09:32 +0100549 setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
550 }
551
552 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200553#ifdef CONFIG_SMP
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200554 if (is_ext_irq_cascaded) {
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200555 setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
Jonas Gorskib37f0f62014-07-12 12:49:42 +0200556 bcm63xx_internal_irq_chip.irq_set_affinity =
557 bcm63xx_internal_set_affinity;
558
559 cpumask_clear(irq_default_affinity);
560 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
561 }
Jonas Gorski56d53ea2014-07-12 12:49:40 +0200562#endif
Maxime Bizone7300d02009-08-18 13:23:37 +0100563}