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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaa7e16d2005-08-29 15:12:56 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040022 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
Robert Hancockfbbb2622006-10-27 19:08:41 -070032 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/kernel.h>
40#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090041#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050046#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <scsi/scsi_host.h>
Robert Hancockfbbb2622006-10-27 19:08:41 -070048#include <scsi/scsi_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <linux/libata.h>
50
51#define DRV_NAME "sata_nv"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040052#define DRV_VERSION "3.5"
Robert Hancockfbbb2622006-10-27 19:08:41 -070053
54#define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Jeff Garzik10ad05d2006-03-22 23:50:50 -050056enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090057 NV_MMIO_BAR = 5,
58
Jeff Garzik10ad05d2006-03-22 23:50:50 -050059 NV_PORTS = 2,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +010060 NV_PIO_MASK = ATA_PIO4,
61 NV_MWDMA_MASK = ATA_MWDMA2,
62 NV_UDMA_MASK = ATA_UDMA6,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050063 NV_PORT0_SCR_REG_OFFSET = 0x00,
64 NV_PORT1_SCR_REG_OFFSET = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Tejun Heo27e4b272006-06-17 15:49:55 +090066 /* INT_STATUS/ENABLE */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050067 NV_INT_STATUS = 0x10,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050068 NV_INT_ENABLE = 0x11,
Tejun Heo27e4b272006-06-17 15:49:55 +090069 NV_INT_STATUS_CK804 = 0x440,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050070 NV_INT_ENABLE_CK804 = 0x441,
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Tejun Heo27e4b272006-06-17 15:49:55 +090072 /* INT_STATUS/ENABLE bits */
73 NV_INT_DEV = 0x01,
74 NV_INT_PM = 0x02,
75 NV_INT_ADDED = 0x04,
76 NV_INT_REMOVED = 0x08,
77
78 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79
Tejun Heo39f87582006-06-17 15:49:56 +090080 NV_INT_ALL = 0x0f,
Tejun Heo5a44eff2006-06-17 15:49:56 +090081 NV_INT_MASK = NV_INT_DEV |
82 NV_INT_ADDED | NV_INT_REMOVED,
Tejun Heo39f87582006-06-17 15:49:56 +090083
Tejun Heo27e4b272006-06-17 15:49:55 +090084 /* INT_CONFIG */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050085 NV_INT_CONFIG = 0x12,
86 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
Jeff Garzik10ad05d2006-03-22 23:50:50 -050088 // For PCI config register 20
89 NV_MCP_SATA_CFG_20 = 0x50,
90 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
Robert Hancockfbbb2622006-10-27 19:08:41 -070091 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
92 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
93 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
94 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
95
96 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_CPB_SZ = 128,
98 NV_ADMA_APRD_SZ = 16,
99 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
100 NV_ADMA_APRD_SZ,
101 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
102 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
103 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
104 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
105
106 /* BAR5 offset to ADMA general registers */
107 NV_ADMA_GEN = 0x400,
108 NV_ADMA_GEN_CTL = 0x00,
109 NV_ADMA_NOTIFIER_CLEAR = 0x30,
110
111 /* BAR5 offset to ADMA ports */
112 NV_ADMA_PORT = 0x480,
113
114 /* size of ADMA port register space */
115 NV_ADMA_PORT_SIZE = 0x100,
116
117 /* ADMA port registers */
118 NV_ADMA_CTL = 0x40,
119 NV_ADMA_CPB_COUNT = 0x42,
120 NV_ADMA_NEXT_CPB_IDX = 0x43,
121 NV_ADMA_STAT = 0x44,
122 NV_ADMA_CPB_BASE_LOW = 0x48,
123 NV_ADMA_CPB_BASE_HIGH = 0x4C,
124 NV_ADMA_APPEND = 0x50,
125 NV_ADMA_NOTIFIER = 0x68,
126 NV_ADMA_NOTIFIER_ERROR = 0x6C,
127
128 /* NV_ADMA_CTL register bits */
129 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
130 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
131 NV_ADMA_CTL_GO = (1 << 7),
132 NV_ADMA_CTL_AIEN = (1 << 8),
133 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
134 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
135
136 /* CPB response flag bits */
137 NV_CPB_RESP_DONE = (1 << 0),
138 NV_CPB_RESP_ATA_ERR = (1 << 3),
139 NV_CPB_RESP_CMD_ERR = (1 << 4),
140 NV_CPB_RESP_CPB_ERR = (1 << 7),
141
142 /* CPB control flag bits */
143 NV_CPB_CTL_CPB_VALID = (1 << 0),
144 NV_CPB_CTL_QUEUE = (1 << 1),
145 NV_CPB_CTL_APRD_VALID = (1 << 2),
146 NV_CPB_CTL_IEN = (1 << 3),
147 NV_CPB_CTL_FPDMA = (1 << 4),
148
149 /* APRD flags */
150 NV_APRD_WRITE = (1 << 1),
151 NV_APRD_END = (1 << 2),
152 NV_APRD_CONT = (1 << 3),
153
154 /* NV_ADMA_STAT flags */
155 NV_ADMA_STAT_TIMEOUT = (1 << 0),
156 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
157 NV_ADMA_STAT_HOTPLUG = (1 << 2),
158 NV_ADMA_STAT_CPBERR = (1 << 4),
159 NV_ADMA_STAT_SERROR = (1 << 5),
160 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
161 NV_ADMA_STAT_IDLE = (1 << 8),
162 NV_ADMA_STAT_LEGACY = (1 << 9),
163 NV_ADMA_STAT_STOPPED = (1 << 10),
164 NV_ADMA_STAT_DONE = (1 << 12),
165 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400166 NV_ADMA_STAT_TIMEOUT,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700167
168 /* port flags */
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
Robert Hancock2dec7552006-11-26 14:20:19 -0600170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700171
Kuan Luof140f0f2007-10-15 15:16:53 -0400172 /* MCP55 reg offset */
173 NV_CTL_MCP55 = 0x400,
174 NV_INT_STATUS_MCP55 = 0x440,
175 NV_INT_ENABLE_MCP55 = 0x444,
176 NV_NCQ_REG_MCP55 = 0x448,
177
178 /* MCP55 */
179 NV_INT_ALL_MCP55 = 0xffff,
180 NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */
181 NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd,
182
183 /* SWNCQ ENABLE BITS*/
184 NV_CTL_PRI_SWNCQ = 0x02,
185 NV_CTL_SEC_SWNCQ = 0x04,
186
187 /* SW NCQ status bits*/
188 NV_SWNCQ_IRQ_DEV = (1 << 0),
189 NV_SWNCQ_IRQ_PM = (1 << 1),
190 NV_SWNCQ_IRQ_ADDED = (1 << 2),
191 NV_SWNCQ_IRQ_REMOVED = (1 << 3),
192
193 NV_SWNCQ_IRQ_BACKOUT = (1 << 4),
194 NV_SWNCQ_IRQ_SDBFIS = (1 << 5),
195 NV_SWNCQ_IRQ_DHREGFIS = (1 << 6),
196 NV_SWNCQ_IRQ_DMASETUP = (1 << 7),
197
198 NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED |
199 NV_SWNCQ_IRQ_REMOVED,
200
Jeff Garzik10ad05d2006-03-22 23:50:50 -0500201};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202
Robert Hancockfbbb2622006-10-27 19:08:41 -0700203/* ADMA Physical Region Descriptor - one SG segment */
204struct nv_adma_prd {
205 __le64 addr;
206 __le32 len;
207 u8 flags;
208 u8 packet_len;
209 __le16 reserved;
210};
211
212enum nv_adma_regbits {
213 CMDEND = (1 << 15), /* end of command list */
214 WNB = (1 << 14), /* wait-not-BSY */
215 IGN = (1 << 13), /* ignore this entry */
216 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
217 DA2 = (1 << (2 + 8)),
218 DA1 = (1 << (1 + 8)),
219 DA0 = (1 << (0 + 8)),
220};
221
222/* ADMA Command Parameter Block
223 The first 5 SG segments are stored inside the Command Parameter Block itself.
224 If there are more than 5 segments the remainder are stored in a separate
225 memory area indicated by next_aprd. */
226struct nv_adma_cpb {
227 u8 resp_flags; /* 0 */
228 u8 reserved1; /* 1 */
229 u8 ctl_flags; /* 2 */
230 /* len is length of taskfile in 64 bit words */
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400231 u8 len; /* 3 */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700232 u8 tag; /* 4 */
233 u8 next_cpb_idx; /* 5 */
234 __le16 reserved2; /* 6-7 */
235 __le16 tf[12]; /* 8-31 */
236 struct nv_adma_prd aprd[5]; /* 32-111 */
237 __le64 next_aprd; /* 112-119 */
238 __le64 reserved3; /* 120-127 */
239};
240
241
242struct nv_adma_port_priv {
243 struct nv_adma_cpb *cpb;
244 dma_addr_t cpb_dma;
245 struct nv_adma_prd *aprd;
246 dma_addr_t aprd_dma;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400247 void __iomem *ctl_block;
248 void __iomem *gen_block;
249 void __iomem *notifier_clear_block;
Robert Hancock8959d302008-02-04 19:39:02 -0600250 u64 adma_dma_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700251 u8 flags;
Robert Hancock5e5c74a2007-02-19 18:42:30 -0600252 int last_issue_ncq;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700253};
254
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600255struct nv_host_priv {
256 unsigned long type;
257};
258
Kuan Luof140f0f2007-10-15 15:16:53 -0400259struct defer_queue {
260 u32 defer_bits;
261 unsigned int head;
262 unsigned int tail;
263 unsigned int tag[ATA_MAX_QUEUE];
264};
265
266enum ncq_saw_flag_list {
267 ncq_saw_d2h = (1U << 0),
268 ncq_saw_dmas = (1U << 1),
269 ncq_saw_sdb = (1U << 2),
270 ncq_saw_backout = (1U << 3),
271};
272
273struct nv_swncq_port_priv {
Tejun Heof60d7012010-05-10 21:41:41 +0200274 struct ata_bmdma_prd *prd; /* our SG list */
Kuan Luof140f0f2007-10-15 15:16:53 -0400275 dma_addr_t prd_dma; /* and its DMA mapping */
276 void __iomem *sactive_block;
277 void __iomem *irq_block;
278 void __iomem *tag_block;
279 u32 qc_active;
280
281 unsigned int last_issue_tag;
282
283 /* fifo circular queue to store deferral command */
284 struct defer_queue defer_queue;
285
286 /* for NCQ interrupt analysis */
287 u32 dhfis_bits;
288 u32 dmafis_bits;
289 u32 sdbfis_bits;
290
291 unsigned int ncq_flags;
292};
293
294
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400295#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
Robert Hancockfbbb2622006-10-27 19:08:41 -0700296
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400297static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +0200298#ifdef CONFIG_PM_SLEEP
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600299static int nv_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900300#endif
Jeff Garzikcca39742006-08-24 03:19:22 -0400301static void nv_ck804_host_stop(struct ata_host *host);
David Howells7d12e782006-10-05 14:55:46 +0100302static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
303static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
304static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900305static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
306static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307
Tejun Heo7f4774b2009-06-10 16:29:07 +0900308static int nv_hardreset(struct ata_link *link, unsigned int *class,
309 unsigned long deadline);
Tejun Heo39f87582006-06-17 15:49:56 +0900310static void nv_nf2_freeze(struct ata_port *ap);
311static void nv_nf2_thaw(struct ata_port *ap);
312static void nv_ck804_freeze(struct ata_port *ap);
313static void nv_ck804_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700314static int nv_adma_slave_config(struct scsi_device *sdev);
Robert Hancock2dec7552006-11-26 14:20:19 -0600315static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700316static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
317static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
318static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
319static void nv_adma_irq_clear(struct ata_port *ap);
320static int nv_adma_port_start(struct ata_port *ap);
321static void nv_adma_port_stop(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900322#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600323static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
324static int nv_adma_port_resume(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900325#endif
Robert Hancock53014e22007-05-05 15:36:36 -0600326static void nv_adma_freeze(struct ata_port *ap);
327static void nv_adma_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700328static void nv_adma_error_handler(struct ata_port *ap);
329static void nv_adma_host_stop(struct ata_host *host);
Robert Hancockf5ecac22007-02-20 21:49:10 -0600330static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800331static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
Tejun Heo39f87582006-06-17 15:49:56 +0900332
Kuan Luof140f0f2007-10-15 15:16:53 -0400333static void nv_mcp55_thaw(struct ata_port *ap);
334static void nv_mcp55_freeze(struct ata_port *ap);
335static void nv_swncq_error_handler(struct ata_port *ap);
336static int nv_swncq_slave_config(struct scsi_device *sdev);
337static int nv_swncq_port_start(struct ata_port *ap);
338static void nv_swncq_qc_prep(struct ata_queued_cmd *qc);
339static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
340static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc);
341static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis);
342static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance);
343#ifdef CONFIG_PM
344static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg);
345static int nv_swncq_port_resume(struct ata_port *ap);
346#endif
347
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348enum nv_host_type
349{
350 GENERIC,
351 NFORCE2,
Tejun Heo27e4b272006-06-17 15:49:55 +0900352 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700353 CK804,
Kuan Luof140f0f2007-10-15 15:16:53 -0400354 ADMA,
Tejun Heo2d775702009-01-25 11:29:38 +0900355 MCP5x,
Kuan Luof140f0f2007-10-15 15:16:53 -0400356 SWNCQ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357};
358
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500359static const struct pci_device_id nv_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400360 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
361 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
362 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
363 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
Tejun Heo2d775702009-01-25 11:29:38 +0900367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x },
368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x },
369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x },
370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x },
Kuan Luoe2e031e2007-10-25 02:14:17 -0400371 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
372 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
373 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400374
375 { } /* terminate list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376};
377
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378static struct pci_driver nv_pci_driver = {
379 .name = DRV_NAME,
380 .id_table = nv_pci_tbl,
381 .probe = nv_init_one,
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +0200382#ifdef CONFIG_PM_SLEEP
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600383 .suspend = ata_pci_device_suspend,
384 .resume = nv_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900385#endif
Tejun Heo1daf9ce2007-05-17 13:13:57 +0200386 .remove = ata_pci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387};
388
Jeff Garzik193515d2005-11-07 00:59:37 -0500389static struct scsi_host_template nv_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900390 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391};
392
Robert Hancockfbbb2622006-10-27 19:08:41 -0700393static struct scsi_host_template nv_adma_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900394 ATA_NCQ_SHT(DRV_NAME),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700395 .can_queue = NV_ADMA_MAX_CPBS,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700396 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700397 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
398 .slave_configure = nv_adma_slave_config,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700399};
400
Kuan Luof140f0f2007-10-15 15:16:53 -0400401static struct scsi_host_template nv_swncq_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900402 ATA_NCQ_SHT(DRV_NAME),
Kuan Luof140f0f2007-10-15 15:16:53 -0400403 .can_queue = ATA_MAX_QUEUE,
Kuan Luof140f0f2007-10-15 15:16:53 -0400404 .sg_tablesize = LIBATA_MAX_PRD,
Kuan Luof140f0f2007-10-15 15:16:53 -0400405 .dma_boundary = ATA_DMA_BOUNDARY,
406 .slave_configure = nv_swncq_slave_config,
Kuan Luof140f0f2007-10-15 15:16:53 -0400407};
408
Tejun Heo7f4774b2009-06-10 16:29:07 +0900409/*
410 * NV SATA controllers have various different problems with hardreset
411 * protocol depending on the specific controller and device.
412 *
413 * GENERIC:
414 *
415 * bko11195 reports that link doesn't come online after hardreset on
416 * generic nv's and there have been several other similar reports on
417 * linux-ide.
418 *
419 * bko12351#c23 reports that warmplug on MCP61 doesn't work with
420 * softreset.
421 *
422 * NF2/3:
423 *
424 * bko3352 reports nf2/3 controllers can't determine device signature
425 * reliably after hardreset. The following thread reports detection
426 * failure on cold boot with the standard debouncing timing.
427 *
428 * http://thread.gmane.org/gmane.linux.ide/34098
429 *
430 * bko12176 reports that hardreset fails to bring up the link during
431 * boot on nf2.
432 *
433 * CK804:
434 *
435 * For initial probing after boot and hot plugging, hardreset mostly
436 * works fine on CK804 but curiously, reprobing on the initial port
437 * by rescanning or rmmod/insmod fails to acquire the initial D2H Reg
438 * FIS in somewhat undeterministic way.
439 *
440 * SWNCQ:
441 *
442 * bko12351 reports that when SWNCQ is enabled, for hotplug to work,
443 * hardreset should be used and hardreset can't report proper
444 * signature, which suggests that mcp5x is closer to nf2 as long as
445 * reset quirkiness is concerned.
446 *
447 * bko12703 reports that boot probing fails for intel SSD with
448 * hardreset. Link fails to come online. Softreset works fine.
449 *
450 * The failures are varied but the following patterns seem true for
451 * all flavors.
452 *
453 * - Softreset during boot always works.
454 *
455 * - Hardreset during boot sometimes fails to bring up the link on
456 * certain comibnations and device signature acquisition is
457 * unreliable.
458 *
459 * - Hardreset is often necessary after hotplug.
460 *
461 * So, preferring softreset for boot probing and error handling (as
462 * hardreset might bring down the link) but using hardreset for
463 * post-boot probing should work around the above issues in most
464 * cases. Define nv_hardreset() which only kicks in for post-boot
465 * probing and use it for all variants.
466 */
467static struct ata_port_operations nv_generic_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900468 .inherits = &ata_bmdma_port_ops,
Alan Coxc96f1732009-03-24 10:23:46 +0000469 .lost_interrupt = ATA_OP_NULL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 .scr_read = nv_scr_read,
471 .scr_write = nv_scr_write,
Tejun Heo7f4774b2009-06-10 16:29:07 +0900472 .hardreset = nv_hardreset,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473};
474
Tejun Heo029cfd62008-03-25 12:22:49 +0900475static struct ata_port_operations nv_nf2_ops = {
Tejun Heo7dac7452009-02-12 10:34:32 +0900476 .inherits = &nv_generic_ops,
Tejun Heo39f87582006-06-17 15:49:56 +0900477 .freeze = nv_nf2_freeze,
478 .thaw = nv_nf2_thaw,
Tejun Heoada364e2006-06-17 15:49:56 +0900479};
480
Tejun Heo029cfd62008-03-25 12:22:49 +0900481static struct ata_port_operations nv_ck804_ops = {
Tejun Heo7f4774b2009-06-10 16:29:07 +0900482 .inherits = &nv_generic_ops,
Tejun Heo39f87582006-06-17 15:49:56 +0900483 .freeze = nv_ck804_freeze,
484 .thaw = nv_ck804_thaw,
Tejun Heoada364e2006-06-17 15:49:56 +0900485 .host_stop = nv_ck804_host_stop,
486};
487
Tejun Heo029cfd62008-03-25 12:22:49 +0900488static struct ata_port_operations nv_adma_ops = {
Tejun Heo3c324282008-11-03 12:37:49 +0900489 .inherits = &nv_ck804_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900490
Robert Hancock2dec7552006-11-26 14:20:19 -0600491 .check_atapi_dma = nv_adma_check_atapi_dma,
Tejun Heo5682ed32008-04-07 22:47:16 +0900492 .sff_tf_read = nv_adma_tf_read,
Tejun Heo31cc23b2007-09-23 13:14:12 +0900493 .qc_defer = ata_std_qc_defer,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700494 .qc_prep = nv_adma_qc_prep,
495 .qc_issue = nv_adma_qc_issue,
Tejun Heo5682ed32008-04-07 22:47:16 +0900496 .sff_irq_clear = nv_adma_irq_clear,
Tejun Heo029cfd62008-03-25 12:22:49 +0900497
Robert Hancock53014e22007-05-05 15:36:36 -0600498 .freeze = nv_adma_freeze,
499 .thaw = nv_adma_thaw,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700500 .error_handler = nv_adma_error_handler,
Robert Hancockf5ecac22007-02-20 21:49:10 -0600501 .post_internal_cmd = nv_adma_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900502
Robert Hancockfbbb2622006-10-27 19:08:41 -0700503 .port_start = nv_adma_port_start,
504 .port_stop = nv_adma_port_stop,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900505#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600506 .port_suspend = nv_adma_port_suspend,
507 .port_resume = nv_adma_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900508#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -0700509 .host_stop = nv_adma_host_stop,
510};
511
Tejun Heo029cfd62008-03-25 12:22:49 +0900512static struct ata_port_operations nv_swncq_ops = {
Tejun Heo7f4774b2009-06-10 16:29:07 +0900513 .inherits = &nv_generic_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900514
Kuan Luof140f0f2007-10-15 15:16:53 -0400515 .qc_defer = ata_std_qc_defer,
516 .qc_prep = nv_swncq_qc_prep,
517 .qc_issue = nv_swncq_qc_issue,
Tejun Heo029cfd62008-03-25 12:22:49 +0900518
Kuan Luof140f0f2007-10-15 15:16:53 -0400519 .freeze = nv_mcp55_freeze,
520 .thaw = nv_mcp55_thaw,
521 .error_handler = nv_swncq_error_handler,
Tejun Heo029cfd62008-03-25 12:22:49 +0900522
Kuan Luof140f0f2007-10-15 15:16:53 -0400523#ifdef CONFIG_PM
524 .port_suspend = nv_swncq_port_suspend,
525 .port_resume = nv_swncq_port_resume,
526#endif
527 .port_start = nv_swncq_port_start,
528};
529
Tejun Heo95947192008-03-25 12:22:49 +0900530struct nv_pi_priv {
531 irq_handler_t irq_handler;
532 struct scsi_host_template *sht;
533};
534
535#define NV_PI_PRIV(_irq_handler, _sht) \
536 &(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht }
537
Tejun Heo1626aeb2007-05-04 12:43:58 +0200538static const struct ata_port_info nv_port_info[] = {
Tejun Heoada364e2006-06-17 15:49:56 +0900539 /* generic */
540 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300541 .flags = ATA_FLAG_SATA,
Tejun Heoada364e2006-06-17 15:49:56 +0900542 .pio_mask = NV_PIO_MASK,
543 .mwdma_mask = NV_MWDMA_MASK,
544 .udma_mask = NV_UDMA_MASK,
545 .port_ops = &nv_generic_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900546 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900547 },
548 /* nforce2/3 */
549 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300550 .flags = ATA_FLAG_SATA,
Tejun Heoada364e2006-06-17 15:49:56 +0900551 .pio_mask = NV_PIO_MASK,
552 .mwdma_mask = NV_MWDMA_MASK,
553 .udma_mask = NV_UDMA_MASK,
554 .port_ops = &nv_nf2_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900555 .private_data = NV_PI_PRIV(nv_nf2_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900556 },
557 /* ck804 */
558 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300559 .flags = ATA_FLAG_SATA,
Tejun Heoada364e2006-06-17 15:49:56 +0900560 .pio_mask = NV_PIO_MASK,
561 .mwdma_mask = NV_MWDMA_MASK,
562 .udma_mask = NV_UDMA_MASK,
563 .port_ops = &nv_ck804_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900564 .private_data = NV_PI_PRIV(nv_ck804_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900565 },
Robert Hancockfbbb2622006-10-27 19:08:41 -0700566 /* ADMA */
567 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300568 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700569 .pio_mask = NV_PIO_MASK,
570 .mwdma_mask = NV_MWDMA_MASK,
571 .udma_mask = NV_UDMA_MASK,
572 .port_ops = &nv_adma_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900573 .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700574 },
Tejun Heo2d775702009-01-25 11:29:38 +0900575 /* MCP5x */
576 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300577 .flags = ATA_FLAG_SATA,
Tejun Heo2d775702009-01-25 11:29:38 +0900578 .pio_mask = NV_PIO_MASK,
579 .mwdma_mask = NV_MWDMA_MASK,
580 .udma_mask = NV_UDMA_MASK,
Tejun Heo7f4774b2009-06-10 16:29:07 +0900581 .port_ops = &nv_generic_ops,
Tejun Heo2d775702009-01-25 11:29:38 +0900582 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
583 },
Kuan Luof140f0f2007-10-15 15:16:53 -0400584 /* SWNCQ */
585 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300586 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
Kuan Luof140f0f2007-10-15 15:16:53 -0400587 .pio_mask = NV_PIO_MASK,
588 .mwdma_mask = NV_MWDMA_MASK,
589 .udma_mask = NV_UDMA_MASK,
590 .port_ops = &nv_swncq_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900591 .private_data = NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht),
Kuan Luof140f0f2007-10-15 15:16:53 -0400592 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593};
594
595MODULE_AUTHOR("NVIDIA");
596MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
597MODULE_LICENSE("GPL");
598MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
599MODULE_VERSION(DRV_VERSION);
600
Rusty Russell90ab5ee2012-01-13 09:32:20 +1030601static bool adma_enabled;
602static bool swncq_enabled = 1;
603static bool msi_enabled;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700604
Robert Hancock2dec7552006-11-26 14:20:19 -0600605static void nv_adma_register_mode(struct ata_port *ap)
606{
Robert Hancock2dec7552006-11-26 14:20:19 -0600607 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600608 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800609 u16 tmp, status;
610 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600611
612 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
613 return;
614
Robert Hancocka2cfe812007-02-05 16:26:03 -0800615 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400616 while (!(status & NV_ADMA_STAT_IDLE) && count < 20) {
Robert Hancocka2cfe812007-02-05 16:26:03 -0800617 ndelay(50);
618 status = readw(mmio + NV_ADMA_STAT);
619 count++;
620 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400621 if (count == 20)
Joe Perchesa9a79df2011-04-15 15:51:59 -0700622 ata_port_warn(ap, "timeout waiting for ADMA IDLE, stat=0x%hx\n",
623 status);
Robert Hancocka2cfe812007-02-05 16:26:03 -0800624
Robert Hancock2dec7552006-11-26 14:20:19 -0600625 tmp = readw(mmio + NV_ADMA_CTL);
626 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
627
Robert Hancocka2cfe812007-02-05 16:26:03 -0800628 count = 0;
629 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400630 while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
Robert Hancocka2cfe812007-02-05 16:26:03 -0800631 ndelay(50);
632 status = readw(mmio + NV_ADMA_STAT);
633 count++;
634 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400635 if (count == 20)
Joe Perchesa9a79df2011-04-15 15:51:59 -0700636 ata_port_warn(ap,
637 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
638 status);
Robert Hancocka2cfe812007-02-05 16:26:03 -0800639
Robert Hancock2dec7552006-11-26 14:20:19 -0600640 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
641}
642
643static void nv_adma_mode(struct ata_port *ap)
644{
Robert Hancock2dec7552006-11-26 14:20:19 -0600645 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600646 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800647 u16 tmp, status;
648 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600649
650 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
651 return;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500652
Robert Hancock2dec7552006-11-26 14:20:19 -0600653 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
654
655 tmp = readw(mmio + NV_ADMA_CTL);
656 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
657
Robert Hancocka2cfe812007-02-05 16:26:03 -0800658 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400659 while (((status & NV_ADMA_STAT_LEGACY) ||
Robert Hancocka2cfe812007-02-05 16:26:03 -0800660 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
661 ndelay(50);
662 status = readw(mmio + NV_ADMA_STAT);
663 count++;
664 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400665 if (count == 20)
Joe Perchesa9a79df2011-04-15 15:51:59 -0700666 ata_port_warn(ap,
Robert Hancocka2cfe812007-02-05 16:26:03 -0800667 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
668 status);
669
Robert Hancock2dec7552006-11-26 14:20:19 -0600670 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
671}
672
Robert Hancockfbbb2622006-10-27 19:08:41 -0700673static int nv_adma_slave_config(struct scsi_device *sdev)
674{
675 struct ata_port *ap = ata_shost_to_port(sdev->host);
Robert Hancock2dec7552006-11-26 14:20:19 -0600676 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock8959d302008-02-04 19:39:02 -0600677 struct nv_adma_port_priv *port0, *port1;
678 struct scsi_device *sdev0, *sdev1;
Robert Hancock2dec7552006-11-26 14:20:19 -0600679 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Robert Hancock8959d302008-02-04 19:39:02 -0600680 unsigned long segment_boundary, flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700681 unsigned short sg_tablesize;
682 int rc;
Robert Hancock2dec7552006-11-26 14:20:19 -0600683 int adma_enable;
684 u32 current_reg, new_reg, config_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700685
686 rc = ata_scsi_slave_config(sdev);
687
688 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
689 /* Not a proper libata device, ignore */
690 return rc;
691
Robert Hancock8959d302008-02-04 19:39:02 -0600692 spin_lock_irqsave(ap->lock, flags);
693
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900694 if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700695 /*
696 * NVIDIA reports that ADMA mode does not support ATAPI commands.
697 * Therefore ATAPI commands are sent through the legacy interface.
698 * However, the legacy interface only supports 32-bit DMA.
699 * Restrict DMA parameters as required by the legacy interface
700 * when an ATAPI device is connected.
701 */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700702 segment_boundary = ATA_DMA_BOUNDARY;
703 /* Subtract 1 since an extra entry may be needed for padding, see
704 libata-scsi.c */
705 sg_tablesize = LIBATA_MAX_PRD - 1;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500706
Robert Hancock2dec7552006-11-26 14:20:19 -0600707 /* Since the legacy DMA engine is in use, we need to disable ADMA
708 on the port. */
709 adma_enable = 0;
710 nv_adma_register_mode(ap);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400711 } else {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700712 segment_boundary = NV_ADMA_DMA_BOUNDARY;
713 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
Robert Hancock2dec7552006-11-26 14:20:19 -0600714 adma_enable = 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700715 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500716
Robert Hancock2dec7552006-11-26 14:20:19 -0600717 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700718
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400719 if (ap->port_no == 1)
Robert Hancock2dec7552006-11-26 14:20:19 -0600720 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
721 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
722 else
723 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
724 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500725
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400726 if (adma_enable) {
Robert Hancock2dec7552006-11-26 14:20:19 -0600727 new_reg = current_reg | config_mask;
728 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400729 } else {
Robert Hancock2dec7552006-11-26 14:20:19 -0600730 new_reg = current_reg & ~config_mask;
731 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
732 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500733
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400734 if (current_reg != new_reg)
Robert Hancock2dec7552006-11-26 14:20:19 -0600735 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500736
Robert Hancock8959d302008-02-04 19:39:02 -0600737 port0 = ap->host->ports[0]->private_data;
738 port1 = ap->host->ports[1]->private_data;
739 sdev0 = ap->host->ports[0]->link.device[0].sdev;
740 sdev1 = ap->host->ports[1]->link.device[0].sdev;
741 if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
742 (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) {
743 /** We have to set the DMA mask to 32-bit if either port is in
744 ATAPI mode, since they are on the same PCI device which is
745 used for DMA mapping. If we set the mask we also need to set
746 the bounce limit on both ports to ensure that the block
747 layer doesn't feed addresses that cause DMA mapping to
748 choke. If either SCSI device is not allocated yet, it's OK
749 since that port will discover its correct setting when it
750 does get allocated.
751 Note: Setting 32-bit mask should not fail. */
752 if (sdev0)
753 blk_queue_bounce_limit(sdev0->request_queue,
754 ATA_DMA_MASK);
755 if (sdev1)
756 blk_queue_bounce_limit(sdev1->request_queue,
757 ATA_DMA_MASK);
758
759 pci_set_dma_mask(pdev, ATA_DMA_MASK);
760 } else {
761 /** This shouldn't fail as it was set to this value before */
762 pci_set_dma_mask(pdev, pp->adma_dma_mask);
763 if (sdev0)
764 blk_queue_bounce_limit(sdev0->request_queue,
765 pp->adma_dma_mask);
766 if (sdev1)
767 blk_queue_bounce_limit(sdev1->request_queue,
768 pp->adma_dma_mask);
769 }
770
Robert Hancockfbbb2622006-10-27 19:08:41 -0700771 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
Martin K. Petersen8a783622010-02-26 00:20:39 -0500772 blk_queue_max_segments(sdev->request_queue, sg_tablesize);
Joe Perchesa9a79df2011-04-15 15:51:59 -0700773 ata_port_info(ap,
774 "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
775 (unsigned long long)*ap->host->dev->dma_mask,
776 segment_boundary, sg_tablesize);
Robert Hancock8959d302008-02-04 19:39:02 -0600777
778 spin_unlock_irqrestore(ap->lock, flags);
779
Robert Hancockfbbb2622006-10-27 19:08:41 -0700780 return rc;
781}
782
Robert Hancock2dec7552006-11-26 14:20:19 -0600783static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
784{
785 struct nv_adma_port_priv *pp = qc->ap->private_data;
786 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
787}
788
Robert Hancockf2fb3442007-03-26 21:43:36 -0800789static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
790{
Robert Hancock3f3debd2007-11-25 16:59:36 -0600791 /* Other than when internal or pass-through commands are executed,
792 the only time this function will be called in ADMA mode will be
793 if a command fails. In the failure case we don't care about going
794 into register mode with ADMA commands pending, as the commands will
795 all shortly be aborted anyway. We assume that NCQ commands are not
796 issued via passthrough, which is the only way that switching into
797 ADMA mode could abort outstanding commands. */
Robert Hancockf2fb3442007-03-26 21:43:36 -0800798 nv_adma_register_mode(ap);
799
Tejun Heo9363c382008-04-07 22:47:16 +0900800 ata_sff_tf_read(ap, tf);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800801}
802
Robert Hancock2dec7552006-11-26 14:20:19 -0600803static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700804{
805 unsigned int idx = 0;
806
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400807 if (tf->flags & ATA_TFLAG_ISADDR) {
Robert Hancockac3d6b82007-02-19 19:02:46 -0600808 if (tf->flags & ATA_TFLAG_LBA48) {
809 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB);
810 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
811 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
812 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
813 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
814 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
815 } else
816 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB);
Jeff Garzika84471f2007-02-26 05:51:33 -0500817
Robert Hancockac3d6b82007-02-19 19:02:46 -0600818 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
819 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
820 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
821 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700822 }
Jeff Garzika84471f2007-02-26 05:51:33 -0500823
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400824 if (tf->flags & ATA_TFLAG_DEVICE)
Robert Hancockac3d6b82007-02-19 19:02:46 -0600825 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700826
827 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
Jeff Garzika84471f2007-02-26 05:51:33 -0500828
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400829 while (idx < 12)
Robert Hancockac3d6b82007-02-19 19:02:46 -0600830 cpb[idx++] = cpu_to_le16(IGN);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700831
832 return idx;
833}
834
Robert Hancock5bd28a42007-02-05 16:26:01 -0800835static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700836{
837 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock2dec7552006-11-26 14:20:19 -0600838 u8 flags = pp->cpb[cpb_num].resp_flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700839
840 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
841
Robert Hancock5bd28a42007-02-05 16:26:01 -0800842 if (unlikely((force_err ||
843 flags & (NV_CPB_RESP_ATA_ERR |
844 NV_CPB_RESP_CMD_ERR |
845 NV_CPB_RESP_CPB_ERR)))) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900846 struct ata_eh_info *ehi = &ap->link.eh_info;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800847 int freeze = 0;
848
849 ata_ehi_clear_desc(ehi);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400850 __ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags);
Robert Hancock5bd28a42007-02-05 16:26:01 -0800851 if (flags & NV_CPB_RESP_ATA_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900852 ata_ehi_push_desc(ehi, "ATA error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800853 ehi->err_mask |= AC_ERR_DEV;
854 } else if (flags & NV_CPB_RESP_CMD_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900855 ata_ehi_push_desc(ehi, "CMD error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800856 ehi->err_mask |= AC_ERR_DEV;
857 } else if (flags & NV_CPB_RESP_CPB_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900858 ata_ehi_push_desc(ehi, "CPB error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800859 ehi->err_mask |= AC_ERR_SYSTEM;
860 freeze = 1;
861 } else {
862 /* notifier error, but no error in CPB flags? */
Tejun Heob64bbc32007-07-16 14:29:39 +0900863 ata_ehi_push_desc(ehi, "unknown");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800864 ehi->err_mask |= AC_ERR_OTHER;
865 freeze = 1;
866 }
867 /* Kill all commands. EH will determine what actually failed. */
868 if (freeze)
869 ata_port_freeze(ap);
870 else
871 ata_port_abort(ap);
Tejun Heo1aadf5c2010-06-25 15:03:34 +0200872 return -1;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800873 }
874
Tejun Heo1aadf5c2010-06-25 15:03:34 +0200875 if (likely(flags & NV_CPB_RESP_DONE))
876 return 1;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800877 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700878}
879
Robert Hancock2dec7552006-11-26 14:20:19 -0600880static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
881{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900882 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Robert Hancock2dec7552006-11-26 14:20:19 -0600883
884 /* freeze if hotplugged */
885 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
886 ata_port_freeze(ap);
887 return 1;
888 }
889
890 /* bail out if not our interrupt */
891 if (!(irq_stat & NV_INT_DEV))
892 return 0;
893
894 /* DEV interrupt w/ no active qc? */
895 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heo9363c382008-04-07 22:47:16 +0900896 ata_sff_check_status(ap);
Robert Hancock2dec7552006-11-26 14:20:19 -0600897 return 1;
898 }
899
900 /* handle interrupt */
Tejun Heoc3b28892010-05-19 22:10:21 +0200901 return ata_bmdma_port_intr(ap, qc);
Robert Hancock2dec7552006-11-26 14:20:19 -0600902}
903
Robert Hancockfbbb2622006-10-27 19:08:41 -0700904static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
905{
906 struct ata_host *host = dev_instance;
907 int i, handled = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600908 u32 notifier_clears[2];
Robert Hancockfbbb2622006-10-27 19:08:41 -0700909
910 spin_lock(&host->lock);
911
912 for (i = 0; i < host->n_ports; i++) {
913 struct ata_port *ap = host->ports[i];
Tejun Heo3e4ec342010-05-10 21:41:30 +0200914 struct nv_adma_port_priv *pp = ap->private_data;
915 void __iomem *mmio = pp->ctl_block;
916 u16 status;
917 u32 gen_ctl;
918 u32 notifier, notifier_error;
919
Robert Hancock2dec7552006-11-26 14:20:19 -0600920 notifier_clears[i] = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700921
Tejun Heo3e4ec342010-05-10 21:41:30 +0200922 /* if ADMA is disabled, use standard ata interrupt handler */
923 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
924 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
925 >> (NV_INT_PORT_SHIFT * i);
926 handled += nv_host_intr(ap, irq_stat);
927 continue;
928 }
Jeff Garzika617c092007-05-21 20:14:23 -0400929
Tejun Heo3e4ec342010-05-10 21:41:30 +0200930 /* if in ATA register mode, check for standard interrupts */
931 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
932 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
933 >> (NV_INT_PORT_SHIFT * i);
934 if (ata_tag_valid(ap->link.active_tag))
935 /** NV_INT_DEV indication seems unreliable
936 at times at least in ADMA mode. Force it
937 on always when a command is active, to
938 prevent losing interrupts. */
939 irq_stat |= NV_INT_DEV;
940 handled += nv_host_intr(ap, irq_stat);
941 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700942
Tejun Heo3e4ec342010-05-10 21:41:30 +0200943 notifier = readl(mmio + NV_ADMA_NOTIFIER);
944 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
945 notifier_clears[i] = notifier | notifier_error;
946
947 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
948
949 if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
950 !notifier_error)
951 /* Nothing to do */
952 continue;
953
954 status = readw(mmio + NV_ADMA_STAT);
955
956 /*
957 * Clear status. Ensure the controller sees the
958 * clearing before we start looking at any of the CPB
959 * statuses, so that any CPB completions after this
960 * point in the handler will raise another interrupt.
961 */
962 writew(status, mmio + NV_ADMA_STAT);
963 readw(mmio + NV_ADMA_STAT); /* flush posted write */
964 rmb();
965
966 handled++; /* irq handled if we got here */
967
968 /* freeze if hotplugged or controller error */
969 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
970 NV_ADMA_STAT_HOTUNPLUG |
971 NV_ADMA_STAT_TIMEOUT |
972 NV_ADMA_STAT_SERROR))) {
973 struct ata_eh_info *ehi = &ap->link.eh_info;
974
975 ata_ehi_clear_desc(ehi);
976 __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
977 if (status & NV_ADMA_STAT_TIMEOUT) {
978 ehi->err_mask |= AC_ERR_SYSTEM;
979 ata_ehi_push_desc(ehi, "timeout");
980 } else if (status & NV_ADMA_STAT_HOTPLUG) {
981 ata_ehi_hotplugged(ehi);
982 ata_ehi_push_desc(ehi, "hotplug");
983 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
984 ata_ehi_hotplugged(ehi);
985 ata_ehi_push_desc(ehi, "hot unplug");
986 } else if (status & NV_ADMA_STAT_SERROR) {
987 /* let EH analyze SError and figure out cause */
988 ata_ehi_push_desc(ehi, "SError");
989 } else
990 ata_ehi_push_desc(ehi, "unknown");
991 ata_port_freeze(ap);
992 continue;
993 }
994
995 if (status & (NV_ADMA_STAT_DONE |
996 NV_ADMA_STAT_CPBERR |
997 NV_ADMA_STAT_CMD_COMPLETE)) {
998 u32 check_commands = notifier_clears[i];
Tejun Heo1aadf5c2010-06-25 15:03:34 +0200999 u32 done_mask = 0;
Tejun Heo752e3862010-06-25 15:02:59 +02001000 int pos, rc;
Tejun Heo3e4ec342010-05-10 21:41:30 +02001001
1002 if (status & NV_ADMA_STAT_CPBERR) {
1003 /* check all active commands */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001004 if (ata_tag_valid(ap->link.active_tag))
Tejun Heo3e4ec342010-05-10 21:41:30 +02001005 check_commands = 1 <<
1006 ap->link.active_tag;
1007 else
1008 check_commands = ap->link.sactive;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001009 }
1010
Tejun Heo3e4ec342010-05-10 21:41:30 +02001011 /* check CPBs for completed commands */
Tejun Heo752e3862010-06-25 15:02:59 +02001012 while ((pos = ffs(check_commands))) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001013 pos--;
Tejun Heo752e3862010-06-25 15:02:59 +02001014 rc = nv_adma_check_cpb(ap, pos,
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001015 notifier_error & (1 << pos));
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001016 if (rc > 0)
1017 done_mask |= 1 << pos;
1018 else if (unlikely(rc < 0))
Tejun Heo752e3862010-06-25 15:02:59 +02001019 check_commands = 0;
Tejun Heo3e4ec342010-05-10 21:41:30 +02001020 check_commands &= ~(1 << pos);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001021 }
Tejun Heo1aadf5c2010-06-25 15:03:34 +02001022 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001023 }
1024 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -05001025
Jeff Garzikb4479162007-10-25 20:47:30 -04001026 if (notifier_clears[0] || notifier_clears[1]) {
Robert Hancock2dec7552006-11-26 14:20:19 -06001027 /* Note: Both notifier clear registers must be written
1028 if either is set, even if one is zero, according to NVIDIA. */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001029 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
1030 writel(notifier_clears[0], pp->notifier_clear_block);
1031 pp = host->ports[1]->private_data;
1032 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancock2dec7552006-11-26 14:20:19 -06001033 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001034
1035 spin_unlock(&host->lock);
1036
1037 return IRQ_RETVAL(handled);
1038}
1039
Robert Hancock53014e22007-05-05 15:36:36 -06001040static void nv_adma_freeze(struct ata_port *ap)
1041{
1042 struct nv_adma_port_priv *pp = ap->private_data;
1043 void __iomem *mmio = pp->ctl_block;
1044 u16 tmp;
1045
1046 nv_ck804_freeze(ap);
1047
1048 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1049 return;
1050
1051 /* clear any outstanding CK804 notifications */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001052 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
Robert Hancock53014e22007-05-05 15:36:36 -06001053 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1054
1055 /* Disable interrupt */
1056 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001057 writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
Robert Hancock53014e22007-05-05 15:36:36 -06001058 mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001059 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancock53014e22007-05-05 15:36:36 -06001060}
1061
1062static void nv_adma_thaw(struct ata_port *ap)
1063{
1064 struct nv_adma_port_priv *pp = ap->private_data;
1065 void __iomem *mmio = pp->ctl_block;
1066 u16 tmp;
1067
1068 nv_ck804_thaw(ap);
1069
1070 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1071 return;
1072
1073 /* Enable interrupt */
1074 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001075 writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
Robert Hancock53014e22007-05-05 15:36:36 -06001076 mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001077 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancock53014e22007-05-05 15:36:36 -06001078}
1079
Robert Hancockfbbb2622006-10-27 19:08:41 -07001080static void nv_adma_irq_clear(struct ata_port *ap)
1081{
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001082 struct nv_adma_port_priv *pp = ap->private_data;
1083 void __iomem *mmio = pp->ctl_block;
Robert Hancock53014e22007-05-05 15:36:36 -06001084 u32 notifier_clears[2];
1085
1086 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
Tejun Heo37f65b82010-05-19 22:10:20 +02001087 ata_bmdma_irq_clear(ap);
Robert Hancock53014e22007-05-05 15:36:36 -06001088 return;
1089 }
1090
1091 /* clear any outstanding CK804 notifications */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001092 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
Robert Hancock53014e22007-05-05 15:36:36 -06001093 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001094
1095 /* clear ADMA status */
Robert Hancock53014e22007-05-05 15:36:36 -06001096 writew(0xffff, mmio + NV_ADMA_STAT);
Jeff Garzika617c092007-05-21 20:14:23 -04001097
Robert Hancock53014e22007-05-05 15:36:36 -06001098 /* clear notifiers - note both ports need to be written with
1099 something even though we are only clearing on one */
1100 if (ap->port_no == 0) {
1101 notifier_clears[0] = 0xFFFFFFFF;
1102 notifier_clears[1] = 0;
1103 } else {
1104 notifier_clears[0] = 0;
1105 notifier_clears[1] = 0xFFFFFFFF;
1106 }
1107 pp = ap->host->ports[0]->private_data;
1108 writel(notifier_clears[0], pp->notifier_clear_block);
1109 pp = ap->host->ports[1]->private_data;
1110 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001111}
1112
Robert Hancockf5ecac22007-02-20 21:49:10 -06001113static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001114{
Robert Hancockf5ecac22007-02-20 21:49:10 -06001115 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001116
Jeff Garzikb4479162007-10-25 20:47:30 -04001117 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
Tejun Heofe06e5f2010-05-10 21:41:39 +02001118 ata_bmdma_post_internal_cmd(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001119}
1120
1121static int nv_adma_port_start(struct ata_port *ap)
1122{
1123 struct device *dev = ap->host->dev;
1124 struct nv_adma_port_priv *pp;
1125 int rc;
1126 void *mem;
1127 dma_addr_t mem_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001128 void __iomem *mmio;
Robert Hancock8959d302008-02-04 19:39:02 -06001129 struct pci_dev *pdev = to_pci_dev(dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001130 u16 tmp;
1131
1132 VPRINTK("ENTER\n");
1133
Robert Hancock8959d302008-02-04 19:39:02 -06001134 /* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
1135 pad buffers */
1136 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1137 if (rc)
1138 return rc;
1139 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1140 if (rc)
1141 return rc;
1142
Tejun Heoc7087652010-05-10 21:41:34 +02001143 /* we might fallback to bmdma, allocate bmdma resources */
1144 rc = ata_bmdma_port_start(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001145 if (rc)
1146 return rc;
1147
Tejun Heo24dc5f32007-01-20 16:00:28 +09001148 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1149 if (!pp)
1150 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001151
Tejun Heo0d5ff562007-02-01 15:06:36 +09001152 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001153 ap->port_no * NV_ADMA_PORT_SIZE;
1154 pp->ctl_block = mmio;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001155 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001156 pp->notifier_clear_block = pp->gen_block +
1157 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1158
Robert Hancock8959d302008-02-04 19:39:02 -06001159 /* Now that the legacy PRD and padding buffer are allocated we can
1160 safely raise the DMA mask to allocate the CPB/APRD table.
1161 These are allowed to fail since we store the value that ends up
1162 being used to set as the bounce limit in slave_config later if
1163 needed. */
1164 pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1165 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1166 pp->adma_dma_mask = *dev->dma_mask;
1167
Tejun Heo24dc5f32007-01-20 16:00:28 +09001168 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1169 &mem_dma, GFP_KERNEL);
1170 if (!mem)
1171 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001172 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1173
1174 /*
1175 * First item in chunk of DMA memory:
1176 * 128-byte command parameter block (CPB)
1177 * one for each command tag
1178 */
1179 pp->cpb = mem;
1180 pp->cpb_dma = mem_dma;
1181
1182 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001183 writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001184
1185 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1186 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1187
1188 /*
1189 * Second item: block of ADMA_SGTBL_LEN s/g entries
1190 */
1191 pp->aprd = mem;
1192 pp->aprd_dma = mem_dma;
1193
1194 ap->private_data = pp;
1195
1196 /* clear any outstanding interrupt conditions */
1197 writew(0xffff, mmio + NV_ADMA_STAT);
1198
1199 /* initialize port variables */
1200 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1201
1202 /* clear CPB fetch count */
1203 writew(0, mmio + NV_ADMA_CPB_COUNT);
1204
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001205 /* clear GO for register mode, enable interrupt */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001206 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001207 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1208 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001209
1210 tmp = readw(mmio + NV_ADMA_CTL);
1211 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001212 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001213 udelay(1);
1214 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001215 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001216
1217 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001218}
1219
1220static void nv_adma_port_stop(struct ata_port *ap)
1221{
Robert Hancockfbbb2622006-10-27 19:08:41 -07001222 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001223 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001224
1225 VPRINTK("ENTER\n");
Robert Hancockfbbb2622006-10-27 19:08:41 -07001226 writew(0, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001227}
1228
Tejun Heo438ac6d2007-03-02 17:31:26 +09001229#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001230static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1231{
1232 struct nv_adma_port_priv *pp = ap->private_data;
1233 void __iomem *mmio = pp->ctl_block;
1234
1235 /* Go to register mode - clears GO */
1236 nv_adma_register_mode(ap);
1237
1238 /* clear CPB fetch count */
1239 writew(0, mmio + NV_ADMA_CPB_COUNT);
1240
1241 /* disable interrupt, shut down port */
1242 writew(0, mmio + NV_ADMA_CTL);
1243
1244 return 0;
1245}
1246
1247static int nv_adma_port_resume(struct ata_port *ap)
1248{
1249 struct nv_adma_port_priv *pp = ap->private_data;
1250 void __iomem *mmio = pp->ctl_block;
1251 u16 tmp;
1252
1253 /* set CPB block location */
1254 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001255 writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001256
1257 /* clear any outstanding interrupt conditions */
1258 writew(0xffff, mmio + NV_ADMA_STAT);
1259
1260 /* initialize port variables */
1261 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1262
1263 /* clear CPB fetch count */
1264 writew(0, mmio + NV_ADMA_CPB_COUNT);
1265
1266 /* clear GO for register mode, enable interrupt */
1267 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001268 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1269 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001270
1271 tmp = readw(mmio + NV_ADMA_CTL);
1272 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001273 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001274 udelay(1);
1275 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001276 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001277
1278 return 0;
1279}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001280#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -07001281
Tejun Heo9a829cc2007-04-17 23:44:08 +09001282static void nv_adma_setup_port(struct ata_port *ap)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001283{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001284 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1285 struct ata_ioports *ioport = &ap->ioaddr;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001286
1287 VPRINTK("ENTER\n");
1288
Tejun Heo9a829cc2007-04-17 23:44:08 +09001289 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001290
Tejun Heo0d5ff562007-02-01 15:06:36 +09001291 ioport->cmd_addr = mmio;
1292 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001293 ioport->error_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001294 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1295 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1296 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1297 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1298 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1299 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001300 ioport->status_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001301 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001302 ioport->altstatus_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001303 ioport->ctl_addr = mmio + 0x20;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001304}
1305
Tejun Heo9a829cc2007-04-17 23:44:08 +09001306static int nv_adma_host_init(struct ata_host *host)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001307{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001308 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001309 unsigned int i;
1310 u32 tmp32;
1311
1312 VPRINTK("ENTER\n");
1313
1314 /* enable ADMA on the ports */
1315 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1316 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1317 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1318 NV_MCP_SATA_CFG_20_PORT1_EN |
1319 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1320
1321 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1322
Tejun Heo9a829cc2007-04-17 23:44:08 +09001323 for (i = 0; i < host->n_ports; i++)
1324 nv_adma_setup_port(host->ports[i]);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001325
Robert Hancockfbbb2622006-10-27 19:08:41 -07001326 return 0;
1327}
1328
1329static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1330 struct scatterlist *sg,
1331 int idx,
1332 struct nv_adma_prd *aprd)
1333{
Robert Hancock41949ed2007-02-19 19:02:27 -06001334 u8 flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001335 if (qc->tf.flags & ATA_TFLAG_WRITE)
1336 flags |= NV_APRD_WRITE;
1337 if (idx == qc->n_elem - 1)
1338 flags |= NV_APRD_END;
1339 else if (idx != 4)
1340 flags |= NV_APRD_CONT;
1341
1342 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1343 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
Robert Hancock2dec7552006-11-26 14:20:19 -06001344 aprd->flags = flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001345 aprd->packet_len = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001346}
1347
1348static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1349{
1350 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001351 struct nv_adma_prd *aprd;
1352 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001353 unsigned int si;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001354
1355 VPRINTK("ENTER\n");
1356
Tejun Heoff2aeb12007-12-05 16:43:11 +09001357 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1358 aprd = (si < 5) ? &cpb->aprd[si] :
1359 &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
1360 nv_adma_fill_aprd(qc, sg, si, aprd);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001361 }
Tejun Heoff2aeb12007-12-05 16:43:11 +09001362 if (si > 5)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001363 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
Robert Hancock41949ed2007-02-19 19:02:27 -06001364 else
1365 cpb->next_aprd = cpu_to_le64(0);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001366}
1367
Robert Hancock382a6652007-02-05 16:26:02 -08001368static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1369{
1370 struct nv_adma_port_priv *pp = qc->ap->private_data;
1371
1372 /* ADMA engine can only be used for non-ATAPI DMA commands,
Robert Hancock3f3debd2007-11-25 16:59:36 -06001373 or interrupt-driven no-data commands. */
Jeff Garzikb4479162007-10-25 20:47:30 -04001374 if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
Robert Hancock3f3debd2007-11-25 16:59:36 -06001375 (qc->tf.flags & ATA_TFLAG_POLLING))
Robert Hancock382a6652007-02-05 16:26:02 -08001376 return 1;
1377
Jeff Garzikb4479162007-10-25 20:47:30 -04001378 if ((qc->flags & ATA_QCFLAG_DMAMAP) ||
Robert Hancock382a6652007-02-05 16:26:02 -08001379 (qc->tf.protocol == ATA_PROT_NODATA))
1380 return 0;
1381
1382 return 1;
1383}
1384
Robert Hancockfbbb2622006-10-27 19:08:41 -07001385static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1386{
1387 struct nv_adma_port_priv *pp = qc->ap->private_data;
1388 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1389 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
Robert Hancockfbbb2622006-10-27 19:08:41 -07001390 NV_CPB_CTL_IEN;
1391
Robert Hancock382a6652007-02-05 16:26:02 -08001392 if (nv_adma_use_reg_mode(qc)) {
Robert Hancock3f3debd2007-11-25 16:59:36 -06001393 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1394 (qc->flags & ATA_QCFLAG_DMAMAP));
Robert Hancock2dec7552006-11-26 14:20:19 -06001395 nv_adma_register_mode(qc->ap);
Tejun Heof47451c2010-05-10 21:41:40 +02001396 ata_bmdma_qc_prep(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001397 return;
1398 }
1399
Robert Hancock41949ed2007-02-19 19:02:27 -06001400 cpb->resp_flags = NV_CPB_RESP_DONE;
1401 wmb();
1402 cpb->ctl_flags = 0;
1403 wmb();
Robert Hancockfbbb2622006-10-27 19:08:41 -07001404
1405 cpb->len = 3;
1406 cpb->tag = qc->tag;
1407 cpb->next_cpb_idx = 0;
1408
1409 /* turn on NCQ flags for NCQ commands */
1410 if (qc->tf.protocol == ATA_PROT_NCQ)
1411 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1412
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001413 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1414
Robert Hancockfbbb2622006-10-27 19:08:41 -07001415 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1416
Jeff Garzikb4479162007-10-25 20:47:30 -04001417 if (qc->flags & ATA_QCFLAG_DMAMAP) {
Robert Hancock382a6652007-02-05 16:26:02 -08001418 nv_adma_fill_sg(qc, cpb);
1419 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1420 } else
1421 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001422
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001423 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID
1424 until we are finished filling in all of the contents */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001425 wmb();
1426 cpb->ctl_flags = ctl_flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001427 wmb();
1428 cpb->resp_flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001429}
1430
1431static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1432{
Robert Hancock2dec7552006-11-26 14:20:19 -06001433 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001434 void __iomem *mmio = pp->ctl_block;
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001435 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001436
1437 VPRINTK("ENTER\n");
1438
Robert Hancock3f3debd2007-11-25 16:59:36 -06001439 /* We can't handle result taskfile with NCQ commands, since
1440 retrieving the taskfile switches us out of ADMA mode and would abort
1441 existing commands. */
1442 if (unlikely(qc->tf.protocol == ATA_PROT_NCQ &&
1443 (qc->flags & ATA_QCFLAG_RESULT_TF))) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07001444 ata_dev_err(qc->dev, "NCQ w/ RESULT_TF not allowed\n");
Robert Hancock3f3debd2007-11-25 16:59:36 -06001445 return AC_ERR_SYSTEM;
1446 }
1447
Robert Hancock382a6652007-02-05 16:26:02 -08001448 if (nv_adma_use_reg_mode(qc)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07001449 /* use ATA register mode */
Robert Hancock382a6652007-02-05 16:26:02 -08001450 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
Robert Hancock3f3debd2007-11-25 16:59:36 -06001451 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1452 (qc->flags & ATA_QCFLAG_DMAMAP));
Robert Hancockfbbb2622006-10-27 19:08:41 -07001453 nv_adma_register_mode(qc->ap);
Tejun Heo360ff782010-05-10 21:41:42 +02001454 return ata_bmdma_qc_issue(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001455 } else
1456 nv_adma_mode(qc->ap);
1457
1458 /* write append register, command tag in lower 8 bits
1459 and (number of cpbs to append -1) in top 8 bits */
1460 wmb();
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001461
Jeff Garzikb4479162007-10-25 20:47:30 -04001462 if (curr_ncq != pp->last_issue_ncq) {
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001463 /* Seems to need some delay before switching between NCQ and
1464 non-NCQ commands, else we get command timeouts and such. */
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001465 udelay(20);
1466 pp->last_issue_ncq = curr_ncq;
1467 }
1468
Robert Hancockfbbb2622006-10-27 19:08:41 -07001469 writew(qc->tag, mmio + NV_ADMA_APPEND);
1470
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001471 DPRINTK("Issued tag %u\n", qc->tag);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001472
1473 return 0;
1474}
1475
David Howells7d12e782006-10-05 14:55:46 +01001476static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477{
Jeff Garzikcca39742006-08-24 03:19:22 -04001478 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479 unsigned int i;
1480 unsigned int handled = 0;
1481 unsigned long flags;
1482
Jeff Garzikcca39742006-08-24 03:19:22 -04001483 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484
Jeff Garzikcca39742006-08-24 03:19:22 -04001485 for (i = 0; i < host->n_ports; i++) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001486 struct ata_port *ap = host->ports[i];
1487 struct ata_queued_cmd *qc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488
Tejun Heo3e4ec342010-05-10 21:41:30 +02001489 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1490 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heoc3b28892010-05-19 22:10:21 +02001491 handled += ata_bmdma_port_intr(ap, qc);
Tejun Heo3e4ec342010-05-10 21:41:30 +02001492 } else {
1493 /*
1494 * No request pending? Clear interrupt status
1495 * anyway, in case there's one pending.
1496 */
1497 ap->ops->sff_check_status(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499 }
1500
Jeff Garzikcca39742006-08-24 03:19:22 -04001501 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502
1503 return IRQ_RETVAL(handled);
1504}
1505
Jeff Garzikcca39742006-08-24 03:19:22 -04001506static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
Tejun Heoada364e2006-06-17 15:49:56 +09001507{
1508 int i, handled = 0;
1509
Jeff Garzikcca39742006-08-24 03:19:22 -04001510 for (i = 0; i < host->n_ports; i++) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001511 handled += nv_host_intr(host->ports[i], irq_stat);
Tejun Heoada364e2006-06-17 15:49:56 +09001512 irq_stat >>= NV_INT_PORT_SHIFT;
1513 }
1514
1515 return IRQ_RETVAL(handled);
1516}
1517
David Howells7d12e782006-10-05 14:55:46 +01001518static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001519{
Jeff Garzikcca39742006-08-24 03:19:22 -04001520 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001521 u8 irq_stat;
1522 irqreturn_t ret;
1523
Jeff Garzikcca39742006-08-24 03:19:22 -04001524 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001525 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
Jeff Garzikcca39742006-08-24 03:19:22 -04001526 ret = nv_do_interrupt(host, irq_stat);
1527 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001528
1529 return ret;
1530}
1531
David Howells7d12e782006-10-05 14:55:46 +01001532static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001533{
Jeff Garzikcca39742006-08-24 03:19:22 -04001534 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001535 u8 irq_stat;
1536 irqreturn_t ret;
1537
Jeff Garzikcca39742006-08-24 03:19:22 -04001538 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001539 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Jeff Garzikcca39742006-08-24 03:19:22 -04001540 ret = nv_do_interrupt(host, irq_stat);
1541 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001542
1543 return ret;
1544}
1545
Tejun Heo82ef04f2008-07-31 17:02:40 +09001546static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001548 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001549 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550
Tejun Heo82ef04f2008-07-31 17:02:40 +09001551 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001552 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553}
1554
Tejun Heo82ef04f2008-07-31 17:02:40 +09001555static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001558 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559
Tejun Heo82ef04f2008-07-31 17:02:40 +09001560 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001561 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562}
1563
Tejun Heo7f4774b2009-06-10 16:29:07 +09001564static int nv_hardreset(struct ata_link *link, unsigned int *class,
1565 unsigned long deadline)
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001566{
Tejun Heo7f4774b2009-06-10 16:29:07 +09001567 struct ata_eh_context *ehc = &link->eh_context;
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001568
Tejun Heo7f4774b2009-06-10 16:29:07 +09001569 /* Do hardreset iff it's post-boot probing, please read the
1570 * comment above port ops for details.
1571 */
1572 if (!(link->ap->pflags & ATA_PFLAG_LOADING) &&
1573 !ata_dev_enabled(link->device))
1574 sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
1575 NULL, NULL);
Tejun Heo6489e322009-10-14 11:18:28 +09001576 else {
1577 const unsigned long *timing = sata_ehc_deb_timing(ehc);
1578 int rc;
1579
1580 if (!(ehc->i.flags & ATA_EHI_QUIET))
Joe Perchesa9a79df2011-04-15 15:51:59 -07001581 ata_link_info(link,
1582 "nv: skipping hardreset on occupied port\n");
Tejun Heo6489e322009-10-14 11:18:28 +09001583
1584 /* make sure the link is online */
1585 rc = sata_link_resume(link, timing, deadline);
1586 /* whine about phy resume failure but proceed */
1587 if (rc && rc != -EOPNOTSUPP)
Joe Perchesa9a79df2011-04-15 15:51:59 -07001588 ata_link_warn(link, "failed to resume link (errno=%d)\n",
1589 rc);
Tejun Heo6489e322009-10-14 11:18:28 +09001590 }
Tejun Heo7f4774b2009-06-10 16:29:07 +09001591
1592 /* device signature acquisition is unreliable */
1593 return -EAGAIN;
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001594}
1595
Tejun Heo39f87582006-06-17 15:49:56 +09001596static void nv_nf2_freeze(struct ata_port *ap)
1597{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001598 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001599 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1600 u8 mask;
1601
Tejun Heo0d5ff562007-02-01 15:06:36 +09001602 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001603 mask &= ~(NV_INT_ALL << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001604 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001605}
1606
1607static void nv_nf2_thaw(struct ata_port *ap)
1608{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001609 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001610 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1611 u8 mask;
1612
Tejun Heo0d5ff562007-02-01 15:06:36 +09001613 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
Tejun Heo39f87582006-06-17 15:49:56 +09001614
Tejun Heo0d5ff562007-02-01 15:06:36 +09001615 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001616 mask |= (NV_INT_MASK << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001617 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001618}
1619
1620static void nv_ck804_freeze(struct ata_port *ap)
1621{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001622 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001623 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1624 u8 mask;
1625
1626 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1627 mask &= ~(NV_INT_ALL << shift);
1628 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1629}
1630
1631static void nv_ck804_thaw(struct ata_port *ap)
1632{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001633 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001634 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1635 u8 mask;
1636
1637 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1638
1639 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1640 mask |= (NV_INT_MASK << shift);
1641 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1642}
1643
Kuan Luof140f0f2007-10-15 15:16:53 -04001644static void nv_mcp55_freeze(struct ata_port *ap)
1645{
1646 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1647 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1648 u32 mask;
1649
1650 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1651
1652 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1653 mask &= ~(NV_INT_ALL_MCP55 << shift);
1654 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
Kuan Luof140f0f2007-10-15 15:16:53 -04001655}
1656
1657static void nv_mcp55_thaw(struct ata_port *ap)
1658{
1659 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1660 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1661 u32 mask;
1662
1663 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1664
1665 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1666 mask |= (NV_INT_MASK_MCP55 << shift);
1667 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
Kuan Luof140f0f2007-10-15 15:16:53 -04001668}
1669
Robert Hancockfbbb2622006-10-27 19:08:41 -07001670static void nv_adma_error_handler(struct ata_port *ap)
1671{
1672 struct nv_adma_port_priv *pp = ap->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04001673 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001674 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001675 int i;
1676 u16 tmp;
Jeff Garzika84471f2007-02-26 05:51:33 -05001677
Jeff Garzikb4479162007-10-25 20:47:30 -04001678 if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) {
Robert Hancock2cb27852007-02-11 18:34:44 -06001679 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1680 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1681 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1682 u32 status = readw(mmio + NV_ADMA_STAT);
Robert Hancock08af7412007-02-19 19:01:59 -06001683 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1684 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
Robert Hancock2cb27852007-02-11 18:34:44 -06001685
Joe Perchesa9a79df2011-04-15 15:51:59 -07001686 ata_port_err(ap,
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001687 "EH in ADMA mode, notifier 0x%X "
Robert Hancock08af7412007-02-19 19:01:59 -06001688 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1689 "next cpb count 0x%X next cpb idx 0x%x\n",
1690 notifier, notifier_error, gen_ctl, status,
1691 cpb_count, next_cpb_idx);
Robert Hancock2cb27852007-02-11 18:34:44 -06001692
Jeff Garzikb4479162007-10-25 20:47:30 -04001693 for (i = 0; i < NV_ADMA_MAX_CPBS; i++) {
Robert Hancock2cb27852007-02-11 18:34:44 -06001694 struct nv_adma_cpb *cpb = &pp->cpb[i];
Jeff Garzikb4479162007-10-25 20:47:30 -04001695 if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) ||
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001696 ap->link.sactive & (1 << i))
Joe Perchesa9a79df2011-04-15 15:51:59 -07001697 ata_port_err(ap,
Robert Hancock2cb27852007-02-11 18:34:44 -06001698 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1699 i, cpb->ctl_flags, cpb->resp_flags);
1700 }
1701 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001702
Robert Hancockfbbb2622006-10-27 19:08:41 -07001703 /* Push us back into port register mode for error handling. */
1704 nv_adma_register_mode(ap);
1705
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001706 /* Mark all of the CPBs as invalid to prevent them from
1707 being executed */
Jeff Garzikb4479162007-10-25 20:47:30 -04001708 for (i = 0; i < NV_ADMA_MAX_CPBS; i++)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001709 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1710
1711 /* clear CPB fetch count */
1712 writew(0, mmio + NV_ADMA_CPB_COUNT);
1713
1714 /* Reset channel */
1715 tmp = readw(mmio + NV_ADMA_CTL);
1716 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzikb4479162007-10-25 20:47:30 -04001717 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001718 udelay(1);
1719 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzikb4479162007-10-25 20:47:30 -04001720 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001721 }
1722
Tejun Heofe06e5f2010-05-10 21:41:39 +02001723 ata_bmdma_error_handler(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001724}
1725
Kuan Luof140f0f2007-10-15 15:16:53 -04001726static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
1727{
1728 struct nv_swncq_port_priv *pp = ap->private_data;
1729 struct defer_queue *dq = &pp->defer_queue;
1730
1731 /* queue is full */
1732 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
1733 dq->defer_bits |= (1 << qc->tag);
1734 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
1735}
1736
1737static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
1738{
1739 struct nv_swncq_port_priv *pp = ap->private_data;
1740 struct defer_queue *dq = &pp->defer_queue;
1741 unsigned int tag;
1742
1743 if (dq->head == dq->tail) /* null queue */
1744 return NULL;
1745
1746 tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)];
1747 dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON;
1748 WARN_ON(!(dq->defer_bits & (1 << tag)));
1749 dq->defer_bits &= ~(1 << tag);
1750
1751 return ata_qc_from_tag(ap, tag);
1752}
1753
1754static void nv_swncq_fis_reinit(struct ata_port *ap)
1755{
1756 struct nv_swncq_port_priv *pp = ap->private_data;
1757
1758 pp->dhfis_bits = 0;
1759 pp->dmafis_bits = 0;
1760 pp->sdbfis_bits = 0;
1761 pp->ncq_flags = 0;
1762}
1763
1764static void nv_swncq_pp_reinit(struct ata_port *ap)
1765{
1766 struct nv_swncq_port_priv *pp = ap->private_data;
1767 struct defer_queue *dq = &pp->defer_queue;
1768
1769 dq->head = 0;
1770 dq->tail = 0;
1771 dq->defer_bits = 0;
1772 pp->qc_active = 0;
1773 pp->last_issue_tag = ATA_TAG_POISON;
1774 nv_swncq_fis_reinit(ap);
1775}
1776
1777static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis)
1778{
1779 struct nv_swncq_port_priv *pp = ap->private_data;
1780
1781 writew(fis, pp->irq_block);
1782}
1783
1784static void __ata_bmdma_stop(struct ata_port *ap)
1785{
1786 struct ata_queued_cmd qc;
1787
1788 qc.ap = ap;
1789 ata_bmdma_stop(&qc);
1790}
1791
1792static void nv_swncq_ncq_stop(struct ata_port *ap)
1793{
1794 struct nv_swncq_port_priv *pp = ap->private_data;
1795 unsigned int i;
1796 u32 sactive;
1797 u32 done_mask;
1798
Joe Perchesa9a79df2011-04-15 15:51:59 -07001799 ata_port_err(ap, "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n",
1800 ap->qc_active, ap->link.sactive);
1801 ata_port_err(ap,
Kuan Luof140f0f2007-10-15 15:16:53 -04001802 "SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n "
1803 "dhfis 0x%X dmafis 0x%X sdbfis 0x%X\n",
1804 pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag,
1805 pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits);
1806
Joe Perchesa9a79df2011-04-15 15:51:59 -07001807 ata_port_err(ap, "ATA_REG 0x%X ERR_REG 0x%X\n",
1808 ap->ops->sff_check_status(ap),
1809 ioread8(ap->ioaddr.error_addr));
Kuan Luof140f0f2007-10-15 15:16:53 -04001810
1811 sactive = readl(pp->sactive_block);
1812 done_mask = pp->qc_active ^ sactive;
1813
Joe Perchesa9a79df2011-04-15 15:51:59 -07001814 ata_port_err(ap, "tag : dhfis dmafis sdbfis sactive\n");
Kuan Luof140f0f2007-10-15 15:16:53 -04001815 for (i = 0; i < ATA_MAX_QUEUE; i++) {
1816 u8 err = 0;
1817 if (pp->qc_active & (1 << i))
1818 err = 0;
1819 else if (done_mask & (1 << i))
1820 err = 1;
1821 else
1822 continue;
1823
Joe Perchesa9a79df2011-04-15 15:51:59 -07001824 ata_port_err(ap,
1825 "tag 0x%x: %01x %01x %01x %01x %s\n", i,
1826 (pp->dhfis_bits >> i) & 0x1,
1827 (pp->dmafis_bits >> i) & 0x1,
1828 (pp->sdbfis_bits >> i) & 0x1,
1829 (sactive >> i) & 0x1,
1830 (err ? "error! tag doesn't exit" : " "));
Kuan Luof140f0f2007-10-15 15:16:53 -04001831 }
1832
1833 nv_swncq_pp_reinit(ap);
Tejun Heo5682ed32008-04-07 22:47:16 +09001834 ap->ops->sff_irq_clear(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001835 __ata_bmdma_stop(ap);
1836 nv_swncq_irq_clear(ap, 0xffff);
1837}
1838
1839static void nv_swncq_error_handler(struct ata_port *ap)
1840{
1841 struct ata_eh_context *ehc = &ap->link.eh_context;
1842
1843 if (ap->link.sactive) {
1844 nv_swncq_ncq_stop(ap);
Tejun Heocf480622008-01-24 00:05:14 +09001845 ehc->i.action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04001846 }
1847
Tejun Heofe06e5f2010-05-10 21:41:39 +02001848 ata_bmdma_error_handler(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001849}
1850
1851#ifdef CONFIG_PM
1852static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg)
1853{
1854 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1855 u32 tmp;
1856
1857 /* clear irq */
1858 writel(~0, mmio + NV_INT_STATUS_MCP55);
1859
1860 /* disable irq */
1861 writel(0, mmio + NV_INT_ENABLE_MCP55);
1862
1863 /* disable swncq */
1864 tmp = readl(mmio + NV_CTL_MCP55);
1865 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
1866 writel(tmp, mmio + NV_CTL_MCP55);
1867
1868 return 0;
1869}
1870
1871static int nv_swncq_port_resume(struct ata_port *ap)
1872{
1873 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1874 u32 tmp;
1875
1876 /* clear irq */
1877 writel(~0, mmio + NV_INT_STATUS_MCP55);
1878
1879 /* enable irq */
1880 writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1881
1882 /* enable swncq */
1883 tmp = readl(mmio + NV_CTL_MCP55);
1884 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1885
1886 return 0;
1887}
1888#endif
1889
1890static void nv_swncq_host_init(struct ata_host *host)
1891{
1892 u32 tmp;
1893 void __iomem *mmio = host->iomap[NV_MMIO_BAR];
1894 struct pci_dev *pdev = to_pci_dev(host->dev);
1895 u8 regval;
1896
1897 /* disable ECO 398 */
1898 pci_read_config_byte(pdev, 0x7f, &regval);
1899 regval &= ~(1 << 7);
1900 pci_write_config_byte(pdev, 0x7f, regval);
1901
1902 /* enable swncq */
1903 tmp = readl(mmio + NV_CTL_MCP55);
1904 VPRINTK("HOST_CTL:0x%X\n", tmp);
1905 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1906
1907 /* enable irq intr */
1908 tmp = readl(mmio + NV_INT_ENABLE_MCP55);
1909 VPRINTK("HOST_ENABLE:0x%X\n", tmp);
1910 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1911
1912 /* clear port irq */
1913 writel(~0x0, mmio + NV_INT_STATUS_MCP55);
1914}
1915
1916static int nv_swncq_slave_config(struct scsi_device *sdev)
1917{
1918 struct ata_port *ap = ata_shost_to_port(sdev->host);
1919 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1920 struct ata_device *dev;
1921 int rc;
1922 u8 rev;
1923 u8 check_maxtor = 0;
1924 unsigned char model_num[ATA_ID_PROD_LEN + 1];
1925
1926 rc = ata_scsi_slave_config(sdev);
1927 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
1928 /* Not a proper libata device, ignore */
1929 return rc;
1930
1931 dev = &ap->link.device[sdev->id];
1932 if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI)
1933 return rc;
1934
1935 /* if MCP51 and Maxtor, then disable ncq */
1936 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA ||
1937 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2)
1938 check_maxtor = 1;
1939
1940 /* if MCP55 and rev <= a2 and Maxtor, then disable ncq */
1941 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA ||
1942 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) {
1943 pci_read_config_byte(pdev, 0x8, &rev);
1944 if (rev <= 0xa2)
1945 check_maxtor = 1;
1946 }
1947
1948 if (!check_maxtor)
1949 return rc;
1950
1951 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
1952
1953 if (strncmp(model_num, "Maxtor", 6) == 0) {
Christoph Hellwigdb5ed4d2014-11-13 15:08:42 +01001954 ata_scsi_change_queue_depth(sdev, 1);
Joe Perchesa9a79df2011-04-15 15:51:59 -07001955 ata_dev_notice(dev, "Disabling SWNCQ mode (depth %x)\n",
1956 sdev->queue_depth);
Kuan Luof140f0f2007-10-15 15:16:53 -04001957 }
1958
1959 return rc;
1960}
1961
1962static int nv_swncq_port_start(struct ata_port *ap)
1963{
1964 struct device *dev = ap->host->dev;
1965 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1966 struct nv_swncq_port_priv *pp;
1967 int rc;
1968
Tejun Heoc7087652010-05-10 21:41:34 +02001969 /* we might fallback to bmdma, allocate bmdma resources */
1970 rc = ata_bmdma_port_start(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001971 if (rc)
1972 return rc;
1973
1974 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1975 if (!pp)
1976 return -ENOMEM;
1977
1978 pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE,
1979 &pp->prd_dma, GFP_KERNEL);
1980 if (!pp->prd)
1981 return -ENOMEM;
1982 memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE);
1983
1984 ap->private_data = pp;
1985 pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
1986 pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2;
1987 pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2;
1988
1989 return 0;
1990}
1991
1992static void nv_swncq_qc_prep(struct ata_queued_cmd *qc)
1993{
1994 if (qc->tf.protocol != ATA_PROT_NCQ) {
Tejun Heof47451c2010-05-10 21:41:40 +02001995 ata_bmdma_qc_prep(qc);
Kuan Luof140f0f2007-10-15 15:16:53 -04001996 return;
1997 }
1998
1999 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2000 return;
2001
2002 nv_swncq_fill_sg(qc);
2003}
2004
2005static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
2006{
2007 struct ata_port *ap = qc->ap;
2008 struct scatterlist *sg;
Kuan Luof140f0f2007-10-15 15:16:53 -04002009 struct nv_swncq_port_priv *pp = ap->private_data;
Tejun Heof60d7012010-05-10 21:41:41 +02002010 struct ata_bmdma_prd *prd;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002011 unsigned int si, idx;
Kuan Luof140f0f2007-10-15 15:16:53 -04002012
2013 prd = pp->prd + ATA_MAX_PRD * qc->tag;
2014
2015 idx = 0;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002016 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Kuan Luof140f0f2007-10-15 15:16:53 -04002017 u32 addr, offset;
2018 u32 sg_len, len;
2019
2020 addr = (u32)sg_dma_address(sg);
2021 sg_len = sg_dma_len(sg);
2022
2023 while (sg_len) {
2024 offset = addr & 0xffff;
2025 len = sg_len;
2026 if ((offset + sg_len) > 0x10000)
2027 len = 0x10000 - offset;
2028
2029 prd[idx].addr = cpu_to_le32(addr);
2030 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2031
2032 idx++;
2033 sg_len -= len;
2034 addr += len;
2035 }
2036 }
2037
Tejun Heoff2aeb12007-12-05 16:43:11 +09002038 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
Kuan Luof140f0f2007-10-15 15:16:53 -04002039}
2040
2041static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
2042 struct ata_queued_cmd *qc)
2043{
2044 struct nv_swncq_port_priv *pp = ap->private_data;
2045
2046 if (qc == NULL)
2047 return 0;
2048
2049 DPRINTK("Enter\n");
2050
2051 writel((1 << qc->tag), pp->sactive_block);
2052 pp->last_issue_tag = qc->tag;
2053 pp->dhfis_bits &= ~(1 << qc->tag);
2054 pp->dmafis_bits &= ~(1 << qc->tag);
2055 pp->qc_active |= (0x1 << qc->tag);
2056
Tejun Heo5682ed32008-04-07 22:47:16 +09002057 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2058 ap->ops->sff_exec_command(ap, &qc->tf);
Kuan Luof140f0f2007-10-15 15:16:53 -04002059
2060 DPRINTK("Issued tag %u\n", qc->tag);
2061
2062 return 0;
2063}
2064
2065static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
2066{
2067 struct ata_port *ap = qc->ap;
2068 struct nv_swncq_port_priv *pp = ap->private_data;
2069
2070 if (qc->tf.protocol != ATA_PROT_NCQ)
Tejun Heo360ff782010-05-10 21:41:42 +02002071 return ata_bmdma_qc_issue(qc);
Kuan Luof140f0f2007-10-15 15:16:53 -04002072
2073 DPRINTK("Enter\n");
2074
2075 if (!pp->qc_active)
2076 nv_swncq_issue_atacmd(ap, qc);
2077 else
2078 nv_swncq_qc_to_dq(ap, qc); /* add qc to defer queue */
2079
2080 return 0;
2081}
2082
2083static void nv_swncq_hotplug(struct ata_port *ap, u32 fis)
2084{
2085 u32 serror;
2086 struct ata_eh_info *ehi = &ap->link.eh_info;
2087
2088 ata_ehi_clear_desc(ehi);
2089
2090 /* AHCI needs SError cleared; otherwise, it might lock up */
2091 sata_scr_read(&ap->link, SCR_ERROR, &serror);
2092 sata_scr_write(&ap->link, SCR_ERROR, serror);
2093
2094 /* analyze @irq_stat */
2095 if (fis & NV_SWNCQ_IRQ_ADDED)
2096 ata_ehi_push_desc(ehi, "hot plug");
2097 else if (fis & NV_SWNCQ_IRQ_REMOVED)
2098 ata_ehi_push_desc(ehi, "hot unplug");
2099
2100 ata_ehi_hotplugged(ehi);
2101
2102 /* okay, let's hand over to EH */
2103 ehi->serror |= serror;
2104
2105 ata_port_freeze(ap);
2106}
2107
2108static int nv_swncq_sdbfis(struct ata_port *ap)
2109{
2110 struct ata_queued_cmd *qc;
2111 struct nv_swncq_port_priv *pp = ap->private_data;
2112 struct ata_eh_info *ehi = &ap->link.eh_info;
2113 u32 sactive;
Kuan Luof140f0f2007-10-15 15:16:53 -04002114 u32 done_mask;
Kuan Luof140f0f2007-10-15 15:16:53 -04002115 u8 host_stat;
2116 u8 lack_dhfis = 0;
2117
2118 host_stat = ap->ops->bmdma_status(ap);
2119 if (unlikely(host_stat & ATA_DMA_ERR)) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002120 /* error when transferring data to/from memory */
Kuan Luof140f0f2007-10-15 15:16:53 -04002121 ata_ehi_clear_desc(ehi);
2122 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2123 ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002124 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002125 return -EINVAL;
2126 }
2127
Tejun Heo5682ed32008-04-07 22:47:16 +09002128 ap->ops->sff_irq_clear(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002129 __ata_bmdma_stop(ap);
2130
2131 sactive = readl(pp->sactive_block);
2132 done_mask = pp->qc_active ^ sactive;
2133
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002134 pp->qc_active &= ~done_mask;
2135 pp->dhfis_bits &= ~done_mask;
2136 pp->dmafis_bits &= ~done_mask;
2137 pp->sdbfis_bits |= done_mask;
2138 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
Kuan Luof140f0f2007-10-15 15:16:53 -04002139
2140 if (!ap->qc_active) {
2141 DPRINTK("over\n");
2142 nv_swncq_pp_reinit(ap);
Tejun Heo752e3862010-06-25 15:02:59 +02002143 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002144 }
2145
2146 if (pp->qc_active & pp->dhfis_bits)
Tejun Heo752e3862010-06-25 15:02:59 +02002147 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002148
2149 if ((pp->ncq_flags & ncq_saw_backout) ||
2150 (pp->qc_active ^ pp->dhfis_bits))
Tejun Heo752e3862010-06-25 15:02:59 +02002151 /* if the controller can't get a device to host register FIS,
Kuan Luof140f0f2007-10-15 15:16:53 -04002152 * The driver needs to reissue the new command.
2153 */
2154 lack_dhfis = 1;
2155
2156 DPRINTK("id 0x%x QC: qc_active 0x%x,"
2157 "SWNCQ:qc_active 0x%X defer_bits %X "
2158 "dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
2159 ap->print_id, ap->qc_active, pp->qc_active,
2160 pp->defer_queue.defer_bits, pp->dhfis_bits,
2161 pp->dmafis_bits, pp->last_issue_tag);
2162
2163 nv_swncq_fis_reinit(ap);
2164
2165 if (lack_dhfis) {
2166 qc = ata_qc_from_tag(ap, pp->last_issue_tag);
2167 nv_swncq_issue_atacmd(ap, qc);
Tejun Heo752e3862010-06-25 15:02:59 +02002168 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002169 }
2170
2171 if (pp->defer_queue.defer_bits) {
2172 /* send deferral queue command */
2173 qc = nv_swncq_qc_from_dq(ap);
2174 WARN_ON(qc == NULL);
2175 nv_swncq_issue_atacmd(ap, qc);
2176 }
2177
Tejun Heo752e3862010-06-25 15:02:59 +02002178 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002179}
2180
2181static inline u32 nv_swncq_tag(struct ata_port *ap)
2182{
2183 struct nv_swncq_port_priv *pp = ap->private_data;
2184 u32 tag;
2185
2186 tag = readb(pp->tag_block) >> 2;
2187 return (tag & 0x1f);
2188}
2189
Tejun Heo752e3862010-06-25 15:02:59 +02002190static void nv_swncq_dmafis(struct ata_port *ap)
Kuan Luof140f0f2007-10-15 15:16:53 -04002191{
2192 struct ata_queued_cmd *qc;
2193 unsigned int rw;
2194 u8 dmactl;
2195 u32 tag;
2196 struct nv_swncq_port_priv *pp = ap->private_data;
2197
2198 __ata_bmdma_stop(ap);
2199 tag = nv_swncq_tag(ap);
2200
2201 DPRINTK("dma setup tag 0x%x\n", tag);
2202 qc = ata_qc_from_tag(ap, tag);
2203
2204 if (unlikely(!qc))
Tejun Heo752e3862010-06-25 15:02:59 +02002205 return;
Kuan Luof140f0f2007-10-15 15:16:53 -04002206
2207 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2208
2209 /* load PRD table addr. */
2210 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
2211 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2212
2213 /* specify data direction, triple-check start bit is clear */
2214 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2215 dmactl &= ~ATA_DMA_WR;
2216 if (!rw)
2217 dmactl |= ATA_DMA_WR;
2218
2219 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Kuan Luof140f0f2007-10-15 15:16:53 -04002220}
2221
2222static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2223{
2224 struct nv_swncq_port_priv *pp = ap->private_data;
2225 struct ata_queued_cmd *qc;
2226 struct ata_eh_info *ehi = &ap->link.eh_info;
2227 u32 serror;
2228 u8 ata_stat;
Kuan Luof140f0f2007-10-15 15:16:53 -04002229
Tejun Heo5682ed32008-04-07 22:47:16 +09002230 ata_stat = ap->ops->sff_check_status(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002231 nv_swncq_irq_clear(ap, fis);
2232 if (!fis)
2233 return;
2234
2235 if (ap->pflags & ATA_PFLAG_FROZEN)
2236 return;
2237
2238 if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
2239 nv_swncq_hotplug(ap, fis);
2240 return;
2241 }
2242
2243 if (!pp->qc_active)
2244 return;
2245
Tejun Heo82ef04f2008-07-31 17:02:40 +09002246 if (ap->ops->scr_read(&ap->link, SCR_ERROR, &serror))
Kuan Luof140f0f2007-10-15 15:16:53 -04002247 return;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002248 ap->ops->scr_write(&ap->link, SCR_ERROR, serror);
Kuan Luof140f0f2007-10-15 15:16:53 -04002249
2250 if (ata_stat & ATA_ERR) {
2251 ata_ehi_clear_desc(ehi);
2252 ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis);
2253 ehi->err_mask |= AC_ERR_DEV;
2254 ehi->serror |= serror;
Tejun Heocf480622008-01-24 00:05:14 +09002255 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002256 ata_port_freeze(ap);
2257 return;
2258 }
2259
2260 if (fis & NV_SWNCQ_IRQ_BACKOUT) {
2261 /* If the IRQ is backout, driver must issue
2262 * the new command again some time later.
2263 */
2264 pp->ncq_flags |= ncq_saw_backout;
2265 }
2266
2267 if (fis & NV_SWNCQ_IRQ_SDBFIS) {
2268 pp->ncq_flags |= ncq_saw_sdb;
2269 DPRINTK("id 0x%x SWNCQ: qc_active 0x%X "
2270 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
2271 ap->print_id, pp->qc_active, pp->dhfis_bits,
2272 pp->dmafis_bits, readl(pp->sactive_block));
Tejun Heo752e3862010-06-25 15:02:59 +02002273 if (nv_swncq_sdbfis(ap) < 0)
Kuan Luof140f0f2007-10-15 15:16:53 -04002274 goto irq_error;
2275 }
2276
2277 if (fis & NV_SWNCQ_IRQ_DHREGFIS) {
2278 /* The interrupt indicates the new command
2279 * was transmitted correctly to the drive.
2280 */
2281 pp->dhfis_bits |= (0x1 << pp->last_issue_tag);
2282 pp->ncq_flags |= ncq_saw_d2h;
2283 if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) {
2284 ata_ehi_push_desc(ehi, "illegal fis transaction");
2285 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002286 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002287 goto irq_error;
2288 }
2289
2290 if (!(fis & NV_SWNCQ_IRQ_DMASETUP) &&
2291 !(pp->ncq_flags & ncq_saw_dmas)) {
Tejun Heo5682ed32008-04-07 22:47:16 +09002292 ata_stat = ap->ops->sff_check_status(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002293 if (ata_stat & ATA_BUSY)
2294 goto irq_exit;
2295
2296 if (pp->defer_queue.defer_bits) {
2297 DPRINTK("send next command\n");
2298 qc = nv_swncq_qc_from_dq(ap);
2299 nv_swncq_issue_atacmd(ap, qc);
2300 }
2301 }
2302 }
2303
2304 if (fis & NV_SWNCQ_IRQ_DMASETUP) {
2305 /* program the dma controller with appropriate PRD buffers
2306 * and start the DMA transfer for requested command.
2307 */
2308 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
2309 pp->ncq_flags |= ncq_saw_dmas;
Tejun Heo752e3862010-06-25 15:02:59 +02002310 nv_swncq_dmafis(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002311 }
2312
2313irq_exit:
2314 return;
2315irq_error:
2316 ata_ehi_push_desc(ehi, "fis:0x%x", fis);
2317 ata_port_freeze(ap);
2318 return;
2319}
2320
2321static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
2322{
2323 struct ata_host *host = dev_instance;
2324 unsigned int i;
2325 unsigned int handled = 0;
2326 unsigned long flags;
2327 u32 irq_stat;
2328
2329 spin_lock_irqsave(&host->lock, flags);
2330
2331 irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55);
2332
2333 for (i = 0; i < host->n_ports; i++) {
2334 struct ata_port *ap = host->ports[i];
2335
Tejun Heo3e4ec342010-05-10 21:41:30 +02002336 if (ap->link.sactive) {
2337 nv_swncq_host_interrupt(ap, (u16)irq_stat);
2338 handled = 1;
2339 } else {
2340 if (irq_stat) /* reserve Hotplug */
2341 nv_swncq_irq_clear(ap, 0xfff0);
Kuan Luof140f0f2007-10-15 15:16:53 -04002342
Tejun Heo3e4ec342010-05-10 21:41:30 +02002343 handled += nv_host_intr(ap, (u8)irq_stat);
Kuan Luof140f0f2007-10-15 15:16:53 -04002344 }
2345 irq_stat >>= NV_INT_PORT_SHIFT_MCP55;
2346 }
2347
2348 spin_unlock_irqrestore(&host->lock, flags);
2349
2350 return IRQ_RETVAL(handled);
2351}
2352
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002353static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002354{
Tejun Heo1626aeb2007-05-04 12:43:58 +02002355 const struct ata_port_info *ppi[] = { NULL, NULL };
Tejun Heo95947192008-03-25 12:22:49 +09002356 struct nv_pi_priv *ipriv;
Tejun Heo9a829cc2007-04-17 23:44:08 +09002357 struct ata_host *host;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002358 struct nv_host_priv *hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002359 int rc;
2360 u32 bar;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002361 void __iomem *base;
Robert Hancockfbbb2622006-10-27 19:08:41 -07002362 unsigned long type = ent->driver_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002363
2364 // Make sure this is a SATA controller by counting the number of bars
2365 // (NVIDIA SATA controllers will always have six bars). Otherwise,
2366 // it's an IDE controller and we ignore it.
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002367 for (bar = 0; bar < 6; bar++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368 if (pci_resource_start(pdev, bar) == 0)
2369 return -ENODEV;
2370
Joe Perches06296a12011-04-15 15:52:00 -07002371 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002372
Tejun Heo24dc5f32007-01-20 16:00:28 +09002373 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002374 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002375 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002376
Tejun Heo9a829cc2007-04-17 23:44:08 +09002377 /* determine type and allocate host */
Kuan Luof140f0f2007-10-15 15:16:53 -04002378 if (type == CK804 && adma_enabled) {
Joe Perchesa44fec12011-04-15 15:51:58 -07002379 dev_notice(&pdev->dev, "Using ADMA mode\n");
Robert Hancockfbbb2622006-10-27 19:08:41 -07002380 type = ADMA;
Tejun Heo2d775702009-01-25 11:29:38 +09002381 } else if (type == MCP5x && swncq_enabled) {
Joe Perchesa44fec12011-04-15 15:51:58 -07002382 dev_notice(&pdev->dev, "Using SWNCQ mode\n");
Tejun Heo2d775702009-01-25 11:29:38 +09002383 type = SWNCQ;
Jeff Garzik360737a2007-10-29 06:49:24 -04002384 }
2385
Tejun Heo1626aeb2007-05-04 12:43:58 +02002386 ppi[0] = &nv_port_info[type];
Tejun Heo95947192008-03-25 12:22:49 +09002387 ipriv = ppi[0]->private_data;
Tejun Heo1c5afdf2010-05-19 22:10:22 +02002388 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Tejun Heo9a829cc2007-04-17 23:44:08 +09002389 if (rc)
2390 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391
Tejun Heo24dc5f32007-01-20 16:00:28 +09002392 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002393 if (!hpriv)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002394 return -ENOMEM;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002395 hpriv->type = type;
Tejun Heo9a829cc2007-04-17 23:44:08 +09002396 host->private_data = hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002397
Tejun Heo9a829cc2007-04-17 23:44:08 +09002398 /* request and iomap NV_MMIO_BAR */
2399 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
2400 if (rc)
2401 return rc;
2402
2403 /* configure SCR access */
2404 base = host->iomap[NV_MMIO_BAR];
2405 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
2406 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
Jeff Garzik02cbd922006-03-22 23:59:46 -05002407
Tejun Heoada364e2006-06-17 15:49:56 +09002408 /* enable SATA space for CK804 */
Robert Hancockfbbb2622006-10-27 19:08:41 -07002409 if (type >= CK804) {
Tejun Heoada364e2006-06-17 15:49:56 +09002410 u8 regval;
2411
2412 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2413 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2414 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
2415 }
2416
Tejun Heo9a829cc2007-04-17 23:44:08 +09002417 /* init ADMA */
Robert Hancockfbbb2622006-10-27 19:08:41 -07002418 if (type == ADMA) {
Tejun Heo9a829cc2007-04-17 23:44:08 +09002419 rc = nv_adma_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002420 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002421 return rc;
Jeff Garzik360737a2007-10-29 06:49:24 -04002422 } else if (type == SWNCQ)
Kuan Luof140f0f2007-10-15 15:16:53 -04002423 nv_swncq_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002424
Tony Vroon51c89492009-08-06 00:50:09 +01002425 if (msi_enabled) {
Joe Perchesa44fec12011-04-15 15:51:58 -07002426 dev_notice(&pdev->dev, "Using MSI\n");
Tony Vroon51c89492009-08-06 00:50:09 +01002427 pci_enable_msi(pdev);
2428 }
2429
Tejun Heo9a829cc2007-04-17 23:44:08 +09002430 pci_set_master(pdev);
Tejun Heo95cc2c72010-05-14 11:48:50 +02002431 return ata_pci_sff_activate_host(host, ipriv->irq_handler, ipriv->sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002432}
2433
Bartlomiej Zolnierkiewicz58eb8cd2014-05-07 17:17:44 +02002434#ifdef CONFIG_PM_SLEEP
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002435static int nv_pci_device_resume(struct pci_dev *pdev)
2436{
Jingoo Han0a86e1c2013-06-03 14:05:36 +09002437 struct ata_host *host = pci_get_drvdata(pdev);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002438 struct nv_host_priv *hpriv = host->private_data;
Robert Hancockce053fa2007-02-05 16:26:04 -08002439 int rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002440
Robert Hancockce053fa2007-02-05 16:26:04 -08002441 rc = ata_pci_device_do_resume(pdev);
Jeff Garzikb4479162007-10-25 20:47:30 -04002442 if (rc)
Robert Hancockce053fa2007-02-05 16:26:04 -08002443 return rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002444
2445 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Jeff Garzikb4479162007-10-25 20:47:30 -04002446 if (hpriv->type >= CK804) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002447 u8 regval;
2448
2449 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2450 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2451 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
2452 }
Jeff Garzikb4479162007-10-25 20:47:30 -04002453 if (hpriv->type == ADMA) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002454 u32 tmp32;
2455 struct nv_adma_port_priv *pp;
2456 /* enable/disable ADMA on the ports appropriately */
2457 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
2458
2459 pp = host->ports[0]->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04002460 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002461 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002462 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002463 else
2464 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002465 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002466 pp = host->ports[1]->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04002467 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002468 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002469 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002470 else
2471 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002472 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002473
2474 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
2475 }
2476 }
2477
2478 ata_host_resume(host);
2479
2480 return 0;
2481}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002482#endif
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002483
Jeff Garzikcca39742006-08-24 03:19:22 -04002484static void nv_ck804_host_stop(struct ata_host *host)
Tejun Heoada364e2006-06-17 15:49:56 +09002485{
Jeff Garzikcca39742006-08-24 03:19:22 -04002486 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heoada364e2006-06-17 15:49:56 +09002487 u8 regval;
2488
2489 /* disable SATA space for CK804 */
2490 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2491 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2492 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
Tejun Heoada364e2006-06-17 15:49:56 +09002493}
2494
Robert Hancockfbbb2622006-10-27 19:08:41 -07002495static void nv_adma_host_stop(struct ata_host *host)
2496{
2497 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002498 u32 tmp32;
2499
Robert Hancockfbbb2622006-10-27 19:08:41 -07002500 /* disable ADMA on the ports */
2501 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
2502 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
2503 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
2504 NV_MCP_SATA_CFG_20_PORT1_EN |
2505 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
2506
2507 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
2508
2509 nv_ck804_host_stop(host);
2510}
2511
Axel Lin2fc75da2012-04-19 13:43:05 +08002512module_pci_driver(nv_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002513
Robert Hancockfbbb2622006-10-27 19:08:41 -07002514module_param_named(adma, adma_enabled, bool, 0444);
Brandon Ehle55f784c2009-03-01 00:02:49 -08002515MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: false)");
Kuan Luof140f0f2007-10-15 15:16:53 -04002516module_param_named(swncq, swncq_enabled, bool, 0444);
Zoltan Boszormenyid21279f2008-03-28 14:33:46 -07002517MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)");
Tony Vroon51c89492009-08-06 00:50:09 +01002518module_param_named(msi, msi_enabled, bool, 0444);
2519MODULE_PARM_DESC(msi, "Enable use of MSI (Default: false)");