blob: 48d85f8b95fe1e97a014a47062e3ebcf27afd314 [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Javier Martin9e15db72012-03-02 09:28:47 +01008 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
Sascha Hauer1f1846c2010-10-06 10:25:55 +02009 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
Thierry Reding73312052013-01-21 11:09:00 +010017#include <linux/err.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020018#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
Javier Martin6bd08122012-03-22 14:54:01 +010027#include <linux/clk.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020028#include <linux/dmaengine.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040029#include <linux/module.h>
Markus Pargmann290ad0f2013-05-26 11:53:20 +020030#include <linux/of_device.h>
31#include <linux/of_dma.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020032
33#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020034#include <linux/platform_data/dma-imx.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020035
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000036#include "dmaengine.h"
Javier Martin9e15db72012-03-02 09:28:47 +010037#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
Javier Martin6bd08122012-03-22 14:54:01 +010038#define IMX_DMA_CHANNELS 16
39
Javier Martinf606ab82012-03-22 14:54:14 +010040#define IMX_DMA_2D_SLOTS 2
41#define IMX_DMA_2D_SLOT_A 0
42#define IMX_DMA_2D_SLOT_B 1
43
Javier Martin6bd08122012-03-22 14:54:01 +010044#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
45#define IMX_DMA_MEMSIZE_32 (0 << 4)
46#define IMX_DMA_MEMSIZE_8 (1 << 4)
47#define IMX_DMA_MEMSIZE_16 (2 << 4)
48#define IMX_DMA_TYPE_LINEAR (0 << 10)
49#define IMX_DMA_TYPE_2D (1 << 10)
50#define IMX_DMA_TYPE_FIFO (2 << 10)
51
52#define IMX_DMA_ERR_BURST (1 << 0)
53#define IMX_DMA_ERR_REQUEST (1 << 1)
54#define IMX_DMA_ERR_TRANSFER (1 << 2)
55#define IMX_DMA_ERR_BUFFER (1 << 3)
56#define IMX_DMA_ERR_TIMEOUT (1 << 4)
57
58#define DMA_DCR 0x00 /* Control Register */
59#define DMA_DISR 0x04 /* Interrupt status Register */
60#define DMA_DIMR 0x08 /* Interrupt mask Register */
61#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
62#define DMA_DRTOSR 0x10 /* Request timeout Register */
63#define DMA_DSESR 0x14 /* Transfer Error Status Register */
64#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
65#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
66#define DMA_WSRA 0x40 /* W-Size Register A */
67#define DMA_XSRA 0x44 /* X-Size Register A */
68#define DMA_YSRA 0x48 /* Y-Size Register A */
69#define DMA_WSRB 0x4c /* W-Size Register B */
70#define DMA_XSRB 0x50 /* X-Size Register B */
71#define DMA_YSRB 0x54 /* Y-Size Register B */
72#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
73#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
74#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
75#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
76#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
77#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
78#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
79#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
80#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
81
82#define DCR_DRST (1<<1)
83#define DCR_DEN (1<<0)
84#define DBTOCR_EN (1<<15)
85#define DBTOCR_CNT(x) ((x) & 0x7fff)
86#define CNTR_CNT(x) ((x) & 0xffffff)
87#define CCR_ACRPT (1<<14)
88#define CCR_DMOD_LINEAR (0x0 << 12)
89#define CCR_DMOD_2D (0x1 << 12)
90#define CCR_DMOD_FIFO (0x2 << 12)
91#define CCR_DMOD_EOBFIFO (0x3 << 12)
92#define CCR_SMOD_LINEAR (0x0 << 10)
93#define CCR_SMOD_2D (0x1 << 10)
94#define CCR_SMOD_FIFO (0x2 << 10)
95#define CCR_SMOD_EOBFIFO (0x3 << 10)
96#define CCR_MDIR_DEC (1<<9)
97#define CCR_MSEL_B (1<<8)
98#define CCR_DSIZ_32 (0x0 << 6)
99#define CCR_DSIZ_8 (0x1 << 6)
100#define CCR_DSIZ_16 (0x2 << 6)
101#define CCR_SSIZ_32 (0x0 << 4)
102#define CCR_SSIZ_8 (0x1 << 4)
103#define CCR_SSIZ_16 (0x2 << 4)
104#define CCR_REN (1<<3)
105#define CCR_RPT (1<<2)
106#define CCR_FRC (1<<1)
107#define CCR_CEN (1<<0)
108#define RTOR_EN (1<<15)
109#define RTOR_CLK (1<<14)
110#define RTOR_PSC (1<<13)
Javier Martin9e15db72012-03-02 09:28:47 +0100111
112enum imxdma_prep_type {
113 IMXDMA_DESC_MEMCPY,
114 IMXDMA_DESC_INTERLEAVED,
115 IMXDMA_DESC_SLAVE_SG,
116 IMXDMA_DESC_CYCLIC,
117};
118
Javier Martinf606ab82012-03-22 14:54:14 +0100119struct imx_dma_2d_config {
120 u16 xsr;
121 u16 ysr;
122 u16 wsr;
123 int count;
124};
125
Javier Martin9e15db72012-03-02 09:28:47 +0100126struct imxdma_desc {
127 struct list_head node;
128 struct dma_async_tx_descriptor desc;
129 enum dma_status status;
130 dma_addr_t src;
131 dma_addr_t dest;
132 size_t len;
Javier Martin2efc3442012-03-22 14:54:03 +0100133 enum dma_transfer_direction direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100134 enum imxdma_prep_type type;
135 /* For memcpy and interleaved */
136 unsigned int config_port;
137 unsigned int config_mem;
138 /* For interleaved transfers */
139 unsigned int x;
140 unsigned int y;
141 unsigned int w;
142 /* For slave sg and cyclic */
143 struct scatterlist *sg;
144 unsigned int sgcount;
145};
146
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200147struct imxdma_channel {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100148 int hw_chaining;
149 struct timer_list watchdog;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200150 struct imxdma_engine *imxdma;
151 unsigned int channel;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200152
Javier Martin9e15db72012-03-02 09:28:47 +0100153 struct tasklet_struct dma_tasklet;
154 struct list_head ld_free;
155 struct list_head ld_queue;
156 struct list_head ld_active;
157 int descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200158 enum dma_slave_buswidth word_size;
159 dma_addr_t per_address;
160 u32 watermark_level;
161 struct dma_chan chan;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200162 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200163 enum dma_status status;
164 int dma_request;
165 struct scatterlist *sg_list;
Javier Martin359291a2012-03-22 14:54:06 +0100166 u32 ccr_from_device;
167 u32 ccr_to_device;
Javier Martinf606ab82012-03-22 14:54:14 +0100168 bool enabled_2d;
169 int slot_2d;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200170};
171
Shawn Guoe51d0f02012-09-15 21:11:28 +0800172enum imx_dma_type {
173 IMX1_DMA,
174 IMX21_DMA,
175 IMX27_DMA,
176};
177
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200178struct imxdma_engine {
179 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +0100180 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200181 struct dma_device dma_device;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100182 void __iomem *base;
Fabio Estevama2367db2012-07-03 15:33:29 -0300183 struct clk *dma_ahb;
184 struct clk *dma_ipg;
Javier Martinf606ab82012-03-22 14:54:14 +0100185 spinlock_t lock;
186 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
Javier Martin6bd08122012-03-22 14:54:01 +0100187 struct imxdma_channel channel[IMX_DMA_CHANNELS];
Shawn Guoe51d0f02012-09-15 21:11:28 +0800188 enum imx_dma_type devtype;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200189};
190
Markus Pargmann290ad0f2013-05-26 11:53:20 +0200191struct imxdma_filter_data {
192 struct imxdma_engine *imxdma;
193 int request;
194};
195
Krzysztof Kozlowskiafe7cde2015-05-02 00:57:46 +0900196static const struct platform_device_id imx_dma_devtype[] = {
Shawn Guoe51d0f02012-09-15 21:11:28 +0800197 {
198 .name = "imx1-dma",
199 .driver_data = IMX1_DMA,
200 }, {
201 .name = "imx21-dma",
202 .driver_data = IMX21_DMA,
203 }, {
204 .name = "imx27-dma",
205 .driver_data = IMX27_DMA,
206 }, {
207 /* sentinel */
208 }
209};
210MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
211
Markus Pargmann290ad0f2013-05-26 11:53:20 +0200212static const struct of_device_id imx_dma_of_dev_id[] = {
213 {
214 .compatible = "fsl,imx1-dma",
215 .data = &imx_dma_devtype[IMX1_DMA],
216 }, {
217 .compatible = "fsl,imx21-dma",
218 .data = &imx_dma_devtype[IMX21_DMA],
219 }, {
220 .compatible = "fsl,imx27-dma",
221 .data = &imx_dma_devtype[IMX27_DMA],
222 }, {
223 /* sentinel */
224 }
225};
226MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
227
Shawn Guoe51d0f02012-09-15 21:11:28 +0800228static inline int is_imx1_dma(struct imxdma_engine *imxdma)
229{
230 return imxdma->devtype == IMX1_DMA;
231}
232
Shawn Guoe51d0f02012-09-15 21:11:28 +0800233static inline int is_imx27_dma(struct imxdma_engine *imxdma)
234{
235 return imxdma->devtype == IMX27_DMA;
236}
237
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200238static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
239{
240 return container_of(chan, struct imxdma_channel, chan);
241}
242
Javier Martin9e15db72012-03-02 09:28:47 +0100243static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200244{
Javier Martin9e15db72012-03-02 09:28:47 +0100245 struct imxdma_desc *desc;
246
247 if (!list_empty(&imxdmac->ld_active)) {
248 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
249 node);
250 if (desc->type == IMXDMA_DESC_CYCLIC)
251 return true;
252 }
253 return false;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200254}
255
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200256
Javier Martincd5cf9d2012-03-22 14:54:12 +0100257
258static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
259 unsigned offset)
Javier Martin6bd08122012-03-22 14:54:01 +0100260{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100261 __raw_writel(val, imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200262}
263
Javier Martincd5cf9d2012-03-22 14:54:12 +0100264static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200265{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100266 return __raw_readl(imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200267}
268
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100269static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200270{
Shawn Guoe51d0f02012-09-15 21:11:28 +0800271 struct imxdma_engine *imxdma = imxdmac->imxdma;
272
273 if (is_imx27_dma(imxdma))
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100274 return imxdmac->hw_chaining;
Javier Martin6bd08122012-03-22 14:54:01 +0100275 else
276 return 0;
277}
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200278
Javier Martin6bd08122012-03-22 14:54:01 +0100279/*
280 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
281 */
Javier Martina6cbb2d2012-03-22 14:54:11 +0100282static inline int imxdma_sg_next(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100283{
Javier Martin2efc3442012-03-22 14:54:03 +0100284 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100285 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100286 struct scatterlist *sg = d->sg;
Javier Martin6bd08122012-03-22 14:54:01 +0100287 unsigned long now;
288
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200289 now = min(d->len, sg_dma_len(sg));
Javier Martin6b0e2f52012-03-22 14:54:09 +0100290 if (d->len != IMX_DMA_LENGTH_LOOP)
291 d->len -= now;
Javier Martin6bd08122012-03-22 14:54:01 +0100292
Javier Martin2efc3442012-03-22 14:54:03 +0100293 if (d->direction == DMA_DEV_TO_MEM)
Javier Martincd5cf9d2012-03-22 14:54:12 +0100294 imx_dmav1_writel(imxdma, sg->dma_address,
295 DMA_DAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100296 else
Javier Martincd5cf9d2012-03-22 14:54:12 +0100297 imx_dmav1_writel(imxdma, sg->dma_address,
298 DMA_SAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100299
Javier Martincd5cf9d2012-03-22 14:54:12 +0100300 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100301
Javier Martinf9b283a2012-03-22 14:54:13 +0100302 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
303 "size 0x%08x\n", __func__, imxdmac->channel,
Javier Martincd5cf9d2012-03-22 14:54:12 +0100304 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
305 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
306 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
Javier Martin6bd08122012-03-22 14:54:01 +0100307
308 return now;
309}
310
Javier Martin2efc3442012-03-22 14:54:03 +0100311static void imxdma_enable_hw(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100312{
Javier Martin2efc3442012-03-22 14:54:03 +0100313 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100314 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100315 int channel = imxdmac->channel;
316 unsigned long flags;
317
Javier Martinf9b283a2012-03-22 14:54:13 +0100318 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100319
Javier Martin6bd08122012-03-22 14:54:01 +0100320 local_irq_save(flags);
321
Javier Martincd5cf9d2012-03-22 14:54:12 +0100322 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
323 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
324 ~(1 << channel), DMA_DIMR);
325 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
326 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100327
Shawn Guoe51d0f02012-09-15 21:11:28 +0800328 if (!is_imx1_dma(imxdma) &&
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100329 d->sg && imxdma_hw_chain(imxdmac)) {
Javier Martin833bc032012-03-22 14:54:07 +0100330 d->sg = sg_next(d->sg);
331 if (d->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100332 u32 tmp;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100333 imxdma_sg_next(d);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100334 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
335 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
336 DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100337 }
338 }
Javier Martin6bd08122012-03-22 14:54:01 +0100339
340 local_irq_restore(flags);
341}
342
343static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
344{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100345 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100346 int channel = imxdmac->channel;
347 unsigned long flags;
348
Javier Martinf9b283a2012-03-22 14:54:13 +0100349 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100350
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100351 if (imxdma_hw_chain(imxdmac))
352 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100353
354 local_irq_save(flags);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100355 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
356 (1 << channel), DMA_DIMR);
357 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
358 ~CCR_CEN, DMA_CCR(channel));
359 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100360 local_irq_restore(flags);
361}
362
Javier Martin6bd08122012-03-22 14:54:01 +0100363static void imxdma_watchdog(unsigned long data)
364{
365 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100366 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100367 int channel = imxdmac->channel;
368
Javier Martincd5cf9d2012-03-22 14:54:12 +0100369 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100370
371 /* Tasklet watchdog error handler */
372 tasklet_schedule(&imxdmac->dma_tasklet);
Javier Martinf9b283a2012-03-22 14:54:13 +0100373 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
374 imxdmac->channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100375}
376
377static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
378{
379 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100380 unsigned int err_mask;
381 int i, disr;
382 int errcode;
383
Javier Martincd5cf9d2012-03-22 14:54:12 +0100384 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100385
Javier Martincd5cf9d2012-03-22 14:54:12 +0100386 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
387 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
388 imx_dmav1_readl(imxdma, DMA_DSESR) |
389 imx_dmav1_readl(imxdma, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100390
391 if (!err_mask)
392 return IRQ_HANDLED;
393
Javier Martincd5cf9d2012-03-22 14:54:12 +0100394 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100395
396 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
397 if (!(err_mask & (1 << i)))
398 continue;
Javier Martin6bd08122012-03-22 14:54:01 +0100399 errcode = 0;
400
Javier Martincd5cf9d2012-03-22 14:54:12 +0100401 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
402 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100403 errcode |= IMX_DMA_ERR_BURST;
404 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100405 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
406 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100407 errcode |= IMX_DMA_ERR_REQUEST;
408 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100409 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
410 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
Javier Martin6bd08122012-03-22 14:54:01 +0100411 errcode |= IMX_DMA_ERR_TRANSFER;
412 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100413 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
414 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100415 errcode |= IMX_DMA_ERR_BUFFER;
416 }
417 /* Tasklet error handler */
418 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
419
Alexander Shiyan1d94fe02014-02-22 22:16:47 +0400420 dev_warn(imxdma->dev,
421 "DMA timeout on channel %d -%s%s%s%s\n", i,
422 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
423 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
424 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
425 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
Javier Martin6bd08122012-03-22 14:54:01 +0100426 }
427 return IRQ_HANDLED;
428}
429
430static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
431{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100432 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100433 int chno = imxdmac->channel;
Javier Martin2efc3442012-03-22 14:54:03 +0100434 struct imxdma_desc *desc;
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200435 unsigned long flags;
Javier Martin6bd08122012-03-22 14:54:01 +0100436
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200437 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin833bc032012-03-22 14:54:07 +0100438 if (list_empty(&imxdmac->ld_active)) {
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200439 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin833bc032012-03-22 14:54:07 +0100440 goto out;
441 }
442
443 desc = list_first_entry(&imxdmac->ld_active,
444 struct imxdma_desc,
445 node);
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200446 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin833bc032012-03-22 14:54:07 +0100447
448 if (desc->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100449 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100450 desc->sg = sg_next(desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100451
Javier Martin833bc032012-03-22 14:54:07 +0100452 if (desc->sg) {
Javier Martina6cbb2d2012-03-22 14:54:11 +0100453 imxdma_sg_next(desc);
Javier Martin6bd08122012-03-22 14:54:01 +0100454
Javier Martincd5cf9d2012-03-22 14:54:12 +0100455 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100456
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100457 if (imxdma_hw_chain(imxdmac)) {
Javier Martin6bd08122012-03-22 14:54:01 +0100458 /* FIXME: The timeout should probably be
459 * configurable
460 */
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100461 mod_timer(&imxdmac->watchdog,
Javier Martin6bd08122012-03-22 14:54:01 +0100462 jiffies + msecs_to_jiffies(500));
463
464 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100465 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100466 } else {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100467 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
468 DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100469 tmp |= CCR_CEN;
470 }
471
Javier Martincd5cf9d2012-03-22 14:54:12 +0100472 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100473
474 if (imxdma_chan_is_doing_cyclic(imxdmac))
475 /* Tasklet progression */
476 tasklet_schedule(&imxdmac->dma_tasklet);
477
478 return;
479 }
480
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100481 if (imxdma_hw_chain(imxdmac)) {
482 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100483 return;
484 }
485 }
486
Javier Martin2efc3442012-03-22 14:54:03 +0100487out:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100488 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100489 /* Tasklet irq */
Javier Martin9e15db72012-03-02 09:28:47 +0100490 tasklet_schedule(&imxdmac->dma_tasklet);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200491}
492
Javier Martin6bd08122012-03-22 14:54:01 +0100493static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200494{
Javier Martin6bd08122012-03-22 14:54:01 +0100495 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100496 int i, disr;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200497
Shawn Guoe51d0f02012-09-15 21:11:28 +0800498 if (!is_imx1_dma(imxdma))
Javier Martin6bd08122012-03-22 14:54:01 +0100499 imxdma_err_handler(irq, dev_id);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200500
Javier Martincd5cf9d2012-03-22 14:54:12 +0100501 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200502
Javier Martinf9b283a2012-03-22 14:54:13 +0100503 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
Javier Martin6bd08122012-03-22 14:54:01 +0100504
Javier Martincd5cf9d2012-03-22 14:54:12 +0100505 imx_dmav1_writel(imxdma, disr, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100506 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100507 if (disr & (1 << i))
Javier Martin6bd08122012-03-22 14:54:01 +0100508 dma_irq_handle_channel(&imxdma->channel[i]);
Javier Martin6bd08122012-03-22 14:54:01 +0100509 }
510
511 return IRQ_HANDLED;
Javier Martin9e15db72012-03-02 09:28:47 +0100512}
513
514static int imxdma_xfer_desc(struct imxdma_desc *d)
515{
516 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100517 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martinf606ab82012-03-22 14:54:14 +0100518 int slot = -1;
519 int i;
Javier Martin9e15db72012-03-02 09:28:47 +0100520
521 /* Configure and enable */
522 switch (d->type) {
Javier Martinf606ab82012-03-22 14:54:14 +0100523 case IMXDMA_DESC_INTERLEAVED:
524 /* Try to get a free 2D slot */
Javier Martinf606ab82012-03-22 14:54:14 +0100525 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
526 if ((imxdma->slots_2d[i].count > 0) &&
527 ((imxdma->slots_2d[i].xsr != d->x) ||
528 (imxdma->slots_2d[i].ysr != d->y) ||
529 (imxdma->slots_2d[i].wsr != d->w)))
530 continue;
531 slot = i;
532 break;
533 }
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200534 if (slot < 0)
Javier Martinf606ab82012-03-22 14:54:14 +0100535 return -EBUSY;
536
537 imxdma->slots_2d[slot].xsr = d->x;
538 imxdma->slots_2d[slot].ysr = d->y;
539 imxdma->slots_2d[slot].wsr = d->w;
540 imxdma->slots_2d[slot].count++;
541
542 imxdmac->slot_2d = slot;
543 imxdmac->enabled_2d = true;
Javier Martinf606ab82012-03-22 14:54:14 +0100544
545 if (slot == IMX_DMA_2D_SLOT_A) {
546 d->config_mem &= ~CCR_MSEL_B;
547 d->config_port &= ~CCR_MSEL_B;
548 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
549 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
550 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
551 } else {
552 d->config_mem |= CCR_MSEL_B;
553 d->config_port |= CCR_MSEL_B;
554 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
555 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
556 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
557 }
558 /*
559 * We fall-through here intentionally, since a 2D transfer is
560 * similar to MEMCPY just adding the 2D slot configuration.
561 */
Javier Martin9e15db72012-03-02 09:28:47 +0100562 case IMXDMA_DESC_MEMCPY:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100563 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
564 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
565 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
Javier Martin3b4b6df2012-03-22 14:54:04 +0100566 DMA_CCR(imxdmac->channel));
567
Javier Martincd5cf9d2012-03-22 14:54:12 +0100568 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
Javier Martin3b4b6df2012-03-22 14:54:04 +0100569
Russell Kingac806a12013-10-31 00:40:30 +0000570 dev_dbg(imxdma->dev,
571 "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
572 __func__, imxdmac->channel,
573 (unsigned long long)d->dest,
574 (unsigned long long)d->src, d->len);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100575
576 break;
Javier Martin6bd08122012-03-22 14:54:01 +0100577 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
Javier Martin9e15db72012-03-02 09:28:47 +0100578 case IMXDMA_DESC_CYCLIC:
Javier Martin9e15db72012-03-02 09:28:47 +0100579 case IMXDMA_DESC_SLAVE_SG:
Javier Martin359291a2012-03-22 14:54:06 +0100580 if (d->direction == DMA_DEV_TO_MEM) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100581 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100582 DMA_SAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100583 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
Javier Martin359291a2012-03-22 14:54:06 +0100584 DMA_CCR(imxdmac->channel));
585
Russell Kingac806a12013-10-31 00:40:30 +0000586 dev_dbg(imxdma->dev,
587 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
588 __func__, imxdmac->channel,
589 d->sg, d->sgcount, d->len,
590 (unsigned long long)imxdmac->per_address);
Javier Martin359291a2012-03-22 14:54:06 +0100591 } else if (d->direction == DMA_MEM_TO_DEV) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100592 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100593 DMA_DAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100594 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
Javier Martin359291a2012-03-22 14:54:06 +0100595 DMA_CCR(imxdmac->channel));
596
Russell Kingac806a12013-10-31 00:40:30 +0000597 dev_dbg(imxdma->dev,
598 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
599 __func__, imxdmac->channel,
600 d->sg, d->sgcount, d->len,
601 (unsigned long long)imxdmac->per_address);
Javier Martin359291a2012-03-22 14:54:06 +0100602 } else {
603 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
604 __func__, imxdmac->channel);
605 return -EINVAL;
606 }
607
Javier Martina6cbb2d2012-03-22 14:54:11 +0100608 imxdma_sg_next(d);
Javier Martin359291a2012-03-22 14:54:06 +0100609
Javier Martin9e15db72012-03-02 09:28:47 +0100610 break;
611 default:
612 return -EINVAL;
613 }
Javier Martin2efc3442012-03-22 14:54:03 +0100614 imxdma_enable_hw(d);
Javier Martin9e15db72012-03-02 09:28:47 +0100615 return 0;
616}
617
618static void imxdma_tasklet(unsigned long data)
619{
620 struct imxdma_channel *imxdmac = (void *)data;
621 struct imxdma_engine *imxdma = imxdmac->imxdma;
622 struct imxdma_desc *desc;
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200623 unsigned long flags;
Javier Martin9e15db72012-03-02 09:28:47 +0100624
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200625 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100626
627 if (list_empty(&imxdmac->ld_active)) {
628 /* Someone might have called terminate all */
Michael Grzeschikfcaaba62013-09-17 15:56:08 +0200629 spin_unlock_irqrestore(&imxdma->lock, flags);
630 return;
Javier Martin9e15db72012-03-02 09:28:47 +0100631 }
632 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
633
Masanari Iidad73111c2012-08-04 23:37:53 +0900634 /* If we are dealing with a cyclic descriptor, keep it on ld_active
635 * and dont mark the descriptor as complete.
Vinod Koul60f29512012-04-20 15:28:07 +0530636 * Only in non-cyclic cases it would be marked as complete
637 */
Javier Martin9e15db72012-03-02 09:28:47 +0100638 if (imxdma_chan_is_doing_cyclic(imxdmac))
639 goto out;
Vinod Koul60f29512012-04-20 15:28:07 +0530640 else
641 dma_cookie_complete(&desc->desc);
Javier Martin9e15db72012-03-02 09:28:47 +0100642
Javier Martinf606ab82012-03-22 14:54:14 +0100643 /* Free 2D slot if it was an interleaved transfer */
644 if (imxdmac->enabled_2d) {
645 imxdma->slots_2d[imxdmac->slot_2d].count--;
646 imxdmac->enabled_2d = false;
647 }
648
Javier Martin9e15db72012-03-02 09:28:47 +0100649 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
650
651 if (!list_empty(&imxdmac->ld_queue)) {
652 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
653 node);
654 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
655 if (imxdma_xfer_desc(desc) < 0)
656 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
657 __func__, imxdmac->channel);
658 }
659out:
Michael Grzeschik5a276fa2013-09-17 15:56:07 +0200660 spin_unlock_irqrestore(&imxdma->lock, flags);
Michael Grzeschikfcaaba62013-09-17 15:56:08 +0200661
662 if (desc->desc.callback)
663 desc->desc.callback(desc->desc.callback_param);
664
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200665}
666
Maxime Ripard502c2ef2014-11-17 14:42:16 +0100667static int imxdma_terminate_all(struct dma_chan *chan)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200668{
669 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100670 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100671 unsigned long flags;
Maxime Ripard502c2ef2014-11-17 14:42:16 +0100672
673 imxdma_disable_hw(imxdmac);
674
675 spin_lock_irqsave(&imxdma->lock, flags);
676 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
677 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
678 spin_unlock_irqrestore(&imxdma->lock, flags);
679 return 0;
680}
681
682static int imxdma_config(struct dma_chan *chan,
683 struct dma_slave_config *dmaengine_cfg)
684{
685 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
686 struct imxdma_engine *imxdma = imxdmac->imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200687 unsigned int mode = 0;
688
Maxime Ripard502c2ef2014-11-17 14:42:16 +0100689 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
690 imxdmac->per_address = dmaengine_cfg->src_addr;
691 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
692 imxdmac->word_size = dmaengine_cfg->src_addr_width;
693 } else {
694 imxdmac->per_address = dmaengine_cfg->dst_addr;
695 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
696 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200697 }
698
Maxime Ripard502c2ef2014-11-17 14:42:16 +0100699 switch (imxdmac->word_size) {
700 case DMA_SLAVE_BUSWIDTH_1_BYTE:
701 mode = IMX_DMA_MEMSIZE_8;
702 break;
703 case DMA_SLAVE_BUSWIDTH_2_BYTES:
704 mode = IMX_DMA_MEMSIZE_16;
705 break;
706 default:
707 case DMA_SLAVE_BUSWIDTH_4_BYTES:
708 mode = IMX_DMA_MEMSIZE_32;
709 break;
710 }
711
712 imxdmac->hw_chaining = 0;
713
714 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
715 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
716 CCR_REN;
717 imxdmac->ccr_to_device =
718 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
719 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
720 imx_dmav1_writel(imxdma, imxdmac->dma_request,
721 DMA_RSSR(imxdmac->channel));
722
723 /* Set burst length */
724 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
725 imxdmac->word_size, DMA_BLR(imxdmac->channel));
726
727 return 0;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200728}
729
730static enum dma_status imxdma_tx_status(struct dma_chan *chan,
731 dma_cookie_t cookie,
732 struct dma_tx_state *txstate)
733{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000734 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200735}
736
737static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
738{
739 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100740 struct imxdma_engine *imxdma = imxdmac->imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200741 dma_cookie_t cookie;
Javier Martin9e15db72012-03-02 09:28:47 +0100742 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200743
Javier Martinf606ab82012-03-22 14:54:14 +0100744 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin660cd0d2012-03-22 14:54:15 +0100745 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000746 cookie = dma_cookie_assign(tx);
Javier Martinf606ab82012-03-22 14:54:14 +0100747 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200748
749 return cookie;
750}
751
752static int imxdma_alloc_chan_resources(struct dma_chan *chan)
753{
754 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
755 struct imx_dma_data *data = chan->private;
756
Javier Martin6c05f092012-02-28 17:08:17 +0100757 if (data != NULL)
758 imxdmac->dma_request = data->dma_request;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200759
Javier Martin9e15db72012-03-02 09:28:47 +0100760 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
761 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200762
Javier Martin9e15db72012-03-02 09:28:47 +0100763 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
764 if (!desc)
765 break;
766 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
767 dma_async_tx_descriptor_init(&desc->desc, chan);
768 desc->desc.tx_submit = imxdma_tx_submit;
769 /* txd.flags will be overwritten in prep funcs */
770 desc->desc.flags = DMA_CTRL_ACK;
Vinod Koul3ded1ad2013-10-16 14:06:24 +0530771 desc->status = DMA_COMPLETE;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200772
Javier Martin9e15db72012-03-02 09:28:47 +0100773 list_add_tail(&desc->node, &imxdmac->ld_free);
774 imxdmac->descs_allocated++;
775 }
776
777 if (!imxdmac->descs_allocated)
778 return -ENOMEM;
779
780 return imxdmac->descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200781}
782
783static void imxdma_free_chan_resources(struct dma_chan *chan)
784{
785 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100786 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100787 struct imxdma_desc *desc, *_desc;
788 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200789
Javier Martinf606ab82012-03-22 14:54:14 +0100790 spin_lock_irqsave(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200791
Javier Martin6bd08122012-03-22 14:54:01 +0100792 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100793 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
794 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
795
Javier Martinf606ab82012-03-22 14:54:14 +0100796 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100797
798 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
799 kfree(desc);
800 imxdmac->descs_allocated--;
801 }
802 INIT_LIST_HEAD(&imxdmac->ld_free);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200803
Sachin Kamat06f8db42013-09-02 13:21:18 +0530804 kfree(imxdmac->sg_list);
805 imxdmac->sg_list = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200806}
807
808static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
809 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530810 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500811 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200812{
813 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
814 struct scatterlist *sg;
Javier Martin9e15db72012-03-02 09:28:47 +0100815 int i, dma_length = 0;
816 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200817
Javier Martin9e15db72012-03-02 09:28:47 +0100818 if (list_empty(&imxdmac->ld_free) ||
819 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200820 return NULL;
821
Javier Martin9e15db72012-03-02 09:28:47 +0100822 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200823
824 for_each_sg(sgl, sg, sg_len, i) {
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200825 dma_length += sg_dma_len(sg);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200826 }
827
Sascha Hauerd07102a2011-01-12 14:13:23 +0100828 switch (imxdmac->word_size) {
829 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200830 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100831 return NULL;
832 break;
833 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200834 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100835 return NULL;
836 break;
837 case DMA_SLAVE_BUSWIDTH_1_BYTE:
838 break;
839 default:
840 return NULL;
841 }
842
Javier Martin9e15db72012-03-02 09:28:47 +0100843 desc->type = IMXDMA_DESC_SLAVE_SG;
844 desc->sg = sgl;
845 desc->sgcount = sg_len;
846 desc->len = dma_length;
Javier Martin2efc3442012-03-22 14:54:03 +0100847 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100848 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100849 desc->src = imxdmac->per_address;
850 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100851 desc->dest = imxdmac->per_address;
852 }
853 desc->desc.callback = NULL;
854 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200855
Javier Martin9e15db72012-03-02 09:28:47 +0100856 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200857}
858
859static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
860 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500861 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200862 unsigned long flags)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200863{
864 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
865 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100866 struct imxdma_desc *desc;
867 int i;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200868 unsigned int periods = buf_len / period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200869
Russell Kingac806a12013-10-31 00:40:30 +0000870 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200871 __func__, imxdmac->channel, buf_len, period_len);
872
Javier Martin9e15db72012-03-02 09:28:47 +0100873 if (list_empty(&imxdmac->ld_free) ||
874 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200875 return NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200876
Javier Martin9e15db72012-03-02 09:28:47 +0100877 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200878
Syam Sidhardhan96a37132013-02-25 04:46:26 +0530879 kfree(imxdmac->sg_list);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200880
881 imxdmac->sg_list = kcalloc(periods + 1,
Michael Grzeschikedc530f2013-09-17 15:56:06 +0200882 sizeof(struct scatterlist), GFP_ATOMIC);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200883 if (!imxdmac->sg_list)
884 return NULL;
885
886 sg_init_table(imxdmac->sg_list, periods);
887
888 for (i = 0; i < periods; i++) {
889 imxdmac->sg_list[i].page_link = 0;
890 imxdmac->sg_list[i].offset = 0;
891 imxdmac->sg_list[i].dma_address = dma_addr;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200892 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200893 dma_addr += period_len;
894 }
895
896 /* close the loop */
897 imxdmac->sg_list[periods].offset = 0;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200898 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200899 imxdmac->sg_list[periods].page_link =
900 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
901
Javier Martin9e15db72012-03-02 09:28:47 +0100902 desc->type = IMXDMA_DESC_CYCLIC;
903 desc->sg = imxdmac->sg_list;
904 desc->sgcount = periods;
905 desc->len = IMX_DMA_LENGTH_LOOP;
Javier Martin2efc3442012-03-22 14:54:03 +0100906 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100907 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100908 desc->src = imxdmac->per_address;
909 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100910 desc->dest = imxdmac->per_address;
911 }
912 desc->desc.callback = NULL;
913 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200914
Javier Martin9e15db72012-03-02 09:28:47 +0100915 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200916}
917
Javier Martin6c05f092012-02-28 17:08:17 +0100918static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
919 struct dma_chan *chan, dma_addr_t dest,
920 dma_addr_t src, size_t len, unsigned long flags)
921{
922 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
923 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100924 struct imxdma_desc *desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100925
Russell Kingac806a12013-10-31 00:40:30 +0000926 dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
927 __func__, imxdmac->channel, (unsigned long long)src,
928 (unsigned long long)dest, len);
Javier Martin6c05f092012-02-28 17:08:17 +0100929
Javier Martin9e15db72012-03-02 09:28:47 +0100930 if (list_empty(&imxdmac->ld_free) ||
931 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200932 return NULL;
933
Javier Martin9e15db72012-03-02 09:28:47 +0100934 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Javier Martin6c05f092012-02-28 17:08:17 +0100935
Javier Martin9e15db72012-03-02 09:28:47 +0100936 desc->type = IMXDMA_DESC_MEMCPY;
937 desc->src = src;
938 desc->dest = dest;
939 desc->len = len;
Javier Martin2efc3442012-03-22 14:54:03 +0100940 desc->direction = DMA_MEM_TO_MEM;
Javier Martin9e15db72012-03-02 09:28:47 +0100941 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
942 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
943 desc->desc.callback = NULL;
944 desc->desc.callback_param = NULL;
945
946 return &desc->desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100947}
948
Javier Martinf606ab82012-03-22 14:54:14 +0100949static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
950 struct dma_chan *chan, struct dma_interleaved_template *xt,
951 unsigned long flags)
952{
953 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
954 struct imxdma_engine *imxdma = imxdmac->imxdma;
955 struct imxdma_desc *desc;
956
Russell Kingac806a12013-10-31 00:40:30 +0000957 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
958 " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
959 imxdmac->channel, (unsigned long long)xt->src_start,
960 (unsigned long long) xt->dst_start,
Javier Martinf606ab82012-03-22 14:54:14 +0100961 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
962 xt->numf, xt->frame_size);
963
964 if (list_empty(&imxdmac->ld_free) ||
965 imxdma_chan_is_doing_cyclic(imxdmac))
966 return NULL;
967
968 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
969 return NULL;
970
971 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
972
973 desc->type = IMXDMA_DESC_INTERLEAVED;
974 desc->src = xt->src_start;
975 desc->dest = xt->dst_start;
976 desc->x = xt->sgl[0].size;
977 desc->y = xt->numf;
978 desc->w = xt->sgl[0].icg + desc->x;
979 desc->len = desc->x * desc->y;
980 desc->direction = DMA_MEM_TO_MEM;
981 desc->config_port = IMX_DMA_MEMSIZE_32;
982 desc->config_mem = IMX_DMA_MEMSIZE_32;
983 if (xt->src_sgl)
984 desc->config_mem |= IMX_DMA_TYPE_2D;
985 if (xt->dst_sgl)
986 desc->config_port |= IMX_DMA_TYPE_2D;
987 desc->desc.callback = NULL;
988 desc->desc.callback_param = NULL;
989
990 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200991}
992
993static void imxdma_issue_pending(struct dma_chan *chan)
994{
Sascha Hauer5b316872012-01-09 10:32:49 +0100995 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100996 struct imxdma_engine *imxdma = imxdmac->imxdma;
997 struct imxdma_desc *desc;
998 unsigned long flags;
Sascha Hauer5b316872012-01-09 10:32:49 +0100999
Javier Martinf606ab82012-03-22 14:54:14 +01001000 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +01001001 if (list_empty(&imxdmac->ld_active) &&
1002 !list_empty(&imxdmac->ld_queue)) {
1003 desc = list_first_entry(&imxdmac->ld_queue,
1004 struct imxdma_desc, node);
1005
1006 if (imxdma_xfer_desc(desc) < 0) {
1007 dev_warn(imxdma->dev,
1008 "%s: channel: %d couldn't issue DMA xfer\n",
1009 __func__, imxdmac->channel);
1010 } else {
1011 list_move_tail(imxdmac->ld_queue.next,
1012 &imxdmac->ld_active);
1013 }
1014 }
Javier Martinf606ab82012-03-22 14:54:14 +01001015 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001016}
1017
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001018static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
1019{
1020 struct imxdma_filter_data *fdata = param;
1021 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
1022
1023 if (chan->device->dev != fdata->imxdma->dev)
1024 return false;
1025
1026 imxdma_chan->dma_request = fdata->request;
1027 chan->private = NULL;
1028
1029 return true;
1030}
1031
1032static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
1033 struct of_dma *ofdma)
1034{
1035 int count = dma_spec->args_count;
1036 struct imxdma_engine *imxdma = ofdma->of_dma_data;
1037 struct imxdma_filter_data fdata = {
1038 .imxdma = imxdma,
1039 };
1040
1041 if (count != 1)
1042 return NULL;
1043
1044 fdata.request = dma_spec->args[0];
1045
1046 return dma_request_channel(imxdma->dma_device.cap_mask,
1047 imxdma_filter_fn, &fdata);
1048}
1049
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001050static int __init imxdma_probe(struct platform_device *pdev)
Javier Martin6bd08122012-03-22 14:54:01 +01001051 {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001052 struct imxdma_engine *imxdma;
Shawn Guo73930eb2012-09-15 15:57:00 +08001053 struct resource *res;
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001054 const struct of_device_id *of_id;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001055 int ret, i;
Shawn Guo73930eb2012-09-15 15:57:00 +08001056 int irq, irq_err;
Javier Martin6bd08122012-03-22 14:54:01 +01001057
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001058 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
1059 if (of_id)
1060 pdev->id_entry = of_id->data;
1061
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001062 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001063 if (!imxdma)
1064 return -ENOMEM;
1065
Markus Pargmann5c6b3e72013-05-26 11:53:21 +02001066 imxdma->dev = &pdev->dev;
Shawn Guoe51d0f02012-09-15 21:11:28 +08001067 imxdma->devtype = pdev->id_entry->driver_data;
1068
Shawn Guo73930eb2012-09-15 15:57:00 +08001069 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding73312052013-01-21 11:09:00 +01001070 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1071 if (IS_ERR(imxdma->base))
1072 return PTR_ERR(imxdma->base);
Shawn Guo73930eb2012-09-15 15:57:00 +08001073
1074 irq = platform_get_irq(pdev, 0);
1075 if (irq < 0)
1076 return irq;
Javier Martincd5cf9d2012-03-22 14:54:12 +01001077
Fabio Estevama2367db2012-07-03 15:33:29 -03001078 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001079 if (IS_ERR(imxdma->dma_ipg))
1080 return PTR_ERR(imxdma->dma_ipg);
Fabio Estevama2367db2012-07-03 15:33:29 -03001081
1082 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001083 if (IS_ERR(imxdma->dma_ahb))
1084 return PTR_ERR(imxdma->dma_ahb);
Fabio Estevama2367db2012-07-03 15:33:29 -03001085
Fabio Estevamfce9a742015-06-20 18:43:44 -03001086 ret = clk_prepare_enable(imxdma->dma_ipg);
1087 if (ret)
1088 return ret;
1089 ret = clk_prepare_enable(imxdma->dma_ahb);
1090 if (ret)
1091 goto disable_dma_ipg_clk;
Javier Martin6bd08122012-03-22 14:54:01 +01001092
1093 /* reset DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001094 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001095
Shawn Guoe51d0f02012-09-15 21:11:28 +08001096 if (is_imx1_dma(imxdma)) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001097 ret = devm_request_irq(&pdev->dev, irq,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001098 dma_irq_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001099 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001100 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
Fabio Estevamfce9a742015-06-20 18:43:44 -03001101 goto disable_dma_ahb_clk;
Javier Martin6bd08122012-03-22 14:54:01 +01001102 }
1103
Shawn Guo73930eb2012-09-15 15:57:00 +08001104 irq_err = platform_get_irq(pdev, 1);
1105 if (irq_err < 0) {
1106 ret = irq_err;
Fabio Estevamfce9a742015-06-20 18:43:44 -03001107 goto disable_dma_ahb_clk;
Shawn Guo73930eb2012-09-15 15:57:00 +08001108 }
1109
1110 ret = devm_request_irq(&pdev->dev, irq_err,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001111 imxdma_err_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001112 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001113 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
Fabio Estevamfce9a742015-06-20 18:43:44 -03001114 goto disable_dma_ahb_clk;
Javier Martin6bd08122012-03-22 14:54:01 +01001115 }
1116 }
1117
1118 /* enable DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001119 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001120
1121 /* clear all interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001122 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +01001123
1124 /* disable interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001125 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001126
1127 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1128
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001129 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1130 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
Javier Martin6c05f092012-02-28 17:08:17 +01001131 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
Javier Martinf606ab82012-03-22 14:54:14 +01001132 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1133
1134 /* Initialize 2D global parameters */
1135 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1136 imxdma->slots_2d[i].count = 0;
1137
1138 spin_lock_init(&imxdma->lock);
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001139
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001140 /* Initialize channel parameters */
Javier Martin6bd08122012-03-22 14:54:01 +01001141 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001142 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1143
Shawn Guoe51d0f02012-09-15 21:11:28 +08001144 if (!is_imx1_dma(imxdma)) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001145 ret = devm_request_irq(&pdev->dev, irq + i,
Javier Martin6bd08122012-03-22 14:54:01 +01001146 dma_irq_handler, 0, "DMA", imxdma);
1147 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001148 dev_warn(imxdma->dev, "Can't register IRQ %d "
1149 "for DMA channel %d\n",
Shawn Guo73930eb2012-09-15 15:57:00 +08001150 irq + i, i);
Fabio Estevamfce9a742015-06-20 18:43:44 -03001151 goto disable_dma_ahb_clk;
Javier Martin6bd08122012-03-22 14:54:01 +01001152 }
Javier Martin2d9c2fc2012-03-22 14:54:10 +01001153 init_timer(&imxdmac->watchdog);
1154 imxdmac->watchdog.function = &imxdma_watchdog;
1155 imxdmac->watchdog.data = (unsigned long)imxdmac;
Sascha Hauer8267f162010-10-20 08:37:19 +02001156 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001157
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001158 imxdmac->imxdma = imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001159
Javier Martin9e15db72012-03-02 09:28:47 +01001160 INIT_LIST_HEAD(&imxdmac->ld_queue);
1161 INIT_LIST_HEAD(&imxdmac->ld_free);
1162 INIT_LIST_HEAD(&imxdmac->ld_active);
1163
1164 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1165 (unsigned long)imxdmac);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001166 imxdmac->chan.device = &imxdma->dma_device;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001167 dma_cookie_init(&imxdmac->chan);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001168 imxdmac->channel = i;
1169
1170 /* Add the channel to the DMAC list */
Javier Martin9e15db72012-03-02 09:28:47 +01001171 list_add_tail(&imxdmac->chan.device_node,
1172 &imxdma->dma_device.channels);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001173 }
1174
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001175 imxdma->dma_device.dev = &pdev->dev;
1176
1177 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1178 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1179 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1180 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1181 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
Javier Martin6c05f092012-02-28 17:08:17 +01001182 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
Javier Martinf606ab82012-03-22 14:54:14 +01001183 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
Maxime Ripard502c2ef2014-11-17 14:42:16 +01001184 imxdma->dma_device.device_config = imxdma_config;
1185 imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001186 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1187
1188 platform_set_drvdata(pdev, imxdma);
1189
Maxime Ripard77a68e52015-07-20 10:41:32 +02001190 imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
Sascha Hauer1e070a62011-01-12 13:14:37 +01001191 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1192 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1193
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001194 ret = dma_async_device_register(&imxdma->dma_device);
1195 if (ret) {
1196 dev_err(&pdev->dev, "unable to register\n");
Fabio Estevamfce9a742015-06-20 18:43:44 -03001197 goto disable_dma_ahb_clk;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001198 }
1199
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001200 if (pdev->dev.of_node) {
1201 ret = of_dma_controller_register(pdev->dev.of_node,
1202 imxdma_xlate, imxdma);
1203 if (ret) {
1204 dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1205 goto err_of_dma_controller;
1206 }
1207 }
1208
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001209 return 0;
1210
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001211err_of_dma_controller:
1212 dma_async_device_unregister(&imxdma->dma_device);
Fabio Estevamfce9a742015-06-20 18:43:44 -03001213disable_dma_ahb_clk:
Fabio Estevama2367db2012-07-03 15:33:29 -03001214 clk_disable_unprepare(imxdma->dma_ahb);
Fabio Estevamfce9a742015-06-20 18:43:44 -03001215disable_dma_ipg_clk:
1216 clk_disable_unprepare(imxdma->dma_ipg);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001217 return ret;
1218}
1219
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001220static int imxdma_remove(struct platform_device *pdev)
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001221{
1222 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001223
1224 dma_async_device_unregister(&imxdma->dma_device);
1225
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001226 if (pdev->dev.of_node)
1227 of_dma_controller_free(pdev->dev.of_node);
1228
Fabio Estevama2367db2012-07-03 15:33:29 -03001229 clk_disable_unprepare(imxdma->dma_ipg);
1230 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001231
1232 return 0;
1233}
1234
1235static struct platform_driver imxdma_driver = {
1236 .driver = {
1237 .name = "imx-dma",
Markus Pargmann290ad0f2013-05-26 11:53:20 +02001238 .of_match_table = imx_dma_of_dev_id,
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001239 },
Shawn Guoe51d0f02012-09-15 21:11:28 +08001240 .id_table = imx_dma_devtype,
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001241 .remove = imxdma_remove,
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001242};
1243
1244static int __init imxdma_module_init(void)
1245{
1246 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1247}
1248subsys_initcall(imxdma_module_init);
1249
1250MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1251MODULE_DESCRIPTION("i.MX dma driver");
1252MODULE_LICENSE("GPL");