Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Samsung SoC DP (Display Port) interface driver. |
| 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. |
| 5 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/delay.h> |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 21 | #include <linux/of.h> |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 22 | |
| 23 | #include <video/exynos_dp.h> |
| 24 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 25 | #include "exynos_dp_core.h" |
| 26 | |
| 27 | static int exynos_dp_init_dp(struct exynos_dp_device *dp) |
| 28 | { |
| 29 | exynos_dp_reset(dp); |
| 30 | |
Jingoo Han | 24db03a | 2012-05-25 16:21:08 +0900 | [diff] [blame] | 31 | exynos_dp_swreset(dp); |
| 32 | |
Jingoo Han | 75435c7 | 2012-08-23 19:55:13 +0900 | [diff] [blame] | 33 | exynos_dp_init_analog_param(dp); |
| 34 | exynos_dp_init_interrupt(dp); |
| 35 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 36 | /* SW defined function Normal operation */ |
| 37 | exynos_dp_enable_sw_function(dp); |
| 38 | |
| 39 | exynos_dp_config_interrupt(dp); |
| 40 | exynos_dp_init_analog_func(dp); |
| 41 | |
| 42 | exynos_dp_init_hpd(dp); |
| 43 | exynos_dp_init_aux(dp); |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | |
| 48 | static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) |
| 49 | { |
| 50 | int timeout_loop = 0; |
| 51 | |
| 52 | exynos_dp_init_hpd(dp); |
| 53 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 54 | usleep_range(200, 210); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 55 | |
| 56 | while (exynos_dp_get_plug_in_status(dp) != 0) { |
| 57 | timeout_loop++; |
| 58 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 59 | dev_err(dp->dev, "failed to get hpd plug status\n"); |
| 60 | return -ETIMEDOUT; |
| 61 | } |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 62 | usleep_range(10, 11); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) |
| 69 | { |
| 70 | int i; |
| 71 | unsigned char sum = 0; |
| 72 | |
| 73 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) |
| 74 | sum = sum + edid_data[i]; |
| 75 | |
| 76 | return sum; |
| 77 | } |
| 78 | |
| 79 | static int exynos_dp_read_edid(struct exynos_dp_device *dp) |
| 80 | { |
| 81 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; |
| 82 | unsigned int extend_block = 0; |
| 83 | unsigned char sum; |
| 84 | unsigned char test_vector; |
| 85 | int retval; |
| 86 | |
| 87 | /* |
| 88 | * EDID device address is 0x50. |
| 89 | * However, if necessary, you must have set upper address |
| 90 | * into E-EDID in I2C device, 0x30. |
| 91 | */ |
| 92 | |
| 93 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 94 | retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 95 | EDID_EXTENSION_FLAG, |
| 96 | &extend_block); |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 97 | if (retval) |
| 98 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 99 | |
| 100 | if (extend_block > 0) { |
| 101 | dev_dbg(dp->dev, "EDID data includes a single extension!\n"); |
| 102 | |
| 103 | /* Read EDID data */ |
| 104 | retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
| 105 | EDID_HEADER_PATTERN, |
| 106 | EDID_BLOCK_LENGTH, |
| 107 | &edid[EDID_HEADER_PATTERN]); |
| 108 | if (retval != 0) { |
| 109 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 110 | return -EIO; |
| 111 | } |
| 112 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 113 | if (sum != 0) { |
| 114 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 115 | return -EIO; |
| 116 | } |
| 117 | |
| 118 | /* Read additional EDID data */ |
| 119 | retval = exynos_dp_read_bytes_from_i2c(dp, |
| 120 | I2C_EDID_DEVICE_ADDR, |
| 121 | EDID_BLOCK_LENGTH, |
| 122 | EDID_BLOCK_LENGTH, |
| 123 | &edid[EDID_BLOCK_LENGTH]); |
| 124 | if (retval != 0) { |
| 125 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 126 | return -EIO; |
| 127 | } |
| 128 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); |
| 129 | if (sum != 0) { |
| 130 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 131 | return -EIO; |
| 132 | } |
| 133 | |
| 134 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST, |
| 135 | &test_vector); |
| 136 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 137 | exynos_dp_write_byte_to_dpcd(dp, |
| 138 | DPCD_ADDR_TEST_EDID_CHECKSUM, |
| 139 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); |
| 140 | exynos_dp_write_byte_to_dpcd(dp, |
| 141 | DPCD_ADDR_TEST_RESPONSE, |
| 142 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 143 | } |
| 144 | } else { |
| 145 | dev_info(dp->dev, "EDID data does not include any extensions.\n"); |
| 146 | |
| 147 | /* Read EDID data */ |
| 148 | retval = exynos_dp_read_bytes_from_i2c(dp, |
| 149 | I2C_EDID_DEVICE_ADDR, |
| 150 | EDID_HEADER_PATTERN, |
| 151 | EDID_BLOCK_LENGTH, |
| 152 | &edid[EDID_HEADER_PATTERN]); |
| 153 | if (retval != 0) { |
| 154 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 155 | return -EIO; |
| 156 | } |
| 157 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 158 | if (sum != 0) { |
| 159 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 160 | return -EIO; |
| 161 | } |
| 162 | |
| 163 | exynos_dp_read_byte_from_dpcd(dp, |
| 164 | DPCD_ADDR_TEST_REQUEST, |
| 165 | &test_vector); |
| 166 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 167 | exynos_dp_write_byte_to_dpcd(dp, |
| 168 | DPCD_ADDR_TEST_EDID_CHECKSUM, |
| 169 | edid[EDID_CHECKSUM]); |
| 170 | exynos_dp_write_byte_to_dpcd(dp, |
| 171 | DPCD_ADDR_TEST_RESPONSE, |
| 172 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | dev_err(dp->dev, "EDID Read success!\n"); |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static int exynos_dp_handle_edid(struct exynos_dp_device *dp) |
| 181 | { |
| 182 | u8 buf[12]; |
| 183 | int i; |
| 184 | int retval; |
| 185 | |
| 186 | /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */ |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 187 | retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV, |
| 188 | 12, buf); |
| 189 | if (retval) |
| 190 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 191 | |
| 192 | /* Read EDID */ |
| 193 | for (i = 0; i < 3; i++) { |
| 194 | retval = exynos_dp_read_edid(dp); |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 195 | if (!retval) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 196 | break; |
| 197 | } |
| 198 | |
| 199 | return retval; |
| 200 | } |
| 201 | |
| 202 | static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, |
| 203 | bool enable) |
| 204 | { |
| 205 | u8 data; |
| 206 | |
| 207 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data); |
| 208 | |
| 209 | if (enable) |
| 210 | exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, |
| 211 | DPCD_ENHANCED_FRAME_EN | |
| 212 | DPCD_LANE_COUNT_SET(data)); |
| 213 | else |
| 214 | exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, |
| 215 | DPCD_LANE_COUNT_SET(data)); |
| 216 | } |
| 217 | |
| 218 | static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) |
| 219 | { |
| 220 | u8 data; |
| 221 | int retval; |
| 222 | |
| 223 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); |
| 224 | retval = DPCD_ENHANCED_FRAME_CAP(data); |
| 225 | |
| 226 | return retval; |
| 227 | } |
| 228 | |
| 229 | static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp) |
| 230 | { |
| 231 | u8 data; |
| 232 | |
| 233 | data = exynos_dp_is_enhanced_mode_available(dp); |
| 234 | exynos_dp_enable_rx_to_enhanced_mode(dp, data); |
| 235 | exynos_dp_enable_enhanced_mode(dp, data); |
| 236 | } |
| 237 | |
| 238 | static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) |
| 239 | { |
| 240 | exynos_dp_set_training_pattern(dp, DP_NONE); |
| 241 | |
| 242 | exynos_dp_write_byte_to_dpcd(dp, |
| 243 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 244 | DPCD_TRAINING_PATTERN_DISABLED); |
| 245 | } |
| 246 | |
| 247 | static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, |
| 248 | int pre_emphasis, int lane) |
| 249 | { |
| 250 | switch (lane) { |
| 251 | case 0: |
| 252 | exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis); |
| 253 | break; |
| 254 | case 1: |
| 255 | exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis); |
| 256 | break; |
| 257 | |
| 258 | case 2: |
| 259 | exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis); |
| 260 | break; |
| 261 | |
| 262 | case 3: |
| 263 | exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis); |
| 264 | break; |
| 265 | } |
| 266 | } |
| 267 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 268 | static int exynos_dp_link_start(struct exynos_dp_device *dp) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 269 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 270 | u8 buf[4]; |
Sean Paul | 49ce41f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 271 | int lane, lane_count, pll_tries, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 272 | |
| 273 | lane_count = dp->link_train.lane_count; |
| 274 | |
| 275 | dp->link_train.lt_state = CLOCK_RECOVERY; |
| 276 | dp->link_train.eq_loop = 0; |
| 277 | |
| 278 | for (lane = 0; lane < lane_count; lane++) |
| 279 | dp->link_train.cr_loop[lane] = 0; |
| 280 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 281 | /* Set link rate and count as you want to establish*/ |
| 282 | exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); |
| 283 | exynos_dp_set_lane_count(dp, dp->link_train.lane_count); |
| 284 | |
| 285 | /* Setup RX configuration */ |
| 286 | buf[0] = dp->link_train.link_rate; |
| 287 | buf[1] = dp->link_train.lane_count; |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 288 | retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 289 | 2, buf); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 290 | if (retval) |
| 291 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 292 | |
| 293 | /* Set TX pre-emphasis to minimum */ |
| 294 | for (lane = 0; lane < lane_count; lane++) |
| 295 | exynos_dp_set_lane_lane_pre_emphasis(dp, |
| 296 | PRE_EMPHASIS_LEVEL_0, lane); |
| 297 | |
Sean Paul | 49ce41f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 298 | /* Wait for PLL lock */ |
| 299 | pll_tries = 0; |
| 300 | while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
| 301 | if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { |
| 302 | dev_err(dp->dev, "Wait for PLL lock timed out\n"); |
| 303 | return -ETIMEDOUT; |
| 304 | } |
| 305 | |
| 306 | pll_tries++; |
| 307 | usleep_range(90, 120); |
| 308 | } |
| 309 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 310 | /* Set training pattern 1 */ |
| 311 | exynos_dp_set_training_pattern(dp, TRAINING_PTN1); |
| 312 | |
| 313 | /* Set RX training pattern */ |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 314 | retval = exynos_dp_write_byte_to_dpcd(dp, |
| 315 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 316 | DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1); |
| 317 | if (retval) |
| 318 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 319 | |
| 320 | for (lane = 0; lane < lane_count; lane++) |
| 321 | buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | |
| 322 | DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 323 | |
| 324 | retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, |
| 325 | lane_count, buf); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 326 | |
| 327 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 328 | } |
| 329 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 330 | static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 331 | { |
| 332 | int shift = (lane & 1) * 4; |
| 333 | u8 link_value = link_status[lane>>1]; |
| 334 | |
| 335 | return (link_value >> shift) & 0xf; |
| 336 | } |
| 337 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 338 | static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 339 | { |
| 340 | int lane; |
| 341 | u8 lane_status; |
| 342 | |
| 343 | for (lane = 0; lane < lane_count; lane++) { |
| 344 | lane_status = exynos_dp_get_lane_status(link_status, lane); |
| 345 | if ((lane_status & DPCD_LANE_CR_DONE) == 0) |
| 346 | return -EINVAL; |
| 347 | } |
| 348 | return 0; |
| 349 | } |
| 350 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 351 | static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, |
| 352 | int lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 353 | { |
| 354 | int lane; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 355 | u8 lane_status; |
| 356 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 357 | if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 358 | return -EINVAL; |
| 359 | |
| 360 | for (lane = 0; lane < lane_count; lane++) { |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 361 | lane_status = exynos_dp_get_lane_status(link_status, lane); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 362 | lane_status &= DPCD_CHANNEL_EQ_BITS; |
| 363 | if (lane_status != DPCD_CHANNEL_EQ_BITS) |
| 364 | return -EINVAL; |
| 365 | } |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 366 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], |
| 371 | int lane) |
| 372 | { |
| 373 | int shift = (lane & 1) * 4; |
| 374 | u8 link_value = adjust_request[lane>>1]; |
| 375 | |
| 376 | return (link_value >> shift) & 0x3; |
| 377 | } |
| 378 | |
| 379 | static unsigned char exynos_dp_get_adjust_request_pre_emphasis( |
| 380 | u8 adjust_request[2], |
| 381 | int lane) |
| 382 | { |
| 383 | int shift = (lane & 1) * 4; |
| 384 | u8 link_value = adjust_request[lane>>1]; |
| 385 | |
| 386 | return ((link_value >> shift) & 0xc) >> 2; |
| 387 | } |
| 388 | |
| 389 | static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, |
| 390 | u8 training_lane_set, int lane) |
| 391 | { |
| 392 | switch (lane) { |
| 393 | case 0: |
| 394 | exynos_dp_set_lane0_link_training(dp, training_lane_set); |
| 395 | break; |
| 396 | case 1: |
| 397 | exynos_dp_set_lane1_link_training(dp, training_lane_set); |
| 398 | break; |
| 399 | |
| 400 | case 2: |
| 401 | exynos_dp_set_lane2_link_training(dp, training_lane_set); |
| 402 | break; |
| 403 | |
| 404 | case 3: |
| 405 | exynos_dp_set_lane3_link_training(dp, training_lane_set); |
| 406 | break; |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | static unsigned int exynos_dp_get_lane_link_training( |
| 411 | struct exynos_dp_device *dp, |
| 412 | int lane) |
| 413 | { |
| 414 | u32 reg; |
| 415 | |
| 416 | switch (lane) { |
| 417 | case 0: |
| 418 | reg = exynos_dp_get_lane0_link_training(dp); |
| 419 | break; |
| 420 | case 1: |
| 421 | reg = exynos_dp_get_lane1_link_training(dp); |
| 422 | break; |
| 423 | case 2: |
| 424 | reg = exynos_dp_get_lane2_link_training(dp); |
| 425 | break; |
| 426 | case 3: |
| 427 | reg = exynos_dp_get_lane3_link_training(dp); |
| 428 | break; |
Jingoo Han | 64c43df | 2012-06-20 10:25:48 +0900 | [diff] [blame] | 429 | default: |
| 430 | WARN_ON(1); |
| 431 | return 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | return reg; |
| 435 | } |
| 436 | |
| 437 | static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) |
| 438 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 439 | exynos_dp_training_pattern_dis(dp); |
| 440 | exynos_dp_set_enhanced_mode(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 441 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 442 | dp->link_train.lt_state = FAILED; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 443 | } |
| 444 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 445 | static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, |
| 446 | u8 adjust_request[2]) |
| 447 | { |
| 448 | int lane, lane_count; |
| 449 | u8 voltage_swing, pre_emphasis, training_lane; |
| 450 | |
| 451 | lane_count = dp->link_train.lane_count; |
| 452 | for (lane = 0; lane < lane_count; lane++) { |
| 453 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 454 | adjust_request, lane); |
| 455 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 456 | adjust_request, lane); |
| 457 | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | |
| 458 | DPCD_PRE_EMPHASIS_SET(pre_emphasis); |
| 459 | |
| 460 | if (voltage_swing == VOLTAGE_LEVEL_3) |
| 461 | training_lane |= DPCD_MAX_SWING_REACHED; |
| 462 | if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) |
| 463 | training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; |
| 464 | |
| 465 | dp->link_train.training_lane[lane] = training_lane; |
| 466 | } |
| 467 | } |
| 468 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 469 | static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) |
| 470 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 471 | int lane, lane_count, retval; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 472 | u8 voltage_swing, pre_emphasis, training_lane; |
| 473 | u8 link_status[2], adjust_request[2]; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 474 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 475 | usleep_range(100, 101); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 476 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 477 | lane_count = dp->link_train.lane_count; |
| 478 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 479 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
| 480 | DPCD_ADDR_LANE0_1_STATUS, 2, link_status); |
| 481 | if (retval) |
| 482 | return retval; |
| 483 | |
| 484 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
| 485 | DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 486 | if (retval) |
| 487 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 488 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 489 | if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
| 490 | /* set training pattern 2 for EQ */ |
| 491 | exynos_dp_set_training_pattern(dp, TRAINING_PTN2); |
| 492 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 493 | retval = exynos_dp_write_byte_to_dpcd(dp, |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 494 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 495 | DPCD_SCRAMBLING_DISABLED | |
| 496 | DPCD_TRAINING_PATTERN_2); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 497 | if (retval) |
| 498 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 499 | |
| 500 | dev_info(dp->dev, "Link Training Clock Recovery success\n"); |
| 501 | dp->link_train.lt_state = EQUALIZER_TRAINING; |
| 502 | } else { |
| 503 | for (lane = 0; lane < lane_count; lane++) { |
| 504 | training_lane = exynos_dp_get_lane_link_training( |
| 505 | dp, lane); |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 506 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 507 | adjust_request, lane); |
| 508 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 509 | adjust_request, lane); |
| 510 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 511 | if (DPCD_VOLTAGE_SWING_GET(training_lane) == |
| 512 | voltage_swing && |
| 513 | DPCD_PRE_EMPHASIS_GET(training_lane) == |
| 514 | pre_emphasis) |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 515 | dp->link_train.cr_loop[lane]++; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 516 | |
| 517 | if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || |
| 518 | voltage_swing == VOLTAGE_LEVEL_3 || |
| 519 | pre_emphasis == PRE_EMPHASIS_LEVEL_3) { |
| 520 | dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", |
| 521 | dp->link_train.cr_loop[lane], |
| 522 | voltage_swing, pre_emphasis); |
| 523 | exynos_dp_reduce_link_rate(dp); |
| 524 | return -EIO; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 525 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 526 | } |
| 527 | } |
| 528 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 529 | exynos_dp_get_adjust_training_lane(dp, adjust_request); |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 530 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 531 | for (lane = 0; lane < lane_count; lane++) |
| 532 | exynos_dp_set_lane_link_training(dp, |
| 533 | dp->link_train.training_lane[lane], lane); |
| 534 | |
| 535 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
| 536 | DPCD_ADDR_TRAINING_LANE0_SET, lane_count, |
| 537 | dp->link_train.training_lane); |
| 538 | if (retval) |
| 539 | return retval; |
| 540 | |
| 541 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) |
| 545 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 546 | int lane, lane_count, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 547 | u32 reg; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 548 | u8 link_align, link_status[2], adjust_request[2]; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 549 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 550 | usleep_range(400, 401); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 551 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 552 | lane_count = dp->link_train.lane_count; |
| 553 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 554 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
| 555 | DPCD_ADDR_LANE0_1_STATUS, 2, link_status); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 556 | if (retval) |
| 557 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 558 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 559 | if (exynos_dp_clock_recovery_ok(link_status, lane_count)) { |
| 560 | exynos_dp_reduce_link_rate(dp); |
| 561 | return -EIO; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 562 | } |
| 563 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 564 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
| 565 | DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); |
| 566 | if (retval) |
| 567 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 568 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 569 | retval = exynos_dp_read_byte_from_dpcd(dp, |
| 570 | DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align); |
| 571 | if (retval) |
| 572 | return retval; |
| 573 | |
| 574 | exynos_dp_get_adjust_training_lane(dp, adjust_request); |
| 575 | |
| 576 | if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) { |
| 577 | /* traing pattern Set to Normal */ |
| 578 | exynos_dp_training_pattern_dis(dp); |
| 579 | |
| 580 | dev_info(dp->dev, "Link Training success!\n"); |
| 581 | |
| 582 | exynos_dp_get_link_bandwidth(dp, ®); |
| 583 | dp->link_train.link_rate = reg; |
| 584 | dev_dbg(dp->dev, "final bandwidth = %.2x\n", |
| 585 | dp->link_train.link_rate); |
| 586 | |
| 587 | exynos_dp_get_lane_count(dp, ®); |
| 588 | dp->link_train.lane_count = reg; |
| 589 | dev_dbg(dp->dev, "final lane count = %.2x\n", |
| 590 | dp->link_train.lane_count); |
| 591 | |
| 592 | /* set enhanced mode if available */ |
| 593 | exynos_dp_set_enhanced_mode(dp); |
| 594 | dp->link_train.lt_state = FINISHED; |
| 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | /* not all locked */ |
| 600 | dp->link_train.eq_loop++; |
| 601 | |
| 602 | if (dp->link_train.eq_loop > MAX_EQ_LOOP) { |
| 603 | dev_err(dp->dev, "EQ Max loop\n"); |
| 604 | exynos_dp_reduce_link_rate(dp); |
| 605 | return -EIO; |
| 606 | } |
| 607 | |
| 608 | for (lane = 0; lane < lane_count; lane++) |
| 609 | exynos_dp_set_lane_link_training(dp, |
| 610 | dp->link_train.training_lane[lane], lane); |
| 611 | |
| 612 | retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, |
| 613 | lane_count, dp->link_train.training_lane); |
| 614 | |
| 615 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 616 | } |
| 617 | |
| 618 | static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 619 | u8 *bandwidth) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 620 | { |
| 621 | u8 data; |
| 622 | |
| 623 | /* |
| 624 | * For DP rev.1.1, Maximum link rate of Main Link lanes |
| 625 | * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps |
| 626 | */ |
| 627 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); |
| 628 | *bandwidth = data; |
| 629 | } |
| 630 | |
| 631 | static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 632 | u8 *lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 633 | { |
| 634 | u8 data; |
| 635 | |
| 636 | /* |
| 637 | * For DP rev.1.1, Maximum number of Main Link lanes |
| 638 | * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes |
| 639 | */ |
| 640 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); |
| 641 | *lane_count = DPCD_MAX_LANE_COUNT(data); |
| 642 | } |
| 643 | |
| 644 | static void exynos_dp_init_training(struct exynos_dp_device *dp, |
| 645 | enum link_lane_count_type max_lane, |
| 646 | enum link_rate_type max_rate) |
| 647 | { |
| 648 | /* |
| 649 | * MACRO_RST must be applied after the PLL_LOCK to avoid |
| 650 | * the DP inter pair skew issue for at least 10 us |
| 651 | */ |
| 652 | exynos_dp_reset_macro(dp); |
| 653 | |
| 654 | /* Initialize by reading RX's DPCD */ |
| 655 | exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); |
| 656 | exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); |
| 657 | |
| 658 | if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && |
| 659 | (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { |
| 660 | dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", |
| 661 | dp->link_train.link_rate); |
| 662 | dp->link_train.link_rate = LINK_RATE_1_62GBPS; |
| 663 | } |
| 664 | |
| 665 | if (dp->link_train.lane_count == 0) { |
| 666 | dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", |
| 667 | dp->link_train.lane_count); |
| 668 | dp->link_train.lane_count = (u8)LANE_COUNT1; |
| 669 | } |
| 670 | |
| 671 | /* Setup TX lane count & rate */ |
| 672 | if (dp->link_train.lane_count > max_lane) |
| 673 | dp->link_train.lane_count = max_lane; |
| 674 | if (dp->link_train.link_rate > max_rate) |
| 675 | dp->link_train.link_rate = max_rate; |
| 676 | |
| 677 | /* All DP analog module power up */ |
| 678 | exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); |
| 679 | } |
| 680 | |
| 681 | static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) |
| 682 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 683 | int retval = 0, training_finished = 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 684 | |
| 685 | dp->link_train.lt_state = START; |
| 686 | |
| 687 | /* Process here */ |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 688 | while (!retval && !training_finished) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 689 | switch (dp->link_train.lt_state) { |
| 690 | case START: |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 691 | retval = exynos_dp_link_start(dp); |
| 692 | if (retval) |
| 693 | dev_err(dp->dev, "LT link start failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 694 | break; |
| 695 | case CLOCK_RECOVERY: |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 696 | retval = exynos_dp_process_clock_recovery(dp); |
| 697 | if (retval) |
| 698 | dev_err(dp->dev, "LT CR failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 699 | break; |
| 700 | case EQUALIZER_TRAINING: |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 701 | retval = exynos_dp_process_equalizer_training(dp); |
| 702 | if (retval) |
| 703 | dev_err(dp->dev, "LT EQ failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 704 | break; |
| 705 | case FINISHED: |
| 706 | training_finished = 1; |
| 707 | break; |
| 708 | case FAILED: |
| 709 | return -EREMOTEIO; |
| 710 | } |
| 711 | } |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 712 | if (retval) |
| 713 | dev_err(dp->dev, "eDP link training failed (%d)\n", retval); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 714 | |
| 715 | return retval; |
| 716 | } |
| 717 | |
| 718 | static int exynos_dp_set_link_train(struct exynos_dp_device *dp, |
| 719 | u32 count, |
| 720 | u32 bwtype) |
| 721 | { |
| 722 | int i; |
| 723 | int retval; |
| 724 | |
| 725 | for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { |
| 726 | exynos_dp_init_training(dp, count, bwtype); |
| 727 | retval = exynos_dp_sw_link_training(dp); |
| 728 | if (retval == 0) |
| 729 | break; |
| 730 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 731 | usleep_range(100, 110); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 732 | } |
| 733 | |
| 734 | return retval; |
| 735 | } |
| 736 | |
| 737 | static int exynos_dp_config_video(struct exynos_dp_device *dp, |
| 738 | struct video_info *video_info) |
| 739 | { |
| 740 | int retval = 0; |
| 741 | int timeout_loop = 0; |
| 742 | int done_count = 0; |
| 743 | |
| 744 | exynos_dp_config_video_slave_mode(dp, video_info); |
| 745 | |
| 746 | exynos_dp_set_video_color_format(dp, video_info->color_depth, |
| 747 | video_info->color_space, |
| 748 | video_info->dynamic_range, |
| 749 | video_info->ycbcr_coeff); |
| 750 | |
| 751 | if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
| 752 | dev_err(dp->dev, "PLL is not locked yet.\n"); |
| 753 | return -EINVAL; |
| 754 | } |
| 755 | |
| 756 | for (;;) { |
| 757 | timeout_loop++; |
| 758 | if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0) |
| 759 | break; |
| 760 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 761 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); |
| 762 | return -ETIMEDOUT; |
| 763 | } |
| 764 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 765 | usleep_range(1, 2); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | /* Set to use the register calculated M/N video */ |
| 769 | exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); |
| 770 | |
| 771 | /* For video bist, Video timing must be generated by register */ |
| 772 | exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); |
| 773 | |
| 774 | /* Disable video mute */ |
| 775 | exynos_dp_enable_video_mute(dp, 0); |
| 776 | |
| 777 | /* Configure video slave mode */ |
| 778 | exynos_dp_enable_video_master(dp, 0); |
| 779 | |
| 780 | /* Enable video */ |
| 781 | exynos_dp_start_video(dp); |
| 782 | |
| 783 | timeout_loop = 0; |
| 784 | |
| 785 | for (;;) { |
| 786 | timeout_loop++; |
| 787 | if (exynos_dp_is_video_stream_on(dp) == 0) { |
| 788 | done_count++; |
| 789 | if (done_count > 10) |
| 790 | break; |
| 791 | } else if (done_count) { |
| 792 | done_count = 0; |
| 793 | } |
| 794 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 795 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); |
| 796 | return -ETIMEDOUT; |
| 797 | } |
| 798 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 799 | usleep_range(1000, 1001); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 800 | } |
| 801 | |
| 802 | if (retval != 0) |
| 803 | dev_err(dp->dev, "Video stream is not detected!\n"); |
| 804 | |
| 805 | return retval; |
| 806 | } |
| 807 | |
| 808 | static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) |
| 809 | { |
| 810 | u8 data; |
| 811 | |
| 812 | if (enable) { |
| 813 | exynos_dp_enable_scrambling(dp); |
| 814 | |
| 815 | exynos_dp_read_byte_from_dpcd(dp, |
| 816 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 817 | &data); |
| 818 | exynos_dp_write_byte_to_dpcd(dp, |
| 819 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 820 | (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); |
| 821 | } else { |
| 822 | exynos_dp_disable_scrambling(dp); |
| 823 | |
| 824 | exynos_dp_read_byte_from_dpcd(dp, |
| 825 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 826 | &data); |
| 827 | exynos_dp_write_byte_to_dpcd(dp, |
| 828 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 829 | (u8)(data | DPCD_SCRAMBLING_DISABLED)); |
| 830 | } |
| 831 | } |
| 832 | |
| 833 | static irqreturn_t exynos_dp_irq_handler(int irq, void *arg) |
| 834 | { |
| 835 | struct exynos_dp_device *dp = arg; |
| 836 | |
| 837 | dev_err(dp->dev, "exynos_dp_irq_handler\n"); |
| 838 | return IRQ_HANDLED; |
| 839 | } |
| 840 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 841 | static void exynos_dp_hotplug(struct work_struct *work) |
| 842 | { |
| 843 | struct exynos_dp_device *dp; |
| 844 | int ret; |
| 845 | |
| 846 | dp = container_of(work, struct exynos_dp_device, hotplug_work); |
| 847 | |
| 848 | ret = exynos_dp_detect_hpd(dp); |
| 849 | if (ret) { |
| 850 | dev_err(dp->dev, "unable to detect hpd\n"); |
| 851 | return; |
| 852 | } |
| 853 | |
| 854 | ret = exynos_dp_handle_edid(dp); |
| 855 | if (ret) { |
| 856 | dev_err(dp->dev, "unable to handle edid\n"); |
| 857 | return; |
| 858 | } |
| 859 | |
| 860 | ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count, |
| 861 | dp->video_info->link_rate); |
| 862 | if (ret) { |
| 863 | dev_err(dp->dev, "unable to do link train\n"); |
| 864 | return; |
| 865 | } |
| 866 | |
| 867 | exynos_dp_enable_scramble(dp, 1); |
| 868 | exynos_dp_enable_rx_to_enhanced_mode(dp, 1); |
| 869 | exynos_dp_enable_enhanced_mode(dp, 1); |
| 870 | |
| 871 | exynos_dp_set_lane_count(dp, dp->video_info->lane_count); |
| 872 | exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate); |
| 873 | |
| 874 | exynos_dp_init_video(dp); |
| 875 | ret = exynos_dp_config_video(dp, dp->video_info); |
| 876 | if (ret) |
| 877 | dev_err(dp->dev, "unable to config video\n"); |
| 878 | } |
| 879 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 880 | #ifdef CONFIG_OF |
| 881 | static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev) |
| 882 | { |
| 883 | struct device_node *dp_node = dev->of_node; |
| 884 | struct exynos_dp_platdata *pd; |
| 885 | struct video_info *dp_video_config; |
| 886 | |
| 887 | pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); |
| 888 | if (!pd) { |
| 889 | dev_err(dev, "memory allocation for pdata failed\n"); |
| 890 | return ERR_PTR(-ENOMEM); |
| 891 | } |
| 892 | dp_video_config = devm_kzalloc(dev, |
| 893 | sizeof(*dp_video_config), GFP_KERNEL); |
| 894 | |
| 895 | if (!dp_video_config) { |
| 896 | dev_err(dev, "memory allocation for video config failed\n"); |
| 897 | return ERR_PTR(-ENOMEM); |
| 898 | } |
| 899 | pd->video_info = dp_video_config; |
| 900 | |
| 901 | dp_video_config->h_sync_polarity = |
| 902 | of_property_read_bool(dp_node, "hsync-active-high"); |
| 903 | |
| 904 | dp_video_config->v_sync_polarity = |
| 905 | of_property_read_bool(dp_node, "vsync-active-high"); |
| 906 | |
| 907 | dp_video_config->interlaced = |
| 908 | of_property_read_bool(dp_node, "interlaced"); |
| 909 | |
| 910 | if (of_property_read_u32(dp_node, "samsung,color-space", |
| 911 | &dp_video_config->color_space)) { |
| 912 | dev_err(dev, "failed to get color-space\n"); |
| 913 | return ERR_PTR(-EINVAL); |
| 914 | } |
| 915 | |
| 916 | if (of_property_read_u32(dp_node, "samsung,dynamic-range", |
| 917 | &dp_video_config->dynamic_range)) { |
| 918 | dev_err(dev, "failed to get dynamic-range\n"); |
| 919 | return ERR_PTR(-EINVAL); |
| 920 | } |
| 921 | |
| 922 | if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff", |
| 923 | &dp_video_config->ycbcr_coeff)) { |
| 924 | dev_err(dev, "failed to get ycbcr-coeff\n"); |
| 925 | return ERR_PTR(-EINVAL); |
| 926 | } |
| 927 | |
| 928 | if (of_property_read_u32(dp_node, "samsung,color-depth", |
| 929 | &dp_video_config->color_depth)) { |
| 930 | dev_err(dev, "failed to get color-depth\n"); |
| 931 | return ERR_PTR(-EINVAL); |
| 932 | } |
| 933 | |
| 934 | if (of_property_read_u32(dp_node, "samsung,link-rate", |
| 935 | &dp_video_config->link_rate)) { |
| 936 | dev_err(dev, "failed to get link-rate\n"); |
| 937 | return ERR_PTR(-EINVAL); |
| 938 | } |
| 939 | |
| 940 | if (of_property_read_u32(dp_node, "samsung,lane-count", |
| 941 | &dp_video_config->lane_count)) { |
| 942 | dev_err(dev, "failed to get lane-count\n"); |
| 943 | return ERR_PTR(-EINVAL); |
| 944 | } |
| 945 | |
| 946 | return pd; |
| 947 | } |
| 948 | |
| 949 | static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp) |
| 950 | { |
| 951 | struct device_node *dp_phy_node; |
| 952 | u32 phy_base; |
| 953 | |
| 954 | dp_phy_node = of_find_node_by_name(dp->dev->of_node, "dptx-phy"); |
| 955 | if (!dp_phy_node) { |
| 956 | dev_err(dp->dev, "could not find dptx-phy node\n"); |
| 957 | return -ENODEV; |
| 958 | } |
| 959 | |
| 960 | if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) { |
| 961 | dev_err(dp->dev, "faild to get reg for dptx-phy\n"); |
| 962 | return -EINVAL; |
| 963 | } |
| 964 | |
| 965 | if (of_property_read_u32(dp_phy_node, "samsung,enable-mask", |
| 966 | &dp->enable_mask)) { |
| 967 | dev_err(dp->dev, "faild to get enable-mask for dptx-phy\n"); |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | |
| 971 | dp->phy_addr = ioremap(phy_base, SZ_4); |
| 972 | if (!dp->phy_addr) { |
| 973 | dev_err(dp->dev, "failed to ioremap dp-phy\n"); |
| 974 | return -ENOMEM; |
| 975 | } |
| 976 | |
| 977 | return 0; |
| 978 | } |
| 979 | |
| 980 | static void exynos_dp_phy_init(struct exynos_dp_device *dp) |
| 981 | { |
| 982 | u32 reg; |
| 983 | |
| 984 | reg = __raw_readl(dp->phy_addr); |
| 985 | reg |= dp->enable_mask; |
| 986 | __raw_writel(reg, dp->phy_addr); |
| 987 | } |
| 988 | |
| 989 | static void exynos_dp_phy_exit(struct exynos_dp_device *dp) |
| 990 | { |
| 991 | u32 reg; |
| 992 | |
| 993 | reg = __raw_readl(dp->phy_addr); |
| 994 | reg &= ~(dp->enable_mask); |
| 995 | __raw_writel(reg, dp->phy_addr); |
| 996 | } |
| 997 | #else |
| 998 | static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev) |
| 999 | { |
| 1000 | return NULL; |
| 1001 | } |
| 1002 | |
| 1003 | static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp) |
| 1004 | { |
| 1005 | return -EINVAL; |
| 1006 | } |
| 1007 | |
| 1008 | static void exynos_dp_phy_init(struct exynos_dp_device *dp) |
| 1009 | { |
| 1010 | return; |
| 1011 | } |
| 1012 | |
| 1013 | static void exynos_dp_phy_exit(struct exynos_dp_device *dp) |
| 1014 | { |
| 1015 | return; |
| 1016 | } |
| 1017 | #endif /* CONFIG_OF */ |
| 1018 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1019 | static int __devinit exynos_dp_probe(struct platform_device *pdev) |
| 1020 | { |
| 1021 | struct resource *res; |
| 1022 | struct exynos_dp_device *dp; |
| 1023 | struct exynos_dp_platdata *pdata; |
| 1024 | |
| 1025 | int ret = 0; |
| 1026 | |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1027 | dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device), |
| 1028 | GFP_KERNEL); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1029 | if (!dp) { |
| 1030 | dev_err(&pdev->dev, "no memory for device data\n"); |
| 1031 | return -ENOMEM; |
| 1032 | } |
| 1033 | |
| 1034 | dp->dev = &pdev->dev; |
| 1035 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1036 | if (pdev->dev.of_node) { |
| 1037 | pdata = exynos_dp_dt_parse_pdata(&pdev->dev); |
| 1038 | if (IS_ERR(pdata)) |
| 1039 | return PTR_ERR(pdata); |
| 1040 | |
| 1041 | ret = exynos_dp_dt_parse_phydata(dp); |
| 1042 | if (ret) |
| 1043 | return ret; |
| 1044 | } else { |
| 1045 | pdata = pdev->dev.platform_data; |
| 1046 | if (!pdata) { |
| 1047 | dev_err(&pdev->dev, "no platform data\n"); |
| 1048 | return -EINVAL; |
| 1049 | } |
| 1050 | } |
| 1051 | |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1052 | dp->clock = devm_clk_get(&pdev->dev, "dp"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1053 | if (IS_ERR(dp->clock)) { |
| 1054 | dev_err(&pdev->dev, "failed to get clock\n"); |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1055 | return PTR_ERR(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1056 | } |
| 1057 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1058 | clk_prepare_enable(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1059 | |
| 1060 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1061 | |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1062 | dp->reg_base = devm_request_and_ioremap(&pdev->dev, res); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1063 | if (!dp->reg_base) { |
| 1064 | dev_err(&pdev->dev, "failed to ioremap\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1065 | return -ENOMEM; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | dp->irq = platform_get_irq(pdev, 0); |
Sean Paul | 1cefc1d | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 1069 | if (dp->irq == -ENXIO) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1070 | dev_err(&pdev->dev, "failed to get irq\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1071 | return -ENODEV; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1072 | } |
| 1073 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 1074 | INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug); |
| 1075 | |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1076 | ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0, |
| 1077 | "exynos-dp", dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1078 | if (ret) { |
| 1079 | dev_err(&pdev->dev, "failed to request irq\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1080 | return ret; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1081 | } |
| 1082 | |
| 1083 | dp->video_info = pdata->video_info; |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1084 | |
| 1085 | if (pdev->dev.of_node) { |
| 1086 | if (dp->phy_addr) |
| 1087 | exynos_dp_phy_init(dp); |
| 1088 | } else { |
| 1089 | if (pdata->phy_init) |
| 1090 | pdata->phy_init(); |
| 1091 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1092 | |
| 1093 | exynos_dp_init_dp(dp); |
| 1094 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1095 | platform_set_drvdata(pdev, dp); |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 1096 | schedule_work(&dp->hotplug_work); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1097 | |
| 1098 | return 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | static int __devexit exynos_dp_remove(struct platform_device *pdev) |
| 1102 | { |
| 1103 | struct exynos_dp_platdata *pdata = pdev->dev.platform_data; |
| 1104 | struct exynos_dp_device *dp = platform_get_drvdata(pdev); |
| 1105 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 1106 | if (work_pending(&dp->hotplug_work)) |
| 1107 | flush_work(&dp->hotplug_work); |
| 1108 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1109 | if (pdev->dev.of_node) { |
| 1110 | if (dp->phy_addr) |
| 1111 | exynos_dp_phy_exit(dp); |
| 1112 | } else { |
| 1113 | if (pdata->phy_exit) |
| 1114 | pdata->phy_exit(); |
| 1115 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1116 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1117 | clk_disable_unprepare(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1118 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 1119 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1120 | return 0; |
| 1121 | } |
| 1122 | |
| 1123 | #ifdef CONFIG_PM_SLEEP |
| 1124 | static int exynos_dp_suspend(struct device *dev) |
| 1125 | { |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1126 | struct exynos_dp_platdata *pdata = dev->platform_data; |
| 1127 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1128 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 1129 | if (work_pending(&dp->hotplug_work)) |
| 1130 | flush_work(&dp->hotplug_work); |
| 1131 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1132 | if (dev->of_node) { |
| 1133 | if (dp->phy_addr) |
| 1134 | exynos_dp_phy_exit(dp); |
| 1135 | } else { |
| 1136 | if (pdata->phy_exit) |
| 1137 | pdata->phy_exit(); |
| 1138 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1139 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1140 | clk_disable_unprepare(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1141 | |
| 1142 | return 0; |
| 1143 | } |
| 1144 | |
| 1145 | static int exynos_dp_resume(struct device *dev) |
| 1146 | { |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1147 | struct exynos_dp_platdata *pdata = dev->platform_data; |
| 1148 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1149 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1150 | if (dev->of_node) { |
| 1151 | if (dp->phy_addr) |
| 1152 | exynos_dp_phy_init(dp); |
| 1153 | } else { |
| 1154 | if (pdata->phy_init) |
| 1155 | pdata->phy_init(); |
| 1156 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1157 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1158 | clk_prepare_enable(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1159 | |
| 1160 | exynos_dp_init_dp(dp); |
| 1161 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame^] | 1162 | schedule_work(&dp->hotplug_work); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1163 | |
| 1164 | return 0; |
| 1165 | } |
| 1166 | #endif |
| 1167 | |
| 1168 | static const struct dev_pm_ops exynos_dp_pm_ops = { |
| 1169 | SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume) |
| 1170 | }; |
| 1171 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1172 | static const struct of_device_id exynos_dp_match[] = { |
| 1173 | { .compatible = "samsung,exynos5-dp" }, |
| 1174 | {}, |
| 1175 | }; |
| 1176 | MODULE_DEVICE_TABLE(of, exynos_dp_match); |
| 1177 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1178 | static struct platform_driver exynos_dp_driver = { |
| 1179 | .probe = exynos_dp_probe, |
| 1180 | .remove = __devexit_p(exynos_dp_remove), |
| 1181 | .driver = { |
| 1182 | .name = "exynos-dp", |
| 1183 | .owner = THIS_MODULE, |
| 1184 | .pm = &exynos_dp_pm_ops, |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1185 | .of_match_table = of_match_ptr(exynos_dp_match), |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1186 | }, |
| 1187 | }; |
| 1188 | |
| 1189 | module_platform_driver(exynos_dp_driver); |
| 1190 | |
| 1191 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
| 1192 | MODULE_DESCRIPTION("Samsung SoC DP Driver"); |
| 1193 | MODULE_LICENSE("GPL"); |