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gerrit-public.fairphone.software / kernel / msm-4.9 / 7a8e5149efd4e20e329beec47e3bb57ce2c5938a / . / arch / arm / boot / dts / imx28.dtsi
blob: a89da5ac71f70de48d0e25119899c41c74e53532 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]23 saif0 = &saif0;
24 saif1 = &saif1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]25 };
26
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]27 cpus {
28 cpu@0 {
29 compatible = "arm,arm926ejs";
30 };
31 };
32
33 apb@80000000 {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 reg = <0x80000000 0x80000>;
38 ranges;
39
40 apbh@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x3c900>;
45 ranges;
46
47 icoll: interrupt-controller@80000000 {
48 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0x80000000 0x2000>;
52 };
53
54 hsadc@80002000 {
55 reg = <0x80002000 2000>;
56 interrupts = <13 87>;
57 status = "disabled";
58 };
59
60 dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]61 compatible = "fsl,imx28-dma-apbh";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]62 reg = <0x80004000 2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]63 };
64
65 perfmon@80006000 {
66 reg = <0x80006000 800>;
67 interrupts = <27>;
68 status = "disabled";
69 };
70
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame^]71 gpmi-nand@8000c000 {
72 compatible = "fsl,imx28-gpmi-nand";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 reg = <0x8000c000 2000>, <0x8000a000 2000>;
76 reg-names = "gpmi-nand", "bch";
77 interrupts = <88>, <41>;
78 interrupt-names = "gpmi-dma", "bch";
79 fsl,gpmi-dma-channel = <4>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]80 status = "disabled";
81 };
82
83 ssp0: ssp@80010000 {
84 reg = <0x80010000 2000>;
85 interrupts = <96 82>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]86 fsl,ssp-dma-channel = <0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]87 status = "disabled";
88 };
89
90 ssp1: ssp@80012000 {
91 reg = <0x80012000 2000>;
92 interrupts = <97 83>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]93 fsl,ssp-dma-channel = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]94 status = "disabled";
95 };
96
97 ssp2: ssp@80014000 {
98 reg = <0x80014000 2000>;
99 interrupts = <98 84>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]100 fsl,ssp-dma-channel = <2>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]101 status = "disabled";
102 };
103
104 ssp3: ssp@80016000 {
105 reg = <0x80016000 2000>;
106 interrupts = <99 85>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]107 fsl,ssp-dma-channel = <3>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]108 status = "disabled";
109 };
110
111 pinctrl@80018000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]114 compatible = "fsl,imx28-pinctrl", "simple-bus";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]115 reg = <0x80018000 2000>;
116
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]117 gpio0: gpio@0 {
118 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
119 interrupts = <127>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio1: gpio@1 {
127 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
128 interrupts = <126>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 gpio2: gpio@2 {
136 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
137 interrupts = <125>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 gpio3: gpio@3 {
145 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
146 interrupts = <124>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 };
152
153 gpio4: gpio@4 {
154 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
155 interrupts = <123>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 };
161
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]162 duart_pins_a: duart@0 {
163 reg = <0>;
164 fsl,pinmux-ids = <0x3102 0x3112>;
165 fsl,drive-strength = <0>;
166 fsl,voltage = <1>;
167 fsl,pull-up = <0>;
168 };
169
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame^]170 gpmi_pins_a: gpmi-nand@0 {
171 reg = <0>;
172 fsl,pinmux-ids = <0x0000 0x0010 0x0020
173 0x0030 0x0040 0x0050 0x0060
174 0x0070 0x0100 0x0110 0x0140
175 0x0150 0x0180 0x0190 0x01a0
176 0x01b0 0x01c0>;
177 fsl,drive-strength = <0>;
178 fsl,voltage = <1>;
179 fsl,pull-up = <0>;
180 };
181
182 gpmi_status_cfg: gpmi-status-cfg {
183 fsl,pinmux-ids = <0x0180 0x0190 0x01c0>;
184 fsl,drive-strength = <2>;
185 };
186
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]187 mac0_pins_a: mac0@0 {
188 reg = <0>;
189 fsl,pinmux-ids = <0x4000 0x4010 0x4020
190 0x4030 0x4040 0x4060 0x4070
191 0x4080 0x4100>;
192 fsl,drive-strength = <1>;
193 fsl,voltage = <1>;
194 fsl,pull-up = <1>;
195 };
196
197 mac1_pins_a: mac1@0 {
198 reg = <0>;
199 fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
200 0x40e1 0x40b1 0x40c1>;
201 fsl,drive-strength = <1>;
202 fsl,voltage = <1>;
203 fsl,pull-up = <1>;
204 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]205
206 mmc0_8bit_pins_a: mmc0-8bit@0 {
207 reg = <0>;
208 fsl,pinmux-ids = <0x2000 0x2010 0x2020
209 0x2030 0x2040 0x2050 0x2060
210 0x2070 0x2080 0x2090 0x20a0>;
211 fsl,drive-strength = <1>;
212 fsl,voltage = <1>;
213 fsl,pull-up = <1>;
214 };
215
216 mmc0_cd_cfg: mmc0-cd-cfg {
217 fsl,pinmux-ids = <0x2090>;
218 fsl,pull-up = <0>;
219 };
220
221 mmc0_sck_cfg: mmc0-sck-cfg {
222 fsl,pinmux-ids = <0x20a0>;
223 fsl,drive-strength = <2>;
224 fsl,pull-up = <0>;
225 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]226
227 i2c0_pins_a: i2c0@0 {
228 reg = <0>;
229 fsl,pinmux-ids = <0x3180 0x3190>;
230 fsl,drive-strength = <1>;
231 fsl,voltage = <1>;
232 fsl,pull-up = <1>;
233 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]234
235 saif0_pins_a: saif0@0 {
236 reg = <0>;
237 fsl,pinmux-ids =
238 <0x3140 0x3150 0x3160 0x3170>;
239 fsl,drive-strength = <2>;
240 fsl,voltage = <1>;
241 fsl,pull-up = <1>;
242 };
243
244 saif1_pins_a: saif1@0 {
245 reg = <0>;
246 fsl,pinmux-ids = <0x31a0>;
247 fsl,drive-strength = <2>;
248 fsl,voltage = <1>;
249 fsl,pull-up = <1>;
250 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]251 };
252
253 digctl@8001c000 {
254 reg = <0x8001c000 2000>;
255 interrupts = <89>;
256 status = "disabled";
257 };
258
259 etm@80022000 {
260 reg = <0x80022000 2000>;
261 status = "disabled";
262 };
263
264 dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]265 compatible = "fsl,imx28-dma-apbx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]266 reg = <0x80024000 2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]267 };
268
269 dcp@80028000 {
270 reg = <0x80028000 2000>;
271 interrupts = <52 53 54>;
272 status = "disabled";
273 };
274
275 pxp@8002a000 {
276 reg = <0x8002a000 2000>;
277 interrupts = <39>;
278 status = "disabled";
279 };
280
281 ocotp@8002c000 {
282 reg = <0x8002c000 2000>;
283 status = "disabled";
284 };
285
286 axi-ahb@8002e000 {
287 reg = <0x8002e000 2000>;
288 status = "disabled";
289 };
290
291 lcdif@80030000 {
292 reg = <0x80030000 2000>;
293 interrupts = <38 86>;
294 status = "disabled";
295 };
296
297 can0: can@80032000 {
298 reg = <0x80032000 2000>;
299 interrupts = <8>;
300 status = "disabled";
301 };
302
303 can1: can@80034000 {
304 reg = <0x80034000 2000>;
305 interrupts = <9>;
306 status = "disabled";
307 };
308
309 simdbg@8003c000 {
310 reg = <0x8003c000 200>;
311 status = "disabled";
312 };
313
314 simgpmisel@8003c200 {
315 reg = <0x8003c200 100>;
316 status = "disabled";
317 };
318
319 simsspsel@8003c300 {
320 reg = <0x8003c300 100>;
321 status = "disabled";
322 };
323
324 simmemsel@8003c400 {
325 reg = <0x8003c400 100>;
326 status = "disabled";
327 };
328
329 gpiomon@8003c500 {
330 reg = <0x8003c500 100>;
331 status = "disabled";
332 };
333
334 simenet@8003c700 {
335 reg = <0x8003c700 100>;
336 status = "disabled";
337 };
338
339 armjtag@8003c800 {
340 reg = <0x8003c800 100>;
341 status = "disabled";
342 };
343 };
344
345 apbx@80040000 {
346 compatible = "simple-bus";
347 #address-cells = <1>;
348 #size-cells = <1>;
349 reg = <0x80040000 0x40000>;
350 ranges;
351
352 clkctl@80040000 {
353 reg = <0x80040000 2000>;
354 status = "disabled";
355 };
356
357 saif0: saif@80042000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]358 compatible = "fsl,imx28-saif";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]359 reg = <0x80042000 2000>;
360 interrupts = <59 80>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]361 fsl,saif-dma-channel = <4>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]362 status = "disabled";
363 };
364
365 power@80044000 {
366 reg = <0x80044000 2000>;
367 status = "disabled";
368 };
369
370 saif1: saif@80046000 {
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]371 compatible = "fsl,imx28-saif";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]372 reg = <0x80046000 2000>;
373 interrupts = <58 81>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]374 fsl,saif-dma-channel = <5>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]375 status = "disabled";
376 };
377
378 lradc@80050000 {
379 reg = <0x80050000 2000>;
380 status = "disabled";
381 };
382
383 spdif@80054000 {
384 reg = <0x80054000 2000>;
385 interrupts = <45 66>;
386 status = "disabled";
387 };
388
389 rtc@80056000 {
390 reg = <0x80056000 2000>;
391 interrupts = <28 29>;
392 status = "disabled";
393 };
394
395 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "fsl,imx28-i2c";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]399 reg = <0x80058000 2000>;
400 interrupts = <111 68>;
401 status = "disabled";
402 };
403
404 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "fsl,imx28-i2c";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]408 reg = <0x8005a000 2000>;
409 interrupts = <110 69>;
410 status = "disabled";
411 };
412
413 pwm@80064000 {
414 reg = <0x80064000 2000>;
415 status = "disabled";
416 };
417
418 timrot@80068000 {
419 reg = <0x80068000 2000>;
420 status = "disabled";
421 };
422
423 auart0: serial@8006a000 {
424 reg = <0x8006a000 0x2000>;
425 interrupts = <112 70 71>;
426 status = "disabled";
427 };
428
429 auart1: serial@8006c000 {
430 reg = <0x8006c000 0x2000>;
431 interrupts = <113 72 73>;
432 status = "disabled";
433 };
434
435 auart2: serial@8006e000 {
436 reg = <0x8006e000 0x2000>;
437 interrupts = <114 74 75>;
438 status = "disabled";
439 };
440
441 auart3: serial@80070000 {
442 reg = <0x80070000 0x2000>;
443 interrupts = <115 76 77>;
444 status = "disabled";
445 };
446
447 auart4: serial@80072000 {
448 reg = <0x80072000 0x2000>;
449 interrupts = <116 78 79>;
450 status = "disabled";
451 };
452
453 duart: serial@80074000 {
454 compatible = "arm,pl011", "arm,primecell";
455 reg = <0x80074000 0x1000>;
456 interrupts = <47>;
457 status = "disabled";
458 };
459
460 usbphy0: usbphy@8007c000 {
461 reg = <0x8007c000 0x2000>;
462 status = "disabled";
463 };
464
465 usbphy1: usbphy@8007e000 {
466 reg = <0x8007e000 0x2000>;
467 status = "disabled";
468 };
469 };
470 };
471
472 ahb@80080000 {
473 compatible = "simple-bus";
474 #address-cells = <1>;
475 #size-cells = <1>;
476 reg = <0x80080000 0x80000>;
477 ranges;
478
479 usbctrl0: usbctrl@80080000 {
480 reg = <0x80080000 0x10000>;
481 status = "disabled";
482 };
483
484 usbctrl1: usbctrl@80090000 {
485 reg = <0x80090000 0x10000>;
486 status = "disabled";
487 };
488
489 dflpt@800c0000 {
490 reg = <0x800c0000 0x10000>;
491 status = "disabled";
492 };
493
494 mac0: ethernet@800f0000 {
495 compatible = "fsl,imx28-fec";
496 reg = <0x800f0000 0x4000>;
497 interrupts = <101>;
498 status = "disabled";
499 };
500
501 mac1: ethernet@800f4000 {
502 compatible = "fsl,imx28-fec";
503 reg = <0x800f4000 0x4000>;
504 interrupts = <102>;
505 status = "disabled";
506 };
507
508 switch@800f8000 {
509 reg = <0x800f8000 0x8000>;
510 status = "disabled";
511 };
512
513 };
514};