blob: 8fbf40e0713cfc9a4dd7ec64bc66010a42afc644 [file] [log] [blame]
Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000026#include <linux/dma-direction.h>
27
28struct scatterlist;
Chris Leechc13c8262006-05-23 17:18:44 -070029
30/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070031 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070032 *
33 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
34 */
35typedef s32 dma_cookie_t;
Steven J. Magnani76bd0612010-02-28 22:18:16 -070036#define DMA_MIN_COOKIE 1
37#define DMA_MAX_COOKIE INT_MAX
Chris Leechc13c8262006-05-23 17:18:44 -070038
39#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
40
41/**
42 * enum dma_status - DMA transaction status
43 * @DMA_SUCCESS: transaction completed successfully
44 * @DMA_IN_PROGRESS: transaction not yet processed
Linus Walleij07934482010-03-26 16:50:49 -070045 * @DMA_PAUSED: transaction is paused
Chris Leechc13c8262006-05-23 17:18:44 -070046 * @DMA_ERROR: transaction failed
47 */
48enum dma_status {
49 DMA_SUCCESS,
50 DMA_IN_PROGRESS,
Linus Walleij07934482010-03-26 16:50:49 -070051 DMA_PAUSED,
Chris Leechc13c8262006-05-23 17:18:44 -070052 DMA_ERROR,
53};
54
55/**
Dan Williams7405f742007-01-02 11:10:43 -070056 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070057 *
58 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
59 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070060 */
61enum dma_transaction_type {
62 DMA_MEMCPY,
63 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070064 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070065 DMA_XOR_VAL,
66 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070067 DMA_MEMSET,
Dan Williams7405f742007-01-02 11:10:43 -070068 DMA_INTERRUPT,
Ira Snydera86ee032010-09-30 11:46:44 +000069 DMA_SG,
Dan Williams59b5ec22009-01-06 11:38:15 -070070 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070071 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070072 DMA_SLAVE,
Sascha Hauer782bc952010-09-30 13:56:32 +000073 DMA_CYCLIC,
Dan Williams7405f742007-01-02 11:10:43 -070074};
75
76/* last transaction type for creation of the capabilities mask */
Sascha Hauer782bc952010-09-30 13:56:32 +000077#define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070078
Dan Williams7405f742007-01-02 11:10:43 -070079
80/**
Dan Williams636bdea2008-04-17 20:17:26 -070081 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070082 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -070083 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -070084 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +010085 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -070086 * acknowledges receipt, i.e. has has a chance to establish any dependency
87 * chains
Dan Williamse1d181e2008-07-04 00:13:40 -070088 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
89 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Maciej Sosnowski4f005db2009-04-23 12:31:51 +020090 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
91 * (if not set, do the source dma-unmapping as page)
92 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
93 * (if not set, do the destination dma-unmapping as page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -070094 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
95 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
96 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
97 * sources that were the result of a previous operation, in the case of a PQ
98 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -070099 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
100 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -0700101 */
Dan Williams636bdea2008-04-17 20:17:26 -0700102enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -0700103 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700104 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700105 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
106 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200107 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
108 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
Dan Williamsf9dd2132009-09-08 17:42:29 -0700109 DMA_PREP_PQ_DISABLE_P = (1 << 6),
110 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
111 DMA_PREP_CONTINUE = (1 << 8),
Dan Williams0403e382009-09-08 17:42:50 -0700112 DMA_PREP_FENCE = (1 << 9),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700113};
114
115/**
Linus Walleijc3635c72010-03-26 16:44:01 -0700116 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
117 * on a running channel.
118 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
119 * @DMA_PAUSE: pause ongoing transfers
120 * @DMA_RESUME: resume paused transfer
Linus Walleijc156d0a2010-08-04 13:37:33 +0200121 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
122 * that need to runtime reconfigure the slave channels (as opposed to passing
123 * configuration data in statically from the platform). An additional
124 * argument of struct dma_slave_config must be passed in with this
125 * command.
Ira Snyder968f19a2010-09-30 11:46:46 +0000126 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
127 * into external start mode.
Linus Walleijc3635c72010-03-26 16:44:01 -0700128 */
129enum dma_ctrl_cmd {
130 DMA_TERMINATE_ALL,
131 DMA_PAUSE,
132 DMA_RESUME,
Linus Walleijc156d0a2010-08-04 13:37:33 +0200133 DMA_SLAVE_CONFIG,
Ira Snyder968f19a2010-09-30 11:46:46 +0000134 FSLDMA_EXTERNAL_START,
Linus Walleijc3635c72010-03-26 16:44:01 -0700135};
136
137/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700138 * enum sum_check_bits - bit position of pq_check_flags
139 */
140enum sum_check_bits {
141 SUM_CHECK_P = 0,
142 SUM_CHECK_Q = 1,
143};
144
145/**
146 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
147 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
148 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
149 */
150enum sum_check_flags {
151 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
152 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
153};
154
155
156/**
Dan Williams7405f742007-01-02 11:10:43 -0700157 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
158 * See linux/cpumask.h
159 */
160typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
161
162/**
Chris Leechc13c8262006-05-23 17:18:44 -0700163 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700164 * @memcpy_count: transaction counter
165 * @bytes_transferred: byte counter
166 */
167
168struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700169 /* stats */
170 unsigned long memcpy_count;
171 unsigned long bytes_transferred;
172};
173
174/**
175 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700176 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700177 * @cookie: last cookie value returned to client
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700178 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700179 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700180 * @device_node: used to add this to the device chan list
181 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700182 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700183 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800184 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700185 */
186struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700187 struct dma_device *device;
188 dma_cookie_t cookie;
189
190 /* sysfs */
191 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700192 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700193
Chris Leechc13c8262006-05-23 17:18:44 -0700194 struct list_head device_node;
Tejun Heoa29d8b82010-02-02 14:39:15 +0900195 struct dma_chan_percpu __percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700196 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700197 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800198 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700199};
200
Dan Williams41d5e592009-01-06 11:38:21 -0700201/**
202 * struct dma_chan_dev - relate sysfs device node to backing channel device
203 * @chan - driver channel device
204 * @device - sysfs device
Dan Williams864498a2009-01-06 11:38:21 -0700205 * @dev_id - parent dma_device dev_id
206 * @idr_ref - reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700207 */
208struct dma_chan_dev {
209 struct dma_chan *chan;
210 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700211 int dev_id;
212 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700213};
214
Linus Walleijc156d0a2010-08-04 13:37:33 +0200215/**
216 * enum dma_slave_buswidth - defines bus with of the DMA slave
217 * device, source or target buses
218 */
219enum dma_slave_buswidth {
220 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
221 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
222 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
223 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
224 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
225};
226
227/**
228 * struct dma_slave_config - dma slave channel runtime config
229 * @direction: whether the data shall go in or out on this slave
230 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
231 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
232 * need to differentiate source and target addresses.
233 * @src_addr: this is the physical address where DMA slave data
234 * should be read (RX), if the source is memory this argument is
235 * ignored.
236 * @dst_addr: this is the physical address where DMA slave data
237 * should be written (TX), if the source is memory this argument
238 * is ignored.
239 * @src_addr_width: this is the width in bytes of the source (RX)
240 * register where DMA data shall be read. If the source
241 * is memory this may be ignored depending on architecture.
242 * Legal values: 1, 2, 4, 8.
243 * @dst_addr_width: same as src_addr_width but for destination
244 * target (TX) mutatis mutandis.
245 * @src_maxburst: the maximum number of words (note: words, as in
246 * units of the src_addr_width member, not bytes) that can be sent
247 * in one burst to the device. Typically something like half the
248 * FIFO depth on I/O peripherals so you don't overflow it. This
249 * may or may not be applicable on memory sources.
250 * @dst_maxburst: same as src_maxburst but for destination target
251 * mutatis mutandis.
252 *
253 * This struct is passed in as configuration data to a DMA engine
254 * in order to set up a certain channel for DMA transport at runtime.
255 * The DMA device/engine has to provide support for an additional
256 * command in the channel config interface, DMA_SLAVE_CONFIG
257 * and this struct will then be passed in as an argument to the
258 * DMA engine device_control() function.
259 *
260 * The rationale for adding configuration information to this struct
261 * is as follows: if it is likely that most DMA slave controllers in
262 * the world will support the configuration option, then make it
263 * generic. If not: if it is fixed so that it be sent in static from
264 * the platform data, then prefer to do that. Else, if it is neither
265 * fixed at runtime, nor generic enough (such as bus mastership on
266 * some CPU family and whatnot) then create a custom slave config
267 * struct and pass that, then make this config a member of that
268 * struct, if applicable.
269 */
270struct dma_slave_config {
271 enum dma_data_direction direction;
272 dma_addr_t src_addr;
273 dma_addr_t dst_addr;
274 enum dma_slave_buswidth src_addr_width;
275 enum dma_slave_buswidth dst_addr_width;
276 u32 src_maxburst;
277 u32 dst_maxburst;
278};
279
Dan Williams41d5e592009-01-06 11:38:21 -0700280static inline const char *dma_chan_name(struct dma_chan *chan)
281{
282 return dev_name(&chan->dev->device);
283}
Dan Williamsd379b012007-07-09 11:56:42 -0700284
Chris Leechc13c8262006-05-23 17:18:44 -0700285void dma_chan_cleanup(struct kref *kref);
286
Chris Leechc13c8262006-05-23 17:18:44 -0700287/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700288 * typedef dma_filter_fn - callback filter for dma_request_channel
289 * @chan: channel to be reviewed
290 * @filter_param: opaque parameter passed through dma_request_channel
291 *
292 * When this optional parameter is specified in a call to dma_request_channel a
293 * suitable channel is passed to this routine for further dispositioning before
294 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700295 * satisfies the given capability mask. It returns 'true' to indicate that the
296 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700297 */
Dan Williams7dd60252009-01-06 11:38:19 -0700298typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700299
Dan Williams7405f742007-01-02 11:10:43 -0700300typedef void (*dma_async_tx_callback)(void *dma_async_param);
301/**
302 * struct dma_async_tx_descriptor - async transaction descriptor
303 * ---dma generic offload fields---
304 * @cookie: tracking cookie for this transaction, set to -EBUSY if
305 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700306 * @flags: flags to augment operation preparation, control completion, and
307 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700308 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700309 * @chan: target channel for this operation
310 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700311 * @callback: routine to call after this operation is complete
312 * @callback_param: general parameter to pass to the callback routine
313 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700314 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700315 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700316 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700317 */
318struct dma_async_tx_descriptor {
319 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700320 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700321 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700322 struct dma_chan *chan;
323 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700324 dma_async_tx_callback callback;
325 void *callback_param;
Dan Williams5fc6d892010-10-07 16:44:50 -0700326#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams19242d72008-04-17 20:17:25 -0700327 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700328 struct dma_async_tx_descriptor *parent;
329 spinlock_t lock;
Dan Williamscaa20d972010-05-17 16:24:16 -0700330#endif
Dan Williams7405f742007-01-02 11:10:43 -0700331};
332
Dan Williams5fc6d892010-10-07 16:44:50 -0700333#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williamscaa20d972010-05-17 16:24:16 -0700334static inline void txd_lock(struct dma_async_tx_descriptor *txd)
335{
336}
337static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
338{
339}
340static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
341{
342 BUG();
343}
344static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
345{
346}
347static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
348{
349}
350static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
351{
352 return NULL;
353}
354static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
355{
356 return NULL;
357}
358
359#else
360static inline void txd_lock(struct dma_async_tx_descriptor *txd)
361{
362 spin_lock_bh(&txd->lock);
363}
364static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
365{
366 spin_unlock_bh(&txd->lock);
367}
368static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
369{
370 txd->next = next;
371 next->parent = txd;
372}
373static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
374{
375 txd->parent = NULL;
376}
377static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
378{
379 txd->next = NULL;
380}
381static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
382{
383 return txd->parent;
384}
385static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
386{
387 return txd->next;
388}
389#endif
390
Chris Leechc13c8262006-05-23 17:18:44 -0700391/**
Linus Walleij07934482010-03-26 16:50:49 -0700392 * struct dma_tx_state - filled in to report the status of
393 * a transfer.
394 * @last: last completed DMA cookie
395 * @used: last issued DMA cookie (i.e. the one in progress)
396 * @residue: the remaining number of bytes left to transmit
397 * on the selected transfer for states DMA_IN_PROGRESS and
398 * DMA_PAUSED if this is implemented in the driver, else 0
399 */
400struct dma_tx_state {
401 dma_cookie_t last;
402 dma_cookie_t used;
403 u32 residue;
404};
405
406/**
Chris Leechc13c8262006-05-23 17:18:44 -0700407 * struct dma_device - info on the entity supplying DMA services
408 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900409 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700410 * @channels: the list of struct dma_chan
411 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700412 * @cap_mask: one or more dma_capability flags
413 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700414 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700415 * @copy_align: alignment shift for memcpy operations
416 * @xor_align: alignment shift for xor operations
417 * @pq_align: alignment shift for pq operations
418 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700419 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700420 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700421 * @device_alloc_chan_resources: allocate resources and return the
422 * number of allocated descriptors
423 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700424 * @device_prep_dma_memcpy: prepares a memcpy operation
425 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700426 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700427 * @device_prep_dma_pq: prepares a pq operation
428 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700429 * @device_prep_dma_memset: prepares a memset operation
430 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700431 * @device_prep_slave_sg: prepares a slave dma operation
Sascha Hauer782bc952010-09-30 13:56:32 +0000432 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
433 * The function takes a buffer of size buf_len. The callback function will
434 * be called after period_len bytes have been transferred.
Linus Walleijc3635c72010-03-26 16:44:01 -0700435 * @device_control: manipulate all pending operations on a channel, returns
436 * zero or error code
Linus Walleij07934482010-03-26 16:50:49 -0700437 * @device_tx_status: poll for transaction completion, the optional
438 * txstate parameter can be supplied with a pointer to get a
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300439 * struct with auxiliary transfer status information, otherwise the call
Linus Walleij07934482010-03-26 16:50:49 -0700440 * will just return a simple status code
Dan Williams7405f742007-01-02 11:10:43 -0700441 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700442 */
443struct dma_device {
444
445 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900446 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700447 struct list_head channels;
448 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700449 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700450 unsigned short max_xor;
451 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700452 u8 copy_align;
453 u8 xor_align;
454 u8 pq_align;
455 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700456 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700457
Chris Leechc13c8262006-05-23 17:18:44 -0700458 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700459 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700460
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700461 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700462 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700463
464 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700465 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700466 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700467 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700468 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700469 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700470 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700471 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700472 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700473 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
474 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
475 unsigned int src_cnt, const unsigned char *scf,
476 size_t len, unsigned long flags);
477 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
478 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
479 unsigned int src_cnt, const unsigned char *scf, size_t len,
480 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700481 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700482 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700483 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700484 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700485 struct dma_chan *chan, unsigned long flags);
Ira Snydera86ee032010-09-30 11:46:44 +0000486 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
487 struct dma_chan *chan,
488 struct scatterlist *dst_sg, unsigned int dst_nents,
489 struct scatterlist *src_sg, unsigned int src_nents,
490 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700491
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700492 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
493 struct dma_chan *chan, struct scatterlist *sgl,
494 unsigned int sg_len, enum dma_data_direction direction,
495 unsigned long flags);
Sascha Hauer782bc952010-09-30 13:56:32 +0000496 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
497 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
498 size_t period_len, enum dma_data_direction direction);
Linus Walleij05827632010-05-17 16:30:42 -0700499 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
500 unsigned long arg);
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700501
Linus Walleij07934482010-03-26 16:50:49 -0700502 enum dma_status (*device_tx_status)(struct dma_chan *chan,
503 dma_cookie_t cookie,
504 struct dma_tx_state *txstate);
Dan Williams7405f742007-01-02 11:10:43 -0700505 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700506};
507
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000508static inline int dmaengine_device_control(struct dma_chan *chan,
509 enum dma_ctrl_cmd cmd,
510 unsigned long arg)
511{
512 return chan->device->device_control(chan, cmd, arg);
513}
514
515static inline int dmaengine_slave_config(struct dma_chan *chan,
516 struct dma_slave_config *config)
517{
518 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
519 (unsigned long)config);
520}
521
522static inline int dmaengine_terminate_all(struct dma_chan *chan)
523{
524 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
525}
526
527static inline int dmaengine_pause(struct dma_chan *chan)
528{
529 return dmaengine_device_control(chan, DMA_PAUSE, 0);
530}
531
532static inline int dmaengine_resume(struct dma_chan *chan)
533{
534 return dmaengine_device_control(chan, DMA_RESUME, 0);
535}
536
Russell King - ARM Linux98d530f2011-01-01 23:00:23 +0000537static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000538{
539 return desc->tx_submit(desc);
540}
541
Dan Williams83544ae2009-09-08 17:42:53 -0700542static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
543{
544 size_t mask;
545
546 if (!align)
547 return true;
548 mask = (1 << align) - 1;
549 if (mask & (off1 | off2 | len))
550 return false;
551 return true;
552}
553
554static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
555 size_t off2, size_t len)
556{
557 return dmaengine_check_align(dev->copy_align, off1, off2, len);
558}
559
560static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
561 size_t off2, size_t len)
562{
563 return dmaengine_check_align(dev->xor_align, off1, off2, len);
564}
565
566static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
567 size_t off2, size_t len)
568{
569 return dmaengine_check_align(dev->pq_align, off1, off2, len);
570}
571
572static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
573 size_t off2, size_t len)
574{
575 return dmaengine_check_align(dev->fill_align, off1, off2, len);
576}
577
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700578static inline void
579dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
580{
581 dma->max_pq = maxpq;
582 if (has_pq_continue)
583 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
584}
585
586static inline bool dmaf_continue(enum dma_ctrl_flags flags)
587{
588 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
589}
590
591static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
592{
593 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
594
595 return (flags & mask) == mask;
596}
597
598static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
599{
600 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
601}
602
Mathieu Lacaged3f3cf82010-08-14 15:02:44 +0200603static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700604{
605 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
606}
607
608/* dma_maxpq - reduce maxpq in the face of continued operations
609 * @dma - dma device with PQ capability
610 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
611 *
612 * When an engine does not support native continuation we need 3 extra
613 * source slots to reuse P and Q with the following coefficients:
614 * 1/ {00} * P : remove P from Q', but use it as a source for P'
615 * 2/ {01} * Q : use Q to continue Q' calculation
616 * 3/ {00} * Q : subtract Q from P' to cancel (2)
617 *
618 * In the case where P is disabled we only need 1 extra source:
619 * 1/ {01} * Q : use Q to continue Q' calculation
620 */
621static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
622{
623 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
624 return dma_dev_to_maxpq(dma);
625 else if (dmaf_p_disabled_continue(flags))
626 return dma_dev_to_maxpq(dma) - 1;
627 else if (dmaf_continue(flags))
628 return dma_dev_to_maxpq(dma) - 3;
629 BUG();
630}
631
Chris Leechc13c8262006-05-23 17:18:44 -0700632/* --- public DMA engine API --- */
633
Dan Williams649274d2009-01-11 00:20:39 -0800634#ifdef CONFIG_DMA_ENGINE
Dan Williams209b84a2009-01-06 11:38:17 -0700635void dmaengine_get(void);
636void dmaengine_put(void);
Dan Williams649274d2009-01-11 00:20:39 -0800637#else
638static inline void dmaengine_get(void)
639{
640}
641static inline void dmaengine_put(void)
642{
643}
644#endif
645
David S. Millerb4bd07c2009-02-06 22:06:43 -0800646#ifdef CONFIG_NET_DMA
647#define net_dmaengine_get() dmaengine_get()
648#define net_dmaengine_put() dmaengine_put()
649#else
650static inline void net_dmaengine_get(void)
651{
652}
653static inline void net_dmaengine_put(void)
654{
655}
656#endif
657
Dan Williams729b5d12009-03-25 09:13:25 -0700658#ifdef CONFIG_ASYNC_TX_DMA
659#define async_dmaengine_get() dmaengine_get()
660#define async_dmaengine_put() dmaengine_put()
Dan Williams5fc6d892010-10-07 16:44:50 -0700661#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams138f4c32009-09-08 17:42:51 -0700662#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
663#else
Dan Williams729b5d12009-03-25 09:13:25 -0700664#define async_dma_find_channel(type) dma_find_channel(type)
Dan Williams5fc6d892010-10-07 16:44:50 -0700665#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
Dan Williams729b5d12009-03-25 09:13:25 -0700666#else
667static inline void async_dmaengine_get(void)
668{
669}
670static inline void async_dmaengine_put(void)
671{
672}
673static inline struct dma_chan *
674async_dma_find_channel(enum dma_transaction_type type)
675{
676 return NULL;
677}
Dan Williams138f4c32009-09-08 17:42:51 -0700678#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams729b5d12009-03-25 09:13:25 -0700679
Dan Williams7405f742007-01-02 11:10:43 -0700680dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
681 void *dest, void *src, size_t len);
682dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
683 struct page *page, unsigned int offset, void *kdata, size_t len);
684dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700685 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700686 unsigned int src_off, size_t len);
687void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
688 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700689
Dan Williams08398752008-07-17 17:59:56 -0700690static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700691{
Dan Williams636bdea2008-04-17 20:17:26 -0700692 tx->flags |= DMA_CTRL_ACK;
693}
694
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700695static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
696{
697 tx->flags &= ~DMA_CTRL_ACK;
698}
699
Dan Williams08398752008-07-17 17:59:56 -0700700static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700701{
Dan Williams08398752008-07-17 17:59:56 -0700702 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700703}
704
Dan Williams7405f742007-01-02 11:10:43 -0700705#define first_dma_cap(mask) __first_dma_cap(&(mask))
706static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
707{
708 return min_t(int, DMA_TX_TYPE_END,
709 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
710}
711
712#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
713static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
714{
715 return min_t(int, DMA_TX_TYPE_END,
716 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
717}
718
719#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
720static inline void
721__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
722{
723 set_bit(tx_type, dstp->bits);
724}
725
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900726#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
727static inline void
728__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
729{
730 clear_bit(tx_type, dstp->bits);
731}
732
Dan Williams33df8ca2009-01-06 11:38:15 -0700733#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
734static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
735{
736 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
737}
738
Dan Williams7405f742007-01-02 11:10:43 -0700739#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
740static inline int
741__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
742{
743 return test_bit(tx_type, srcp->bits);
744}
745
746#define for_each_dma_cap_mask(cap, mask) \
747 for ((cap) = first_dma_cap(mask); \
748 (cap) < DMA_TX_TYPE_END; \
749 (cap) = next_dma_cap((cap), (mask)))
750
Chris Leechc13c8262006-05-23 17:18:44 -0700751/**
Dan Williams7405f742007-01-02 11:10:43 -0700752 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700753 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700754 *
755 * This allows drivers to push copies to HW in batches,
756 * reducing MMIO writes where possible.
757 */
Dan Williams7405f742007-01-02 11:10:43 -0700758static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700759{
Dan Williamsec8670f2008-03-01 07:51:29 -0700760 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700761}
762
Dan Williams7405f742007-01-02 11:10:43 -0700763#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
764
Chris Leechc13c8262006-05-23 17:18:44 -0700765/**
Dan Williams7405f742007-01-02 11:10:43 -0700766 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700767 * @chan: DMA channel
768 * @cookie: transaction identifier to check status of
769 * @last: returns last completed cookie, can be NULL
770 * @used: returns last issued cookie, can be NULL
771 *
772 * If @last and @used are passed in, upon return they reflect the driver
773 * internal state and can be used with dma_async_is_complete() to check
774 * the status of multiple cookies without re-checking hardware state.
775 */
Dan Williams7405f742007-01-02 11:10:43 -0700776static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700777 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
778{
Linus Walleij07934482010-03-26 16:50:49 -0700779 struct dma_tx_state state;
780 enum dma_status status;
781
782 status = chan->device->device_tx_status(chan, cookie, &state);
783 if (last)
784 *last = state.last;
785 if (used)
786 *used = state.used;
787 return status;
Chris Leechc13c8262006-05-23 17:18:44 -0700788}
789
Dan Williams7405f742007-01-02 11:10:43 -0700790#define dma_async_memcpy_complete(chan, cookie, last, used)\
791 dma_async_is_tx_complete(chan, cookie, last, used)
792
Chris Leechc13c8262006-05-23 17:18:44 -0700793/**
794 * dma_async_is_complete - test a cookie against chan state
795 * @cookie: transaction identifier to test status of
796 * @last_complete: last know completed transaction
797 * @last_used: last cookie value handed out
798 *
799 * dma_async_is_complete() is used in dma_async_memcpy_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000800 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700801 */
802static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
803 dma_cookie_t last_complete, dma_cookie_t last_used)
804{
805 if (last_complete <= last_used) {
806 if ((cookie <= last_complete) || (cookie > last_used))
807 return DMA_SUCCESS;
808 } else {
809 if ((cookie <= last_complete) && (cookie > last_used))
810 return DMA_SUCCESS;
811 }
812 return DMA_IN_PROGRESS;
813}
814
Dan Williamsbca34692010-03-26 16:52:10 -0700815static inline void
816dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
817{
818 if (st) {
819 st->last = last;
820 st->used = used;
821 st->residue = residue;
822 }
823}
824
Dan Williams7405f742007-01-02 11:10:43 -0700825enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -0700826#ifdef CONFIG_DMA_ENGINE
827enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
Dan Williamsc50331e2009-01-19 15:33:14 -0700828void dma_issue_pending_all(void);
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100829struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
830void dma_release_channel(struct dma_chan *chan);
Dan Williams07f22112009-01-05 17:14:31 -0700831#else
832static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
833{
834 return DMA_SUCCESS;
835}
Dan Williamsc50331e2009-01-19 15:33:14 -0700836static inline void dma_issue_pending_all(void)
837{
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100838}
839static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
840 dma_filter_fn fn, void *fn_param)
841{
842 return NULL;
843}
844static inline void dma_release_channel(struct dma_chan *chan)
845{
Dan Williamsc50331e2009-01-19 15:33:14 -0700846}
Dan Williams07f22112009-01-05 17:14:31 -0700847#endif
Chris Leechc13c8262006-05-23 17:18:44 -0700848
849/* --- DMA device --- */
850
851int dma_async_device_register(struct dma_device *device);
852void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -0700853void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Dan Williamsbec08512009-01-06 11:38:14 -0700854struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dan Williams59b5ec22009-01-06 11:38:15 -0700855#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
Chris Leechc13c8262006-05-23 17:18:44 -0700856
Chris Leechde5506e2006-05-23 17:50:37 -0700857/* --- Helper iov-locking functions --- */
858
859struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +0000860 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -0700861 int nr_pages;
862 struct page **pages;
863};
864
865struct dma_pinned_list {
866 int nr_iovecs;
867 struct dma_page_list page_list[0];
868};
869
870struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
871void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
872
873dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
874 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
875dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
876 struct dma_pinned_list *pinned_list, struct page *page,
877 unsigned int offset, size_t len);
878
Chris Leechc13c8262006-05-23 17:18:44 -0700879#endif /* DMAENGINE_H */