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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Dave Jones1f729e02006-06-04 19:37:58 -04002 * (c) 2003-2006 Advanced Micro Devices, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 */
7
8struct powernow_k8_data {
9 unsigned int cpu;
10
11 u32 numps; /* number of p-states */
12 u32 batps; /* number of p-states supported on battery */
13
14 /* these values are constant when the PSB is used to determine
15 * vid/fid pairings, but are modified during the ->target() call
16 * when ACPI is used */
17 u32 rvo; /* ramp voltage offset */
18 u32 irt; /* isochronous relief time */
19 u32 vidmvs; /* usable value calculated from mvs */
20 u32 vstable; /* voltage stabilization time, units 20 us */
21 u32 plllock; /* pll lock time, units 1 us */
Dave Jones841e40b2005-07-28 09:40:04 -070022 u32 exttype; /* extended interface = 1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Mark Langsdorfc5829cd2007-10-17 16:52:08 -050024 /* keep track of the current fid / vid or pstate */
Andreas Herrmanna266d9f2008-11-21 14:49:25 +010025 u32 currvid;
26 u32 currfid;
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
28 /* the powernow_table includes all frequency and vid/fid pairings:
29 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
30 * frequency is in kHz */
31 struct cpufreq_frequency_table *powernow_table;
32
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 /* the acpi table needs to be kept. it's only available if ACPI was
34 * used to determine valid frequency/vid/fid states */
Linus Torvaldsf607e3a2008-08-19 13:34:59 -070035 struct acpi_processor_performance acpi_data;
Thomas Renninger57f4fa62009-02-04 01:17:45 +010036
Dave Jones1f729e02006-06-04 19:37:58 -040037 /* we need to keep track of associated cores, but let cpufreq
38 * handle hotplug events - so just point at cpufreq pol->cpus
39 * structure */
Rusty Russell835481d2009-01-04 05:18:06 -080040 struct cpumask *available_cores;
Linus Torvalds1da177e2005-04-16 15:20:36 -070041};
42
Linus Torvalds1da177e2005-04-16 15:20:36 -070043/* processor's cpuid instruction support */
44#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
45#define CPUID_XFAM 0x0ff00000 /* extended family */
46#define CPUID_XFAM_K8 0
47#define CPUID_XMOD 0x000f0000 /* extended model */
Mark Langsdorf6c9cda72007-12-14 13:00:23 -060048#define CPUID_XMOD_REV_MASK 0x000c0000
Dave Jones30046e52007-05-13 11:55:14 -040049#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#define CPUID_USE_XFAM_XMOD 0x00000f00
51#define CPUID_GET_MAX_CAPABILITIES 0x80000000
52#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
53#define P_STATE_TRANSITION_CAPABLE 6
54
55/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
56/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
57/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
58/* the register number is placed in ecx, and the data is returned in edx:eax. */
59
60#define MSR_FIDVID_CTL 0xc0010041
61#define MSR_FIDVID_STATUS 0xc0010042
62
63/* Field definitions within the FID VID Low Control MSR : */
64#define MSR_C_LO_INIT_FID_VID 0x00010000
Dave Jones841e40b2005-07-28 09:40:04 -070065#define MSR_C_LO_NEW_VID 0x00003f00
66#define MSR_C_LO_NEW_FID 0x0000003f
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#define MSR_C_LO_VID_SHIFT 8
68
69/* Field definitions within the FID VID High Control MSR : */
Dave Jones32ee8c32006-02-28 00:43:23 -050070#define MSR_C_HI_STP_GNT_TO 0x000fffff
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
72/* Field definitions within the FID VID Low Status MSR : */
Dave Jones841e40b2005-07-28 09:40:04 -070073#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
74#define MSR_S_LO_MAX_RAMP_VID 0x3f000000
Linus Torvalds1da177e2005-04-16 15:20:36 -070075#define MSR_S_LO_MAX_FID 0x003f0000
76#define MSR_S_LO_START_FID 0x00003f00
77#define MSR_S_LO_CURRENT_FID 0x0000003f
78
79/* Field definitions within the FID VID High Status MSR : */
Dave Jones841e40b2005-07-28 09:40:04 -070080#define MSR_S_HI_MIN_WORKING_VID 0x3f000000
81#define MSR_S_HI_MAX_WORKING_VID 0x003f0000
82#define MSR_S_HI_START_VID 0x00003f00
83#define MSR_S_HI_CURRENT_VID 0x0000003f
84#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -070085
86/*
87 * There are restrictions frequencies have to follow:
88 * - only 1 entry in the low fid table ( <=1.4GHz )
89 * - lowest entry in the high fid table must be >= 2 * the entry in the
90 * low fid table
91 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
92 * in the low fid table
Langsdorf, Mark019a61b2005-11-29 14:18:03 -060093 * - the parts can only step at <= 200 MHz intervals, odd fid values are
94 * supported in revision G and later revisions.
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 * - lowest frequency must be >= interprocessor hypertransport link speed
96 * (only applies to MP systems obviously)
97 */
98
99/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
Langsdorf, Mark019a61b2005-11-29 14:18:03 -0600100#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
102
103#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
104#define HI_VCOFREQ_TABLE_BOTTOM 1600
105
106#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
107
108#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
Dave Jones841e40b2005-07-28 09:40:04 -0700109#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111#define MIN_FREQ 800 /* Min and max freqs, per spec */
112#define MAX_FREQ 5000
113
Langsdorf, Mark019a61b2005-11-29 14:18:03 -0600114#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
Dave Jones841e40b2005-07-28 09:40:04 -0700115#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
116
117#define VID_OFF 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
119#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
120
121#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
122
123#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
Simon Arlott27b46d72007-10-20 01:13:56 +0200124#define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126/*
Simon Arlott27b46d72007-10-20 01:13:56 +0200127 * Most values of interest are encoded in a single field of the _PSS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 * entries: the "control" value.
129 */
Dave Jones32ee8c32006-02-28 00:43:23 -0500130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131#define IRT_SHIFT 30
132#define RVO_SHIFT 28
Dave Jones2bcad932005-07-29 09:56:41 -0700133#define EXT_TYPE_SHIFT 27
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134#define PLL_L_SHIFT 20
135#define MVS_SHIFT 18
136#define VST_SHIFT 11
137#define VID_SHIFT 6
138#define IRT_MASK 3
139#define RVO_MASK 3
Dave Jones2bcad932005-07-29 09:56:41 -0700140#define EXT_TYPE_MASK 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141#define PLL_L_MASK 0x7f
142#define MVS_MASK 3
143#define VST_MASK 0x7f
144#define VID_MASK 0x1f
Langsdorf, Mark6cad6472006-06-08 10:33:19 -0500145#define FID_MASK 0x1f
146#define EXT_VID_MASK 0x3f
147#define EXT_FID_MASK 0x3f
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148
149
150/*
151 * Version 1.4 of the PSB table. This table is constructed by BIOS and is
152 * to tell the OS's power management driver which VIDs and FIDs are
153 * supported by this particular processor.
154 * If the data in the PSB / PST is wrong, then this driver will program the
155 * wrong values into hardware, which is very likely to lead to a crash.
156 */
157
158#define PSB_ID_STRING "AMDK7PNOW!"
159#define PSB_ID_STRING_LEN 10
160
161#define PSB_VERSION_1_4 0x14
162
163struct psb_s {
164 u8 signature[10];
165 u8 tableversion;
166 u8 flags1;
167 u16 vstable;
168 u8 flags2;
169 u8 num_tables;
170 u32 cpuid;
171 u8 plllocktime;
172 u8 maxfid;
173 u8 maxvid;
174 u8 numps;
175};
176
177/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
178struct pst_s {
179 u8 fid;
180 u8 vid;
181};
182
Mark Langsdorfa2e1b4c2009-07-26 10:55:25 -0500183static int core_voltage_pre_transition(struct powernow_k8_data *data,
184 u32 reqvid, u32 regfid);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
186static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
187
188static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
Dave Jones065b8072005-05-31 19:03:46 -0700189
Dave Jones1f729e02006-06-04 19:37:58 -0400190static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);