Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Texas Instruments. |
Brian Niebuhr | 43abb11 | 2010-10-06 18:34:47 +0530 | [diff] [blame] | 3 | * Copyright (C) 2010 EF Johnson Technologies |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/gpio.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/clk.h> |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 28 | #include <linux/dmaengine.h> |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 29 | #include <linux/dma-mapping.h> |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 30 | #include <linux/edma.h> |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 31 | #include <linux/of.h> |
| 32 | #include <linux/of_device.h> |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 33 | #include <linux/of_gpio.h> |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 34 | #include <linux/spi/spi.h> |
| 35 | #include <linux/spi/spi_bitbang.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 36 | #include <linux/slab.h> |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 37 | |
Arnd Bergmann | ec2a083 | 2012-08-24 15:11:34 +0200 | [diff] [blame] | 38 | #include <linux/platform_data/spi-davinci.h> |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 39 | |
| 40 | #define SPI_NO_RESOURCE ((resource_size_t)-1) |
| 41 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 42 | #define CS_DEFAULT 0xFF |
| 43 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 44 | #define SPIFMT_PHASE_MASK BIT(16) |
| 45 | #define SPIFMT_POLARITY_MASK BIT(17) |
| 46 | #define SPIFMT_DISTIMER_MASK BIT(18) |
| 47 | #define SPIFMT_SHIFTDIR_MASK BIT(20) |
| 48 | #define SPIFMT_WAITENA_MASK BIT(21) |
| 49 | #define SPIFMT_PARITYENA_MASK BIT(22) |
| 50 | #define SPIFMT_ODD_PARITY_MASK BIT(23) |
| 51 | #define SPIFMT_WDELAY_MASK 0x3f000000u |
| 52 | #define SPIFMT_WDELAY_SHIFT 24 |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 53 | #define SPIFMT_PRESCALE_SHIFT 8 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 54 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 55 | /* SPIPC0 */ |
| 56 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ |
| 57 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ |
| 58 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ |
| 59 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 60 | |
| 61 | #define SPIINT_MASKALL 0x0101035F |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 62 | #define SPIINT_MASKINT 0x0000015F |
| 63 | #define SPI_INTLVL_1 0x000001FF |
| 64 | #define SPI_INTLVL_0 0x00000000 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 65 | |
Brian Niebuhr | cfbc5d1 | 2010-08-12 12:27:33 +0530 | [diff] [blame] | 66 | /* SPIDAT1 (upper 16 bit defines) */ |
| 67 | #define SPIDAT1_CSHOLD_MASK BIT(12) |
| 68 | |
| 69 | /* SPIGCR1 */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 70 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
| 71 | #define SPIGCR1_MASTER_MASK BIT(0) |
Brian Niebuhr | 3f27b57 | 2010-10-06 18:25:43 +0530 | [diff] [blame] | 72 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 73 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
Sekhar Nori | 8e206f1 | 2010-08-20 16:20:49 +0530 | [diff] [blame] | 74 | #define SPIGCR1_SPIENA_MASK BIT(24) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 75 | |
| 76 | /* SPIBUF */ |
| 77 | #define SPIBUF_TXFULL_MASK BIT(29) |
| 78 | #define SPIBUF_RXEMPTY_MASK BIT(31) |
| 79 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 80 | /* SPIDELAY */ |
| 81 | #define SPIDELAY_C2TDELAY_SHIFT 24 |
| 82 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) |
| 83 | #define SPIDELAY_T2CDELAY_SHIFT 16 |
| 84 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) |
| 85 | #define SPIDELAY_T2EDELAY_SHIFT 8 |
| 86 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) |
| 87 | #define SPIDELAY_C2EDELAY_SHIFT 0 |
| 88 | #define SPIDELAY_C2EDELAY_MASK 0xFF |
| 89 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 90 | /* Error Masks */ |
| 91 | #define SPIFLG_DLEN_ERR_MASK BIT(0) |
| 92 | #define SPIFLG_TIMEOUT_MASK BIT(1) |
| 93 | #define SPIFLG_PARERR_MASK BIT(2) |
| 94 | #define SPIFLG_DESYNC_MASK BIT(3) |
| 95 | #define SPIFLG_BITERR_MASK BIT(4) |
| 96 | #define SPIFLG_OVRRUN_MASK BIT(6) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 97 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 98 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
| 99 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ |
| 100 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ |
| 101 | | SPIFLG_OVRRUN_MASK) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 102 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 103 | #define SPIINT_DMA_REQ_EN BIT(16) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 104 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 105 | /* SPI Controller registers */ |
| 106 | #define SPIGCR0 0x00 |
| 107 | #define SPIGCR1 0x04 |
| 108 | #define SPIINT 0x08 |
| 109 | #define SPILVL 0x0c |
| 110 | #define SPIFLG 0x10 |
| 111 | #define SPIPC0 0x14 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 112 | #define SPIDAT1 0x3c |
| 113 | #define SPIBUF 0x40 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 114 | #define SPIDELAY 0x48 |
| 115 | #define SPIDEF 0x4c |
| 116 | #define SPIFMT0 0x50 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 117 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 118 | /* SPI Controller driver's private data. */ |
| 119 | struct davinci_spi { |
| 120 | struct spi_bitbang bitbang; |
| 121 | struct clk *clk; |
| 122 | |
| 123 | u8 version; |
| 124 | resource_size_t pbase; |
| 125 | void __iomem *base; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 126 | u32 irq; |
| 127 | struct completion done; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 128 | |
| 129 | const void *tx; |
| 130 | void *rx; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 131 | int rcount; |
| 132 | int wcount; |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 133 | |
| 134 | struct dma_chan *dma_rx; |
| 135 | struct dma_chan *dma_tx; |
| 136 | int dma_rx_chnum; |
| 137 | int dma_tx_chnum; |
| 138 | |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 139 | struct davinci_spi_platform_data pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 140 | |
| 141 | void (*get_rx)(u32 rx_data, struct davinci_spi *); |
| 142 | u32 (*get_tx)(struct davinci_spi *); |
| 143 | |
Murali Karicheri | 7480e75 | 2014-07-31 20:33:14 +0300 | [diff] [blame] | 144 | u8 *bytes_per_word; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 145 | }; |
| 146 | |
Brian Niebuhr | 53a31b0 | 2010-08-16 15:05:51 +0530 | [diff] [blame] | 147 | static struct davinci_spi_config davinci_spi_default_cfg; |
| 148 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 149 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 150 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 151 | if (dspi->rx) { |
| 152 | u8 *rx = dspi->rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 153 | *rx++ = (u8)data; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 154 | dspi->rx = rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 155 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 158 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 159 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 160 | if (dspi->rx) { |
| 161 | u16 *rx = dspi->rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 162 | *rx++ = (u16)data; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 163 | dspi->rx = rx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 164 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 165 | } |
| 166 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 167 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 168 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 169 | u32 data = 0; |
Jingoo Han | 859c337 | 2014-09-02 11:48:00 +0900 | [diff] [blame^] | 170 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 171 | if (dspi->tx) { |
| 172 | const u8 *tx = dspi->tx; |
Jingoo Han | 859c337 | 2014-09-02 11:48:00 +0900 | [diff] [blame^] | 173 | |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 174 | data = *tx++; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 175 | dspi->tx = tx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 176 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 177 | return data; |
| 178 | } |
| 179 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 180 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 181 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 182 | u32 data = 0; |
Jingoo Han | 859c337 | 2014-09-02 11:48:00 +0900 | [diff] [blame^] | 183 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 184 | if (dspi->tx) { |
| 185 | const u16 *tx = dspi->tx; |
Jingoo Han | 859c337 | 2014-09-02 11:48:00 +0900 | [diff] [blame^] | 186 | |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 187 | data = *tx++; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 188 | dspi->tx = tx; |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 189 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 190 | return data; |
| 191 | } |
| 192 | |
| 193 | static inline void set_io_bits(void __iomem *addr, u32 bits) |
| 194 | { |
| 195 | u32 v = ioread32(addr); |
| 196 | |
| 197 | v |= bits; |
| 198 | iowrite32(v, addr); |
| 199 | } |
| 200 | |
| 201 | static inline void clear_io_bits(void __iomem *addr, u32 bits) |
| 202 | { |
| 203 | u32 v = ioread32(addr); |
| 204 | |
| 205 | v &= ~bits; |
| 206 | iowrite32(v, addr); |
| 207 | } |
| 208 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 209 | /* |
| 210 | * Interface to control the chip select signal |
| 211 | */ |
| 212 | static void davinci_spi_chipselect(struct spi_device *spi, int value) |
| 213 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 214 | struct davinci_spi *dspi; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 215 | struct davinci_spi_platform_data *pdata; |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 216 | u8 chip_sel = spi->chip_select; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 217 | u16 spidat1 = CS_DEFAULT; |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 218 | bool gpio_chipsel = false; |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 219 | int gpio; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 220 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 221 | dspi = spi_master_get_devdata(spi->master); |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 222 | pdata = &dspi->pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 223 | |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 224 | if (spi->cs_gpio >= 0) { |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 225 | /* SPI core parse and update master->cs_gpio */ |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 226 | gpio_chipsel = true; |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 227 | gpio = spi->cs_gpio; |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 228 | } |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 229 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 230 | /* |
| 231 | * Board specific chip select logic decides the polarity and cs |
| 232 | * line for the controller |
| 233 | */ |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 234 | if (gpio_chipsel) { |
| 235 | if (value == BITBANG_CS_ACTIVE) |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 236 | gpio_set_value(gpio, spi->mode & SPI_CS_HIGH); |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 237 | else |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 238 | gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH)); |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 239 | } else { |
| 240 | if (value == BITBANG_CS_ACTIVE) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 241 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
| 242 | spidat1 &= ~(0x1 << chip_sel); |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 243 | } |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 244 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 245 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 246 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | /** |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 250 | * davinci_spi_get_prescale - Calculates the correct prescale value |
| 251 | * @maxspeed_hz: the maximum rate the SPI clock can run at |
| 252 | * |
| 253 | * This function calculates the prescale value that generates a clock rate |
| 254 | * less than or equal to the specified maximum. |
| 255 | * |
| 256 | * Returns: calculated prescale - 1 for easy programming into SPI registers |
| 257 | * or negative error number if valid prescalar cannot be updated. |
| 258 | */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 259 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 260 | u32 max_speed_hz) |
| 261 | { |
| 262 | int ret; |
| 263 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 264 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 265 | |
| 266 | if (ret < 3 || ret > 256) |
| 267 | return -EINVAL; |
| 268 | |
| 269 | return ret - 1; |
| 270 | } |
| 271 | |
| 272 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 273 | * davinci_spi_setup_transfer - This functions will determine transfer method |
| 274 | * @spi: spi device on which data transfer to be done |
| 275 | * @t: spi transfer in which transfer info is filled |
| 276 | * |
| 277 | * This function determines data transfer method (8/16/32 bit transfer). |
| 278 | * It will also set the SPI Clock Control register according to |
| 279 | * SPI slave device freq. |
| 280 | */ |
| 281 | static int davinci_spi_setup_transfer(struct spi_device *spi, |
| 282 | struct spi_transfer *t) |
| 283 | { |
| 284 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 285 | struct davinci_spi *dspi; |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 286 | struct davinci_spi_config *spicfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 287 | u8 bits_per_word = 0; |
Sachin Kamat | 32ea394 | 2013-09-11 16:05:04 +0530 | [diff] [blame] | 288 | u32 hz = 0, spifmt = 0; |
| 289 | int prescale; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 290 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 291 | dspi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 292 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
| 293 | if (!spicfg) |
| 294 | spicfg = &davinci_spi_default_cfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 295 | |
| 296 | if (t) { |
| 297 | bits_per_word = t->bits_per_word; |
| 298 | hz = t->speed_hz; |
| 299 | } |
| 300 | |
| 301 | /* if bits_per_word is not set then set it default */ |
| 302 | if (!bits_per_word) |
| 303 | bits_per_word = spi->bits_per_word; |
| 304 | |
| 305 | /* |
| 306 | * Assign function pointer to appropriate transfer method |
| 307 | * 8bit, 16bit or 32bit transfer |
| 308 | */ |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 309 | if (bits_per_word <= 8) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 310 | dspi->get_rx = davinci_spi_rx_buf_u8; |
| 311 | dspi->get_tx = davinci_spi_tx_buf_u8; |
| 312 | dspi->bytes_per_word[spi->chip_select] = 1; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 313 | } else { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 314 | dspi->get_rx = davinci_spi_rx_buf_u16; |
| 315 | dspi->get_tx = davinci_spi_tx_buf_u16; |
| 316 | dspi->bytes_per_word[spi->chip_select] = 2; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 317 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 318 | |
| 319 | if (!hz) |
| 320 | hz = spi->max_speed_hz; |
| 321 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 322 | /* Set up SPIFMTn register, unique to this chipselect. */ |
| 323 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 324 | prescale = davinci_spi_get_prescale(dspi, hz); |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 325 | if (prescale < 0) |
| 326 | return prescale; |
| 327 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 328 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 329 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 330 | if (spi->mode & SPI_LSB_FIRST) |
| 331 | spifmt |= SPIFMT_SHIFTDIR_MASK; |
| 332 | |
| 333 | if (spi->mode & SPI_CPOL) |
| 334 | spifmt |= SPIFMT_POLARITY_MASK; |
| 335 | |
| 336 | if (!(spi->mode & SPI_CPHA)) |
| 337 | spifmt |= SPIFMT_PHASE_MASK; |
| 338 | |
| 339 | /* |
| 340 | * Version 1 hardware supports two basic SPI modes: |
| 341 | * - Standard SPI mode uses 4 pins, with chipselect |
| 342 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) |
| 343 | * (distinct from SPI_3WIRE, with just one data wire; |
| 344 | * or similar variants without MOSI or without MISO) |
| 345 | * |
| 346 | * Version 2 hardware supports an optional handshaking signal, |
| 347 | * so it can support two more modes: |
| 348 | * - 5 pin SPI variant is standard SPI plus SPI_READY |
| 349 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) |
| 350 | */ |
| 351 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 352 | if (dspi->version == SPI_VERSION_2) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 353 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 354 | u32 delay = 0; |
| 355 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 356 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
| 357 | & SPIFMT_WDELAY_MASK); |
| 358 | |
| 359 | if (spicfg->odd_parity) |
| 360 | spifmt |= SPIFMT_ODD_PARITY_MASK; |
| 361 | |
| 362 | if (spicfg->parity_enable) |
| 363 | spifmt |= SPIFMT_PARITYENA_MASK; |
| 364 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 365 | if (spicfg->timer_disable) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 366 | spifmt |= SPIFMT_DISTIMER_MASK; |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 367 | } else { |
| 368 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) |
| 369 | & SPIDELAY_C2TDELAY_MASK; |
| 370 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) |
| 371 | & SPIDELAY_T2CDELAY_MASK; |
| 372 | } |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 373 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 374 | if (spi->mode & SPI_READY) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 375 | spifmt |= SPIFMT_WAITENA_MASK; |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 376 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
| 377 | & SPIDELAY_T2EDELAY_MASK; |
| 378 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) |
| 379 | & SPIDELAY_C2EDELAY_MASK; |
| 380 | } |
| 381 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 382 | iowrite32(delay, dspi->base + SPIDELAY); |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 383 | } |
| 384 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 385 | iowrite32(spifmt, dspi->base + SPIFMT0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 390 | /** |
| 391 | * davinci_spi_setup - This functions will set default transfer method |
| 392 | * @spi: spi device on which data transfer to be done |
| 393 | * |
| 394 | * This functions sets the default transfer method. |
| 395 | */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 396 | static int davinci_spi_setup(struct spi_device *spi) |
| 397 | { |
Brian Niebuhr | b23a5d4 | 2010-09-24 18:53:32 +0530 | [diff] [blame] | 398 | int retval = 0; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 399 | struct davinci_spi *dspi; |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 400 | struct davinci_spi_platform_data *pdata; |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 401 | struct spi_master *master = spi->master; |
| 402 | struct device_node *np = spi->dev.of_node; |
| 403 | bool internal_cs = true; |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 404 | unsigned long flags = GPIOF_DIR_OUT; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 405 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 406 | dspi = spi_master_get_devdata(spi->master); |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 407 | pdata = &dspi->pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 408 | |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 409 | flags |= (spi->mode & SPI_CS_HIGH) ? GPIOF_INIT_LOW : GPIOF_INIT_HIGH; |
| 410 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 411 | if (!(spi->mode & SPI_NO_CS)) { |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 412 | if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 413 | retval = gpio_request_one(spi->cs_gpio, |
| 414 | flags, dev_name(&spi->dev)); |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 415 | internal_cs = false; |
| 416 | } else if (pdata->chip_sel && |
| 417 | spi->chip_select < pdata->num_chipselect && |
| 418 | pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 419 | spi->cs_gpio = pdata->chip_sel[spi->chip_select]; |
| 420 | retval = gpio_request_one(spi->cs_gpio, |
| 421 | flags, dev_name(&spi->dev)); |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 422 | internal_cs = false; |
| 423 | } |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 424 | } |
| 425 | |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 426 | if (retval) { |
| 427 | dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", |
| 428 | spi->cs_gpio, retval); |
| 429 | return retval; |
| 430 | } |
| 431 | |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 432 | if (internal_cs) |
| 433 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
| 434 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 435 | if (spi->mode & SPI_READY) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 436 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 437 | |
| 438 | if (spi->mode & SPI_LOOP) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 439 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 440 | else |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 441 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 442 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 443 | return retval; |
| 444 | } |
| 445 | |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 446 | static void davinci_spi_cleanup(struct spi_device *spi) |
| 447 | { |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 448 | if (spi->cs_gpio >= 0) |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 449 | gpio_free(spi->cs_gpio); |
| 450 | } |
| 451 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 452 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 453 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 454 | struct device *sdev = dspi->bitbang.master->dev.parent; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 455 | |
| 456 | if (int_status & SPIFLG_TIMEOUT_MASK) { |
| 457 | dev_dbg(sdev, "SPI Time-out Error\n"); |
| 458 | return -ETIMEDOUT; |
| 459 | } |
| 460 | if (int_status & SPIFLG_DESYNC_MASK) { |
| 461 | dev_dbg(sdev, "SPI Desynchronization Error\n"); |
| 462 | return -EIO; |
| 463 | } |
| 464 | if (int_status & SPIFLG_BITERR_MASK) { |
| 465 | dev_dbg(sdev, "SPI Bit error\n"); |
| 466 | return -EIO; |
| 467 | } |
| 468 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 469 | if (dspi->version == SPI_VERSION_2) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 470 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
| 471 | dev_dbg(sdev, "SPI Data Length Error\n"); |
| 472 | return -EIO; |
| 473 | } |
| 474 | if (int_status & SPIFLG_PARERR_MASK) { |
| 475 | dev_dbg(sdev, "SPI Parity Error\n"); |
| 476 | return -EIO; |
| 477 | } |
| 478 | if (int_status & SPIFLG_OVRRUN_MASK) { |
| 479 | dev_dbg(sdev, "SPI Data Overrun error\n"); |
| 480 | return -EIO; |
| 481 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 482 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
| 483 | dev_dbg(sdev, "SPI Buffer Init Active\n"); |
| 484 | return -EBUSY; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | /** |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 492 | * davinci_spi_process_events - check for and handle any SPI controller events |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 493 | * @dspi: the controller data |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 494 | * |
| 495 | * This function will check the SPIFLG register and handle any events that are |
| 496 | * detected there |
| 497 | */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 498 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 499 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 500 | u32 buf, status, errors = 0, spidat1; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 501 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 502 | buf = ioread32(dspi->base + SPIBUF); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 503 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 504 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
| 505 | dspi->get_rx(buf & 0xFFFF, dspi); |
| 506 | dspi->rcount--; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 507 | } |
| 508 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 509 | status = ioread32(dspi->base + SPIFLG); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 510 | |
| 511 | if (unlikely(status & SPIFLG_ERROR_MASK)) { |
| 512 | errors = status & SPIFLG_ERROR_MASK; |
| 513 | goto out; |
| 514 | } |
| 515 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 516 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
| 517 | spidat1 = ioread32(dspi->base + SPIDAT1); |
| 518 | dspi->wcount--; |
| 519 | spidat1 &= ~0xFFFF; |
| 520 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); |
| 521 | iowrite32(spidat1, dspi->base + SPIDAT1); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | out: |
| 525 | return errors; |
| 526 | } |
| 527 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 528 | static void davinci_spi_dma_rx_callback(void *data) |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 529 | { |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 530 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 531 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 532 | dspi->rcount = 0; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 533 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 534 | if (!dspi->wcount && !dspi->rcount) |
| 535 | complete(&dspi->done); |
| 536 | } |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 537 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 538 | static void davinci_spi_dma_tx_callback(void *data) |
| 539 | { |
| 540 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
| 541 | |
| 542 | dspi->wcount = 0; |
| 543 | |
| 544 | if (!dspi->wcount && !dspi->rcount) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 545 | complete(&dspi->done); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 546 | } |
| 547 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 548 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 549 | * davinci_spi_bufs - functions which will handle transfer data |
| 550 | * @spi: spi device on which data transfer to be done |
| 551 | * @t: spi transfer in which transfer info is filled |
| 552 | * |
| 553 | * This function will put data to be transferred into data register |
| 554 | * of SPI controller and then wait until the completion will be marked |
| 555 | * by the IRQ Handler. |
| 556 | */ |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 557 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 558 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 559 | struct davinci_spi *dspi; |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 560 | int data_type, ret = -ENOMEM; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 561 | u32 tx_data, spidat1; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 562 | u32 errors = 0; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 563 | struct davinci_spi_config *spicfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 564 | struct davinci_spi_platform_data *pdata; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 565 | unsigned uninitialized_var(rx_buf_count); |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 566 | void *dummy_buf = NULL; |
| 567 | struct scatterlist sg_rx, sg_tx; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 568 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 569 | dspi = spi_master_get_devdata(spi->master); |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 570 | pdata = &dspi->pdata; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 571 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
| 572 | if (!spicfg) |
| 573 | spicfg = &davinci_spi_default_cfg; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 574 | |
| 575 | /* convert len to words based on bits_per_word */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 576 | data_type = dspi->bytes_per_word[spi->chip_select]; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 577 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 578 | dspi->tx = t->tx_buf; |
| 579 | dspi->rx = t->rx_buf; |
| 580 | dspi->wcount = t->len / data_type; |
| 581 | dspi->rcount = dspi->wcount; |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 582 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 583 | spidat1 = ioread32(dspi->base + SPIDAT1); |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 584 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 585 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
| 586 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 587 | |
Wolfram Sang | 16735d0 | 2013-11-14 14:32:02 -0800 | [diff] [blame] | 588 | reinit_completion(&dspi->done); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 589 | |
| 590 | if (spicfg->io_type == SPI_IO_TYPE_INTR) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 591 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 592 | |
| 593 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
| 594 | /* start the transfer */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 595 | dspi->wcount--; |
| 596 | tx_data = dspi->get_tx(dspi); |
| 597 | spidat1 &= 0xFFFF0000; |
| 598 | spidat1 |= tx_data & 0xFFFF; |
| 599 | iowrite32(spidat1, dspi->base + SPIDAT1); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 600 | } else { |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 601 | struct dma_slave_config dma_rx_conf = { |
| 602 | .direction = DMA_DEV_TO_MEM, |
| 603 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, |
| 604 | .src_addr_width = data_type, |
| 605 | .src_maxburst = 1, |
| 606 | }; |
| 607 | struct dma_slave_config dma_tx_conf = { |
| 608 | .direction = DMA_MEM_TO_DEV, |
| 609 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, |
| 610 | .dst_addr_width = data_type, |
| 611 | .dst_maxburst = 1, |
| 612 | }; |
| 613 | struct dma_async_tx_descriptor *rxdesc; |
| 614 | struct dma_async_tx_descriptor *txdesc; |
| 615 | void *buf; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 616 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 617 | dummy_buf = kzalloc(t->len, GFP_KERNEL); |
| 618 | if (!dummy_buf) |
| 619 | goto err_alloc_dummy_buf; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 620 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 621 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); |
| 622 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 623 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 624 | sg_init_table(&sg_rx, 1); |
| 625 | if (!t->rx_buf) |
| 626 | buf = dummy_buf; |
Michael Williamson | b1178b2 | 2011-03-14 11:49:02 -0400 | [diff] [blame] | 627 | else |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 628 | buf = t->rx_buf; |
| 629 | t->rx_dma = dma_map_single(&spi->dev, buf, |
| 630 | t->len, DMA_FROM_DEVICE); |
| 631 | if (!t->rx_dma) { |
| 632 | ret = -EFAULT; |
| 633 | goto err_rx_map; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 634 | } |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 635 | sg_dma_address(&sg_rx) = t->rx_dma; |
| 636 | sg_dma_len(&sg_rx) = t->len; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 637 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 638 | sg_init_table(&sg_tx, 1); |
| 639 | if (!t->tx_buf) |
| 640 | buf = dummy_buf; |
| 641 | else |
| 642 | buf = (void *)t->tx_buf; |
| 643 | t->tx_dma = dma_map_single(&spi->dev, buf, |
Christian Eggers | 89c66ee | 2013-07-29 20:54:09 +0200 | [diff] [blame] | 644 | t->len, DMA_TO_DEVICE); |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 645 | if (!t->tx_dma) { |
| 646 | ret = -EFAULT; |
| 647 | goto err_tx_map; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 648 | } |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 649 | sg_dma_address(&sg_tx) = t->tx_dma; |
| 650 | sg_dma_len(&sg_tx) = t->len; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 651 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 652 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, |
| 653 | &sg_rx, 1, DMA_DEV_TO_MEM, |
| 654 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 655 | if (!rxdesc) |
| 656 | goto err_desc; |
| 657 | |
| 658 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, |
| 659 | &sg_tx, 1, DMA_MEM_TO_DEV, |
| 660 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 661 | if (!txdesc) |
| 662 | goto err_desc; |
| 663 | |
| 664 | rxdesc->callback = davinci_spi_dma_rx_callback; |
| 665 | rxdesc->callback_param = (void *)dspi; |
| 666 | txdesc->callback = davinci_spi_dma_tx_callback; |
| 667 | txdesc->callback_param = (void *)dspi; |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 668 | |
| 669 | if (pdata->cshold_bug) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 670 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 671 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 672 | dmaengine_submit(rxdesc); |
| 673 | dmaengine_submit(txdesc); |
| 674 | |
| 675 | dma_async_issue_pending(dspi->dma_rx); |
| 676 | dma_async_issue_pending(dspi->dma_tx); |
| 677 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 678 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 679 | } |
Brian Niebuhr | cf90fe7 | 2010-08-20 17:02:49 +0530 | [diff] [blame] | 680 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 681 | /* Wait for the transfer to complete */ |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 682 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 683 | wait_for_completion_interruptible(&(dspi->done)); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 684 | } else { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 685 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
| 686 | errors = davinci_spi_process_events(dspi); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 687 | if (errors) |
| 688 | break; |
| 689 | cpu_relax(); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 690 | } |
| 691 | } |
| 692 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 693 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 694 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 695 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 696 | |
| 697 | dma_unmap_single(&spi->dev, t->rx_dma, |
| 698 | t->len, DMA_FROM_DEVICE); |
| 699 | dma_unmap_single(&spi->dev, t->tx_dma, |
| 700 | t->len, DMA_TO_DEVICE); |
| 701 | kfree(dummy_buf); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 702 | } |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 703 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 704 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
| 705 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
Brian Niebuhr | 3f27b57 | 2010-10-06 18:25:43 +0530 | [diff] [blame] | 706 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 707 | /* |
| 708 | * Check for bit error, desync error,parity error,timeout error and |
| 709 | * receive overflow errors |
| 710 | */ |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 711 | if (errors) { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 712 | ret = davinci_spi_check_error(dspi, errors); |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 713 | WARN(!ret, "%s: error reported but no error found!\n", |
| 714 | dev_name(&spi->dev)); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 715 | return ret; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 716 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 717 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 718 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 719 | dev_err(&spi->dev, "SPI data transfer error\n"); |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 720 | return -EIO; |
| 721 | } |
| 722 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 723 | return t->len; |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 724 | |
| 725 | err_desc: |
| 726 | dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); |
| 727 | err_tx_map: |
| 728 | dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); |
| 729 | err_rx_map: |
| 730 | kfree(dummy_buf); |
| 731 | err_alloc_dummy_buf: |
| 732 | return ret; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 733 | } |
| 734 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 735 | /** |
Murali Karicheri | 32310aa | 2012-12-21 15:13:26 -0500 | [diff] [blame] | 736 | * dummy_thread_fn - dummy thread function |
| 737 | * @irq: IRQ number for this SPI Master |
| 738 | * @context_data: structure for SPI Master controller davinci_spi |
| 739 | * |
| 740 | * This is to satisfy the request_threaded_irq() API so that the irq |
| 741 | * handler is called in interrupt context. |
| 742 | */ |
| 743 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) |
| 744 | { |
| 745 | return IRQ_HANDLED; |
| 746 | } |
| 747 | |
| 748 | /** |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 749 | * davinci_spi_irq - Interrupt handler for SPI Master Controller |
| 750 | * @irq: IRQ number for this SPI Master |
| 751 | * @context_data: structure for SPI Master controller davinci_spi |
| 752 | * |
| 753 | * ISR will determine that interrupt arrives either for READ or WRITE command. |
| 754 | * According to command it will do the appropriate action. It will check |
| 755 | * transfer length and if it is not zero then dispatch transfer command again. |
| 756 | * If transfer length is zero then it will indicate the COMPLETION so that |
| 757 | * davinci_spi_bufs function can go ahead. |
| 758 | */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 759 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 760 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 761 | struct davinci_spi *dspi = data; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 762 | int status; |
| 763 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 764 | status = davinci_spi_process_events(dspi); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 765 | if (unlikely(status != 0)) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 766 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 767 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 768 | if ((!dspi->rcount && !dspi->wcount) || status) |
| 769 | complete(&dspi->done); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 770 | |
| 771 | return IRQ_HANDLED; |
| 772 | } |
| 773 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 774 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 775 | { |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 776 | dma_cap_mask_t mask; |
| 777 | struct device *sdev = dspi->bitbang.master->dev.parent; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 778 | int r; |
| 779 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 780 | dma_cap_zero(mask); |
| 781 | dma_cap_set(DMA_SLAVE, mask); |
| 782 | |
| 783 | dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, |
| 784 | &dspi->dma_rx_chnum); |
| 785 | if (!dspi->dma_rx) { |
| 786 | dev_err(sdev, "request RX DMA channel failed\n"); |
| 787 | r = -ENODEV; |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 788 | goto rx_dma_failed; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 789 | } |
| 790 | |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 791 | dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, |
| 792 | &dspi->dma_tx_chnum); |
| 793 | if (!dspi->dma_tx) { |
| 794 | dev_err(sdev, "request TX DMA channel failed\n"); |
| 795 | r = -ENODEV; |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 796 | goto tx_dma_failed; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 797 | } |
| 798 | |
| 799 | return 0; |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 800 | |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 801 | tx_dma_failed: |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 802 | dma_release_channel(dspi->dma_rx); |
Brian Niebuhr | 523c37e | 2010-10-04 17:35:34 +0530 | [diff] [blame] | 803 | rx_dma_failed: |
| 804 | return r; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 805 | } |
| 806 | |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 807 | #if defined(CONFIG_OF) |
| 808 | static const struct of_device_id davinci_spi_of_match[] = { |
| 809 | { |
Manjunathappa, Prakash | 804413f | 2013-04-03 19:39:06 +0530 | [diff] [blame] | 810 | .compatible = "ti,dm6441-spi", |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 811 | }, |
| 812 | { |
Manjunathappa, Prakash | 804413f | 2013-04-03 19:39:06 +0530 | [diff] [blame] | 813 | .compatible = "ti,da830-spi", |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 814 | .data = (void *)SPI_VERSION_2, |
| 815 | }, |
| 816 | { }, |
| 817 | }; |
Manjunathappa, Prakash | 0d2d0cc | 2013-02-25 16:14:07 +0530 | [diff] [blame] | 818 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 819 | |
| 820 | /** |
| 821 | * spi_davinci_get_pdata - Get platform data from DTS binding |
| 822 | * @pdev: ptr to platform data |
| 823 | * @dspi: ptr to driver data |
| 824 | * |
| 825 | * Parses and populates pdata in dspi from device tree bindings. |
| 826 | * |
| 827 | * NOTE: Not all platform data params are supported currently. |
| 828 | */ |
| 829 | static int spi_davinci_get_pdata(struct platform_device *pdev, |
| 830 | struct davinci_spi *dspi) |
| 831 | { |
| 832 | struct device_node *node = pdev->dev.of_node; |
| 833 | struct davinci_spi_platform_data *pdata; |
| 834 | unsigned int num_cs, intr_line = 0; |
| 835 | const struct of_device_id *match; |
| 836 | |
| 837 | pdata = &dspi->pdata; |
| 838 | |
| 839 | pdata->version = SPI_VERSION_1; |
Axel Lin | b53b34f | 2014-02-06 11:45:08 +0800 | [diff] [blame] | 840 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 841 | if (!match) |
| 842 | return -ENODEV; |
| 843 | |
| 844 | /* match data has the SPI version number for SPI_VERSION_2 */ |
| 845 | if (match->data == (void *)SPI_VERSION_2) |
| 846 | pdata->version = SPI_VERSION_2; |
| 847 | |
| 848 | /* |
| 849 | * default num_cs is 1 and all chipsel are internal to the chip |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 850 | * indicated by chip_sel being NULL or cs_gpios being NULL or |
| 851 | * set to -ENOENT. num-cs includes internal as well as gpios. |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 852 | * indicated by chip_sel being NULL. GPIO based CS is not |
| 853 | * supported yet in DT bindings. |
| 854 | */ |
| 855 | num_cs = 1; |
| 856 | of_property_read_u32(node, "num-cs", &num_cs); |
| 857 | pdata->num_chipselect = num_cs; |
| 858 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); |
| 859 | pdata->intr_line = intr_line; |
| 860 | return 0; |
| 861 | } |
| 862 | #else |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 863 | static struct davinci_spi_platform_data |
| 864 | *spi_davinci_get_pdata(struct platform_device *pdev, |
| 865 | struct davinci_spi *dspi) |
| 866 | { |
| 867 | return -ENODEV; |
| 868 | } |
| 869 | #endif |
| 870 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 871 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 872 | * davinci_spi_probe - probe function for SPI Master Controller |
| 873 | * @pdev: platform_device structure which contains plateform specific data |
Brian Niebuhr | 035540f | 2010-10-06 18:32:40 +0530 | [diff] [blame] | 874 | * |
| 875 | * According to Linux Device Model this function will be invoked by Linux |
| 876 | * with platform_device struct which contains the device specific info. |
| 877 | * This function will map the SPI controller's memory, register IRQ, |
| 878 | * Reset SPI controller and setting its registers to default value. |
| 879 | * It will invoke spi_bitbang_start to create work queue so that client driver |
| 880 | * can register transfer method to work queue. |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 881 | */ |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 882 | static int davinci_spi_probe(struct platform_device *pdev) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 883 | { |
| 884 | struct spi_master *master; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 885 | struct davinci_spi *dspi; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 886 | struct davinci_spi_platform_data *pdata; |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 887 | struct resource *r; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 888 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; |
| 889 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; |
Grygorii Strashko | c060014 | 2014-08-01 19:40:33 +0300 | [diff] [blame] | 890 | int ret = 0; |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 891 | u32 spipc0; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 892 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 893 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
| 894 | if (master == NULL) { |
| 895 | ret = -ENOMEM; |
| 896 | goto err; |
| 897 | } |
| 898 | |
Jingoo Han | 24b5a82 | 2013-05-23 19:20:40 +0900 | [diff] [blame] | 899 | platform_set_drvdata(pdev, master); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 900 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 901 | dspi = spi_master_get_devdata(master); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 902 | |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 903 | if (dev_get_platdata(&pdev->dev)) { |
| 904 | pdata = dev_get_platdata(&pdev->dev); |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 905 | dspi->pdata = *pdata; |
| 906 | } else { |
| 907 | /* update dspi pdata with that from the DT */ |
| 908 | ret = spi_davinci_get_pdata(pdev, dspi); |
| 909 | if (ret < 0) |
| 910 | goto free_master; |
| 911 | } |
| 912 | |
| 913 | /* pdata in dspi is now updated and point pdata to that */ |
| 914 | pdata = &dspi->pdata; |
| 915 | |
Murali Karicheri | 7480e75 | 2014-07-31 20:33:14 +0300 | [diff] [blame] | 916 | dspi->bytes_per_word = devm_kzalloc(&pdev->dev, |
| 917 | sizeof(*dspi->bytes_per_word) * |
| 918 | pdata->num_chipselect, GFP_KERNEL); |
| 919 | if (dspi->bytes_per_word == NULL) { |
| 920 | ret = -ENOMEM; |
| 921 | goto free_master; |
| 922 | } |
| 923 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 924 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 925 | if (r == NULL) { |
| 926 | ret = -ENOENT; |
| 927 | goto free_master; |
| 928 | } |
| 929 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 930 | dspi->pbase = r->start; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 931 | |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 932 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
| 933 | if (IS_ERR(dspi->base)) { |
| 934 | ret = PTR_ERR(dspi->base); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 935 | goto free_master; |
| 936 | } |
| 937 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 938 | dspi->irq = platform_get_irq(pdev, 0); |
| 939 | if (dspi->irq <= 0) { |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 940 | ret = -EINVAL; |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 941 | goto free_master; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 942 | } |
| 943 | |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 944 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
| 945 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 946 | if (ret) |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 947 | goto free_master; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 948 | |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 949 | dspi->bitbang.master = master; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 950 | |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 951 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 952 | if (IS_ERR(dspi->clk)) { |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 953 | ret = -ENODEV; |
Jingoo Han | 5b3bb59 | 2013-12-09 19:12:03 +0900 | [diff] [blame] | 954 | goto free_master; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 955 | } |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 956 | clk_prepare_enable(dspi->clk); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 957 | |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 958 | master->dev.of_node = pdev->dev.of_node; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 959 | master->bus_num = pdev->id; |
| 960 | master->num_chipselect = pdata->num_chipselect; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 961 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 962 | master->setup = davinci_spi_setup; |
Murali Karicheri | a88e34e | 2014-08-01 19:40:32 +0300 | [diff] [blame] | 963 | master->cleanup = davinci_spi_cleanup; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 964 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 965 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
| 966 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 967 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 968 | dspi->version = pdata->version; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 969 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 970 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
| 971 | if (dspi->version == SPI_VERSION_2) |
| 972 | dspi->bitbang.flags |= SPI_READY; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 973 | |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 974 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 975 | if (r) |
| 976 | dma_rx_chan = r->start; |
| 977 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 978 | if (r) |
| 979 | dma_tx_chan = r->start; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 980 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 981 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 982 | if (dma_rx_chan != SPI_NO_RESOURCE && |
Michael Williamson | 2e3e2a5 | 2011-02-08 07:59:55 -0500 | [diff] [blame] | 983 | dma_tx_chan != SPI_NO_RESOURCE) { |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 984 | dspi->dma_rx_chnum = dma_rx_chan; |
| 985 | dspi->dma_tx_chnum = dma_tx_chan; |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 986 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 987 | ret = davinci_spi_request_dma(dspi); |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 988 | if (ret) |
| 989 | goto free_clk; |
| 990 | |
Brian Niebuhr | 87467bd | 2010-10-06 17:03:10 +0530 | [diff] [blame] | 991 | dev_info(&pdev->dev, "DMA: supported\n"); |
Jingoo Han | 859c337 | 2014-09-02 11:48:00 +0900 | [diff] [blame^] | 992 | dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n", |
| 993 | &dma_rx_chan, &dma_tx_chan, |
Michael Williamson | 2e3e2a5 | 2011-02-08 07:59:55 -0500 | [diff] [blame] | 994 | pdata->dma_event_q); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 995 | } |
| 996 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 997 | dspi->get_rx = davinci_spi_rx_buf_u8; |
| 998 | dspi->get_tx = davinci_spi_tx_buf_u8; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 999 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1000 | init_completion(&dspi->done); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1001 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1002 | /* Reset In/OUT SPI module */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1003 | iowrite32(0, dspi->base + SPIGCR0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1004 | udelay(100); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1005 | iowrite32(1, dspi->base + SPIGCR0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1006 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 1007 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 1008 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1009 | iowrite32(spipc0, dspi->base + SPIPC0); |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 1010 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1011 | if (pdata->intr_line) |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1012 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1013 | else |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1014 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1015 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1016 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
Brian Niebuhr | 843a713 | 2010-08-12 12:49:05 +0530 | [diff] [blame] | 1017 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1018 | /* master mode default */ |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1019 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
| 1020 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); |
| 1021 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1022 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1023 | ret = spi_bitbang_start(&dspi->bitbang); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1024 | if (ret) |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 1025 | goto free_dma; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1026 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1027 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1028 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1029 | return ret; |
| 1030 | |
Sekhar Nori | 903ca25 | 2010-10-01 14:51:40 +0530 | [diff] [blame] | 1031 | free_dma: |
Matt Porter | 048177c | 2012-08-22 21:09:36 -0400 | [diff] [blame] | 1032 | dma_release_channel(dspi->dma_rx); |
| 1033 | dma_release_channel(dspi->dma_tx); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1034 | free_clk: |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 1035 | clk_disable_unprepare(dspi->clk); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1036 | free_master: |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 1037 | spi_master_put(master); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1038 | err: |
| 1039 | return ret; |
| 1040 | } |
| 1041 | |
| 1042 | /** |
| 1043 | * davinci_spi_remove - remove function for SPI Master Controller |
| 1044 | * @pdev: platform_device structure which contains plateform specific data |
| 1045 | * |
| 1046 | * This function will do the reverse action of davinci_spi_probe function |
| 1047 | * It will free the IRQ and SPI controller's memory region. |
| 1048 | * It will also call spi_bitbang_stop to destroy the work queue which was |
| 1049 | * created by spi_bitbang_start. |
| 1050 | */ |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1051 | static int davinci_spi_remove(struct platform_device *pdev) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1052 | { |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1053 | struct davinci_spi *dspi; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1054 | struct spi_master *master; |
| 1055 | |
Jingoo Han | 24b5a82 | 2013-05-23 19:20:40 +0900 | [diff] [blame] | 1056 | master = platform_get_drvdata(pdev); |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1057 | dspi = spi_master_get_devdata(master); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1058 | |
Sekhar Nori | 212d4b6 | 2010-10-11 10:41:39 +0530 | [diff] [blame] | 1059 | spi_bitbang_stop(&dspi->bitbang); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1060 | |
Murali Karicheri | aae7147 | 2012-12-11 16:20:39 -0500 | [diff] [blame] | 1061 | clk_disable_unprepare(dspi->clk); |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 1062 | spi_master_put(master); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1063 | |
| 1064 | return 0; |
| 1065 | } |
| 1066 | |
| 1067 | static struct platform_driver davinci_spi_driver = { |
Brian Niebuhr | d8c174c | 2010-10-06 18:47:16 +0530 | [diff] [blame] | 1068 | .driver = { |
| 1069 | .name = "spi_davinci", |
| 1070 | .owner = THIS_MODULE, |
Axel Lin | b53b34f | 2014-02-06 11:45:08 +0800 | [diff] [blame] | 1071 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
Brian Niebuhr | d8c174c | 2010-10-06 18:47:16 +0530 | [diff] [blame] | 1072 | }, |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 1073 | .probe = davinci_spi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1074 | .remove = davinci_spi_remove, |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1075 | }; |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 1076 | module_platform_driver(davinci_spi_driver); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1077 | |
| 1078 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); |
| 1079 | MODULE_LICENSE("GPL"); |