blob: 86e44ad95ae0a5eff04f36c5b768fd8135e4eece [file] [log] [blame]
Clarence Ipaac9f332016-08-31 15:46:35 -04001/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040012
13#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
Clarence Ip4ce59322016-06-26 22:27:51 -040015#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040016#include <uapi/drm/sde_drm.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040017
18#include "msm_prop.h"
19
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070020#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040021#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040022#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040023#include "sde_hw_sspp.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040024#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070025#include "sde_crtc.h"
Lloyd Atkinson8772e202016-09-26 17:52:16 -040026#include "sde_vbif.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040027
Clarence Ip13a8cf42016-09-29 17:27:47 -040028#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
29 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
30
31#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
33
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040034#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
35#define PHASE_STEP_SHIFT 21
36#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
37#define PHASE_RESIDUAL 15
38
Clarence Ipe78efb72016-06-24 18:35:21 -040039#define SHARP_STRENGTH_DEFAULT 32
40#define SHARP_EDGE_THR_DEFAULT 112
41#define SHARP_SMOOTH_THR_DEFAULT 8
42#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040043
Clarence Ip5e2a9222016-06-26 22:38:24 -040044#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070045
Clarence Ipcae1bb62016-07-07 12:07:13 -040046#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
47
Clarence Ip282dad62016-09-27 17:07:35 -040048/* dirty bits for update function */
49#define SDE_PLANE_DIRTY_RECTS 0x1
50#define SDE_PLANE_DIRTY_FORMAT 0x2
51#define SDE_PLANE_DIRTY_SHARPEN 0x4
52#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
53
Alan Kwong1a00e4d2016-07-18 09:42:30 -040054/**
55 * enum sde_plane_qos - Different qos configurations for each pipe
56 *
57 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
58 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
59 * this configuration is mutually exclusive from VBLANK_CTRL.
60 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
61 */
62enum sde_plane_qos {
63 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
64 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
65 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
66};
67
Clarence Ip5fc00c52016-09-23 15:03:34 -040068/*
69 * struct sde_plane - local sde plane structure
70 * @csc_cfg: Decoded user configuration for csc
71 * @csc_usr_ptr: Points to csc_cfg if valid user config available
72 * @csc_ptr: Points to sde_csc_cfg structure to use for current
73 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070074struct sde_plane {
75 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040076
77 int mmu_id;
78
Clarence Ip730e7192016-06-26 22:45:09 -040079 struct mutex lock;
80
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040081 enum sde_sspp pipe;
82 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070083 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -040084 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040085
86 struct sde_hw_pipe *pipe_hw;
87 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -040088 struct sde_hw_sharp_cfg sharp_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -040089 struct sde_hw_scaler3_cfg scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040090 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -040091 uint32_t color_fill;
92 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040093 bool is_rt_pipe;
Clarence Ip4ce59322016-06-26 22:27:51 -040094
Clarence Ipb43d4592016-09-08 14:21:35 -040095 struct sde_hw_pixel_ext pixel_ext;
96 bool pixel_ext_usr;
97
Clarence Ip373f8592016-05-26 00:58:42 -040098 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -040099 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -0400100 struct sde_csc_cfg *csc_ptr;
101
Clarence Ip4c1d9772016-06-26 09:35:38 -0400102 const struct sde_sspp_sub_blks *pipe_sblk;
103
Clarence Ip5e2a9222016-06-26 22:38:24 -0400104 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400105
Clarence Ipaa0faf42016-05-30 12:07:48 -0400106 struct msm_property_info property_info;
107 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700108 struct drm_property_blob *blob_info;
Clarence Ip730e7192016-06-26 22:45:09 -0400109
Clarence Ip4ce59322016-06-26 22:27:51 -0400110 /* debugfs related stuff */
111 struct dentry *debugfs_root;
112 struct sde_debugfs_regset32 debugfs_src;
113 struct sde_debugfs_regset32 debugfs_scaler;
114 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700115};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700116
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700117#define to_sde_plane(x) container_of(x, struct sde_plane, base)
118
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400119static bool sde_plane_enabled(struct drm_plane_state *state)
120{
Clarence Ipdbde9832016-06-26 09:48:36 -0400121 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400122}
123
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400124/**
125 * _sde_plane_calc_fill_level - calculate fill level of the given source format
126 * @plane: Pointer to drm plane
127 * @fmt: Pointer to source buffer format
128 * @src_wdith: width of source buffer
129 * Return: fill level corresponding to the source buffer/format or 0 if error
130 */
131static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
132 const struct sde_format *fmt, u32 src_width)
133{
134 struct sde_plane *psde;
135 u32 fixed_buff_size;
136 u32 total_fl;
137
138 if (!plane || !fmt) {
139 SDE_ERROR("invalid arguments\n");
140 return 0;
141 }
142
143 psde = to_sde_plane(plane);
144 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
145
146 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
147 if (fmt->chroma_sample == SDE_CHROMA_420) {
148 /* NV12 */
149 total_fl = (fixed_buff_size / 2) /
150 ((src_width + 32) * fmt->bpp);
151 } else {
152 /* non NV12 */
153 total_fl = (fixed_buff_size) /
154 ((src_width + 32) * fmt->bpp);
155 }
156 } else {
157 total_fl = (fixed_buff_size * 2) /
158 ((src_width + 32) * fmt->bpp);
159 }
160
161 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
162 plane->base.id, psde->pipe - SSPP_VIG0,
163 fmt->base.pixel_format, src_width, total_fl);
164
165 return total_fl;
166}
167
168/**
169 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
170 * @total_fl: fill level
171 * Return: LUT setting corresponding to the fill level
172 */
173static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
174{
175 u32 qos_lut;
176
177 if (total_fl <= 4)
178 qos_lut = 0x1B;
179 else if (total_fl <= 5)
180 qos_lut = 0x5B;
181 else if (total_fl <= 6)
182 qos_lut = 0x15B;
183 else if (total_fl <= 7)
184 qos_lut = 0x55B;
185 else if (total_fl <= 8)
186 qos_lut = 0x155B;
187 else if (total_fl <= 9)
188 qos_lut = 0x555B;
189 else if (total_fl <= 10)
190 qos_lut = 0x1555B;
191 else if (total_fl <= 11)
192 qos_lut = 0x5555B;
193 else if (total_fl <= 12)
194 qos_lut = 0x15555B;
195 else
196 qos_lut = 0x55555B;
197
198 return qos_lut;
199}
200
201/**
202 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
203 * @total_fl: fill level
204 * Return: LUT setting corresponding to the fill level
205 */
206static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
207{
208 u32 qos_lut;
209
210 if (total_fl <= 10)
211 qos_lut = 0x1AAff;
212 else if (total_fl <= 11)
213 qos_lut = 0x5AAFF;
214 else if (total_fl <= 12)
215 qos_lut = 0x15AAFF;
216 else
217 qos_lut = 0x55AAFF;
218
219 return qos_lut;
220}
221
222/**
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400223 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
224 * @plane: Pointer to drm plane
225 * @fb: Pointer to framebuffer associated with the given plane
226 */
227static void _sde_plane_set_qos_lut(struct drm_plane *plane,
228 struct drm_framebuffer *fb)
229{
230 struct sde_plane *psde;
231 const struct sde_format *fmt = NULL;
232 u32 qos_lut;
233 u32 total_fl = 0;
234
235 if (!plane || !fb) {
236 SDE_ERROR("invalid arguments plane %d fb %d\n",
237 plane != 0, fb != 0);
238 return;
239 }
240
241 psde = to_sde_plane(plane);
242
243 if (!psde->pipe_hw || !psde->pipe_sblk) {
244 SDE_ERROR("invalid arguments\n");
245 return;
246 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
247 return;
248 }
249
250 if (!psde->is_rt_pipe) {
251 qos_lut = psde->pipe_sblk->creq_lut_nrt;
252 } else {
253 fmt = sde_get_sde_format_ext(
254 fb->pixel_format,
255 fb->modifier,
256 drm_format_num_planes(fb->pixel_format));
257 total_fl = _sde_plane_calc_fill_level(plane, fmt,
258 psde->pipe_cfg.src_rect.w);
259
260 if (SDE_FORMAT_IS_LINEAR(fmt))
261 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
262 else
263 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
264 }
265
266 psde->pipe_qos_cfg.creq_lut = qos_lut;
267
268 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
269 (fmt) ? fmt->base.pixel_format : 0,
270 psde->is_rt_pipe, total_fl, qos_lut,
271 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
272
273 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
274 plane->base.id,
275 psde->pipe - SSPP_VIG0,
276 (fmt) ? fmt->base.pixel_format : 0,
277 psde->is_rt_pipe, total_fl, qos_lut);
278
279 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
280}
281
282/**
283 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
284 * @plane: Pointer to drm plane
285 * @fb: Pointer to framebuffer associated with the given plane
286 */
287static void _sde_plane_set_danger_lut(struct drm_plane *plane,
288 struct drm_framebuffer *fb)
289{
290 struct sde_plane *psde;
291 const struct sde_format *fmt = NULL;
292 u32 danger_lut, safe_lut;
293
294 if (!plane || !fb) {
295 SDE_ERROR("invalid arguments\n");
296 return;
297 }
298
299 psde = to_sde_plane(plane);
300
301 if (!psde->pipe_hw || !psde->pipe_sblk) {
302 SDE_ERROR("invalid arguments\n");
303 return;
304 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
305 return;
306 }
307
308 if (!psde->is_rt_pipe) {
309 danger_lut = psde->pipe_sblk->danger_lut_nrt;
310 safe_lut = psde->pipe_sblk->safe_lut_nrt;
311 } else {
312 fmt = sde_get_sde_format_ext(
313 fb->pixel_format,
314 fb->modifier,
315 drm_format_num_planes(fb->pixel_format));
316
317 if (SDE_FORMAT_IS_LINEAR(fmt)) {
318 danger_lut = psde->pipe_sblk->danger_lut_linear;
319 safe_lut = psde->pipe_sblk->safe_lut_linear;
320 } else {
321 danger_lut = psde->pipe_sblk->danger_lut_tile;
322 safe_lut = psde->pipe_sblk->safe_lut_tile;
323 }
324 }
325
326 psde->pipe_qos_cfg.danger_lut = danger_lut;
327 psde->pipe_qos_cfg.safe_lut = safe_lut;
328
329 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
330 (fmt) ? fmt->base.pixel_format : 0,
331 (fmt) ? fmt->fetch_mode : 0,
332 psde->pipe_qos_cfg.danger_lut,
333 psde->pipe_qos_cfg.safe_lut);
334
335 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
336 plane->base.id,
337 psde->pipe - SSPP_VIG0,
338 fmt ? fmt->base.pixel_format : 0,
339 fmt ? fmt->fetch_mode : -1,
340 psde->pipe_qos_cfg.danger_lut,
341 psde->pipe_qos_cfg.safe_lut);
342
343 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
344 &psde->pipe_qos_cfg);
345}
346
347/**
348 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
349 * @plane: Pointer to drm plane
350 * @enable: true to enable QoS control
351 * @flags: QoS control mode (enum sde_plane_qos)
352 */
353static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
354 bool enable, u32 flags)
355{
356 struct sde_plane *psde;
357
358 if (!plane) {
359 SDE_ERROR("invalid arguments\n");
360 return;
361 }
362
363 psde = to_sde_plane(plane);
364
365 if (!psde->pipe_hw || !psde->pipe_sblk) {
366 SDE_ERROR("invalid arguments\n");
367 return;
368 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
369 return;
370 }
371
372 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
373 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
374 psde->pipe_qos_cfg.danger_vblank =
375 psde->pipe_sblk->danger_vblank;
376 psde->pipe_qos_cfg.vblank_en = enable;
377 }
378
379 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
380 /* this feature overrules previous VBLANK_CTRL */
381 psde->pipe_qos_cfg.vblank_en = false;
382 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
383 }
384
385 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
386 psde->pipe_qos_cfg.danger_safe_en = enable;
387
388 if (!psde->is_rt_pipe) {
389 psde->pipe_qos_cfg.vblank_en = false;
390 psde->pipe_qos_cfg.danger_safe_en = false;
391 }
392
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400393 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400394 plane->base.id,
395 psde->pipe - SSPP_VIG0,
396 psde->pipe_qos_cfg.danger_safe_en,
397 psde->pipe_qos_cfg.vblank_en,
398 psde->pipe_qos_cfg.creq_vblank,
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400399 psde->pipe_qos_cfg.danger_vblank,
400 psde->is_rt_pipe);
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400401
402 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
403 &psde->pipe_qos_cfg);
404}
405
Alan Kwong5d324e42016-07-28 22:56:18 -0400406/**
407 * _sde_plane_set_ot_limit - set OT limit for the given plane
408 * @plane: Pointer to drm plane
409 * @crtc: Pointer to drm crtc
410 */
411static void _sde_plane_set_ot_limit(struct drm_plane *plane,
412 struct drm_crtc *crtc)
413{
414 struct sde_plane *psde;
415 struct sde_vbif_set_ot_params ot_params;
416 struct msm_drm_private *priv;
417 struct sde_kms *sde_kms;
418
419 if (!plane || !plane->dev || !crtc) {
420 SDE_ERROR("invalid arguments plane %d crtc %d\n",
421 plane != 0, crtc != 0);
422 return;
423 }
424
425 priv = plane->dev->dev_private;
426 if (!priv || !priv->kms) {
427 SDE_ERROR("invalid KMS reference\n");
428 return;
429 }
430
431 sde_kms = to_sde_kms(priv->kms);
432 psde = to_sde_plane(plane);
433 if (!psde->pipe_hw) {
434 SDE_ERROR("invalid pipe reference\n");
435 return;
436 }
437
438 memset(&ot_params, 0, sizeof(ot_params));
439 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
440 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
441 ot_params.width = psde->pipe_cfg.src_rect.w;
442 ot_params.height = psde->pipe_cfg.src_rect.h;
443 ot_params.is_wfd = !psde->is_rt_pipe;
444 ot_params.frame_rate = crtc->mode.vrefresh;
445 ot_params.vbif_idx = VBIF_RT;
446 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
447 ot_params.rd = true;
448
449 sde_vbif_set_ot_limit(sde_kms, &ot_params);
450}
451
Clarence Ipcae1bb62016-07-07 12:07:13 -0400452/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400453static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400454 struct sde_plane_state *pstate, uint64_t fd)
455{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400456 if (!psde || !pstate) {
457 SDE_ERROR("invalid arg(s), plane %d state %d\n",
458 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400459 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400460 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400461
462 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400463 if (pstate->input_fence)
464 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400465
466 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400467 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400468
Clarence Ip13a8cf42016-09-29 17:27:47 -0400469 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400470}
471
Clarence Ipcae1bb62016-07-07 12:07:13 -0400472int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400473{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400474 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400475 struct sde_plane_state *pstate;
Clarence Ip78a04ed2016-10-04 15:57:45 -0400476 uint32_t prefix;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400477 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400478 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400479
480 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700481 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400482 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400483 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400484 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400485 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400486 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400487 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400488
Clarence Ipcae1bb62016-07-07 12:07:13 -0400489 if (input_fence) {
Clarence Ip78a04ed2016-10-04 15:57:45 -0400490 prefix = sde_sync_get_name_prefix(input_fence);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400491 ret = sde_sync_wait(input_fence, wait_ms);
Clarence Ip78a04ed2016-10-04 15:57:45 -0400492
493 MSM_EVT(plane->dev,
494 plane->base.id,
495 (uint64_t)-ret << (sizeof(uint32_t) * CHAR_BIT)
496 | prefix);
497
Clarence Ipcae1bb62016-07-07 12:07:13 -0400498 switch (ret) {
499 case 0:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400500 SDE_DEBUG_PLANE(psde, "signaled\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400501 break;
502 case -ETIME:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400503 SDE_ERROR_PLANE(psde, "%ums timeout on %08X\n",
504 wait_ms, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400505 psde->is_error = true;
506 break;
507 default:
Clarence Ip78a04ed2016-10-04 15:57:45 -0400508 SDE_ERROR_PLANE(psde, "error %d on %08X\n",
509 ret, prefix);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400510 psde->is_error = true;
511 break;
512 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400513 } else {
514 ret = 0;
515 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400516 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400517 return ret;
518}
519
Clarence Ip282dad62016-09-27 17:07:35 -0400520static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400521 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400522 struct sde_hw_pipe_cfg *pipe_cfg,
523 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400524{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400525 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400526 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400527
Clarence Ip13a8cf42016-09-29 17:27:47 -0400528 if (!plane || !pstate || !pipe_cfg || !fb) {
529 SDE_ERROR(
530 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
531 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400532 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400533 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400534
535 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400536 if (!psde->pipe_hw) {
537 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400538 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400539 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400540
Clarence Ipb6eb2362016-09-08 16:18:13 -0400541 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
542 if (ret == -EAGAIN)
543 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
544 else if (ret)
545 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
546 else if (psde->pipe_hw->ops.setup_sourceaddress)
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400547 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400548}
549
Clarence Ipcb410d42016-06-26 22:52:33 -0400550static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400551 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
552 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400553 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400554 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
555{
556}
557
Clarence Ipcb410d42016-06-26 22:52:33 -0400558/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400559 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400560 * @psde: Pointer to SDE plane object
561 * @src: Source size
562 * @dst: Destination size
563 * @phase_steps: Pointer to output array for phase steps
564 * @filter: Pointer to output array for filter type
565 * @fmt: Pointer to format definition
566 * @chroma_subsampling: Subsampling amount for chroma channel
567 *
568 * Returns: 0 on success
569 */
570static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400571 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400572 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400573 uint32_t chroma_subsampling)
574{
Clarence Ipcb410d42016-06-26 22:52:33 -0400575 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400576 SDE_ERROR(
577 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
578 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400579 return -EINVAL;
580 }
581
Clarence Ip4c1d9772016-06-26 09:35:38 -0400582 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400583 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400584 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400585 phase_steps[SDE_SSPP_COMP_1_2] =
586 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
587 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
588 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400589
590 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400591 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400592 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400593 (src <= dst) ? SDE_SCALE_FILTER_BIL :
594 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400595
Clarence Ipdbde9832016-06-26 09:48:36 -0400596 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400597 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400598 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
599 } else {
600 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
601 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400602 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400603 }
604 } else {
605 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400606 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
607 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
608 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400609 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400610 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400611}
612
Clarence Ipcb410d42016-06-26 22:52:33 -0400613/**
614 * _sde_plane_setup_pixel_ext - determine default pixel extension values
615 * @psde: Pointer to SDE plane object
616 * @src: Source size
617 * @dst: Destination size
618 * @decimated_src: Source size after decimation, if any
619 * @phase_steps: Pointer to output array for phase steps
620 * @out_src: Output array for pixel extension values
621 * @out_edge1: Output array for pixel extension first edge
622 * @out_edge2: Output array for pixel extension second edge
623 * @filter: Pointer to array for filter type
624 * @fmt: Pointer to format definition
625 * @chroma_subsampling: Subsampling amount for chroma channel
626 * @post_compare: Whether to chroma subsampled source size for comparisions
627 */
628static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400629 uint32_t src, uint32_t dst, uint32_t decimated_src,
630 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400631 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400632 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400633 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400634{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400635 int64_t edge1, edge2, caf;
636 uint32_t src_work;
637 int i, tmp;
638
Clarence Ipcb410d42016-06-26 22:52:33 -0400639 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400640 out_edge2 && filter && fmt) {
641 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400642 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400643 caf = PHASE_STEP_UNIT_SCALE;
644 else
645 caf = 0;
646
647 for (i = 0; i < SDE_MAX_PLANES; i++) {
648 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400649 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400650 src_work /= chroma_subsampling;
651 if (post_compare)
652 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400653 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400654 /* unity */
655 edge1 = 0;
656 edge2 = 0;
657 } else if (dst >= src) {
658 /* upscale */
659 edge1 = (1 << PHASE_RESIDUAL);
660 edge1 -= caf;
661 edge2 = (1 << PHASE_RESIDUAL);
662 edge2 += (dst - 1) * *(phase_steps + i);
663 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
664 edge2 += caf;
665 edge2 = -(edge2);
666 } else {
667 /* downscale */
668 edge1 = 0;
669 edge2 = (dst - 1) * *(phase_steps + i);
670 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
671 edge2 += *(phase_steps + i);
672 edge2 = -(edge2);
673 }
674
675 /* only enable CAF for luma plane */
676 caf = 0;
677
678 /* populate output arrays */
679 *(out_src + i) = src_work;
680
681 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400682 if (edge1 >= 0) {
683 tmp = (uint32_t)edge1;
684 tmp >>= PHASE_STEP_SHIFT;
685 *(out_edge1 + i) = -tmp;
686 } else {
687 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400688 *(out_edge1 + i) =
689 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
690 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400691 }
692 if (edge2 >= 0) {
693 tmp = (uint32_t)edge2;
694 tmp >>= PHASE_STEP_SHIFT;
695 *(out_edge2 + i) = -tmp;
696 } else {
697 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400698 *(out_edge2 + i) =
699 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
700 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400701 }
702 }
703 }
704}
705
Clarence Ip5fc00c52016-09-23 15:03:34 -0400706static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400707{
708 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
709 {
Clarence Ip373f8592016-05-26 00:58:42 -0400710 /* S15.16 format */
711 0x00012A00, 0x00000000, 0x00019880,
712 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
713 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400714 },
Clarence Ip373f8592016-05-26 00:58:42 -0400715 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400716 { 0xfff0, 0xff80, 0xff80,},
717 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400718 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400719 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400720 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400721 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400722
Clarence Ip5fc00c52016-09-23 15:03:34 -0400723 if (!psde) {
724 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400725 return;
726 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400727
Clarence Ipcae1bb62016-07-07 12:07:13 -0400728 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400729 if (psde->csc_usr_ptr)
730 psde->csc_ptr = psde->csc_usr_ptr;
731 else
Clarence Ip373f8592016-05-26 00:58:42 -0400732 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400733
Clarence Ip13a8cf42016-09-29 17:27:47 -0400734 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400735 psde->csc_ptr->csc_mv[0],
736 psde->csc_ptr->csc_mv[1],
737 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400738}
739
Clarence Ipcb410d42016-06-26 22:52:33 -0400740static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400741 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400742 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700743{
Clarence Ipb43d4592016-09-08 14:21:35 -0400744 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -0400745 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Clarence Ipb43d4592016-09-08 14:21:35 -0400746 uint32_t tmp, i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400747
Clarence Ipb43d4592016-09-08 14:21:35 -0400748 if (!psde || !fmt) {
749 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
750 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400751 return;
Clarence Ipb43d4592016-09-08 14:21:35 -0400752 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400753
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400754 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400755
Clarence Ipdedbba92016-09-27 17:43:10 -0400756 psde->pipe_cfg.horz_decimation =
757 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
758 psde->pipe_cfg.vert_decimation =
759 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400760
761 /* don't chroma subsample if decimating */
762 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400763 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400764 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400765 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400766
Clarence Ip5e2a9222016-06-26 22:38:24 -0400767 /* update scaler */
768 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400769 if (!psde->pixel_ext_usr) {
770 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -0400771 _sde_plane_setup_scaler3(psde,
772 psde->pipe_cfg.src_rect.w,
773 psde->pipe_cfg.src_rect.h,
774 psde->pipe_cfg.dst_rect.w,
775 psde->pipe_cfg.dst_rect.h,
776 &psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400777 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400778 }
Clarence Ipb43d4592016-09-08 14:21:35 -0400779 } else if (!psde->pixel_ext_usr) {
780 /* calculate default configuration for QSEED2 */
781 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400782
Clarence Ip13a8cf42016-09-29 17:27:47 -0400783 SDE_DEBUG_PLANE(psde, "default config\n");
Clarence Ipb43d4592016-09-08 14:21:35 -0400784 _sde_plane_setup_scaler2(psde,
785 psde->pipe_cfg.src_rect.w,
786 psde->pipe_cfg.dst_rect.w,
787 pe->phase_step_x,
788 pe->horz_filter, fmt, chroma_subsmpl_h);
789 _sde_plane_setup_scaler2(psde,
790 psde->pipe_cfg.src_rect.h,
791 psde->pipe_cfg.dst_rect.h,
792 pe->phase_step_y,
793 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400794
Clarence Ip5e2a9222016-06-26 22:38:24 -0400795 /* calculate left/right/top/bottom pixel extensions */
Clarence Ipcb410d42016-06-26 22:52:33 -0400796 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400797 psde->pipe_cfg.horz_decimation);
Clarence Ipdbde9832016-06-26 09:48:36 -0400798 if (SDE_FORMAT_IS_YUV(fmt))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400799 tmp &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400800 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
801 psde->pipe_cfg.dst_rect.w, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400802 pe->phase_step_x,
803 pe->roi_w,
804 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400805 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400806 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400807
Clarence Ipcb410d42016-06-26 22:52:33 -0400808 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400809 psde->pipe_cfg.vert_decimation);
Clarence Ipcb410d42016-06-26 22:52:33 -0400810 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
811 psde->pipe_cfg.dst_rect.h, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400812 pe->phase_step_y,
813 pe->roi_h,
814 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400815 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400816 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400817
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400818 for (i = 0; i < SDE_MAX_PLANES; i++) {
819 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400820 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400821 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400822 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400823
824 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400825 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400826 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400827 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400828
829 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400830 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400831 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400832 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400833
834 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400835 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400836 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400837 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400838 }
839 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400840}
841
Clarence Ipcae1bb62016-07-07 12:07:13 -0400842/**
843 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -0400844 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -0400845 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
846 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
847 * Returns: 0 on success
848 */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400849static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -0400850 uint32_t color, uint32_t alpha)
851{
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400852 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400853
Clarence Ip13a8cf42016-09-29 17:27:47 -0400854 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700855 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400856 return -EINVAL;
857 }
858
Clarence Ipcb410d42016-06-26 22:52:33 -0400859 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400860 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400861 return -EINVAL;
862 }
863
Clarence Ip13a8cf42016-09-29 17:27:47 -0400864 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400865
Clarence Ipcb410d42016-06-26 22:52:33 -0400866 /*
867 * select fill format to match user property expectation,
868 * h/w only supports RGB variants
869 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400870 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400871
872 /* update sspp */
873 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
874 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
875 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
876
877 /* override scaler/decimation if solid fill */
878 psde->pipe_cfg.src_rect.x = 0;
879 psde->pipe_cfg.src_rect.y = 0;
880 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
881 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
882
883 _sde_plane_setup_scaler(psde, fmt, 0);
884
885 if (psde->pipe_hw->ops.setup_format)
886 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
887 fmt, SDE_SSPP_SOLID_FILL);
888
889 if (psde->pipe_hw->ops.setup_rects)
890 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
891 &psde->pipe_cfg, &psde->pixel_ext);
892 }
893
894 return 0;
895}
896
897static int _sde_plane_mode_set(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -0700898 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -0400899{
Clarence Ipc47a0692016-10-11 10:54:17 -0400900 uint32_t nplanes, src_flags;
Clarence Ipcb410d42016-06-26 22:52:33 -0400901 struct sde_plane *psde;
902 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400903 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -0700904 struct drm_crtc *crtc;
905 struct drm_framebuffer *fb;
906 struct sde_rect src, dst;
907 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -0400908 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -0400909
Clarence Ip13a8cf42016-09-29 17:27:47 -0400910 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -0400911 SDE_ERROR("invalid plane\n");
912 return -EINVAL;
913 } else if (!plane->state) {
914 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400915 return -EINVAL;
916 }
917
918 psde = to_sde_plane(plane);
919 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -0400920
Dhaval Patel47302cf2016-08-18 15:04:28 -0700921 crtc = state->crtc;
922 fb = state->fb;
923 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400924 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
925 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -0700926 return -EINVAL;
927 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400928 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400929 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -0400930
Clarence Ip282dad62016-09-27 17:07:35 -0400931 /* determine what needs to be refreshed */
932 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
933 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400934 case PLANE_PROP_SCALER_V1:
Clarence Ipdedbba92016-09-27 17:43:10 -0400935 case PLANE_PROP_H_DECIMATE:
936 case PLANE_PROP_V_DECIMATE:
937 case PLANE_PROP_SRC_CONFIG:
938 case PLANE_PROP_ZPOS:
Clarence Ip282dad62016-09-27 17:07:35 -0400939 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
940 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400941 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -0400942 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
943 break;
944 case PLANE_PROP_COLOR_FILL:
945 /* potentially need to refresh everything */
946 pstate->dirty = SDE_PLANE_DIRTY_ALL;
947 break;
948 case PLANE_PROP_ROTATION:
949 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
950 break;
Clarence Ip282dad62016-09-27 17:07:35 -0400951 case PLANE_PROP_INFO:
952 case PLANE_PROP_ALPHA:
953 case PLANE_PROP_INPUT_FENCE:
954 case PLANE_PROP_BLEND_OP:
955 /* no special action required */
956 break;
957 default:
958 /* unknown property, refresh everything */
959 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
960 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
961 break;
962 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400963 }
964
Clarence Ip282dad62016-09-27 17:07:35 -0400965 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
966 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -0400967
968 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
969
Clarence Ip282dad62016-09-27 17:07:35 -0400970 /* early out if nothing dirty */
971 if (!pstate->dirty)
972 return 0;
973 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400974
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400975 psde->is_rt_pipe = sde_crtc_is_rt(crtc);
Clarence Ip282dad62016-09-27 17:07:35 -0400976 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
977
978 /* update roi config */
979 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
980 POPULATE_RECT(&src, state->src_x, state->src_y,
981 state->src_w, state->src_h, q16_data);
982 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
983 state->crtc_w, state->crtc_h, !q16_data);
984
Clarence Ip13a8cf42016-09-29 17:27:47 -0400985 SDE_DEBUG_PLANE(psde,
986 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -0400987 fb->base.id, src.x, src.y, src.w, src.h,
988 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
989 drm_get_format_name(fmt->base.pixel_format),
990 SDE_FORMAT_IS_UBWC(fmt));
991
992 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
993 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400994 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -0400995 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
996 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
997 src.h /= 2;
998 src.y = DIV_ROUND_UP(src.y, 2);
999 src.y &= ~0x1;
1000 }
1001
1002 psde->pipe_cfg.src_rect = src;
1003 psde->pipe_cfg.dst_rect = dst;
1004
1005 /* check for color fill */
1006 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
1007 PLANE_PROP_COLOR_FILL);
1008 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
1009 /* skip remaining processing on color fill */
1010 pstate->dirty = 0x0;
1011 } else if (psde->pipe_hw->ops.setup_rects) {
1012 _sde_plane_setup_scaler(psde, fmt, pstate);
1013
Clarence Ip282dad62016-09-27 17:07:35 -04001014 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
1015 &psde->pipe_cfg, &psde->pixel_ext);
1016 }
Dhaval Patel48c76022016-09-01 17:51:23 -07001017 }
1018
Clarence Ip282dad62016-09-27 17:07:35 -04001019 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
1020 psde->pipe_hw->ops.setup_format) {
1021 src_flags = 0x0;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001022 SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001023 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
1024 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1025 BIT(DRM_REFLECT_X))
1026 src_flags |= SDE_SSPP_FLIP_LR;
1027 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1028 BIT(DRM_REFLECT_Y))
1029 src_flags |= SDE_SSPP_FLIP_UD;
1030
1031 /* update format */
1032 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags);
1033
1034 /* update csc */
1035 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04001036 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04001037 else
1038 psde->csc_ptr = 0;
1039 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001040
Clarence Ipe78efb72016-06-24 18:35:21 -04001041 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04001042 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
1043 psde->pipe_hw->ops.setup_sharpening) {
1044 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
1045 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
1046 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
1047 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04001048
Clarence Ipe78efb72016-06-24 18:35:21 -04001049 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04001050 &psde->sharp_cfg);
1051 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001052
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001053 _sde_plane_set_qos_lut(plane, fb);
1054 _sde_plane_set_danger_lut(plane, fb);
1055
Alan Kwong5d324e42016-07-28 22:56:18 -04001056 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001057 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04001058 _sde_plane_set_ot_limit(plane, crtc);
1059 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001060
Clarence Ip282dad62016-09-27 17:07:35 -04001061 /* clear dirty */
1062 pstate->dirty = 0x0;
1063
Clarence Ip5e2a9222016-06-26 22:38:24 -04001064 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001065}
1066
1067static int sde_plane_prepare_fb(struct drm_plane *plane,
1068 const struct drm_plane_state *new_state)
1069{
1070 struct drm_framebuffer *fb = new_state->fb;
1071 struct sde_plane *psde = to_sde_plane(plane);
1072
1073 if (!new_state->fb)
1074 return 0;
1075
Clarence Ip13a8cf42016-09-29 17:27:47 -04001076 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001077 return msm_framebuffer_prepare(fb, psde->mmu_id);
1078}
1079
1080static void sde_plane_cleanup_fb(struct drm_plane *plane,
1081 const struct drm_plane_state *old_state)
1082{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001083 struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
1084 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001085
1086 if (!fb)
1087 return;
1088
Clarence Ip13a8cf42016-09-29 17:27:47 -04001089 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001090 msm_framebuffer_cleanup(fb, psde->mmu_id);
1091}
1092
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001093static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
1094 struct drm_plane_state *state,
1095 struct drm_plane_state *old_state)
1096{
1097 struct sde_plane_state *pstate = to_sde_plane_state(state);
1098
Dhaval Patel47302cf2016-08-18 15:04:28 -07001099 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04001100 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001101 return;
1102
Clarence Ip282dad62016-09-27 17:07:35 -04001103 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
1104 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001105 SDE_DEBUG_PLANE(psde,
1106 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001107 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001108 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001109 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001110 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001111 } else if (state->src_w != old_state->src_w ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07001112 state->src_h != old_state->src_h ||
1113 state->src_x != old_state->src_x ||
1114 state->src_y != old_state->src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001115 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001116 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001117 } else if (state->crtc_w != old_state->crtc_w ||
1118 state->crtc_h != old_state->crtc_h ||
1119 state->crtc_x != old_state->crtc_x ||
1120 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001121 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001122 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1123 }
1124
1125 if (!state->fb || !old_state->fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001126 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001127 } else if (state->fb->pixel_format != old_state->fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001128 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001129 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001130 } else {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001131 uint64_t *new_mods = state->fb->modifier;
1132 uint64_t *old_mods = old_state->fb->modifier;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001133 uint32_t *new_pitches = state->fb->pitches;
1134 uint32_t *old_pitches = old_state->fb->pitches;
1135 uint32_t *new_offset = state->fb->offsets;
1136 uint32_t *old_offset = old_state->fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001137 int i;
1138
1139 for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
1140 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001141 SDE_DEBUG_PLANE(psde,
1142 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001143 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001144 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001145 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1146 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001147 break;
1148 }
1149 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001150 for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
1151 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001152 SDE_DEBUG_PLANE(psde,
1153 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001154 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001155 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001156 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001157 break;
1158 }
1159 }
Dhaval Patel47302cf2016-08-18 15:04:28 -07001160 for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
1161 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001162 SDE_DEBUG_PLANE(psde,
1163 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001164 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001165 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001166 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1167 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001168 break;
1169 }
1170 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001171 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001172}
1173
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001174static int sde_plane_atomic_check(struct drm_plane *plane,
1175 struct drm_plane_state *state)
1176{
Clarence Ipdedbba92016-09-27 17:43:10 -04001177 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04001178 struct sde_plane *psde;
1179 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001180 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001181 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04001182 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001183 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
1184 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04001185
1186 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001187 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1188 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04001189 ret = -EINVAL;
1190 goto exit;
1191 }
1192
1193 psde = to_sde_plane(plane);
1194 pstate = to_sde_plane_state(state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001195
1196 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001197 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001198 ret = -EINVAL;
1199 goto exit;
1200 }
1201
Clarence Ipdedbba92016-09-27 17:43:10 -04001202 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1203 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04001204
1205 /* src values are in Q16 fixed point, convert to integer */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001206 POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
1207 state->src_h, q16_data);
1208 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
1209 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04001210
Dhaval Patel47302cf2016-08-18 15:04:28 -07001211 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
1212 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04001213
Dhaval Patel47302cf2016-08-18 15:04:28 -07001214 max_upscale = psde->pipe_sblk->maxupscale;
1215 max_downscale = psde->pipe_sblk->maxdwnscale;
1216 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04001217
Clarence Ip13a8cf42016-09-29 17:27:47 -04001218 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001219 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001220
Dhaval Patel47302cf2016-08-18 15:04:28 -07001221 if (!sde_plane_enabled(state))
1222 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04001223
Dhaval Patel47302cf2016-08-18 15:04:28 -07001224 fmt = to_sde_format(msm_framebuffer_format(state->fb));
1225
1226 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
1227
1228 if (SDE_FORMAT_IS_YUV(fmt) &&
1229 (!(psde->features & SDE_SSPP_SCALER) ||
1230 !(psde->features & BIT(SDE_SSPP_CSC)))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001231 SDE_ERROR_PLANE(psde,
1232 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07001233 ret = -EINVAL;
1234
1235 /* check src bounds */
1236 } else if (state->fb->width > MAX_IMG_WIDTH ||
1237 state->fb->height > MAX_IMG_HEIGHT ||
1238 src.w < min_src_size || src.h < min_src_size ||
1239 CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
1240 CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001241 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001242 src.x, src.y, src.w, src.h);
1243 ret = -E2BIG;
1244
1245 /* valid yuv image */
1246 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
1247 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001248 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001249 src.x, src.y, src.w, src.h);
1250 ret = -EINVAL;
1251
1252 /* min dst support */
1253 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001254 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001255 dst.x, dst.y, dst.w, dst.h);
1256 ret = -EINVAL;
1257
1258 /* decimation validation */
1259 } else if (deci_w || deci_h) {
1260 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
1261 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001262 SDE_ERROR_PLANE(psde,
1263 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001264 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001265 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001266 SDE_ERROR_PLANE(psde,
1267 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001268 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001269 }
1270
Dhaval Patel47302cf2016-08-18 15:04:28 -07001271 } else if (!(psde->features & SDE_SSPP_SCALER) &&
1272 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001273 SDE_ERROR_PLANE(psde,
1274 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001275 src.w, src.h, dst.w, dst.h);
1276 ret = -EINVAL;
1277
1278 /* check decimated source width */
1279 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001280 SDE_ERROR_PLANE(psde,
1281 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001282 src.w, src_deci_w, max_linewidth);
1283 ret = -E2BIG;
1284
1285 /* check max scaler capability */
1286 } else if (((src_deci_w * max_upscale) < dst.w) ||
1287 ((src_deci_h * max_upscale) < dst.h) ||
1288 ((dst.w * max_downscale) < src_deci_w) ||
1289 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001290 SDE_ERROR_PLANE(psde,
1291 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001292 src_deci_w, src_deci_h, dst.w, dst.h);
1293 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001294 }
1295
Dhaval Patel47302cf2016-08-18 15:04:28 -07001296modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001297 if (!ret)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001298 _sde_plane_atomic_check_mode_changed(psde, state, plane->state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001299exit:
1300 return ret;
1301}
1302
Clarence Ipcae1bb62016-07-07 12:07:13 -04001303/**
1304 * sde_plane_flush - final plane operations before commit flush
1305 * @plane: Pointer to drm plane structure
1306 */
1307void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04001308{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001309 struct sde_plane *psde;
1310
Clarence Ip13a8cf42016-09-29 17:27:47 -04001311 if (!plane) {
1312 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001313 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001314 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04001315
1316 psde = to_sde_plane(plane);
1317
1318 /*
1319 * These updates have to be done immediately before the plane flush
1320 * timing, and may not be moved to the atomic_update/mode_set functions.
1321 */
1322 if (psde->is_error)
1323 /* force white frame with 0% alpha pipe output on error */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001324 _sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001325 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
1326 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001327 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001328 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
1329 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
1330
1331 /* flag h/w flush complete */
1332 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04001333 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001334}
1335
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001336static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001337 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001338{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001339 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001340 struct drm_plane_state *state;
1341 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001342
Clarence Ip13a8cf42016-09-29 17:27:47 -04001343 if (!plane) {
1344 SDE_ERROR("invalid plane\n");
1345 return;
1346 } else if (!plane->state) {
1347 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001348 return;
1349 }
1350
Clarence Ip13a8cf42016-09-29 17:27:47 -04001351 psde = to_sde_plane(plane);
1352 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001353 state = plane->state;
1354 pstate = to_sde_plane_state(state);
1355
Clarence Ip13a8cf42016-09-29 17:27:47 -04001356 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001357
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001358 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001359 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001360 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001361 int ret;
1362
Dhaval Patel47302cf2016-08-18 15:04:28 -07001363 ret = _sde_plane_mode_set(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001364 /* atomic_check should have ensured that this doesn't fail */
1365 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001366 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001367}
1368
Dhaval Patel47302cf2016-08-18 15:04:28 -07001369
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001370/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001371static void _sde_plane_install_properties(struct drm_plane *plane,
Clarence Ipc47a0692016-10-11 10:54:17 -04001372 struct sde_mdss_cfg *catalog)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001373{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001374 static const struct drm_prop_enum_list e_blend_op[] = {
1375 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1376 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1377 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1378 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1379 };
1380 static const struct drm_prop_enum_list e_src_config[] = {
1381 {SDE_DRM_DEINTERLACE, "deinterlace"}
1382 };
Clarence Ipea3d6262016-07-15 16:20:11 -04001383 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07001384 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001385 struct sde_plane *psde = to_sde_plane(plane);
Clarence Ipc47a0692016-10-11 10:54:17 -04001386 int zpos_max = 255;
1387 int zpos_def = 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001388
Clarence Ip13a8cf42016-09-29 17:27:47 -04001389 if (!plane || !psde) {
1390 SDE_ERROR("invalid plane\n");
1391 return;
1392 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
1393 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
1394 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001395 return;
Clarence Ipc47a0692016-10-11 10:54:17 -04001396 } else if (!catalog) {
1397 SDE_ERROR("invalid catalog\n");
1398 return;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001399 }
1400
Clarence Ipc47a0692016-10-11 10:54:17 -04001401 if (sde_is_custom_client()) {
1402 if (catalog->mixer_count && catalog->mixer)
1403 zpos_max = catalog->mixer[0].sblk->maxblendstages;
1404 } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
1405 /* reserve zpos == 0 for primary planes */
1406 zpos_def = drm_plane_index(plane) + 1;
1407 }
1408
1409 msm_property_install_range(&psde->property_info, "zpos",
1410 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001411
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001412 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001413 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001414
Dhaval Patel47302cf2016-08-18 15:04:28 -07001415 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001416 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07001417 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001418
Clarence Ipdedbba92016-09-27 17:43:10 -04001419 if (psde->pipe_sblk->maxhdeciexp) {
1420 msm_property_install_range(&psde->property_info, "h_decimate",
1421 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0,
1422 PLANE_PROP_H_DECIMATE);
1423 }
1424
1425 if (psde->pipe_sblk->maxvdeciexp) {
1426 msm_property_install_range(&psde->property_info, "v_decimate",
1427 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0,
1428 PLANE_PROP_V_DECIMATE);
1429 }
1430
Clarence Ipb43d4592016-09-08 14:21:35 -04001431 if (psde->features & SDE_SSPP_SCALER) {
1432 msm_property_install_volatile_range(&psde->property_info,
1433 "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
1434 }
1435
Clarence Ip5fc00c52016-09-23 15:03:34 -04001436 if (psde->features & BIT(SDE_SSPP_CSC)) {
1437 msm_property_install_volatile_range(&psde->property_info,
1438 "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1);
1439 }
1440
Clarence Ip5e2a9222016-06-26 22:38:24 -04001441 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001442 msm_property_install_rotation(&psde->property_info,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001443 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001444
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001445 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001446 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001447
Dhaval Patel47302cf2016-08-18 15:04:28 -07001448 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
1449 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
1450
1451 if (psde->pipe_hw->ops.setup_solidfill)
1452 msm_property_install_range(&psde->property_info, "color_fill",
1453 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
1454
Dhaval Patel4e574842016-08-23 15:11:37 -07001455 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001456 if (!info) {
1457 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07001458 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001459 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001460
1461 msm_property_install_blob(&psde->property_info, "capabilities",
1462 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
1463 sde_kms_info_reset(info);
1464
Clarence Ipea3d6262016-07-15 16:20:11 -04001465 format_list = psde->pipe_sblk->format_list;
1466 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04001467 sde_kms_info_start(info, "pixel_formats");
1468 while (format_list->fourcc_format) {
1469 sde_kms_info_append_format(info,
1470 format_list->fourcc_format,
1471 format_list->modifier);
1472 ++format_list;
1473 }
1474 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04001475 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001476
1477 sde_kms_info_add_keyint(info, "max_linewidth",
1478 psde->pipe_sblk->maxlinewidth);
1479 sde_kms_info_add_keyint(info, "max_upscale",
1480 psde->pipe_sblk->maxupscale);
1481 sde_kms_info_add_keyint(info, "max_downscale",
1482 psde->pipe_sblk->maxdwnscale);
1483 sde_kms_info_add_keyint(info, "max_horizontal_deci",
1484 psde->pipe_sblk->maxhdeciexp);
1485 sde_kms_info_add_keyint(info, "max_vertical_deci",
1486 psde->pipe_sblk->maxvdeciexp);
1487 msm_property_set_blob(&psde->property_info, &psde->blob_info,
1488 info->data, info->len, PLANE_PROP_INFO);
1489
1490 kfree(info);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001491}
1492
Clarence Ip5fc00c52016-09-23 15:03:34 -04001493static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
1494{
1495 struct sde_drm_csc_v1 csc_v1;
1496 int i;
1497
1498 if (!psde) {
1499 SDE_ERROR("invalid plane\n");
1500 return;
1501 }
1502
1503 psde->csc_usr_ptr = NULL;
1504 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001505 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001506 return;
1507 }
1508
1509 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001510 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001511 return;
1512 }
1513
Clarence Ipb43d4592016-09-08 14:21:35 -04001514 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04001515 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
1516 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
1517 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
1518 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
1519 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
1520 }
1521 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
1522 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
1523 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
1524 }
1525 psde->csc_usr_ptr = &psde->csc_cfg;
1526}
1527
Clarence Ipb43d4592016-09-08 14:21:35 -04001528static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
1529{
1530 struct sde_drm_scaler_v1 scale_v1;
1531 struct sde_hw_pixel_ext *pe;
1532 int i;
1533
1534 if (!psde) {
1535 SDE_ERROR("invalid plane\n");
1536 return;
1537 }
1538
1539 psde->pixel_ext_usr = false;
1540 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001541 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001542 return;
1543 }
1544
1545 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001546 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001547 return;
1548 }
1549
1550 /* populate from user space */
1551 pe = &(psde->pixel_ext);
1552 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1553 for (i = 0; i < SDE_MAX_PLANES; i++) {
1554 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
1555 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
1556 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
1557 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
1558
1559 pe->horz_filter[i] = scale_v1.horz_filter[i];
1560 pe->vert_filter[i] = scale_v1.vert_filter[i];
1561 }
1562 for (i = 0; i < SDE_MAX_PLANES; i++) {
1563 pe->num_ext_pxls_left[i] = scale_v1.lr.num_pxls_start[i];
1564 pe->num_ext_pxls_right[i] = scale_v1.lr.num_pxls_end[i];
1565 pe->left_ftch[i] = scale_v1.lr.ftch_start[i];
1566 pe->right_ftch[i] = scale_v1.lr.ftch_end[i];
1567 pe->left_rpt[i] = scale_v1.lr.rpt_start[i];
1568 pe->right_rpt[i] = scale_v1.lr.rpt_end[i];
1569 pe->roi_w[i] = scale_v1.lr.roi[i];
1570
1571 pe->num_ext_pxls_top[i] = scale_v1.tb.num_pxls_start[i];
1572 pe->num_ext_pxls_btm[i] = scale_v1.tb.num_pxls_end[i];
1573 pe->top_ftch[i] = scale_v1.tb.ftch_start[i];
1574 pe->btm_ftch[i] = scale_v1.tb.ftch_end[i];
1575 pe->top_rpt[i] = scale_v1.tb.rpt_start[i];
1576 pe->btm_rpt[i] = scale_v1.tb.rpt_end[i];
1577 pe->roi_h[i] = scale_v1.tb.roi[i];
1578 }
1579 psde->pixel_ext_usr = true;
1580
Clarence Ip13a8cf42016-09-29 17:27:47 -04001581 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001582}
1583
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001584static int sde_plane_atomic_set_property(struct drm_plane *plane,
1585 struct drm_plane_state *state, struct drm_property *property,
1586 uint64_t val)
1587{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001588 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001589 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001590 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001591
Clarence Ip13a8cf42016-09-29 17:27:47 -04001592 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001593
1594 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001595 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001596 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001597 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001598 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001599 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001600 ret = msm_property_atomic_set(&psde->property_info,
1601 pstate->property_values, pstate->property_blobs,
1602 property, val);
1603 if (!ret) {
1604 idx = msm_property_index(&psde->property_info,
1605 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001606 switch (idx) {
1607 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04001608 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001609 break;
1610 case PLANE_PROP_CSC_V1:
1611 _sde_plane_set_csc_v1(psde, (void *)val);
1612 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04001613 case PLANE_PROP_SCALER_V1:
1614 _sde_plane_set_scaler_v1(psde, (void *)val);
1615 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001616 default:
1617 /* nothing to do */
1618 break;
1619 }
Clarence Ipe78efb72016-06-24 18:35:21 -04001620 }
1621 }
1622
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001623 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001624}
1625
1626static int sde_plane_set_property(struct drm_plane *plane,
1627 struct drm_property *property, uint64_t val)
1628{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001629 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001630
Clarence Ipae4e60c2016-06-26 22:44:04 -04001631 return sde_plane_atomic_set_property(plane,
1632 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001633}
1634
1635static int sde_plane_atomic_get_property(struct drm_plane *plane,
1636 const struct drm_plane_state *state,
1637 struct drm_property *property, uint64_t *val)
1638{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001639 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001640 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001641 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001642
Clarence Ipaa0faf42016-05-30 12:07:48 -04001643 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001644 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001645 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001646 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001647 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001648 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001649 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001650 ret = msm_property_atomic_get(&psde->property_info,
1651 pstate->property_values, pstate->property_blobs,
1652 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001653 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001654
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001655 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001656}
1657
1658static void sde_plane_destroy(struct drm_plane *plane)
1659{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001660 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001661
Clarence Ip13a8cf42016-09-29 17:27:47 -04001662 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001663
Clarence Ip13a8cf42016-09-29 17:27:47 -04001664 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001665 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1666
Clarence Ip4ce59322016-06-26 22:27:51 -04001667 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001668
Dhaval Patel4e574842016-08-23 15:11:37 -07001669 if (psde->blob_info)
1670 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001671 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001672 mutex_destroy(&psde->lock);
1673
Clarence Ip4ce59322016-06-26 22:27:51 -04001674 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001675
Clarence Ip4ce59322016-06-26 22:27:51 -04001676 /* this will destroy the states as well */
1677 drm_plane_cleanup(plane);
1678
Clarence Ip4c1d9772016-06-26 09:35:38 -04001679 if (psde->pipe_hw)
1680 sde_hw_sspp_destroy(psde->pipe_hw);
1681
Clarence Ip4ce59322016-06-26 22:27:51 -04001682 kfree(psde);
1683 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001684}
1685
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001686static void sde_plane_destroy_state(struct drm_plane *plane,
1687 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001688{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001689 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001690 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001691
Clarence Ipae4e60c2016-06-26 22:44:04 -04001692 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001693 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1694 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001695 return;
1696 }
1697
Clarence Ipaa0faf42016-05-30 12:07:48 -04001698 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001699 pstate = to_sde_plane_state(state);
1700
Clarence Ip13a8cf42016-09-29 17:27:47 -04001701 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001702
Clarence Ipe78efb72016-06-24 18:35:21 -04001703 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001704 if (state->fb)
1705 drm_framebuffer_unreference(state->fb);
1706
Clarence Ipae4e60c2016-06-26 22:44:04 -04001707 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001708 if (pstate->input_fence)
1709 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001710
Clarence Ipaa0faf42016-05-30 12:07:48 -04001711 /* destroy value helper */
1712 msm_property_destroy_state(&psde->property_info, pstate,
1713 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001714}
1715
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001716static struct drm_plane_state *
1717sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001718{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001719 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001720 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001721 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04001722 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001723
Clarence Ip13a8cf42016-09-29 17:27:47 -04001724 if (!plane) {
1725 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001726 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001727 } else if (!plane->state) {
1728 SDE_ERROR("invalid plane state\n");
1729 return NULL;
1730 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001731
Clarence Ip730e7192016-06-26 22:45:09 -04001732 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001733 psde = to_sde_plane(plane);
1734 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001735 if (!pstate) {
1736 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001737 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001738 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001739
Clarence Ip13a8cf42016-09-29 17:27:47 -04001740 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001741
1742 /* duplicate value helper */
1743 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
1744 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001745
Clarence Ip730e7192016-06-26 22:45:09 -04001746 /* add ref count for frame buffer */
1747 if (pstate->base.fb)
1748 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001749
Clarence Ip17e908b2016-09-29 15:58:00 -04001750 /* clear out any input fence */
1751 pstate->input_fence = 0;
1752 input_fence_default = msm_property_get_default(
1753 &psde->property_info, PLANE_PROP_INPUT_FENCE);
1754 msm_property_set_property(&psde->property_info, pstate->property_values,
1755 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001756
Clarence Ip282dad62016-09-27 17:07:35 -04001757 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04001758 pstate->pending = false;
1759
1760 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001761}
1762
1763static void sde_plane_reset(struct drm_plane *plane)
1764{
Clarence Ipae4e60c2016-06-26 22:44:04 -04001765 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001766 struct sde_plane_state *pstate;
1767
Clarence Ipae4e60c2016-06-26 22:44:04 -04001768 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001769 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001770 return;
1771 }
1772
Clarence Ip730e7192016-06-26 22:45:09 -04001773 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001774 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001775
Clarence Ipae4e60c2016-06-26 22:44:04 -04001776 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001777 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04001778 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001779 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04001780 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001781
Clarence Ipaa0faf42016-05-30 12:07:48 -04001782 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001783 if (!pstate) {
1784 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001785 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001786 }
Clarence Ip730e7192016-06-26 22:45:09 -04001787
Clarence Ipaa0faf42016-05-30 12:07:48 -04001788 /* reset value helper */
1789 msm_property_reset_state(&psde->property_info, pstate,
1790 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001791
1792 pstate->base.plane = plane;
1793
1794 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001795}
1796
1797static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001798 .update_plane = drm_atomic_helper_update_plane,
1799 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001800 .destroy = sde_plane_destroy,
1801 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001802 .atomic_set_property = sde_plane_atomic_set_property,
1803 .atomic_get_property = sde_plane_atomic_get_property,
1804 .reset = sde_plane_reset,
1805 .atomic_duplicate_state = sde_plane_duplicate_state,
1806 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001807};
1808
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001809static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
1810 .prepare_fb = sde_plane_prepare_fb,
1811 .cleanup_fb = sde_plane_cleanup_fb,
1812 .atomic_check = sde_plane_atomic_check,
1813 .atomic_update = sde_plane_atomic_update,
1814};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001815
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001816enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001817{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001818 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001819}
1820
Clarence Ip4ce59322016-06-26 22:27:51 -04001821static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
1822{
1823 const struct sde_sspp_sub_blks *sblk = 0;
1824 const struct sde_sspp_cfg *cfg = 0;
1825
1826 if (psde && psde->pipe_hw)
1827 cfg = psde->pipe_hw->cap;
1828 if (cfg)
1829 sblk = cfg->sblk;
1830
1831 if (kms && sblk) {
1832 /* create overall sub-directory for the pipe */
1833 psde->debugfs_root =
1834 debugfs_create_dir(psde->pipe_name,
1835 sde_debugfs_get_root(kms));
1836 if (psde->debugfs_root) {
1837 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001838 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04001839 psde->debugfs_root, &psde->features);
1840
1841 /* add register dump support */
1842 sde_debugfs_setup_regset32(&psde->debugfs_src,
1843 sblk->src_blk.base + cfg->base,
1844 sblk->src_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001845 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001846 sde_debugfs_create_regset32("src_blk", 0444,
1847 psde->debugfs_root, &psde->debugfs_src);
1848
1849 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
1850 sblk->scaler_blk.base + cfg->base,
1851 sblk->scaler_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001852 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001853 sde_debugfs_create_regset32("scaler_blk", 0444,
1854 psde->debugfs_root,
1855 &psde->debugfs_scaler);
1856
1857 sde_debugfs_setup_regset32(&psde->debugfs_csc,
1858 sblk->csc_blk.base + cfg->base,
1859 sblk->csc_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001860 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001861 sde_debugfs_create_regset32("csc_blk", 0444,
1862 psde->debugfs_root, &psde->debugfs_csc);
1863 }
1864 }
1865}
1866
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001867/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04001868struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip2bbf7b32016-09-23 15:07:16 -04001869 uint32_t pipe, bool primary_plane,
1870 unsigned long possible_crtcs)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001871{
1872 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001873 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001874 struct msm_drm_private *priv;
1875 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001876 enum drm_plane_type type;
Clarence Ipc47a0692016-10-11 10:54:17 -04001877 int ret = -EINVAL;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001878
1879 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001880 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001881 goto exit;
1882 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001883
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001884 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04001885 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001886 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04001887 goto exit;
1888 }
1889
1890 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001891 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04001892 goto exit;
1893 }
1894 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001895
Clarence Ip4c1d9772016-06-26 09:35:38 -04001896 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001897 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001898 goto exit;
1899 }
1900
Clarence Ip4ce59322016-06-26 22:27:51 -04001901 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001902 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
1903 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001904 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001905 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001906 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001907 }
1908
Clarence Ip4c1d9772016-06-26 09:35:38 -04001909 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001910 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001911 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04001912 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001913
Clarence Ip4c1d9772016-06-26 09:35:38 -04001914 /* initialize underlying h/w driver */
1915 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
1916 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001917 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001918 ret = PTR_ERR(psde->pipe_hw);
1919 goto clean_plane;
1920 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001921 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001922 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001923 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001924
1925 /* cache features mask for later */
1926 psde->features = psde->pipe_hw->cap->features;
1927 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04001928 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001929 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04001930 goto clean_sspp;
1931 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001932
1933 /* add plane to DRM framework */
Clarence Ipea3d6262016-07-15 16:20:11 -04001934 psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
1935 psde->formats,
1936 0,
1937 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001938
Clarence Ip4c1d9772016-06-26 09:35:38 -04001939 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001940 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001941 goto clean_sspp;
1942 }
1943
1944 if (psde->features & BIT(SDE_SSPP_CURSOR))
1945 type = DRM_PLANE_TYPE_CURSOR;
1946 else if (primary_plane)
1947 type = DRM_PLANE_TYPE_PRIMARY;
1948 else
1949 type = DRM_PLANE_TYPE_OVERLAY;
Clarence Ip2bbf7b32016-09-23 15:07:16 -04001950 ret = drm_universal_plane_init(dev, plane, possible_crtcs,
1951 &sde_plane_funcs, psde->formats, psde->nformats, type);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001952 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04001953 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001954
Clarence Ip4c1d9772016-06-26 09:35:38 -04001955 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001956 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001957
Clarence Ipaa0faf42016-05-30 12:07:48 -04001958 msm_property_init(&psde->property_info, &plane->base, dev,
1959 priv->plane_property, psde->property_data,
1960 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
1961 sizeof(struct sde_plane_state));
1962
Clarence Ipc47a0692016-10-11 10:54:17 -04001963 _sde_plane_install_properties(plane, kms->catalog);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001964
Clarence Ip4ce59322016-06-26 22:27:51 -04001965 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04001966 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04001967
Clarence Ip730e7192016-06-26 22:45:09 -04001968 mutex_init(&psde->lock);
1969
Clarence Ip4ce59322016-06-26 22:27:51 -04001970 _sde_plane_init_debugfs(psde, kms);
1971
Clarence Ip13a8cf42016-09-29 17:27:47 -04001972 DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001973 return plane;
1974
Clarence Ip4c1d9772016-06-26 09:35:38 -04001975clean_sspp:
1976 if (psde && psde->pipe_hw)
1977 sde_hw_sspp_destroy(psde->pipe_hw);
1978clean_plane:
1979 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04001980exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001981 return ERR_PTR(ret);
1982}