Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2 | * Performance events x86 architecture code |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 3 | * |
Ingo Molnar | 9814451 | 2009-04-29 14:52:50 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
| 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 11 | * |
| 12 | * For licencing details see kernel-base/COPYING |
| 13 | */ |
| 14 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 15 | #include <linux/perf_event.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 16 | #include <linux/capability.h> |
| 17 | #include <linux/notifier.h> |
| 18 | #include <linux/hardirq.h> |
| 19 | #include <linux/kprobes.h> |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 21 | #include <linux/kdebug.h> |
| 22 | #include <linux/sched.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 23 | #include <linux/uaccess.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 24 | #include <linux/slab.h> |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 25 | #include <linux/highmem.h> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 26 | #include <linux/cpu.h> |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 27 | #include <linux/bitops.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 28 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 29 | #include <asm/apic.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 30 | #include <asm/stacktrace.h> |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 31 | #include <asm/nmi.h> |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 32 | #include <asm/compat.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 33 | |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 34 | #if 0 |
| 35 | #undef wrmsrl |
| 36 | #define wrmsrl(msr, val) \ |
| 37 | do { \ |
| 38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ |
| 39 | (unsigned long)(val)); \ |
| 40 | native_write_msr((msr), (u32)((u64)(val)), \ |
| 41 | (u32)((u64)(val) >> 32)); \ |
| 42 | } while (0) |
| 43 | #endif |
| 44 | |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 45 | /* |
| 46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context |
| 47 | */ |
| 48 | static unsigned long |
| 49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) |
| 50 | { |
| 51 | unsigned long offset, addr = (unsigned long)from; |
| 52 | int type = in_nmi() ? KM_NMI : KM_IRQ0; |
| 53 | unsigned long size, len = 0; |
| 54 | struct page *page; |
| 55 | void *map; |
| 56 | int ret; |
| 57 | |
| 58 | do { |
| 59 | ret = __get_user_pages_fast(addr, 1, 0, &page); |
| 60 | if (!ret) |
| 61 | break; |
| 62 | |
| 63 | offset = addr & (PAGE_SIZE - 1); |
| 64 | size = min(PAGE_SIZE - offset, n - len); |
| 65 | |
| 66 | map = kmap_atomic(page, type); |
| 67 | memcpy(to, map+offset, size); |
| 68 | kunmap_atomic(map, type); |
| 69 | put_page(page); |
| 70 | |
| 71 | len += size; |
| 72 | to += size; |
| 73 | addr += size; |
| 74 | |
| 75 | } while (len < n); |
| 76 | |
| 77 | return len; |
| 78 | } |
| 79 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 80 | struct event_constraint { |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 81 | union { |
| 82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 83 | u64 idxmsk64; |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 84 | }; |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 85 | u64 code; |
| 86 | u64 cmask; |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 87 | int weight; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 88 | }; |
| 89 | |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 90 | struct amd_nb { |
| 91 | int nb_id; /* NorthBridge id */ |
| 92 | int refcnt; /* reference count */ |
| 93 | struct perf_event *owners[X86_PMC_IDX_MAX]; |
| 94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; |
| 95 | }; |
| 96 | |
Peter Zijlstra | caff2be | 2010-03-03 12:02:30 +0100 | [diff] [blame] | 97 | #define MAX_LBR_ENTRIES 16 |
| 98 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 99 | struct cpu_hw_events { |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 100 | /* |
| 101 | * Generic x86 PMC bits |
| 102 | */ |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 103 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 104 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 105 | int enabled; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 106 | |
| 107 | int n_events; |
| 108 | int n_added; |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame^] | 109 | int n_txn; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 110 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 111 | u64 tags[X86_PMC_IDX_MAX]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 112 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 113 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 114 | unsigned int group_flag; |
| 115 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 116 | /* |
| 117 | * Intel DebugStore bits |
| 118 | */ |
| 119 | struct debug_store *ds; |
| 120 | u64 pebs_enabled; |
| 121 | |
| 122 | /* |
Peter Zijlstra | caff2be | 2010-03-03 12:02:30 +0100 | [diff] [blame] | 123 | * Intel LBR bits |
| 124 | */ |
| 125 | int lbr_users; |
| 126 | void *lbr_context; |
| 127 | struct perf_branch_stack lbr_stack; |
| 128 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; |
| 129 | |
| 130 | /* |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 131 | * AMD specific bits |
| 132 | */ |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 133 | struct amd_nb *amd_nb; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 134 | }; |
| 135 | |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 136 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 137 | { .idxmsk64 = (n) }, \ |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 138 | .code = (c), \ |
| 139 | .cmask = (m), \ |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 140 | .weight = (w), \ |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 141 | } |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 142 | |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 143 | #define EVENT_CONSTRAINT(c, n, m) \ |
| 144 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) |
| 145 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 146 | /* |
| 147 | * Constraint on the Event code. |
| 148 | */ |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 149 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
Robert Richter | a098f44 | 2010-03-30 11:28:21 +0200 | [diff] [blame] | 150 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 151 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 152 | /* |
| 153 | * Constraint on the Event code + UMask + fixed-mask |
Robert Richter | a098f44 | 2010-03-30 11:28:21 +0200 | [diff] [blame] | 154 | * |
| 155 | * filter mask to validate fixed counter events. |
| 156 | * the following filters disqualify for fixed counters: |
| 157 | * - inv |
| 158 | * - edge |
| 159 | * - cnt-mask |
| 160 | * The other filters are supported by fixed counters. |
| 161 | * The any-thread option is supported starting with v3. |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 162 | */ |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 163 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
Robert Richter | a098f44 | 2010-03-30 11:28:21 +0200 | [diff] [blame] | 164 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 165 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 166 | /* |
| 167 | * Constraint on the Event code + UMask |
| 168 | */ |
| 169 | #define PEBS_EVENT_CONSTRAINT(c, n) \ |
| 170 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) |
| 171 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 172 | #define EVENT_CONSTRAINT_END \ |
| 173 | EVENT_CONSTRAINT(0, 0, 0) |
| 174 | |
| 175 | #define for_each_event_constraint(e, c) \ |
Robert Richter | a1f2b70 | 2010-04-13 22:23:15 +0200 | [diff] [blame] | 176 | for ((e) = (c); (e)->weight; (e)++) |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 177 | |
Peter Zijlstra | 8db909a | 2010-03-03 17:07:40 +0100 | [diff] [blame] | 178 | union perf_capabilities { |
| 179 | struct { |
| 180 | u64 lbr_format : 6; |
| 181 | u64 pebs_trap : 1; |
| 182 | u64 pebs_arch_reg : 1; |
| 183 | u64 pebs_format : 4; |
| 184 | u64 smm_freeze : 1; |
| 185 | }; |
| 186 | u64 capabilities; |
| 187 | }; |
| 188 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 189 | /* |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 190 | * struct x86_pmu - generic x86 pmu |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 191 | */ |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 192 | struct x86_pmu { |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 193 | /* |
| 194 | * Generic x86 PMC bits |
| 195 | */ |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 196 | const char *name; |
| 197 | int version; |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 198 | int (*handle_irq)(struct pt_regs *); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 199 | void (*disable_all)(void); |
Peter Zijlstra | 11164cd | 2010-03-26 14:08:44 +0100 | [diff] [blame] | 200 | void (*enable_all)(int added); |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 201 | void (*enable)(struct perf_event *); |
| 202 | void (*disable)(struct perf_event *); |
Peter Zijlstra | b4cdc5c | 2010-03-30 17:00:06 +0200 | [diff] [blame] | 203 | int (*hw_config)(struct perf_event *event); |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 204 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 205 | unsigned eventsel; |
| 206 | unsigned perfctr; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 207 | u64 (*event_map)(int); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 208 | int max_events; |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 209 | int num_counters; |
| 210 | int num_counters_fixed; |
| 211 | int cntval_bits; |
| 212 | u64 cntval_mask; |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 213 | int apic; |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 214 | u64 max_period; |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 215 | struct event_constraint * |
| 216 | (*get_event_constraints)(struct cpu_hw_events *cpuc, |
| 217 | struct perf_event *event); |
| 218 | |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 219 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
| 220 | struct perf_event *event); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 221 | struct event_constraint *event_constraints; |
Peter Zijlstra | 3c44780 | 2010-03-04 21:49:01 +0100 | [diff] [blame] | 222 | void (*quirks)(void); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 223 | |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 224 | int (*cpu_prepare)(int cpu); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 225 | void (*cpu_starting)(int cpu); |
| 226 | void (*cpu_dying)(int cpu); |
| 227 | void (*cpu_dead)(int cpu); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 228 | |
| 229 | /* |
| 230 | * Intel Arch Perfmon v2+ |
| 231 | */ |
Peter Zijlstra | 8db909a | 2010-03-03 17:07:40 +0100 | [diff] [blame] | 232 | u64 intel_ctrl; |
| 233 | union perf_capabilities intel_cap; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 234 | |
| 235 | /* |
| 236 | * Intel DebugStore bits |
| 237 | */ |
| 238 | int bts, pebs; |
| 239 | int pebs_record_size; |
| 240 | void (*drain_pebs)(struct pt_regs *regs); |
| 241 | struct event_constraint *pebs_constraints; |
Peter Zijlstra | caff2be | 2010-03-03 12:02:30 +0100 | [diff] [blame] | 242 | |
| 243 | /* |
| 244 | * Intel LBR |
| 245 | */ |
| 246 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ |
| 247 | int lbr_nr; /* hardware stack size */ |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 248 | }; |
| 249 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 250 | static struct x86_pmu x86_pmu __read_mostly; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 251 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 252 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 253 | .enabled = 1, |
| 254 | }; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 255 | |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 256 | static int x86_perf_event_set_period(struct perf_event *event); |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 257 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 258 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 259 | * Generalized hw caching related hw_event table, filled |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 260 | * in on a per model basis. A value of 0 means |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 261 | * 'not supported', -1 means 'hw_event makes no sense on |
| 262 | * this CPU', any other value means the raw hw_event |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 263 | * ID. |
| 264 | */ |
| 265 | |
| 266 | #define C(x) PERF_COUNT_HW_CACHE_##x |
| 267 | |
| 268 | static u64 __read_mostly hw_cache_event_ids |
| 269 | [PERF_COUNT_HW_CACHE_MAX] |
| 270 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 271 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 272 | |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 273 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 274 | * Propagate event elapsed time into the generic event. |
| 275 | * Can only be executed on the CPU where the event is active. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 276 | * Returns the delta events processed. |
| 277 | */ |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 278 | static u64 |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 279 | x86_perf_event_update(struct perf_event *event) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 280 | { |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 281 | struct hw_perf_event *hwc = &event->hw; |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 282 | int shift = 64 - x86_pmu.cntval_bits; |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 283 | u64 prev_raw_count, new_raw_count; |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 284 | int idx = hwc->idx; |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 285 | s64 delta; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 286 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 287 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 288 | return 0; |
| 289 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 290 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 291 | * Careful: an NMI might modify the previous event value. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 292 | * |
| 293 | * Our tactic to handle this is to first atomically read and |
| 294 | * exchange a new raw count - then add that new-prev delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 295 | * count to the generic event atomically: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 296 | */ |
| 297 | again: |
| 298 | prev_raw_count = atomic64_read(&hwc->prev_count); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 299 | rdmsrl(hwc->event_base + idx, new_raw_count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 300 | |
| 301 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 302 | new_raw_count) != prev_raw_count) |
| 303 | goto again; |
| 304 | |
| 305 | /* |
| 306 | * Now we have the new raw value and have updated the prev |
| 307 | * timestamp already. We can now calculate the elapsed delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 308 | * (event-)time and add that to the generic event. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 309 | * |
| 310 | * Careful, not all hw sign-extends above the physical width |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 311 | * of the count. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 312 | */ |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 313 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 314 | delta >>= shift; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 315 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 316 | atomic64_add(delta, &event->count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 317 | atomic64_sub(delta, &hwc->period_left); |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 318 | |
| 319 | return new_raw_count; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 320 | } |
| 321 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 322 | static atomic_t active_events; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 323 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 324 | |
Robert Richter | b27ea29 | 2010-03-17 12:49:10 +0100 | [diff] [blame] | 325 | #ifdef CONFIG_X86_LOCAL_APIC |
| 326 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 327 | static bool reserve_pmc_hardware(void) |
| 328 | { |
| 329 | int i; |
| 330 | |
| 331 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 332 | disable_lapic_nmi_watchdog(); |
| 333 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 334 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 335 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 336 | goto perfctr_fail; |
| 337 | } |
| 338 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 339 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 340 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 341 | goto eventsel_fail; |
| 342 | } |
| 343 | |
| 344 | return true; |
| 345 | |
| 346 | eventsel_fail: |
| 347 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 348 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 349 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 350 | i = x86_pmu.num_counters; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 351 | |
| 352 | perfctr_fail: |
| 353 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 354 | release_perfctr_nmi(x86_pmu.perfctr + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 355 | |
| 356 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 357 | enable_lapic_nmi_watchdog(); |
| 358 | |
| 359 | return false; |
| 360 | } |
| 361 | |
| 362 | static void release_pmc_hardware(void) |
| 363 | { |
| 364 | int i; |
| 365 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 366 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 367 | release_perfctr_nmi(x86_pmu.perfctr + i); |
| 368 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 372 | enable_lapic_nmi_watchdog(); |
| 373 | } |
| 374 | |
Robert Richter | b27ea29 | 2010-03-17 12:49:10 +0100 | [diff] [blame] | 375 | #else |
| 376 | |
| 377 | static bool reserve_pmc_hardware(void) { return true; } |
| 378 | static void release_pmc_hardware(void) {} |
| 379 | |
| 380 | #endif |
| 381 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 382 | static int reserve_ds_buffers(void); |
| 383 | static void release_ds_buffers(void); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 384 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 385 | static void hw_perf_event_destroy(struct perf_event *event) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 386 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 387 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 388 | release_pmc_hardware(); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 389 | release_ds_buffers(); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 390 | mutex_unlock(&pmc_reserve_mutex); |
| 391 | } |
| 392 | } |
| 393 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 394 | static inline int x86_pmu_initialized(void) |
| 395 | { |
| 396 | return x86_pmu.handle_irq != NULL; |
| 397 | } |
| 398 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 399 | static inline int |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 400 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 401 | { |
| 402 | unsigned int cache_type, cache_op, cache_result; |
| 403 | u64 config, val; |
| 404 | |
| 405 | config = attr->config; |
| 406 | |
| 407 | cache_type = (config >> 0) & 0xff; |
| 408 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 409 | return -EINVAL; |
| 410 | |
| 411 | cache_op = (config >> 8) & 0xff; |
| 412 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 413 | return -EINVAL; |
| 414 | |
| 415 | cache_result = (config >> 16) & 0xff; |
| 416 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 417 | return -EINVAL; |
| 418 | |
| 419 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; |
| 420 | |
| 421 | if (val == 0) |
| 422 | return -ENOENT; |
| 423 | |
| 424 | if (val == -1) |
| 425 | return -EINVAL; |
| 426 | |
| 427 | hwc->config |= val; |
| 428 | |
| 429 | return 0; |
| 430 | } |
| 431 | |
Robert Richter | c1726f3 | 2010-04-13 22:23:11 +0200 | [diff] [blame] | 432 | static int x86_setup_perfctr(struct perf_event *event) |
| 433 | { |
| 434 | struct perf_event_attr *attr = &event->attr; |
| 435 | struct hw_perf_event *hwc = &event->hw; |
| 436 | u64 config; |
| 437 | |
| 438 | if (!hwc->sample_period) { |
| 439 | hwc->sample_period = x86_pmu.max_period; |
| 440 | hwc->last_period = hwc->sample_period; |
| 441 | atomic64_set(&hwc->period_left, hwc->sample_period); |
| 442 | } else { |
| 443 | /* |
| 444 | * If we have a PMU initialized but no APIC |
| 445 | * interrupts, we cannot sample hardware |
| 446 | * events (user-space has to fall back and |
| 447 | * sample via a hrtimer based software event): |
| 448 | */ |
| 449 | if (!x86_pmu.apic) |
| 450 | return -EOPNOTSUPP; |
| 451 | } |
| 452 | |
| 453 | if (attr->type == PERF_TYPE_RAW) |
| 454 | return 0; |
| 455 | |
| 456 | if (attr->type == PERF_TYPE_HW_CACHE) |
| 457 | return set_ext_hw_attr(hwc, attr); |
| 458 | |
| 459 | if (attr->config >= x86_pmu.max_events) |
| 460 | return -EINVAL; |
| 461 | |
| 462 | /* |
| 463 | * The generic map: |
| 464 | */ |
| 465 | config = x86_pmu.event_map(attr->config); |
| 466 | |
| 467 | if (config == 0) |
| 468 | return -ENOENT; |
| 469 | |
| 470 | if (config == -1LL) |
| 471 | return -EINVAL; |
| 472 | |
| 473 | /* |
| 474 | * Branch tracing: |
| 475 | */ |
| 476 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && |
| 477 | (hwc->sample_period == 1)) { |
| 478 | /* BTS is not supported by this architecture. */ |
| 479 | if (!x86_pmu.bts) |
| 480 | return -EOPNOTSUPP; |
| 481 | |
| 482 | /* BTS is currently only allowed for user-mode. */ |
| 483 | if (!attr->exclude_kernel) |
| 484 | return -EOPNOTSUPP; |
| 485 | } |
| 486 | |
| 487 | hwc->config |= config; |
| 488 | |
| 489 | return 0; |
| 490 | } |
Robert Richter | 4261e0e | 2010-04-13 22:23:10 +0200 | [diff] [blame] | 491 | |
Peter Zijlstra | b4cdc5c | 2010-03-30 17:00:06 +0200 | [diff] [blame] | 492 | static int x86_pmu_hw_config(struct perf_event *event) |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 493 | { |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 494 | if (event->attr.precise_ip) { |
| 495 | int precise = 0; |
| 496 | |
| 497 | /* Support for constant skid */ |
| 498 | if (x86_pmu.pebs) |
| 499 | precise++; |
| 500 | |
| 501 | /* Support for IP fixup */ |
| 502 | if (x86_pmu.lbr_nr) |
| 503 | precise++; |
| 504 | |
| 505 | if (event->attr.precise_ip > precise) |
| 506 | return -EOPNOTSUPP; |
| 507 | } |
| 508 | |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 509 | /* |
| 510 | * Generate PMC IRQs: |
| 511 | * (keep 'enabled' bit clear for now) |
| 512 | */ |
Peter Zijlstra | b4cdc5c | 2010-03-30 17:00:06 +0200 | [diff] [blame] | 513 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 514 | |
| 515 | /* |
| 516 | * Count user and OS events unless requested not to |
| 517 | */ |
Peter Zijlstra | b4cdc5c | 2010-03-30 17:00:06 +0200 | [diff] [blame] | 518 | if (!event->attr.exclude_user) |
| 519 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; |
| 520 | if (!event->attr.exclude_kernel) |
| 521 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; |
| 522 | |
| 523 | if (event->attr.type == PERF_TYPE_RAW) |
| 524 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 525 | |
Robert Richter | 9d0fcba6 | 2010-04-13 22:23:12 +0200 | [diff] [blame] | 526 | return x86_setup_perfctr(event); |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 527 | } |
| 528 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 529 | /* |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 530 | * Setup the hardware configuration for a given attr_type |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 531 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 532 | static int __hw_perf_event_init(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 533 | { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 534 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 535 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 536 | if (!x86_pmu_initialized()) |
| 537 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 538 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 539 | err = 0; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 540 | if (!atomic_inc_not_zero(&active_events)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 541 | mutex_lock(&pmc_reserve_mutex); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 542 | if (atomic_read(&active_events) == 0) { |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 543 | if (!reserve_pmc_hardware()) |
| 544 | err = -EBUSY; |
Stephane Eranian | 4b24a88 | 2010-03-17 23:21:01 +0200 | [diff] [blame] | 545 | else { |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 546 | err = reserve_ds_buffers(); |
Stephane Eranian | 4b24a88 | 2010-03-17 23:21:01 +0200 | [diff] [blame] | 547 | if (err) |
| 548 | release_pmc_hardware(); |
| 549 | } |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 550 | } |
| 551 | if (!err) |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 552 | atomic_inc(&active_events); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 553 | mutex_unlock(&pmc_reserve_mutex); |
| 554 | } |
| 555 | if (err) |
| 556 | return err; |
| 557 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 558 | event->destroy = hw_perf_event_destroy; |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 559 | |
Robert Richter | 4261e0e | 2010-04-13 22:23:10 +0200 | [diff] [blame] | 560 | event->hw.idx = -1; |
| 561 | event->hw.last_cpu = -1; |
| 562 | event->hw.last_tag = ~0ULL; |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 563 | |
Robert Richter | 9d0fcba6 | 2010-04-13 22:23:12 +0200 | [diff] [blame] | 564 | return x86_pmu.hw_config(event); |
Robert Richter | 4261e0e | 2010-04-13 22:23:10 +0200 | [diff] [blame] | 565 | } |
| 566 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 567 | static void x86_pmu_disable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 568 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 569 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 570 | int idx; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 571 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 572 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 573 | u64 val; |
| 574 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 575 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 576 | continue; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 577 | rdmsrl(x86_pmu.eventsel + idx, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 578 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 579 | continue; |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 580 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 581 | wrmsrl(x86_pmu.eventsel + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 582 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 583 | } |
| 584 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 585 | void hw_perf_disable(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 586 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 587 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 588 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 589 | if (!x86_pmu_initialized()) |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 590 | return; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 591 | |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 592 | if (!cpuc->enabled) |
| 593 | return; |
| 594 | |
| 595 | cpuc->n_added = 0; |
| 596 | cpuc->enabled = 0; |
| 597 | barrier(); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 598 | |
| 599 | x86_pmu.disable_all(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 600 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 601 | |
Peter Zijlstra | 11164cd | 2010-03-26 14:08:44 +0100 | [diff] [blame] | 602 | static void x86_pmu_enable_all(int added) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 603 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 604 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 605 | int idx; |
| 606 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 607 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 608 | struct perf_event *event = cpuc->events[idx]; |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 609 | u64 val; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 610 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 611 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 612 | continue; |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 613 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 614 | val = event->hw.config; |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 615 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 616 | wrmsrl(x86_pmu.eventsel + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 617 | } |
| 618 | } |
| 619 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 620 | static const struct pmu pmu; |
| 621 | |
| 622 | static inline int is_x86_event(struct perf_event *event) |
| 623 | { |
| 624 | return event->pmu == &pmu; |
| 625 | } |
| 626 | |
| 627 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
| 628 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 629 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 630 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 631 | int i, j, w, wmax, num = 0; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 632 | struct hw_perf_event *hwc; |
| 633 | |
| 634 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 635 | |
| 636 | for (i = 0; i < n; i++) { |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 637 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
| 638 | constraints[i] = c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | /* |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 642 | * fastpath, try to reuse previous register |
| 643 | */ |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 644 | for (i = 0; i < n; i++) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 645 | hwc = &cpuc->event_list[i]->hw; |
Peter Zijlstra | 81269a0 | 2010-01-22 14:55:22 +0100 | [diff] [blame] | 646 | c = constraints[i]; |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 647 | |
| 648 | /* never assigned */ |
| 649 | if (hwc->idx == -1) |
| 650 | break; |
| 651 | |
| 652 | /* constraint still honored */ |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 653 | if (!test_bit(hwc->idx, c->idxmsk)) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 654 | break; |
| 655 | |
| 656 | /* not already used */ |
| 657 | if (test_bit(hwc->idx, used_mask)) |
| 658 | break; |
| 659 | |
Peter Zijlstra | 34538ee | 2010-03-02 21:16:55 +0100 | [diff] [blame] | 660 | __set_bit(hwc->idx, used_mask); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 661 | if (assign) |
| 662 | assign[i] = hwc->idx; |
| 663 | } |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 664 | if (i == n) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 665 | goto done; |
| 666 | |
| 667 | /* |
| 668 | * begin slow path |
| 669 | */ |
| 670 | |
| 671 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 672 | |
| 673 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 674 | * weight = number of possible counters |
| 675 | * |
| 676 | * 1 = most constrained, only works on one counter |
| 677 | * wmax = least constrained, works on any counter |
| 678 | * |
| 679 | * assign events to counters starting with most |
| 680 | * constrained events. |
| 681 | */ |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 682 | wmax = x86_pmu.num_counters; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 683 | |
| 684 | /* |
| 685 | * when fixed event counters are present, |
| 686 | * wmax is incremented by 1 to account |
| 687 | * for one more choice |
| 688 | */ |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 689 | if (x86_pmu.num_counters_fixed) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 690 | wmax++; |
| 691 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 692 | for (w = 1, num = n; num && w <= wmax; w++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 693 | /* for each event */ |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 694 | for (i = 0; num && i < n; i++) { |
Peter Zijlstra | 81269a0 | 2010-01-22 14:55:22 +0100 | [diff] [blame] | 695 | c = constraints[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 696 | hwc = &cpuc->event_list[i]->hw; |
| 697 | |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 698 | if (c->weight != w) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 699 | continue; |
| 700 | |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 701 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 702 | if (!test_bit(j, used_mask)) |
| 703 | break; |
| 704 | } |
| 705 | |
| 706 | if (j == X86_PMC_IDX_MAX) |
| 707 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 708 | |
Peter Zijlstra | 34538ee | 2010-03-02 21:16:55 +0100 | [diff] [blame] | 709 | __set_bit(j, used_mask); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 710 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 711 | if (assign) |
| 712 | assign[i] = j; |
| 713 | num--; |
| 714 | } |
| 715 | } |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 716 | done: |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 717 | /* |
| 718 | * scheduling failed or is just a simulation, |
| 719 | * free resources if necessary |
| 720 | */ |
| 721 | if (!assign || num) { |
| 722 | for (i = 0; i < n; i++) { |
| 723 | if (x86_pmu.put_event_constraints) |
| 724 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); |
| 725 | } |
| 726 | } |
| 727 | return num ? -ENOSPC : 0; |
| 728 | } |
| 729 | |
| 730 | /* |
| 731 | * dogrp: true if must collect siblings events (group) |
| 732 | * returns total number of events and error code |
| 733 | */ |
| 734 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) |
| 735 | { |
| 736 | struct perf_event *event; |
| 737 | int n, max_count; |
| 738 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 739 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 740 | |
| 741 | /* current number of events already accepted */ |
| 742 | n = cpuc->n_events; |
| 743 | |
| 744 | if (is_x86_event(leader)) { |
| 745 | if (n >= max_count) |
| 746 | return -ENOSPC; |
| 747 | cpuc->event_list[n] = leader; |
| 748 | n++; |
| 749 | } |
| 750 | if (!dogrp) |
| 751 | return n; |
| 752 | |
| 753 | list_for_each_entry(event, &leader->sibling_list, group_entry) { |
| 754 | if (!is_x86_event(event) || |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 755 | event->state <= PERF_EVENT_STATE_OFF) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 756 | continue; |
| 757 | |
| 758 | if (n >= max_count) |
| 759 | return -ENOSPC; |
| 760 | |
| 761 | cpuc->event_list[n] = event; |
| 762 | n++; |
| 763 | } |
| 764 | return n; |
| 765 | } |
| 766 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 767 | static inline void x86_assign_hw_event(struct perf_event *event, |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 768 | struct cpu_hw_events *cpuc, int i) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 769 | { |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 770 | struct hw_perf_event *hwc = &event->hw; |
| 771 | |
| 772 | hwc->idx = cpuc->assign[i]; |
| 773 | hwc->last_cpu = smp_processor_id(); |
| 774 | hwc->last_tag = ++cpuc->tags[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 775 | |
| 776 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { |
| 777 | hwc->config_base = 0; |
| 778 | hwc->event_base = 0; |
| 779 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { |
| 780 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 781 | /* |
| 782 | * We set it so that event_base + idx in wrmsr/rdmsr maps to |
| 783 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: |
| 784 | */ |
| 785 | hwc->event_base = |
| 786 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; |
| 787 | } else { |
| 788 | hwc->config_base = x86_pmu.eventsel; |
| 789 | hwc->event_base = x86_pmu.perfctr; |
| 790 | } |
| 791 | } |
| 792 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 793 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
| 794 | struct cpu_hw_events *cpuc, |
| 795 | int i) |
| 796 | { |
| 797 | return hwc->idx == cpuc->assign[i] && |
| 798 | hwc->last_cpu == smp_processor_id() && |
| 799 | hwc->last_tag == cpuc->tags[i]; |
| 800 | } |
| 801 | |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 802 | static int x86_pmu_start(struct perf_event *event); |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 803 | static void x86_pmu_stop(struct perf_event *event); |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 804 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 805 | void hw_perf_enable(void) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 806 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 807 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 808 | struct perf_event *event; |
| 809 | struct hw_perf_event *hwc; |
Peter Zijlstra | 11164cd | 2010-03-26 14:08:44 +0100 | [diff] [blame] | 810 | int i, added = cpuc->n_added; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 811 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 812 | if (!x86_pmu_initialized()) |
Ingo Molnar | 2b9ff0d | 2008-12-14 18:36:30 +0100 | [diff] [blame] | 813 | return; |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 814 | |
| 815 | if (cpuc->enabled) |
| 816 | return; |
| 817 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 818 | if (cpuc->n_added) { |
Peter Zijlstra | 19925ce | 2010-03-06 13:20:40 +0100 | [diff] [blame] | 819 | int n_running = cpuc->n_events - cpuc->n_added; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 820 | /* |
| 821 | * apply assignment obtained either from |
| 822 | * hw_perf_group_sched_in() or x86_pmu_enable() |
| 823 | * |
| 824 | * step1: save events moving to new counters |
| 825 | * step2: reprogram moved events into new counters |
| 826 | */ |
Peter Zijlstra | 19925ce | 2010-03-06 13:20:40 +0100 | [diff] [blame] | 827 | for (i = 0; i < n_running; i++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 828 | event = cpuc->event_list[i]; |
| 829 | hwc = &event->hw; |
| 830 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 831 | /* |
| 832 | * we can avoid reprogramming counter if: |
| 833 | * - assigned same counter as last time |
| 834 | * - running on same CPU as last time |
| 835 | * - no other event has used the counter since |
| 836 | */ |
| 837 | if (hwc->idx == -1 || |
| 838 | match_prev_assignment(hwc, cpuc, i)) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 839 | continue; |
| 840 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 841 | x86_pmu_stop(event); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 842 | } |
| 843 | |
| 844 | for (i = 0; i < cpuc->n_events; i++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 845 | event = cpuc->event_list[i]; |
| 846 | hwc = &event->hw; |
| 847 | |
Peter Zijlstra | 45e16a6 | 2010-03-11 13:40:30 +0100 | [diff] [blame] | 848 | if (!match_prev_assignment(hwc, cpuc, i)) |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 849 | x86_assign_hw_event(event, cpuc, i); |
Peter Zijlstra | 45e16a6 | 2010-03-11 13:40:30 +0100 | [diff] [blame] | 850 | else if (i < n_running) |
| 851 | continue; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 852 | |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 853 | x86_pmu_start(event); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 854 | } |
| 855 | cpuc->n_added = 0; |
| 856 | perf_events_lapic_init(); |
| 857 | } |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 858 | |
| 859 | cpuc->enabled = 1; |
| 860 | barrier(); |
| 861 | |
Peter Zijlstra | 11164cd | 2010-03-26 14:08:44 +0100 | [diff] [blame] | 862 | x86_pmu.enable_all(added); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 863 | } |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 864 | |
Robert Richter | 31fa58a | 2010-04-13 22:23:14 +0200 | [diff] [blame] | 865 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
| 866 | u64 enable_mask) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 867 | { |
Robert Richter | 31fa58a | 2010-04-13 22:23:14 +0200 | [diff] [blame] | 868 | wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 869 | } |
| 870 | |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 871 | static inline void x86_pmu_disable_event(struct perf_event *event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 872 | { |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 873 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 874 | |
| 875 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 876 | } |
| 877 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 878 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 879 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 880 | /* |
| 881 | * Set the next IRQ period, based on the hwc->period_left value. |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 882 | * To be called with the event disabled in hw: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 883 | */ |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 884 | static int |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 885 | x86_perf_event_set_period(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 886 | { |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 887 | struct hw_perf_event *hwc = &event->hw; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 888 | s64 left = atomic64_read(&hwc->period_left); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 889 | s64 period = hwc->sample_period; |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 890 | int ret = 0, idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 891 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 892 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 893 | return 0; |
| 894 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 895 | /* |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 896 | * If we are way outside a reasonable range then just skip forward: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 897 | */ |
| 898 | if (unlikely(left <= -period)) { |
| 899 | left = period; |
| 900 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 901 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 902 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 903 | } |
| 904 | |
| 905 | if (unlikely(left <= 0)) { |
| 906 | left += period; |
| 907 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 908 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 909 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 910 | } |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 911 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 912 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 913 | */ |
| 914 | if (unlikely(left < 2)) |
| 915 | left = 2; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 916 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 917 | if (left > x86_pmu.max_period) |
| 918 | left = x86_pmu.max_period; |
| 919 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 920 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 921 | |
| 922 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 923 | * The hw event starts counting from this event offset, |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 924 | * mark it to be able to extra future deltas: |
| 925 | */ |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 926 | atomic64_set(&hwc->prev_count, (u64)-left); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 927 | |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 928 | wrmsrl(hwc->event_base + idx, |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 929 | (u64)(-left) & x86_pmu.cntval_mask); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 930 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 931 | perf_event_update_userpage(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 932 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 933 | return ret; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 934 | } |
| 935 | |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 936 | static void x86_pmu_enable_event(struct perf_event *event) |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 937 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 938 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 939 | if (cpuc->enabled) |
Robert Richter | 31fa58a | 2010-04-13 22:23:14 +0200 | [diff] [blame] | 940 | __x86_pmu_enable_event(&event->hw, |
| 941 | ARCH_PERFMON_EVENTSEL_ENABLE); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 942 | } |
| 943 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 944 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 945 | * activate a single event |
| 946 | * |
| 947 | * The event is added to the group of enabled events |
| 948 | * but only if it can be scehduled with existing events. |
| 949 | * |
| 950 | * Called with PMU disabled. If successful and return value 1, |
| 951 | * then guaranteed to call perf_enable() and hw_perf_enable() |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 952 | */ |
| 953 | static int x86_pmu_enable(struct perf_event *event) |
| 954 | { |
| 955 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 956 | struct hw_perf_event *hwc; |
| 957 | int assign[X86_PMC_IDX_MAX]; |
| 958 | int n, n0, ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 959 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 960 | hwc = &event->hw; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 961 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 962 | n0 = cpuc->n_events; |
| 963 | n = collect_events(cpuc, event, false); |
| 964 | if (n < 0) |
| 965 | return n; |
Ingo Molnar | 53b441a | 2009-05-25 21:41:28 +0200 | [diff] [blame] | 966 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 967 | /* |
| 968 | * If group events scheduling transaction was started, |
| 969 | * skip the schedulability test here, it will be peformed |
| 970 | * at commit time(->commit_txn) as a whole |
| 971 | */ |
| 972 | if (cpuc->group_flag & PERF_EVENT_TXN_STARTED) |
| 973 | goto out; |
| 974 | |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 975 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 976 | if (ret) |
| 977 | return ret; |
| 978 | /* |
| 979 | * copy new assignment, now we know it is possible |
| 980 | * will be used by hw_perf_enable() |
| 981 | */ |
| 982 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 983 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 984 | out: |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 985 | cpuc->n_events = n; |
Peter Zijlstra | 356e1f2 | 2010-03-06 13:49:56 +0100 | [diff] [blame] | 986 | cpuc->n_added += n - n0; |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame^] | 987 | cpuc->n_txn += n - n0; |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 988 | |
Ingo Molnar | 95cdd2e | 2008-12-21 13:50:42 +0100 | [diff] [blame] | 989 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 990 | } |
| 991 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 992 | static int x86_pmu_start(struct perf_event *event) |
| 993 | { |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 994 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 995 | int idx = event->hw.idx; |
| 996 | |
| 997 | if (idx == -1) |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 998 | return -EAGAIN; |
| 999 | |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 1000 | x86_perf_event_set_period(event); |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 1001 | cpuc->events[idx] = event; |
| 1002 | __set_bit(idx, cpuc->active_mask); |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 1003 | x86_pmu.enable(event); |
Peter Zijlstra | c08053e | 2010-03-06 13:19:24 +0100 | [diff] [blame] | 1004 | perf_event_update_userpage(event); |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1005 | |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1009 | static void x86_pmu_unthrottle(struct perf_event *event) |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1010 | { |
Peter Zijlstra | 71e2d28 | 2010-03-08 17:51:33 +0100 | [diff] [blame] | 1011 | int ret = x86_pmu_start(event); |
| 1012 | WARN_ON_ONCE(ret); |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1013 | } |
| 1014 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1015 | void perf_event_print_debug(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1016 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1017 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1018 | u64 pebs; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1019 | struct cpu_hw_events *cpuc; |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1020 | unsigned long flags; |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1021 | int cpu, idx; |
| 1022 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1023 | if (!x86_pmu.num_counters) |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1024 | return; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1025 | |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1026 | local_irq_save(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1027 | |
| 1028 | cpu = smp_processor_id(); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1029 | cpuc = &per_cpu(cpu_hw_events, cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1030 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1031 | if (x86_pmu.version >= 2) { |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1032 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 1033 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1034 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 1035 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1036 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1037 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1038 | pr_info("\n"); |
| 1039 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 1040 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 1041 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 1042 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1043 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1044 | } |
Peter Zijlstra | 7645a24 | 2010-03-08 13:51:31 +0100 | [diff] [blame] | 1045 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1046 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1047 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 1048 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
| 1049 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1050 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1051 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1052 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1053 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1054 | cpu, idx, pmc_ctrl); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1055 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1056 | cpu, idx, pmc_count); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1057 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1058 | cpu, idx, prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1059 | } |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1060 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1061 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 1062 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1063 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1064 | cpu, idx, pmc_count); |
| 1065 | } |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1066 | local_irq_restore(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1067 | } |
| 1068 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1069 | static void x86_pmu_stop(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1070 | { |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1071 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1072 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1073 | int idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1074 | |
Peter Zijlstra | 71e2d28 | 2010-03-08 17:51:33 +0100 | [diff] [blame] | 1075 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
| 1076 | return; |
| 1077 | |
Peter Zijlstra | aff3d91 | 2010-03-02 20:32:08 +0100 | [diff] [blame] | 1078 | x86_pmu.disable(event); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1079 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1080 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1081 | * Drain the remaining delta count out of a event |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1082 | * that we are disabling: |
| 1083 | */ |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 1084 | x86_perf_event_update(event); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1085 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1086 | cpuc->events[idx] = NULL; |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1087 | } |
| 1088 | |
| 1089 | static void x86_pmu_disable(struct perf_event *event) |
| 1090 | { |
| 1091 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1092 | int i; |
| 1093 | |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame^] | 1094 | /* |
| 1095 | * If we're called during a txn, we don't need to do anything. |
| 1096 | * The events never got scheduled and ->cancel_txn will truncate |
| 1097 | * the event_list. |
| 1098 | */ |
| 1099 | if (cpuc->group_flag & PERF_EVENT_TXN_STARTED) |
| 1100 | return; |
| 1101 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1102 | x86_pmu_stop(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 1103 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1104 | for (i = 0; i < cpuc->n_events; i++) { |
| 1105 | if (event == cpuc->event_list[i]) { |
| 1106 | |
| 1107 | if (x86_pmu.put_event_constraints) |
| 1108 | x86_pmu.put_event_constraints(cpuc, event); |
| 1109 | |
| 1110 | while (++i < cpuc->n_events) |
| 1111 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
| 1112 | |
| 1113 | --cpuc->n_events; |
Peter Zijlstra | 6c9687a | 2010-01-25 11:57:25 +0100 | [diff] [blame] | 1114 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1115 | } |
| 1116 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1117 | perf_event_update_userpage(event); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1118 | } |
| 1119 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1120 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1121 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1122 | struct perf_sample_data data; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1123 | struct cpu_hw_events *cpuc; |
| 1124 | struct perf_event *event; |
| 1125 | struct hw_perf_event *hwc; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1126 | int idx, handled = 0; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1127 | u64 val; |
| 1128 | |
Peter Zijlstra | dc1d628 | 2010-03-03 15:55:04 +0100 | [diff] [blame] | 1129 | perf_sample_data_init(&data, 0); |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1130 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1131 | cpuc = &__get_cpu_var(cpu_hw_events); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1132 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1133 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1134 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1135 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1136 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1137 | event = cpuc->events[idx]; |
| 1138 | hwc = &event->hw; |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1139 | |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 1140 | val = x86_perf_event_update(event); |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1141 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 1142 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1143 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1144 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1145 | * event overflow |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1146 | */ |
| 1147 | handled = 1; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1148 | data.period = event->hw.last_period; |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1149 | |
Peter Zijlstra | 07088ed | 2010-03-02 20:16:01 +0100 | [diff] [blame] | 1150 | if (!x86_perf_event_set_period(event)) |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1151 | continue; |
| 1152 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1153 | if (perf_event_overflow(event, 1, &data, regs)) |
Peter Zijlstra | 71e2d28 | 2010-03-08 17:51:33 +0100 | [diff] [blame] | 1154 | x86_pmu_stop(event); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1155 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1156 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1157 | if (handled) |
| 1158 | inc_irq_stat(apic_perf_irqs); |
| 1159 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1160 | return handled; |
| 1161 | } |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 1162 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1163 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
| 1164 | { |
| 1165 | irq_enter(); |
| 1166 | ack_APIC_irq(); |
| 1167 | inc_irq_stat(apic_pending_irqs); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1168 | perf_event_do_pending(); |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1169 | irq_exit(); |
| 1170 | } |
| 1171 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1172 | void set_perf_event_pending(void) |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1173 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1174 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 7d42896 | 2009-09-23 11:03:37 +0200 | [diff] [blame] | 1175 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
| 1176 | return; |
| 1177 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1178 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1179 | #endif |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1180 | } |
| 1181 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1182 | void perf_events_lapic_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1183 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1184 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1185 | return; |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1186 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1187 | /* |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1188 | * Always use NMI for PMU |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1189 | */ |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1190 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1191 | } |
| 1192 | |
| 1193 | static int __kprobes |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1194 | perf_event_nmi_handler(struct notifier_block *self, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1195 | unsigned long cmd, void *__args) |
| 1196 | { |
| 1197 | struct die_args *args = __args; |
| 1198 | struct pt_regs *regs; |
| 1199 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1200 | if (!atomic_read(&active_events)) |
Peter Zijlstra | 63a809a | 2009-05-01 12:23:17 +0200 | [diff] [blame] | 1201 | return NOTIFY_DONE; |
| 1202 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1203 | switch (cmd) { |
| 1204 | case DIE_NMI: |
| 1205 | case DIE_NMI_IPI: |
| 1206 | break; |
| 1207 | |
| 1208 | default: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1209 | return NOTIFY_DONE; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1210 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1211 | |
| 1212 | regs = args->regs; |
| 1213 | |
| 1214 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1215 | /* |
| 1216 | * Can't rely on the handled return value to say it was our NMI, two |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1217 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1218 | * |
| 1219 | * If the first NMI handles both, the latter will be empty and daze |
| 1220 | * the CPU. |
| 1221 | */ |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 1222 | x86_pmu.handle_irq(regs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1223 | |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1224 | return NOTIFY_STOP; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1225 | } |
| 1226 | |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1227 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
| 1228 | .notifier_call = perf_event_nmi_handler, |
| 1229 | .next = NULL, |
| 1230 | .priority = 1 |
| 1231 | }; |
| 1232 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1233 | static struct event_constraint unconstrained; |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 1234 | static struct event_constraint emptyconstraint; |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1235 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1236 | static struct event_constraint * |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1237 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1238 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1239 | struct event_constraint *c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1240 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1241 | if (x86_pmu.event_constraints) { |
| 1242 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1243 | if ((event->hw.config & c->cmask) == c->code) |
| 1244 | return c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1245 | } |
| 1246 | } |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1247 | |
| 1248 | return &unconstrained; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1249 | } |
| 1250 | |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1251 | #include "perf_event_amd.c" |
| 1252 | #include "perf_event_p6.c" |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 1253 | #include "perf_event_p4.c" |
Peter Zijlstra | caff2be | 2010-03-03 12:02:30 +0100 | [diff] [blame] | 1254 | #include "perf_event_intel_lbr.c" |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1255 | #include "perf_event_intel_ds.c" |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1256 | #include "perf_event_intel.c" |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1257 | |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1258 | static int __cpuinit |
| 1259 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
| 1260 | { |
| 1261 | unsigned int cpu = (long)hcpu; |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1262 | int ret = NOTIFY_OK; |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1263 | |
| 1264 | switch (action & ~CPU_TASKS_FROZEN) { |
| 1265 | case CPU_UP_PREPARE: |
| 1266 | if (x86_pmu.cpu_prepare) |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1267 | ret = x86_pmu.cpu_prepare(cpu); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1268 | break; |
| 1269 | |
| 1270 | case CPU_STARTING: |
| 1271 | if (x86_pmu.cpu_starting) |
| 1272 | x86_pmu.cpu_starting(cpu); |
| 1273 | break; |
| 1274 | |
| 1275 | case CPU_DYING: |
| 1276 | if (x86_pmu.cpu_dying) |
| 1277 | x86_pmu.cpu_dying(cpu); |
| 1278 | break; |
| 1279 | |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1280 | case CPU_UP_CANCELED: |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1281 | case CPU_DEAD: |
| 1282 | if (x86_pmu.cpu_dead) |
| 1283 | x86_pmu.cpu_dead(cpu); |
| 1284 | break; |
| 1285 | |
| 1286 | default: |
| 1287 | break; |
| 1288 | } |
| 1289 | |
Peter Zijlstra | b38b24e | 2010-03-23 19:31:15 +0100 | [diff] [blame] | 1290 | return ret; |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1291 | } |
| 1292 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1293 | static void __init pmu_check_apic(void) |
| 1294 | { |
| 1295 | if (cpu_has_apic) |
| 1296 | return; |
| 1297 | |
| 1298 | x86_pmu.apic = 0; |
| 1299 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
| 1300 | pr_info("no hardware sampling interrupt available.\n"); |
| 1301 | } |
| 1302 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1303 | void __init init_hw_perf_events(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1304 | { |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 1305 | struct event_constraint *c; |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1306 | int err; |
| 1307 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1308 | pr_info("Performance Events: "); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1309 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1310 | switch (boot_cpu_data.x86_vendor) { |
| 1311 | case X86_VENDOR_INTEL: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1312 | err = intel_pmu_init(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1313 | break; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1314 | case X86_VENDOR_AMD: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1315 | err = amd_pmu_init(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1316 | break; |
Robert Richter | 4138960 | 2009-04-29 12:47:00 +0200 | [diff] [blame] | 1317 | default: |
| 1318 | return; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1319 | } |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1320 | if (err != 0) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1321 | pr_cont("no PMU driver, software events only.\n"); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1322 | return; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1323 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1324 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1325 | pmu_check_apic(); |
| 1326 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1327 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1328 | |
Peter Zijlstra | 3c44780 | 2010-03-04 21:49:01 +0100 | [diff] [blame] | 1329 | if (x86_pmu.quirks) |
| 1330 | x86_pmu.quirks(); |
| 1331 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1332 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1333 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1334 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
| 1335 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1336 | } |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1337 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
| 1338 | perf_max_events = x86_pmu.num_counters; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1339 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1340 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1341 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1342 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
| 1343 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1344 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1345 | |
Robert Richter | d6dc0b4 | 2010-03-17 12:49:13 +0100 | [diff] [blame] | 1346 | x86_pmu.intel_ctrl |= |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1347 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1348 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1349 | perf_events_lapic_init(); |
| 1350 | register_die_notifier(&perf_event_nmi_notifier); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1351 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1352 | unconstrained = (struct event_constraint) |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1353 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
| 1354 | 0, x86_pmu.num_counters); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1355 | |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 1356 | if (x86_pmu.event_constraints) { |
| 1357 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
Robert Richter | a098f44 | 2010-03-30 11:28:21 +0200 | [diff] [blame] | 1358 | if (c->cmask != X86_RAW_EVENT_MASK) |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 1359 | continue; |
| 1360 | |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1361 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
| 1362 | c->weight += x86_pmu.num_counters; |
Peter Zijlstra | b622d64 | 2010-02-01 15:36:30 +0100 | [diff] [blame] | 1363 | } |
| 1364 | } |
| 1365 | |
Ingo Molnar | 57c0c15 | 2009-09-21 12:20:38 +0200 | [diff] [blame] | 1366 | pr_info("... version: %d\n", x86_pmu.version); |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1367 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
| 1368 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); |
| 1369 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); |
Ingo Molnar | 57c0c15 | 2009-09-21 12:20:38 +0200 | [diff] [blame] | 1370 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 1371 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
Robert Richter | d6dc0b4 | 2010-03-17 12:49:13 +0100 | [diff] [blame] | 1372 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
Peter Zijlstra | 3f6da39 | 2010-03-05 13:01:18 +0100 | [diff] [blame] | 1373 | |
| 1374 | perf_cpu_notifier(x86_pmu_notifier); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1375 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1376 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1377 | static inline void x86_pmu_read(struct perf_event *event) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1378 | { |
Peter Zijlstra | cc2ad4b | 2010-03-02 20:18:39 +0100 | [diff] [blame] | 1379 | x86_perf_event_update(event); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1380 | } |
| 1381 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1382 | /* |
| 1383 | * Start group events scheduling transaction |
| 1384 | * Set the flag to make pmu::enable() not perform the |
| 1385 | * schedulability test, it will be performed at commit time |
| 1386 | */ |
| 1387 | static void x86_pmu_start_txn(const struct pmu *pmu) |
| 1388 | { |
| 1389 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1390 | |
| 1391 | cpuc->group_flag |= PERF_EVENT_TXN_STARTED; |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame^] | 1392 | cpuc->n_txn = 0; |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1393 | } |
| 1394 | |
| 1395 | /* |
| 1396 | * Stop group events scheduling transaction |
| 1397 | * Clear the flag and pmu::enable() will perform the |
| 1398 | * schedulability test. |
| 1399 | */ |
| 1400 | static void x86_pmu_cancel_txn(const struct pmu *pmu) |
| 1401 | { |
| 1402 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1403 | |
| 1404 | cpuc->group_flag &= ~PERF_EVENT_TXN_STARTED; |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame^] | 1405 | /* |
| 1406 | * Truncate the collected events. |
| 1407 | */ |
| 1408 | cpuc->n_added -= cpuc->n_txn; |
| 1409 | cpuc->n_events -= cpuc->n_txn; |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1410 | } |
| 1411 | |
| 1412 | /* |
| 1413 | * Commit group events scheduling transaction |
| 1414 | * Perform the group schedulability test as a whole |
| 1415 | * Return 0 if success |
| 1416 | */ |
| 1417 | static int x86_pmu_commit_txn(const struct pmu *pmu) |
| 1418 | { |
| 1419 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1420 | int assign[X86_PMC_IDX_MAX]; |
| 1421 | int n, ret; |
| 1422 | |
| 1423 | n = cpuc->n_events; |
| 1424 | |
| 1425 | if (!x86_pmu_initialized()) |
| 1426 | return -EAGAIN; |
| 1427 | |
| 1428 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
| 1429 | if (ret) |
| 1430 | return ret; |
| 1431 | |
| 1432 | /* |
| 1433 | * copy new assignment, now we know it is possible |
| 1434 | * will be used by hw_perf_enable() |
| 1435 | */ |
| 1436 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
| 1437 | |
Stephane Eranian | 90151c35 | 2010-05-25 16:23:10 +0200 | [diff] [blame^] | 1438 | /* |
| 1439 | * Clear out the txn count so that ->cancel_txn() which gets |
| 1440 | * run after ->commit_txn() doesn't undo things. |
| 1441 | */ |
| 1442 | cpuc->n_txn = 0; |
| 1443 | |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1444 | return 0; |
| 1445 | } |
| 1446 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1447 | static const struct pmu pmu = { |
| 1448 | .enable = x86_pmu_enable, |
| 1449 | .disable = x86_pmu_disable, |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1450 | .start = x86_pmu_start, |
| 1451 | .stop = x86_pmu_stop, |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1452 | .read = x86_pmu_read, |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1453 | .unthrottle = x86_pmu_unthrottle, |
Lin Ming | 4d1c52b | 2010-04-23 13:56:12 +0800 | [diff] [blame] | 1454 | .start_txn = x86_pmu_start_txn, |
| 1455 | .cancel_txn = x86_pmu_cancel_txn, |
| 1456 | .commit_txn = x86_pmu_commit_txn, |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1457 | }; |
| 1458 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1459 | /* |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1460 | * validate that we can schedule this event |
| 1461 | */ |
| 1462 | static int validate_event(struct perf_event *event) |
| 1463 | { |
| 1464 | struct cpu_hw_events *fake_cpuc; |
| 1465 | struct event_constraint *c; |
| 1466 | int ret = 0; |
| 1467 | |
| 1468 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); |
| 1469 | if (!fake_cpuc) |
| 1470 | return -ENOMEM; |
| 1471 | |
| 1472 | c = x86_pmu.get_event_constraints(fake_cpuc, event); |
| 1473 | |
| 1474 | if (!c || !c->weight) |
| 1475 | ret = -ENOSPC; |
| 1476 | |
| 1477 | if (x86_pmu.put_event_constraints) |
| 1478 | x86_pmu.put_event_constraints(fake_cpuc, event); |
| 1479 | |
| 1480 | kfree(fake_cpuc); |
| 1481 | |
| 1482 | return ret; |
| 1483 | } |
| 1484 | |
| 1485 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1486 | * validate a single event group |
| 1487 | * |
| 1488 | * validation include: |
Ingo Molnar | 184f412 | 2010-01-27 08:39:39 +0100 | [diff] [blame] | 1489 | * - check events are compatible which each other |
| 1490 | * - events do not compete for the same counter |
| 1491 | * - number of events <= number of counters |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1492 | * |
| 1493 | * validation ensures the group can be loaded onto the |
| 1494 | * PMU if it was the only group available. |
| 1495 | */ |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1496 | static int validate_group(struct perf_event *event) |
| 1497 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1498 | struct perf_event *leader = event->group_leader; |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1499 | struct cpu_hw_events *fake_cpuc; |
| 1500 | int ret, n; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1501 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1502 | ret = -ENOMEM; |
| 1503 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); |
| 1504 | if (!fake_cpuc) |
| 1505 | goto out; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1506 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1507 | /* |
| 1508 | * the event is not yet connected with its |
| 1509 | * siblings therefore we must first collect |
| 1510 | * existing siblings, then add the new event |
| 1511 | * before we can simulate the scheduling |
| 1512 | */ |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1513 | ret = -ENOSPC; |
| 1514 | n = collect_events(fake_cpuc, leader, true); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1515 | if (n < 0) |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1516 | goto out_free; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1517 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1518 | fake_cpuc->n_events = n; |
| 1519 | n = collect_events(fake_cpuc, event, false); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1520 | if (n < 0) |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1521 | goto out_free; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1522 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1523 | fake_cpuc->n_events = n; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1524 | |
Cyrill Gorcunov | a072738 | 2010-03-11 19:54:39 +0300 | [diff] [blame] | 1525 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1526 | |
| 1527 | out_free: |
| 1528 | kfree(fake_cpuc); |
| 1529 | out: |
| 1530 | return ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1531 | } |
| 1532 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1533 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1534 | { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1535 | const struct pmu *tmp; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1536 | int err; |
| 1537 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1538 | err = __hw_perf_event_init(event); |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1539 | if (!err) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1540 | /* |
| 1541 | * we temporarily connect event to its pmu |
| 1542 | * such that validate_group() can classify |
| 1543 | * it as an x86 event using is_x86_event() |
| 1544 | */ |
| 1545 | tmp = event->pmu; |
| 1546 | event->pmu = &pmu; |
| 1547 | |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1548 | if (event->group_leader != event) |
| 1549 | err = validate_group(event); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1550 | else |
| 1551 | err = validate_event(event); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1552 | |
| 1553 | event->pmu = tmp; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1554 | } |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1555 | if (err) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1556 | if (event->destroy) |
| 1557 | event->destroy(event); |
Peter Zijlstra | 9ea98e1 | 2009-03-30 19:07:09 +0200 | [diff] [blame] | 1558 | return ERR_PTR(err); |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1559 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1560 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1561 | return &pmu; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1562 | } |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1563 | |
| 1564 | /* |
| 1565 | * callchain support |
| 1566 | */ |
| 1567 | |
| 1568 | static inline |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1569 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1570 | { |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1571 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1572 | entry->ip[entry->nr++] = ip; |
| 1573 | } |
| 1574 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1575 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
| 1576 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1577 | |
| 1578 | |
| 1579 | static void |
| 1580 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) |
| 1581 | { |
| 1582 | /* Ignore warnings */ |
| 1583 | } |
| 1584 | |
| 1585 | static void backtrace_warning(void *data, char *msg) |
| 1586 | { |
| 1587 | /* Ignore warnings */ |
| 1588 | } |
| 1589 | |
| 1590 | static int backtrace_stack(void *data, char *name) |
| 1591 | { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1592 | return 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1593 | } |
| 1594 | |
| 1595 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 1596 | { |
| 1597 | struct perf_callchain_entry *entry = data; |
| 1598 | |
Frederic Weisbecker | 6f4dee0 | 2010-03-18 23:47:01 +0100 | [diff] [blame] | 1599 | callchain_store(entry, addr); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1600 | } |
| 1601 | |
| 1602 | static const struct stacktrace_ops backtrace_ops = { |
| 1603 | .warning = backtrace_warning, |
| 1604 | .warning_symbol = backtrace_warning_symbol, |
| 1605 | .stack = backtrace_stack, |
| 1606 | .address = backtrace_address, |
Frederic Weisbecker | 06d65bd | 2009-12-17 05:40:34 +0100 | [diff] [blame] | 1607 | .walk_stack = print_context_stack_bp, |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1608 | }; |
| 1609 | |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1610 | #include "../dumpstack.h" |
| 1611 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1612 | static void |
| 1613 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1614 | { |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1615 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1616 | callchain_store(entry, regs->ip); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1617 | |
Frederic Weisbecker | 48b5ba9 | 2009-12-31 05:53:02 +0100 | [diff] [blame] | 1618 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1619 | } |
| 1620 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1621 | #ifdef CONFIG_COMPAT |
| 1622 | static inline int |
| 1623 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1624 | { |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1625 | /* 32-bit process in 64-bit kernel. */ |
| 1626 | struct stack_frame_ia32 frame; |
| 1627 | const void __user *fp; |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1628 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1629 | if (!test_thread_flag(TIF_IA32)) |
| 1630 | return 0; |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1631 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1632 | fp = compat_ptr(regs->bp); |
| 1633 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
| 1634 | unsigned long bytes; |
| 1635 | frame.next_frame = 0; |
| 1636 | frame.return_address = 0; |
| 1637 | |
| 1638 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
| 1639 | if (bytes != sizeof(frame)) |
| 1640 | break; |
| 1641 | |
| 1642 | if (fp < compat_ptr(regs->sp)) |
| 1643 | break; |
| 1644 | |
| 1645 | callchain_store(entry, frame.return_address); |
| 1646 | fp = compat_ptr(frame.next_frame); |
| 1647 | } |
| 1648 | return 1; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1649 | } |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1650 | #else |
| 1651 | static inline int |
| 1652 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1653 | { |
| 1654 | return 0; |
| 1655 | } |
| 1656 | #endif |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1657 | |
| 1658 | static void |
| 1659 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1660 | { |
| 1661 | struct stack_frame frame; |
| 1662 | const void __user *fp; |
| 1663 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1664 | if (!user_mode(regs)) |
| 1665 | regs = task_pt_regs(current); |
| 1666 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1667 | fp = (void __user *)regs->bp; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1668 | |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1669 | callchain_store(entry, PERF_CONTEXT_USER); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1670 | callchain_store(entry, regs->ip); |
| 1671 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1672 | if (perf_callchain_user32(regs, entry)) |
| 1673 | return; |
| 1674 | |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1675 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1676 | unsigned long bytes; |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1677 | frame.next_frame = NULL; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1678 | frame.return_address = 0; |
| 1679 | |
Torok Edwin | 257ef9d | 2010-03-17 12:07:16 +0200 | [diff] [blame] | 1680 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
| 1681 | if (bytes != sizeof(frame)) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1682 | break; |
| 1683 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1684 | if ((unsigned long)fp < regs->sp) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1685 | break; |
| 1686 | |
| 1687 | callchain_store(entry, frame.return_address); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1688 | fp = frame.next_frame; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1689 | } |
| 1690 | } |
| 1691 | |
| 1692 | static void |
| 1693 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1694 | { |
| 1695 | int is_user; |
| 1696 | |
| 1697 | if (!regs) |
| 1698 | return; |
| 1699 | |
| 1700 | is_user = user_mode(regs); |
| 1701 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1702 | if (is_user && current->state != TASK_RUNNING) |
| 1703 | return; |
| 1704 | |
| 1705 | if (!is_user) |
| 1706 | perf_callchain_kernel(regs, entry); |
| 1707 | |
| 1708 | if (current->mm) |
| 1709 | perf_callchain_user(regs, entry); |
| 1710 | } |
| 1711 | |
| 1712 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) |
| 1713 | { |
| 1714 | struct perf_callchain_entry *entry; |
| 1715 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1716 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
| 1717 | /* TODO: We don't support guest os callchain now */ |
| 1718 | return NULL; |
| 1719 | } |
| 1720 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1721 | if (in_nmi()) |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1722 | entry = &__get_cpu_var(pmc_nmi_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1723 | else |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1724 | entry = &__get_cpu_var(pmc_irq_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1725 | |
| 1726 | entry->nr = 0; |
| 1727 | |
| 1728 | perf_do_callchain(regs, entry); |
| 1729 | |
| 1730 | return entry; |
| 1731 | } |
Frederic Weisbecker | 5331d7b | 2010-03-04 21:15:56 +0100 | [diff] [blame] | 1732 | |
| 1733 | void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip) |
| 1734 | { |
| 1735 | regs->ip = ip; |
| 1736 | /* |
| 1737 | * perf_arch_fetch_caller_regs adds another call, we need to increment |
| 1738 | * the skip level |
| 1739 | */ |
| 1740 | regs->bp = rewind_frame_pointer(skip + 1); |
| 1741 | regs->cs = __KERNEL_CS; |
Peter Zijlstra | 87f44bb | 2010-05-25 11:02:55 +0200 | [diff] [blame] | 1742 | /* |
| 1743 | * We abuse bit 3 to pass exact information, see perf_misc_flags |
| 1744 | * and the comment with PERF_EFLAGS_EXACT. |
| 1745 | */ |
| 1746 | regs->flags = 0; |
Frederic Weisbecker | 5331d7b | 2010-03-04 21:15:56 +0100 | [diff] [blame] | 1747 | } |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1748 | |
| 1749 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
| 1750 | { |
| 1751 | unsigned long ip; |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 1752 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1753 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
| 1754 | ip = perf_guest_cbs->get_guest_ip(); |
| 1755 | else |
| 1756 | ip = instruction_pointer(regs); |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 1757 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1758 | return ip; |
| 1759 | } |
| 1760 | |
| 1761 | unsigned long perf_misc_flags(struct pt_regs *regs) |
| 1762 | { |
| 1763 | int misc = 0; |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 1764 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1765 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
Zhang, Yanmin | dcf46b9 | 2010-04-20 10:13:58 +0800 | [diff] [blame] | 1766 | if (perf_guest_cbs->is_user_mode()) |
| 1767 | misc |= PERF_RECORD_MISC_GUEST_USER; |
| 1768 | else |
| 1769 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; |
| 1770 | } else { |
| 1771 | if (user_mode(regs)) |
| 1772 | misc |= PERF_RECORD_MISC_USER; |
| 1773 | else |
| 1774 | misc |= PERF_RECORD_MISC_KERNEL; |
| 1775 | } |
| 1776 | |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1777 | if (regs->flags & PERF_EFLAGS_EXACT) |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1778 | misc |= PERF_RECORD_MISC_EXACT_IP; |
Zhang, Yanmin | 39447b3 | 2010-04-19 13:32:41 +0800 | [diff] [blame] | 1779 | |
| 1780 | return misc; |
| 1781 | } |